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(parent: a1319b5) | patch
spi: cadence_qspi: Fix OSPI DDR mode alignment issue
authorPadmarao Begari <padmarao.begari@amd.com>
Mon, 6 Jan 2025 09:51:20 +0000 (15:21 +0530)
committerMichal Simek <michal.simek@amd.com>
Wed, 5 Feb 2025 15:22:55 +0000 (16:22 +0100)
commit1621851495d341efb9c62c07a3d82feaa12cd03e
tree9a2e56ae72f92441d4b72843dcc111ca3473d8c5tree | snapshot
parenta1319b5487522b1cdf981ae8bb02118fc53a801fcommit | diff
spi: cadence_qspi: Fix OSPI DDR mode alignment issue

If the least significant bit of the address is set to one when
using the DDR protocol for data transfer then the results are
indeterminate for few flash devices. To fix this the least
significant bit of the address is set to zero.

Signed-off-by: Padmarao Begari <padmarao.begari@amd.com>
Link: https://lore.kernel.org/r/20250106095120.800753-1-padmarao.begari@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
drivers/spi/cadence_ospi_versal.c diff | blob | history
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