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(parent: ba365c3) | patch
net: mediatek: use correct register field for SGMII speed selection
authorWeijie Gao <weijie.gao@mediatek.com>
Tue, 17 Dec 2024 08:39:23 +0000 (16:39 +0800)
committerTom Rini <trini@konsulko.com>
Tue, 31 Dec 2024 16:58:52 +0000 (10:58 -0600)
commit0d4d8e6f47ef22ea6b3041b4c0cb27b4ed4bf188
tree42abfbccbf70c21179e3633c1203818f53f8a080tree | snapshot
parentba365c3d23411620d86b5baf621c8f5a4000ab33commit | diff
net: mediatek: use correct register field for SGMII speed selection

The register field for SGMII speed selection is a 2-bit field with
value 0 for 1Gbps and 1 for 2.5Gbps (2/3 are reserved).
So it's necessary to set both bits instead of just setting/clearing
only the lower bit.

Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
drivers/net/mtk_eth.c diff | blob | history
drivers/net/mtk_eth.h diff | blob | history
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