mmc: am654_sdhci: Fix HIGH_SPEED_ENA
authorJudith Mendez <jm@ti.com>
Thu, 17 Apr 2025 23:43:32 +0000 (18:43 -0500)
committerTom Rini <trini@konsulko.com>
Thu, 24 Apr 2025 16:44:52 +0000 (10:44 -0600)
commit02c6913a97934c3b68629739b9c6273539e37a96
treea0154e6f281697cd01b3e25944c40ffa38212a06
parentc511c708aaf00d850f2c8eee7d083466a04109b7
mmc: am654_sdhci: Fix HIGH_SPEED_ENA

High Speed enable bit switches data launch from the falling
clock edge (half cycle timing) to the rising clock edge (full
cycle timing). For all SD UHS modes, data launch must happen
at the rising clock edge, so set HIGH_SPEED_ENA for SDR12 and
SDR25 modes. For all HS modes, data launch must happen at the
falling clock edge, so do not set HIGH_SPEED_ENA for MMC_HS_52.

Signed-off-by: Judith Mendez <jm@ti.com>
Reviewed-by: Bryan Brattlof <bb@ti.com>
drivers/mmc/am654_sdhci.c