OMAP3: Move get_device_type() function to not duplicate code

[pandora-x-loader.git] / board / overo / overo.c

diff --git a/board/overo/overo.c b/board/overo/overo.c
index 4ca1ecf..b942c5b 100644 (file)
--- a/board/overo/overo.c
+++ b/board/overo/overo.c
@@ -30,6 +30,7 @@
 #include <command.h>
 #include <part.h>
 #include <fat.h>
+#include <i2c.h>
 #include <asm/arch/cpu.h>
 #include <asm/arch/bits.h>
 #include <asm/arch/gpio.h>
@@ -98,16 +99,6 @@ int board_init(void)
        return 0;
 }
 
-/*************************************************************
- *  get_device_type(): tell if GP/HS/EMU/TST
- *************************************************************/
-u32 get_device_type(void)
-{
-       int mode;
-       mode = __raw_readl(CONTROL_STATUS) & (DEVICE_MASK);
-       return mode >>= 8;
-}
-
 /************************************************
  * get_sysboot_value(void) - return SYS_BOOT[4:0]
  ************************************************/
@@ -350,6 +341,16 @@ u32 cpu_is_3410(void)
 int get_board_revision(void)
 {
        int revision;
+       unsigned char data;
+
+       /* board revisions <= R2410 connect 4030 irq_1 to gpio112             */
+       /* these boards should return a revision number of 0                  */
+       /* the code below forces a 4030 RTC irq to ensure that gpio112 is low */
+       data = 0x01;
+       i2c_write(0x4B, 0x29, 1, &data, 1);
+       data = 0x0c;
+       i2c_write(0x4B, 0x2b, 1, &data, 1);
+       i2c_read(0x4B, 0x2a, 1, &data, 1);
 
        if (!omap_request_gpio(112) &&
            !omap_request_gpio(113) &&
@@ -441,6 +442,17 @@ void config_3430sdram_ddr(void)
                __raw_writel(SDP_3430_SDRC_RFR_CTRL_165MHz, SDRC_RFR_CTRL_0);
                __raw_writel(SDP_3430_SDRC_RFR_CTRL_165MHz, SDRC_RFR_CTRL_1);
                break;
+       case 2: /* Hynix 256MB/512MB, 1/2 banks of 256MB */
+               __raw_writel(0x2, SDRC_CS_CFG); /* 256MB/bank */
+               __raw_writel(SDP_SDRC_MDCFG_0_DDR_HYNIX, SDRC_MCFG_0);
+               __raw_writel(SDP_SDRC_MDCFG_0_DDR_HYNIX, SDRC_MCFG_1);
+               __raw_writel(HYNIX_V_ACTIMA_165, SDRC_ACTIM_CTRLA_0);
+               __raw_writel(HYNIX_V_ACTIMB_165, SDRC_ACTIM_CTRLB_0);
+               __raw_writel(HYNIX_V_ACTIMA_165, SDRC_ACTIM_CTRLA_1);
+               __raw_writel(HYNIX_V_ACTIMB_165, SDRC_ACTIM_CTRLB_1);
+               __raw_writel(SDP_3430_SDRC_RFR_CTRL_165MHz, SDRC_RFR_CTRL_0);
+               __raw_writel(SDP_3430_SDRC_RFR_CTRL_165MHz, SDRC_RFR_CTRL_1);
+               break;
        default:
                __raw_writel(0x1, SDRC_CS_CFG); /* 128MB/bank */
                __raw_writel(SDP_SDRC_MDCFG_0_DDR, SDRC_MCFG_0);
@@ -588,7 +600,7 @@ void prcm_init(void)
         * and sil_index will get the values for that SysClk for the
         * appropriate silicon rev.
         */
-       sil_index = get_cpu_rev() - 1;
+       sil_index = (get_cpu_rev() == CPU_3XX_ES10) ? 0 : 1;
 
        /* Unlock MPU DPLL (slows things down, and needed later) */
        sr32(CM_CLKEN_PLL_MPU, 0, 3, PLL_LOW_POWER_BYPASS);