Pandora Sourcecodes - openembedded.git/blob

   1 From 13ed8be9848adff30bcfdcbe16bce3d2c6bb02f1 Mon Sep 17 00:00:00 2001
   2 From: Steve Sakoman <steve@sakoman.com>
   3 Date: Wed, 3 Feb 2010 12:26:30 -0800
   4 Subject: [PATCH 05/50] OMAP3: add entry for rev 3.1.2, check and display max cpu clock for rev > 3.0
   5
   6 ---
   7  cpu/arm_cortexa8/omap3/sys_info.c  |   24 ++++++++++++++++++++++--
   8  include/asm-arm/arch-omap3/cpu.h   |    8 +++++++-
   9  include/asm-arm/arch-omap3/omap3.h |    3 ++-
  10  3 files changed, 31 insertions(+), 4 deletions(-)
  11
  12 diff --git a/cpu/arm_cortexa8/omap3/sys_info.c b/cpu/arm_cortexa8/omap3/sys_info.c
  13 index 08fb32e..e227f67 100644
  14 --- a/cpu/arm_cortexa8/omap3/sys_info.c
  15 +++ b/cpu/arm_cortexa8/omap3/sys_info.c
  16 @@ -39,7 +39,10 @@ static char *rev_s[CPU_3XX_MAX_REV] = {
  17                                 "2.0",
  18                                 "2.1",
  19                                 "3.0",
  20 -                               "3.1"};
  21 +                               "3.1",
  22 +                               "UNKNOWN",
  23 +                               "UNKNOWN",
  24 +                               "3.1.2"};
  25
  26  /*****************************************************************
  27   * dieid_num_r(void) - read and set die ID
  28 @@ -104,6 +107,16 @@ u32 get_cpu_rev(void)
  29         }
  30  }
  31
  32 +/*****************************************************************
  33 + * get_sku_id(void) - read sku_id to get info on max clock rate
  34 + *****************************************************************/
  35 +u32 get_sku_id(void)
  36 +{
  37 +       struct ctrl_id *id_base = (struct ctrl_id *)OMAP34XX_ID_L4_IO_BASE;
  38 +       return (readl(&id_base->sku_id) & SKUID_CLK_MASK);
  39 +}
  40 +
  41 +
  42  /****************************************************
  43   * is_mem_sdr() - return 1 if mem type in use is SDR
  44   ****************************************************/
  45 @@ -291,9 +304,16 @@ int print_cpuinfo (void)
  46                 sec_s = "?";
  47         }
  48
  49 -       printf("OMAP%s-%s ES%s, CPU-OPP2 L3-165MHz\n",
  50 +       printf("OMAP%s-%s ES%s, CPU-OPP2, L3-165MHz, ",
  51                         cpu_s, sec_s, rev_s[get_cpu_rev()]);
  52
  53 +       printf("Max clock-");
  54 +       if ((get_cpu_rev() >= CPU_3XX_ES31) && (get_sku_id() == SKUID_CLK_720MHZ))
  55 +               printf("720Mhz\n");
  56 +       else    printf("600Mhz\n");
  57 +
  58 +
  59 +
  60         return 0;
  61  }
  62  #endif /* CONFIG_DISPLAY_CPUINFO */
  63 diff --git a/include/asm-arm/arch-omap3/cpu.h b/include/asm-arm/arch-omap3/cpu.h
  64 index aa8de32..f769571 100644
  65 --- a/include/asm-arm/arch-omap3/cpu.h
  66 +++ b/include/asm-arm/arch-omap3/cpu.h
  67 @@ -72,7 +72,8 @@ struct ctrl_id {
  68         u8 res1[0x4];
  69         u32 idcode;             /* 0x04 */
  70         u32 prod_id;            /* 0x08 */
  71 -       u8 res2[0x0C];
  72 +       u32 sku_id;             /* 0x0c */
  73 +       u8 res2[0x08];
  74         u32 die_id_0;           /* 0x18 */
  75         u32 die_id_1;           /* 0x1C */
  76         u32 die_id_2;           /* 0x20 */
  77 @@ -89,6 +90,11 @@ struct ctrl_id {
  78  #define HS_DEVICE              0x2
  79  #define GP_DEVICE              0x3
  80
  81 +/* device speed */
  82 +#define SKUID_CLK_MASK         0xf
  83 +#define SKUID_CLK_600MHZ       0x0
  84 +#define SKUID_CLK_720MHZ       0x8
  85 +
  86  #define GPMC_BASE              (OMAP34XX_GPMC_BASE)
  87  #define GPMC_CONFIG_CS0                0x60
  88  #define GPMC_CONFIG_CS0_BASE   (GPMC_BASE + GPMC_CONFIG_CS0)
  89 diff --git a/include/asm-arm/arch-omap3/omap3.h b/include/asm-arm/arch-omap3/omap3.h
  90 index 12815f6..1349b8b 100644
  91 --- a/include/asm-arm/arch-omap3/omap3.h
  92 +++ b/include/asm-arm/arch-omap3/omap3.h
  93 @@ -176,7 +176,8 @@ struct gpio {
  94  #define CPU_3XX_ES21           2
  95  #define CPU_3XX_ES30           3
  96  #define CPU_3XX_ES31           4
  97 -#define CPU_3XX_MAX_REV                (CPU_3XX_ES31 + 1)
  98 +#define CPU_3XX_ES312          7
  99 +#define CPU_3XX_MAX_REV                8
 100
 101  #define CPU_3XX_ID_SHIFT       28
 102
 103 --
 104 1.6.6.1
 105