Pandora Sourcecodes - openembedded.git/blob

   1 From 750f7ddc0881834f3400c40e9a59d11f9427cf99 Mon Sep 17 00:00:00 2001
   2 From: Tomi Valkeinen <tomi.valkeinen@nokia.com>
   3 Date: Wed, 29 Apr 2009 17:26:30 +0300
   4 Subject: [PATCH 59/69] DSS2: DSI: configure ENTER/EXIT_HS_MODE_LATENCY
   5
   6 ---
   7  drivers/video/omap2/dss/dsi.c |   49 ++++++++++++++++++++++++++++++++--------
   8  1 files changed, 39 insertions(+), 10 deletions(-)
   9
  10 diff --git a/drivers/video/omap2/dss/dsi.c b/drivers/video/omap2/dss/dsi.c
  11 index d8df353..5225ed6 100644
  12 --- a/drivers/video/omap2/dss/dsi.c
  13 +++ b/drivers/video/omap2/dss/dsi.c
  14 @@ -2309,15 +2309,26 @@ static int dsi_proto_config(struct omap_display *display)
  15         return 0;
  16  }
  17
  18 -static void dsi_proto_timings(void)
  19 -{
  20 -       int tlpx_half, tclk_zero, tclk_prepare, tclk_trail;
  21 -       int tclk_pre, tclk_post;
  22 -       int ddr_clk_pre, ddr_clk_post;
  23 +static void dsi_proto_timings(struct omap_display *display)
  24 +{
  25 +       unsigned tlpx, tclk_zero, tclk_prepare, tclk_trail;
  26 +       unsigned tclk_pre, tclk_post;
  27 +       unsigned ths_prepare, ths_prepare_ths_zero, ths_zero;
  28 +       unsigned ths_trail, ths_exit;
  29 +       unsigned ddr_clk_pre, ddr_clk_post;
  30 +       unsigned enter_hs_mode_lat, exit_hs_mode_lat;
  31 +       unsigned ths_eot;
  32         u32 r;
  33
  34 +       r = dsi_read_reg(DSI_DSIPHY_CFG0);
  35 +       ths_prepare = FLD_GET(r, 31, 24);
  36 +       ths_prepare_ths_zero = FLD_GET(r, 23, 16);
  37 +       ths_zero = ths_prepare_ths_zero - ths_prepare;
  38 +       ths_trail = FLD_GET(r, 15, 8);
  39 +       ths_exit = FLD_GET(r, 7, 0);
  40 +
  41         r = dsi_read_reg(DSI_DSIPHY_CFG1);
  42 -       tlpx_half = FLD_GET(r, 22, 16);
  43 +       tlpx = FLD_GET(r, 22, 16) * 2;
  44         tclk_trail = FLD_GET(r, 15, 8);
  45         tclk_zero = FLD_GET(r, 7, 0);
  46
  47 @@ -2329,17 +2340,35 @@ static void dsi_proto_timings(void)
  48         /* min 60ns + 52*UI */
  49         tclk_post = ns2ddr(60) + 26;
  50
  51 -       ddr_clk_pre = (tclk_pre + tlpx_half*2 + tclk_zero + tclk_prepare) / 4;
  52 -       ddr_clk_post = (tclk_post + tclk_trail) / 4;
  53 +       ddr_clk_pre = DIV_ROUND_UP(tclk_pre + tlpx + tclk_zero + tclk_prepare,
  54 +                       4);
  55 +       ddr_clk_post = DIV_ROUND_UP(tclk_post + tclk_trail, 4);
  56
  57         r = dsi_read_reg(DSI_CLK_TIMING);
  58         r = FLD_MOD(r, ddr_clk_pre, 15, 8);
  59         r = FLD_MOD(r, ddr_clk_post, 7, 0);
  60         dsi_write_reg(DSI_CLK_TIMING, r);
  61
  62 -       DSSDBG("ddr_clk_pre %d, ddr_clk_post %d\n",
  63 +       DSSDBG("ddr_clk_pre %u, ddr_clk_post %u\n",
  64                         ddr_clk_pre,
  65                         ddr_clk_post);
  66 +
  67 +       /* ths_eot is 2 for 2 datalanes and 4 for 1 datalane */
  68 +       if (display->hw_config.u.dsi.data1_lane != 0 &&
  69 +                       display->hw_config.u.dsi.data2_lane != 0)
  70 +               ths_eot = 2;
  71 +       else
  72 +               ths_eot = 4;
  73 +
  74 +       enter_hs_mode_lat = DIV_ROUND_UP(tlpx + ths_prepare + ths_zero, 4) + 4;
  75 +       exit_hs_mode_lat = DIV_ROUND_UP(ths_trail + ths_exit, 4) + 1 + ths_eot;
  76 +
  77 +       r = FLD_VAL(enter_hs_mode_lat, 31, 16) |
  78 +               FLD_VAL(exit_hs_mode_lat, 15, 0);
  79 +       dsi_write_reg(DSI_VM_TIMING7, r);
  80 +
  81 +       DSSDBG("enter_hs_mode_lat %u, exit_hs_mode_lat %u\n",
  82 +                       enter_hs_mode_lat, exit_hs_mode_lat);
  83  }
  84
  85
  86 @@ -3340,7 +3369,7 @@ static int dsi_display_init_dsi(struct omap_display *display)
  87
  88         _dsi_print_reset_status();
  89
  90 -       dsi_proto_timings();
  91 +       dsi_proto_timings(display);
  92         dsi_set_lp_clk_divisor();
  93
  94         if (1)
  95 --
  96 1.6.2.4
  97