Pandora Sourcecodes - openembedded.git/blob

   1 From 908b7949544571e9acc1fe0cce918f6e338926c9 Mon Sep 17 00:00:00 2001
   2 From: Ranjith Lohithakshan <ranjithl@ti.com>
   3 Date: Fri, 28 May 2010 15:13:18 +0530
   4 Subject: [PATCH 1/9] OMAP3: SDRC: add 100MHz timing data for Hynix H8KDS0UN0MER-4EM
   5
   6 Also, the refresh control value used at 200MHz was incorrect. Fixed
   7 that as well.
   8
   9 Signed-off-by: Ranjith Lohithakshan <ranjithl@ti.com>
  10 ---
  11  arch/arm/mach-omap2/sdram-hynix-h8kds0un0mer-4em.h |    9 ++++++++-
  12  1 files changed, 8 insertions(+), 1 deletions(-)
  13
  14 diff --git a/arch/arm/mach-omap2/sdram-hynix-h8kds0un0mer-4em.h b/arch/arm/mach-omap2/sdram-hynix-h8kds0un0mer-4em.h
  15 index 06433e6..c147586 100644
  16 --- a/arch/arm/mach-omap2/sdram-hynix-h8kds0un0mer-4em.h
  17 +++ b/arch/arm/mach-omap2/sdram-hynix-h8kds0un0mer-4em.h
  18 @@ -19,10 +19,17 @@ static struct omap_sdrc_params h8kds0un0mer4em_sdrc_params[] = {
  19                 .rate        = 200000000,
  20                 .actim_ctrla = 0x92e1c4c6,
  21                 .actim_ctrlb = 0x0002111c,
  22 -               .rfr_ctrl    = 0x0004dc01,
  23 +               .rfr_ctrl    = 0x0005e601,
  24                 .mr          = 0x00000032,
  25         },
  26         [1] = {
  27 +               .rate        = 100000000,
  28 +               .actim_ctrla = 0x49912283,
  29 +               .actim_ctrlb = 0x0002110e,
  30 +               .rfr_ctrl    = 0x0002da01,
  31 +               .mr          = 0x00000032,
  32 +    },
  33 +       [2] = {
  34                 .rate        = 0
  35         },
  36  };
  37 --
  38 1.6.2.4
  39