1 From fd092c7f2286fab34cf42c6c56360ae7794dbc7f Mon Sep 17 00:00:00 2001
2 From: Mans Rullgard <mans@mansr.com>
3 Date: Wed, 14 Apr 2010 17:10:28 +0100
4 Subject: [PATCH 30/50] OMAP3: apply Cortex-A8 errata workarounds only on affected revisions
6 The workarounds for errata 621766 and 725233 should only be applied
7 on affected Cortex-A8 revisions. Recent chips use r3px cores where
10 Signed-off-by: Mans Rullgard <mans@mansr.com>
12 cpu/arm_cortexa8/omap3/cache.S | 13 ++++++++++---
13 1 files changed, 10 insertions(+), 3 deletions(-)
15 diff --git a/cpu/arm_cortexa8/omap3/cache.S b/cpu/arm_cortexa8/omap3/cache.S
16 index 61e6946..932e4eb 100644
17 --- a/cpu/arm_cortexa8/omap3/cache.S
18 +++ b/cpu/arm_cortexa8/omap3/cache.S
19 @@ -163,14 +163,21 @@ l2_cache_disable:
21 *****************************************************************************/
23 + mrc p15, 0, r0, c0, c0, 0 @ read main ID register
24 + and r2, r0, #0x00f00000 @ variant
25 + and r3, r0, #0x0000000f @ revision
26 + orr r1, r3, r2, lsr #20-4 @ combine variant and revision
28 mrc p15, 0, r0, c1, c0, 1
29 orr r0, r0, #0x10 @ Enable ASA
30 - orr r0, r0, #1 << 5 @ Enable L1NEON
31 + @ Enable L1NEON on pre-r2p1 (erratum 621766 workaround)
33 + orrlt r0, r0, #1 << 5
34 .word 0xE1600070 @ SMC
36 mrc p15, 1, r0, c9, c0, 2
37 - @ Set PLD_FWD bit in L2AUXCR (Cortex-A8 erratum 725233 workaround)
38 - orr r0, r0, #1 << 27
39 + @ Set PLD_FWD bit in L2AUXCR on pre-r2p1 (erratum 725233 workaround)
41 + orrlt r0, r0, #1 << 27
42 .word 0xE1600070 @ SMC