Pandora Sourcecodes - openembedded.git/blob

   1 From 500b0887632165f77f2604b07df746b4a3a16d2c Mon Sep 17 00:00:00 2001
   2 From: Hugo Villeneuve <hugo@hugovil.com>
   3 Date: Fri, 6 Mar 2009 10:23:44 -0500
   4 Subject: [PATCH 10/12] Add generic FPGA bitstream loader driver
   5
   6 This driver is a generic interface for programming a
   7 bitstream into a FPGA. It can work with serial or
   8 parallel programming interfaces and support multiple
   9 devices and partial reconfiguration. Currently Xilinx
  10 XC3S and XC4V FPGAs are implemented, but other
  11 manufacturers like Altera could be easily added.
  12
  13 Signed-off-by: Hugo Villeneuve <hugo@hugovil.com>
  14 ---
  15  drivers/misc/Kconfig      |   31 ++
  16  drivers/misc/Makefile     |    3 +
  17  drivers/misc/fpgadl.c     |  806 +++++++++++++++++++++++++++++++++++++++++++++
  18  drivers/misc/fpgadl_par.c |  258 +++++++++++++++
  19  drivers/misc/fpgadl_ser.c |  244 ++++++++++++++
  20  include/linux/fpgadl.h    |   96 ++++++
  21  6 files changed, 1438 insertions(+), 0 deletions(-)
  22  create mode 100644 drivers/misc/fpgadl.c
  23  create mode 100644 drivers/misc/fpgadl_par.c
  24  create mode 100644 drivers/misc/fpgadl_ser.c
  25  create mode 100644 include/linux/fpgadl.h
  26
  27 diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
  28 index a11e2a0..bdc0517 100644
  29 --- a/drivers/misc/Kconfig
  30 +++ b/drivers/misc/Kconfig
  31 @@ -510,6 +510,37 @@ config SGI_GRU_DEBUG
  32         This option enables addition debugging code for the SGI GRU driver. If
  33         you are unsure, say N.
  34
  35 +config FPGADL
  36 +       tristate "FPGA bitstream loader support"
  37 +       help
  38 +         This option enables support for the FPGA bitstream loader.
  39 +
  40 +         To compile this driver as a module, choose M here: the
  41 +         module will be called fpgadl.
  42 +
  43 +         If unsure, say N.
  44 +
  45 +config FPGADL_SER
  46 +       tristate "FPGA serial programming driver"
  47 +       depends on SPI_MASTER && FPGADL
  48 +       help
  49 +         Say Y here if your FPGA bitstream is loaded using a serial
  50 +         interface (SPI).
  51 +
  52 +         To compile this driver as a module, choose M here: the
  53 +         module will be called fpgadl_ser.
  54 +
  55 +config FPGADL_PAR
  56 +       tristate "FPGA parallel programming driver"
  57 +       depends on FPGADL
  58 +       select BITREVERSE
  59 +       help
  60 +         Say Y here if your FPGA bitstream is loaded using a parallel
  61 +         interface.
  62 +
  63 +         To compile this driver as a module, choose M here: the
  64 +         module will be called fpgadl_par.
  65 +
  66  source "drivers/misc/c2port/Kconfig"
  67
  68  endif # MISC_DEVICES
  69 diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
  70 index 78be134..4fb6dfc 100644
  71 --- a/drivers/misc/Makefile
  72 +++ b/drivers/misc/Makefile
  73 @@ -32,5 +32,8 @@ obj-$(CONFIG_ENCLOSURE_SERVICES) += enclosure.o
  74  obj-$(CONFIG_KGDB_TESTS)       += kgdbts.o
  75  obj-$(CONFIG_SGI_XP)           += sgi-xp/
  76  obj-$(CONFIG_SGI_GRU)          += sgi-gru/
  77 +obj-$(CONFIG_FPGADL)           += fpgadl.o
  78 +obj-$(CONFIG_FPGADL_SER)       += fpgadl_ser.o
  79 +obj-$(CONFIG_FPGADL_PAR)       += fpgadl_par.o
  80  obj-$(CONFIG_HP_ILO)           += hpilo.o
  81  obj-$(CONFIG_C2PORT)           += c2port/
  82 diff --git a/drivers/misc/fpgadl.c b/drivers/misc/fpgadl.c
  83 new file mode 100644
  84 index 0000000..2f03d9b
  85 --- /dev/null
  86 +++ b/drivers/misc/fpgadl.c
  87 @@ -0,0 +1,806 @@
  88 +/*
  89 + * fpgadl core driver
  90 + *
  91 + * Copyright (C) 2008 Lyrtech <www.lyrtech.com>
  92 + *
  93 + * Based on code found in book "Linux Device Drivers" by
  94 + * Alessandro Rubini and Jonathan Corbet, published by O'Reilly & Associates.
  95 + *
  96 + * This program is free software; you can redistribute it and/or modify
  97 + * it under the terms of the GNU General Public License as published by
  98 + * the Free Software Foundation; either version 2 of the License, or
  99 + * (at your option) any later version.
 100 + *
 101 + * This program is distributed in the hope that it will be useful,
 102 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
 103 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 104 + * GNU General Public License for more details.
 105 + *
 106 + * You should have received a copy of the GNU General Public License
 107 + * along with this program; if not, write to the Free Software
 108 + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 109 + */
 110 +
 111 +#include <linux/kernel.h>
 112 +#include <linux/module.h>
 113 +#include <linux/moduleparam.h>
 114 +#include <linux/init.h>
 115 +#include <linux/device.h>
 116 +#include <linux/platform_device.h>
 117 +#include <linux/miscdevice.h>
 118 +#include <linux/string.h>
 119 +#include <linux/err.h>
 120 +#include <linux/fs.h>
 121 +#include <linux/firmware.h>
 122 +#include <linux/delay.h>
 123 +#include <linux/fpgadl.h>
 124 +
 125 +#include <asm/gpio.h>
 126 +#include <asm/uaccess.h>
 127 +
 128 +#define MODULE_NAME "fpgadl"
 129 +
 130 +/* Define this to enable verbose debug messages */
 131 +#define FPGADL_DEBUG 1
 132 +
 133 +static const char fpgadl_driver_version[] = "v1.0";
 134 +
 135 +/* Module parameters */
 136 +static unsigned int fpgadl_debug;
 137 +EXPORT_SYMBOL_GPL(fpgadl_debug);
 138 +module_param_named(debug, fpgadl_debug, int, 0644);
 139 +
 140 +#ifdef FPGADL_DEBUG
 141 +#define INFOMSG(fmt, args...)                                          \
 142 +       do {                                                            \
 143 +               printk(KERN_INFO "%s: "fmt"\n", MODULE_NAME, ## args);  \
 144 +       } while (0)
 145 +#define DBGMSG(fmt, args...)                                           \
 146 +       do {                                                            \
 147 +               if (fpgadl_debug > 0)                                   \
 148 +                       printk(KERN_DEBUG "%s: "fmt"\n", \
 149 +                              MODULE_NAME, ## args);    \
 150 +       } while (0)
 151 +#define DBGMSG_ENTER()                         \
 152 +       DBGMSG("%s() enter", __func__);
 153 +#define DBGMSG_LEAVE()                         \
 154 +       DBGMSG("%s() leave", __func__);
 155 +#else
 156 +#define INFOMSG(fmt, args...) do {} while (0)
 157 +#define DBGMSG(fmt, args...) do {} while (0)
 158 +#define DBGMSG_ENTER() do {} while (0)
 159 +#define DBGMSG_LEAVE() do {} while (0)
 160 +#endif
 161 +
 162 +#define FAILMSG(fmt, args...)                                          \
 163 +       do {                                                            \
 164 +               printk(KERN_ERR "%s: "fmt"\n", MODULE_NAME, ## args);   \
 165 +       } while (0)
 166 +
 167 +#define FPGA_WAIT_TIMEOUT      100000
 168 +#define XFER_SIZE              100     /* Transfer size when writing bytes to
 169 +                                        * device. */
 170 +
 171 +#define BITSTREAM_MAX_SIZE_OVERHEAD 10240
 172 +
 173 +#define XC3S_WORD_SIZE 2
 174 +#define XC4V_WORD_SIZE 4
 175 +
 176 +#define BITSTREAM_SYNC_BYTE1           0xAA
 177 +#define BITSTREAM_SYNC_BYTE2           0x99
 178 +#define BITSTREAM_SYNC_BYTE3           0x55
 179 +#define BITSTREAM_SYNC_BYTE4           0x66
 180 +
 181 +#define BITSTREAM_PACKET_HEADER_TYPE1  1
 182 +#define BITSTREAM_PACKET_HEADER_TYPE2  2
 183 +#define BITSTREAM_TYPE1_OPCODE_WRITE   2
 184 +#define BITSTREAM_TYPE1_REG_ADDR_FDRI  2
 185 +
 186 +/* Structure of a TYPE1 packet. */
 187 +struct t1_pkt_xc4v_t {
 188 +       u32 word_count:11;
 189 +       u32 reserved2:2;
 190 +       u32 address:5;
 191 +       u32 reserved1:9;
 192 +       u32 opcode:2;
 193 +       u32 header:3;
 194 +};
 195 +
 196 +struct t1_pkt_xc3s_t {
 197 +       u16 word_count:5;
 198 +       u16 address:6;
 199 +       u16 opcode:2;
 200 +       u16 header:3; /* type */
 201 +};
 202 +
 203 +/* Structure of a TYPE2 packet. */
 204 +struct t2_pkt_xc4v_t {
 205 +       u32 word_count:27;
 206 +       u32 opcode:2; /* Reserved. */
 207 +       u32 header:3;
 208 +};
 209 +
 210 +struct t2_pkt_xc3s_t {
 211 +       u16 word_count:11;
 212 +       u16 opcode:2; /* Reserved. */
 213 +       u16 header:3;
 214 +};
 215 +
 216 +#define MAX_FPGADL_DEV 4
 217 +
 218 +static int fpgadl_dev_count;
 219 +static struct fpgadl_device *fpgadl_dev_array[MAX_FPGADL_DEV];
 220 +
 221 +int fpgadl_is_bitstream_loaded(const char *name)
 222 +{
 223 +       int k;
 224 +       struct fpgadl_device *fpgadl_dev;
 225 +
 226 +       DBGMSG_ENTER();
 227 +
 228 +       for (k = 0; k < MAX_FPGADL_DEV; k++) {
 229 +               fpgadl_dev = fpgadl_dev_array[k];
 230 +               if (fpgadl_dev)
 231 +                       if (strncmp(fpgadl_dev->name, name, strlen(name)) == 0)
 232 +                               return fpgadl_dev->bitstream_loaded;
 233 +       }
 234 +
 235 +       FAILMSG("  Device <%s> not found", name);
 236 +       return -ENOMEM;
 237 +}
 238 +EXPORT_SYMBOL(fpgadl_is_bitstream_loaded);
 239 +
 240 +/* Respond to hotplug events. */
 241 +static int fpgadl_uevent(struct device *dev, struct kobj_uevent_env *env)
 242 +{
 243 +       DBGMSG_ENTER();
 244 +
 245 +       if (add_uevent_var(env, "FPGADL_BUS_VERSION=%s", fpgadl_driver_version))
 246 +               return -ENOMEM;
 247 +       return 0;
 248 +};
 249 +
 250 +/*
 251 + * Toggles the CCLK line on the board-specific interface the number of times
 252 + * specified by <cycles>.
 253 + */
 254 +static int bitstr_load_make_clock(struct fpgadl_device *fpgadl_dev,
 255 +                                 int cycles)
 256 +{
 257 +       int retval;
 258 +       int k;
 259 +       u8 dummy = 0;
 260 +
 261 +       for (k = 0; k < cycles; k++) {
 262 +               retval = fpgadl_dev->write_byte(fpgadl_dev, &dummy, 1);
 263 +               if (retval < 0)
 264 +                       return retval;
 265 +       }
 266 +
 267 +       return 0;
 268 +}
 269 +
 270 +/* Search for bitstream sync word. */
 271 +static int bitstr_search_sync_word(const u8 *buffer, size_t length,
 272 +                                  const u8 *sync_word, ssize_t sync_word_size)
 273 +{
 274 +       int k;
 275 +
 276 +       for (k = 0; k < length; k++, buffer++) {
 277 +               if (memcmp(buffer, sync_word, sync_word_size) == 0) {
 278 +                       DBGMSG("  Synchronization word found at offset 0x%02X",
 279 +                              k);
 280 +                       return k;
 281 +               }
 282 +       }
 283 +
 284 +       return 0;
 285 +}
 286 +
 287 +static int bitstr_get_payload_size(int fpga_family, int sws,
 288 +                                  const u8 *buffer, ssize_t length)
 289 +{
 290 +       int index = 0;
 291 +
 292 +       /* Find the payload size. */
 293 +       while (index < length) {
 294 +               switch (fpga_family) {
 295 +               case FPGA_FAMILY_XILINX_XC4V:
 296 +               {
 297 +                       u32 tmp = ntohl(*((u32 *) &buffer[index]));
 298 +                       struct t1_pkt_xc4v_t *t1 =
 299 +                               (struct t1_pkt_xc4v_t *) &tmp;
 300 +
 301 +                       /* Search for type 1 packet header. */
 302 +                       if ((t1->header == BITSTREAM_PACKET_HEADER_TYPE1) &&
 303 +                           (t1->opcode == BITSTREAM_TYPE1_OPCODE_WRITE) &&
 304 +                           (t1->address == BITSTREAM_TYPE1_REG_ADDR_FDRI)) {
 305 +                               if (t1->word_count != 0)
 306 +                                       return t1->word_count;
 307 +                               else {
 308 +                                       struct t2_pkt_xc4v_t *t2;
 309 +
 310 +                                       tmp = ntohl(*((u32 *)
 311 +                                                     &buffer[index + sws]));
 312 +                                       t2 = (struct t2_pkt_xc4v_t *) &tmp;
 313 +
 314 +                                       /* Search for type 2 packet header just
 315 +                                        * after type1 packet. */
 316 +                                       if ((t2->header ==
 317 +                                            BITSTREAM_PACKET_HEADER_TYPE2))
 318 +                                               return t2->word_count;
 319 +                               }
 320 +                       }
 321 +               }
 322 +               break;
 323 +               case FPGA_FAMILY_XILINX_XC3S:
 324 +               {
 325 +                       u16 tmp = ntohs(*((u16 *) &buffer[index]));
 326 +                       struct t2_pkt_xc3s_t *t2 =
 327 +                               (struct t2_pkt_xc3s_t *) &tmp;
 328 +
 329 +                       /* Search for type 2 packet header just after
 330 +                        * type1 packet. */
 331 +                       if ((t2->header == BITSTREAM_PACKET_HEADER_TYPE2)) {
 332 +                               DBGMSG("  Type 2 packet found at offset $%02X",
 333 +                                      index);
 334 +                               return ntohl(*((u32 *) &buffer[index + sws]));
 335 +                       }
 336 +                       /* Word-size aligned when sync word has been found. */
 337 +                       index += sws;
 338 +               }
 339 +               break;
 340 +               }
 341 +
 342 +               /* Word-size aligned when sync word has been found. */
 343 +               index += sws;
 344 +       }
 345 +
 346 +       return 0; /* Not found */
 347 +}
 348 +
 349 +/*
 350 + * Return value:
 351 + *   0: Error
 352 + *   1: Full bitstream
 353 + *   2: Partial bitstream
 354 + */
 355 +static int bitstream_parse_header(const u8 *buffer, size_t length,
 356 +                                 int fpga_family, size_t payload_full_size)
 357 +{
 358 +       int index = 0;
 359 +       size_t payload_size = 0;
 360 +       u8 sync_word[] = {
 361 +               BITSTREAM_SYNC_BYTE1,
 362 +               BITSTREAM_SYNC_BYTE2,
 363 +               BITSTREAM_SYNC_BYTE3,
 364 +               BITSTREAM_SYNC_BYTE4,
 365 +       };
 366 +       int sync_word_size; /* Size in bytes */
 367 +
 368 +       switch (fpga_family) {
 369 +       case FPGA_FAMILY_XILINX_XC3S:
 370 +               sync_word_size = XC3S_WORD_SIZE;
 371 +               break;
 372 +       case FPGA_FAMILY_XILINX_XC4V:
 373 +               sync_word_size = XC4V_WORD_SIZE;
 374 +               break;
 375 +       default:
 376 +               FAILMSG("Error, invalid FPGA family number");
 377 +               return BITSTREAM_MODE_UNKNOWN;
 378 +       }
 379 +
 380 +       /* Search for bitstream sync word. */
 381 +       index = bitstr_search_sync_word(buffer, length,
 382 +                                       sync_word, sync_word_size);
 383 +       if (index == 0) {
 384 +               FAILMSG("Error: Synchronization word not found");
 385 +               return BITSTREAM_MODE_UNKNOWN;
 386 +       }
 387 +
 388 +       /* Get payload size. */
 389 +       payload_size = bitstr_get_payload_size(fpga_family, sync_word_size,
 390 +                                              &buffer[index], length - index);
 391 +       payload_size *= sync_word_size; /* Length in bytes. */
 392 +
 393 +       if (payload_size == 0) {
 394 +               /* Warning only, assuming FULL bitstream. */
 395 +               DBGMSG("  Warning: payload size not found");
 396 +               return BITSTREAM_MODE_FULL;
 397 +       } else {
 398 +               DBGMSG("  Payload size: %d kb", payload_size / 1024);
 399 +
 400 +               /* Is it a full or a partial bitstream? */
 401 +               if (payload_size == payload_full_size)
 402 +                       return BITSTREAM_MODE_FULL;
 403 +               else
 404 +                       return BITSTREAM_MODE_PARTIAL;
 405 +       }
 406 +}
 407 +
 408 +/*
 409 + * Bitstreams supported: Full or Partial.
 410 + * Note: Full bitstream that supports partial bitstream must be generated with
 411 + *       option "Persist = true" in ISE.
 412 + */
 413 +static int fpgadl_bitstream_load(struct fpgadl_device *fpgadl_dev,
 414 +                                const u8 *data, size_t size)
 415 +{
 416 +       int k;
 417 +       int retval;
 418 +       int timeout_counter;
 419 +
 420 +       fpgadl_dev->bitstream_loaded = 0;
 421 +
 422 +       fpgadl_dev->bitstream_mode =
 423 +               bitstream_parse_header(data, size,
 424 +                                      fpgadl_dev->pdata->fpga_family,
 425 +                                      fpgadl_dev->pdata->payload_full_size);
 426 +       switch (fpgadl_dev->bitstream_mode) {
 427 +       case BITSTREAM_MODE_FULL:
 428 +               DBGMSG("  Bitstream type: FULL");
 429 +               /* Toggle PROG_B Pin and wait 300nS before proceeding. */
 430 +               gpio_set_value(fpgadl_dev->pdata->program_b, 0);
 431 +               udelay(1);
 432 +
 433 +               /* Confirm that INIT_B is low */
 434 +               if (gpio_get_value(fpgadl_dev->pdata->init_b) != 0) {
 435 +                       FAILMSG("Error: INIT_B not LOW when PROG is LOW");
 436 +                       return -EIO;
 437 +               }
 438 +
 439 +               break;
 440 +       case BITSTREAM_MODE_PARTIAL:
 441 +               DBGMSG("  Bitstream type: PARTIAL");
 442 +               break;
 443 +       case BITSTREAM_MODE_UNKNOWN:
 444 +       default:
 445 +               FAILMSG("  Bitstream type: UNKNOWN");
 446 +               return -EINVAL;
 447 +               break;
 448 +       }
 449 +
 450 +       /* For partial bitstream, PROGRAM_B is already high. */
 451 +       retval = bitstr_load_make_clock(fpgadl_dev, 3);
 452 +       if (retval < 0)
 453 +               return retval;
 454 +
 455 +       gpio_set_value(fpgadl_dev->pdata->program_b, 1);
 456 +
 457 +       /* Wait for INIT_B pin to go high. */
 458 +       timeout_counter = 0;
 459 +       while ((gpio_get_value(fpgadl_dev->pdata->init_b) == 0) &&
 460 +              (timeout_counter < FPGA_WAIT_TIMEOUT)) {
 461 +               retval = bitstr_load_make_clock(fpgadl_dev, 3);
 462 +               if (retval < 0)
 463 +                       return retval;
 464 +
 465 +               timeout_counter++;
 466 +       }
 467 +
 468 +       if (timeout_counter == FPGA_WAIT_TIMEOUT) {
 469 +               /* Timeout error. */
 470 +               FAILMSG("Error: timeout while waiting for INIT_B to go HIGH");
 471 +               return -EIO;
 472 +       }
 473 +
 474 +       /* Send actual bitstream data to FPGA one byte at a time. */
 475 +       for (k = 0; k < size; k += XFER_SIZE) {
 476 +               retval = fpgadl_dev->write_byte(fpgadl_dev,
 477 +                                               (u8 *) &data[k], XFER_SIZE);
 478 +               if (retval < 0)
 479 +                       return retval;
 480 +
 481 +               if (fpgadl_dev->pdata->check_init_low) {
 482 +                       if (gpio_get_value(fpgadl_dev->pdata->init_b) == 0) {
 483 +                               /* Error if INIT_B goes low here. */
 484 +                               FAILMSG("Error: INIT_B LOW during programming");
 485 +                               return -EIO;
 486 +                       }
 487 +               }
 488 +       }
 489 +
 490 +       /* Pulse the clock line ten times at the end. */
 491 +       retval = bitstr_load_make_clock(fpgadl_dev, 10);
 492 +       if (retval < 0)
 493 +               return retval;
 494 +
 495 +       /* FPGA DONE pin must go high. */
 496 +       timeout_counter = 0;
 497 +       while ((gpio_get_value(fpgadl_dev->pdata->done) == 0) &&
 498 +              (timeout_counter < FPGA_WAIT_TIMEOUT))
 499 +               timeout_counter++;
 500 +
 501 +       if (gpio_get_value(fpgadl_dev->pdata->done) == 0) {
 502 +               /* Timeout error. */
 503 +               FAILMSG("Error: timeout while waiting for DONE to go HIGH");
 504 +               return -EIO;
 505 +       }
 506 +
 507 +       INFOMSG("Bitstream loaded");
 508 +       fpgadl_dev->bitstream_loaded = 1;
 509 +
 510 +       return 0;
 511 +}
 512 +
 513 +/* Open method. */
 514 +static int fpgadl_open(struct inode *inode, struct file *filp)
 515 +{
 516 +       int k;
 517 +       int found = 0;
 518 +       struct fpgadl_device *fpgadl_dev;
 519 +
 520 +       DBGMSG_ENTER();
 521 +       DBGMSG("  Opening device minor %d", MINOR(inode->i_rdev));
 522 +
 523 +       for (k = 0; k < fpgadl_dev_count; k++) {
 524 +               fpgadl_dev = fpgadl_dev_array[k];
 525 +               if (fpgadl_dev) {
 526 +                       if (fpgadl_dev->miscdev.minor == MINOR(inode->i_rdev)) {
 527 +                               found = 1;
 528 +                               break;
 529 +                       }
 530 +               }
 531 +       }
 532 +
 533 +       if (!found) {
 534 +               FAILMSG("  Invalid minor device");
 535 +               return -ENOMEM;
 536 +       }
 537 +
 538 +       filp->private_data = fpgadl_dev;
 539 +
 540 +       fpgadl_dev->bitstream_length = 0;
 541 +       fpgadl_dev->bitstream_data = kmalloc(fpgadl_dev->bitstream_max_size,
 542 +                                            GFP_KERNEL);
 543 +       if (!fpgadl_dev->bitstream_data) {
 544 +               FAILMSG("Failed to allocate memory for bitstream");
 545 +               return -ENOMEM;
 546 +       }
 547 +
 548 +       fpgadl_dev->bitstream_buffer_allocated = 1;
 549 +
 550 +       return 0;
 551 +}
 552 +
 553 +/* Write method. Fill buffer with bitstream data. */
 554 +static ssize_t fpgadl_write(struct file *filp, const char __user *buff,
 555 +                           size_t count, loff_t *offp)
 556 +{
 557 +       struct fpgadl_device *fpgadl_dev = filp->private_data;
 558 +
 559 +       if ((fpgadl_dev->bitstream_length + count) >=
 560 +           fpgadl_dev->bitstream_max_size) {
 561 +               FAILMSG("Bitstream buffer size exceeded");
 562 +               return -EFBIG;
 563 +       }
 564 +
 565 +       if (copy_from_user(fpgadl_dev->bitstream_data +
 566 +                          fpgadl_dev->bitstream_length,
 567 +                          (void __user *) buff, count))
 568 +               return -EFAULT;
 569 +
 570 +       fpgadl_dev->bitstream_length += count;
 571 +
 572 +       return count;
 573 +}
 574 +
 575 +/* Release method. This will initiate the FPGA programming. */
 576 +static int fpgadl_release(struct inode *inode, struct file *filp)
 577 +{
 578 +       int retval;
 579 +       struct fpgadl_device *fpgadl_dev = filp->private_data;
 580 +
 581 +       if (!fpgadl_dev->bitstream_data)
 582 +               return -EFAULT;
 583 +
 584 +       retval = fpgadl_bitstream_load(fpgadl_dev,
 585 +                                      fpgadl_dev->bitstream_data,
 586 +                                      fpgadl_dev->bitstream_length);
 587 +       kfree(fpgadl_dev->bitstream_data);
 588 +       fpgadl_dev->bitstream_buffer_allocated = 0;
 589 +
 590 +       return retval;
 591 +}
 592 +
 593 +static struct file_operations fops_fpgadl = {
 594 +       .owner   = THIS_MODULE,
 595 +       .open    = fpgadl_open,
 596 +       .write   = fpgadl_write,
 597 +       .release = fpgadl_release
 598 +};
 599 +
 600 +/* Match fpgadl devices to drivers. Just do a simple name test. */
 601 +static int fpgadl_device_match(struct device *dev,
 602 +                              struct device_driver *drv)
 603 +{
 604 +       DBGMSG_ENTER();
 605 +       return !strncmp(dev->bus_id, drv->name, strlen(drv->name));
 606 +}
 607 +
 608 +static ssize_t show_version(struct device_driver *driver, char *buf)
 609 +{
 610 +       struct fpgadl_driver *fpgadldriver = to_fpgadl_driver(driver);
 611 +
 612 +       sprintf(buf, "%s\n", fpgadldriver->version);
 613 +       return strlen(buf);
 614 +}
 615 +
 616 +int fpgadl_register_driver(struct fpgadl_driver *drv)
 617 +{
 618 +       int res;
 619 +
 620 +       DBGMSG_ENTER();
 621 +
 622 +       /* Initialize common driver fields */
 623 +       drv->driver.bus = &fpgadl_bus_type;
 624 +
 625 +       /* Register with core */
 626 +       res = driver_register(&drv->driver);
 627 +       if (res)
 628 +               FAILMSG("  driver_register() failed");
 629 +
 630 +       drv->version_attr.attr.name = "version";
 631 +       drv->version_attr.attr.owner = drv->module;
 632 +       drv->version_attr.attr.mode = S_IRUGO;
 633 +       drv->version_attr.show = show_version;
 634 +       drv->version_attr.store = NULL;
 635 +       res = driver_create_file(&drv->driver, &drv->version_attr);
 636 +
 637 +       return res;
 638 +}
 639 +EXPORT_SYMBOL(fpgadl_register_driver);
 640 +
 641 +void fpgadl_unregister_driver(struct fpgadl_driver *drv)
 642 +{
 643 +       DBGMSG_ENTER();
 644 +       driver_unregister(&drv->driver);
 645 +}
 646 +EXPORT_SYMBOL(fpgadl_unregister_driver);
 647 +
 648 +/* The fpgadl bus device. */
 649 +static void fpgadl_bus_release(struct device *dev)
 650 +{
 651 +       DBGMSG_ENTER();
 652 +}
 653 +
 654 +struct device fpgadl_bus = {
 655 +       .bus_id   = "fpgadl0",
 656 +       .release  = fpgadl_bus_release
 657 +};
 658 +
 659 +struct bus_type fpgadl_bus_type = {
 660 +       .name = "fpgadl",
 661 +       .match = fpgadl_device_match,
 662 +       .uevent  = fpgadl_uevent,
 663 +};
 664 +EXPORT_SYMBOL(fpgadl_bus_type);
 665 +
 666 +/* Export a simple sysfs attribute. */
 667 +static ssize_t show_bus_version(struct bus_type *bus, char *buf)
 668 +{
 669 +       return snprintf(buf, PAGE_SIZE, "%s\n", fpgadl_driver_version);
 670 +}
 671 +
 672 +static BUS_ATTR(version, S_IRUGO, show_bus_version, NULL);
 673 +
 674 +/*
 675 + * fpgadl devices.
 676 + * For now, no references to fpgadlbus devices go out which are not
 677 + * tracked via the module reference count, so we use a no-op
 678 + * release function.
 679 + */
 680 +static void fpgadl_dev_release(struct device *dev)
 681 +{
 682 +       DBGMSG_ENTER();
 683 +}
 684 +
 685 +/* Release DaVinci GPIO to FPGA control pins. */
 686 +static void fpgadl_release_gpio(struct fpgadl_pdata_t *pdata)
 687 +{
 688 +       gpio_free(pdata->done);
 689 +       gpio_free(pdata->init_b);
 690 +       gpio_free(pdata->program_b);
 691 +}
 692 +
 693 +static int fpgadl_setup_gpio(struct fpgadl_pdata_t *pdata)
 694 +{
 695 +       int retval;
 696 +
 697 +       /* Configure FPGA PROGRAM_B GPIO. */
 698 +       retval = gpio_request(pdata->program_b, "fpga_program_b");
 699 +       if (retval == 0) /* FPGA_PROGRAM_B must be initially HIGH. */
 700 +               retval = gpio_direction_output(pdata->program_b, 1);
 701 +       if (retval != 0)
 702 +               goto gpio_error;
 703 +
 704 +       /* Configure FPGA INIT_B GPIO. */
 705 +       retval = gpio_request(pdata->init_b, "fpga_init_b");
 706 +       if (retval == 0)
 707 +               retval = gpio_direction_input(pdata->init_b);
 708 +       if (retval != 0)
 709 +               goto gpio_error;
 710 +
 711 +       /* Configure FPGA DONE GPIO. */
 712 +       retval = gpio_request(pdata->done, "fpga_done");
 713 +       if (retval == 0)
 714 +               retval = gpio_direction_input(pdata->done);
 715 +       if (retval != 0)
 716 +               goto gpio_error;
 717 +
 718 +       return 0;
 719 +
 720 +gpio_error:
 721 +       fpgadl_release_gpio(pdata);
 722 +       return retval;
 723 +}
 724 +
 725 +static void fpgadl_cleanup(struct fpgadl_device *fpgadl_dev)
 726 +{
 727 +       DBGMSG_ENTER();
 728 +
 729 +       if (!fpgadl_dev)
 730 +               return;
 731 +
 732 +       fpgadl_dev_array[fpgadl_dev->id] = NULL;
 733 +
 734 +       /* Get rid of any allocated buffer, not freed */
 735 +       if (fpgadl_dev->bitstream_buffer_allocated)
 736 +               kfree(fpgadl_dev->bitstream_data);
 737 +
 738 +       switch (fpgadl_dev->state) {
 739 +       case FPGADL_DEV_STATE_CHAR_DEV_REGISTERED:
 740 +               misc_deregister(&fpgadl_dev->miscdev);
 741 +       case FPGADL_DEV_STATE_GPIO_REGISTERED:
 742 +               fpgadl_release_gpio(fpgadl_dev->pdata);
 743 +       case FPGADL_DEV_STATE_DEVICE_REGISTERED:
 744 +               device_unregister(&fpgadl_dev->dev);
 745 +       case FPGADL_DEV_STATE_START:
 746 +               break;
 747 +       }
 748 +}
 749 +
 750 +int fpgadl_register_device(struct fpgadl_device *fpgadl_dev)
 751 +{
 752 +       int res;
 753 +       const struct firmware *fw_entry;
 754 +
 755 +       DBGMSG_ENTER();
 756 +
 757 +       fpgadl_dev->state = FPGADL_DEV_STATE_START;
 758 +
 759 +       /* Sanity checks. */
 760 +       if (!fpgadl_dev->name) {
 761 +               FAILMSG("  Error, missing device name");
 762 +               res = -EFAULT;
 763 +               goto error;
 764 +       }
 765 +
 766 +       if (!fpgadl_dev->write_byte) {
 767 +               FAILMSG("  Error, missing write_byte() callback");
 768 +               res = -ENOMEM;
 769 +               goto error;
 770 +       }
 771 +
 772 +       if (fpgadl_dev_count == MAX_FPGADL_DEV) {
 773 +               FAILMSG("Maximum number of devices reached (%d)",
 774 +                       fpgadl_dev_count);
 775 +               res = -ENODEV;
 776 +               goto error;
 777 +       }
 778 +
 779 +       DBGMSG("  device %d", fpgadl_dev_count);
 780 +
 781 +       /* Set some default values. */
 782 +       fpgadl_dev->bitstream_loaded = 0;
 783 +       fpgadl_dev->bitstream_buffer_allocated = 0;
 784 +       fpgadl_dev->bitstream_max_size =
 785 +               fpgadl_dev->pdata->payload_full_size +
 786 +               BITSTREAM_MAX_SIZE_OVERHEAD;
 787 +
 788 +       fpgadl_dev->dev.bus = &fpgadl_bus_type;
 789 +       fpgadl_dev->dev.parent = &fpgadl_bus;
 790 +       fpgadl_dev->dev.release = fpgadl_dev_release;
 791 +       strncpy(fpgadl_dev->dev.bus_id, fpgadl_dev->name, BUS_ID_SIZE);
 792 +       res = device_register(&fpgadl_dev->dev);
 793 +       if (res) {
 794 +               FAILMSG("  device_register() failed");
 795 +               goto error;
 796 +       }
 797 +       fpgadl_dev->state = FPGADL_DEV_STATE_DEVICE_REGISTERED;
 798 +
 799 +       res = fpgadl_setup_gpio(fpgadl_dev->pdata);
 800 +       if (res < 0) {
 801 +               FAILMSG("Error registering GPIOs");
 802 +               goto error;
 803 +       }
 804 +       fpgadl_dev->state = FPGADL_DEV_STATE_GPIO_REGISTERED;
 805 +
 806 +       fpgadl_dev->miscdev.name = fpgadl_dev->name;
 807 +       fpgadl_dev->miscdev.minor = MISC_DYNAMIC_MINOR;
 808 +       fpgadl_dev->miscdev.fops = &fops_fpgadl;
 809 +       res = misc_register(&fpgadl_dev->miscdev);
 810 +       if (res < 0) {
 811 +               FAILMSG("Error registering misc driver");
 812 +               goto error;
 813 +       }
 814 +       DBGMSG("  MINOR = %d", fpgadl_dev->miscdev.minor);
 815 +       fpgadl_dev->state = FPGADL_DEV_STATE_CHAR_DEV_REGISTERED;
 816 +
 817 +       /* Try to load firmware through hotplug if available. */
 818 +       res = request_firmware(&fw_entry, fpgadl_dev->pdata->bitstream_name,
 819 +                              &fpgadl_dev->dev);
 820 +       if (res < 0) {
 821 +               /* Not an error preventing the driver from being loaded. */
 822 +               res = 0;
 823 +               DBGMSG("Info: firmware not available");
 824 +       } else {
 825 +               res = fpgadl_bitstream_load(fpgadl_dev, fw_entry->data,
 826 +                                           fw_entry->size);
 827 +               release_firmware(fw_entry);
 828 +       }
 829 +
 830 +       fpgadl_dev->id = fpgadl_dev_count;
 831 +       fpgadl_dev_array[fpgadl_dev_count] = fpgadl_dev;
 832 +       fpgadl_dev_count++;
 833 +
 834 +       return 0;
 835 +
 836 +error:
 837 +       fpgadl_cleanup(fpgadl_dev);
 838 +       return res;
 839 +}
 840 +EXPORT_SYMBOL(fpgadl_register_device);
 841 +
 842 +void fpgadl_unregister_device(struct fpgadl_device *fpgadl_dev)
 843 +{
 844 +       DBGMSG_ENTER();
 845 +       fpgadl_cleanup(fpgadl_dev);
 846 +}
 847 +EXPORT_SYMBOL(fpgadl_unregister_device);
 848 +
 849 +static int __init fpgadl_init(void)
 850 +{
 851 +       int res;
 852 +
 853 +       DBGMSG_ENTER();
 854 +       INFOMSG("FPGA bitstream loader %s", fpgadl_driver_version);
 855 +
 856 +       res = bus_register(&fpgadl_bus_type);
 857 +       if (res) {
 858 +               FAILMSG("  bus_register() failed");
 859 +               goto fail_bus;
 860 +       }
 861 +
 862 +       if (bus_create_file(&fpgadl_bus_type, &bus_attr_version)) {
 863 +               FAILMSG("Unable to create version attribute");
 864 +               goto fail_create_file;
 865 +       }
 866 +
 867 +       res = device_register(&fpgadl_bus);
 868 +       if (res) {
 869 +               FAILMSG("  failed registering %s", fpgadl_bus.bus_id);
 870 +               goto fail_dev_reg;
 871 +       }
 872 +
 873 +       return 0;
 874 +
 875 +fail_dev_reg:
 876 +fail_create_file:
 877 +       bus_unregister(&fpgadl_bus_type);
 878 +fail_bus:
 879 +       return res;
 880 +}
 881 +module_init(fpgadl_init);
 882 +
 883 +static void __exit fpgadl_exit(void)
 884 +{
 885 +       DBGMSG_ENTER();
 886 +       device_unregister(&fpgadl_bus);
 887 +       bus_unregister(&fpgadl_bus_type);
 888 +}
 889 +module_exit(fpgadl_exit);
 890 +
 891 +MODULE_AUTHOR("Hugo Villeneuve <hvilleneuve@lyrtech.com>");
 892 +MODULE_DESCRIPTION("FPGA bitstream loader");
 893 +MODULE_LICENSE("GPL");
 894 diff --git a/drivers/misc/fpgadl_par.c b/drivers/misc/fpgadl_par.c
 895 new file mode 100644
 896 index 0000000..66f8eba
 897 --- /dev/null
 898 +++ b/drivers/misc/fpgadl_par.c
 899 @@ -0,0 +1,258 @@
 900 +/*
 901 + * fpgadl_par.c - FPGA parallel programming driver
 902 + *
 903 + * Copyright (C) 2008 Lyrtech <www.lyrtech.com>
 904 + *
 905 + * This program is free software; you can redistribute it and/or modify
 906 + * it under the terms of the GNU General Public License as published by
 907 + * the Free Software Foundation; either version 2 of the License, or
 908 + * (at your option) any later version.
 909 + *
 910 + * This program is distributed in the hope that it will be useful,
 911 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
 912 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 913 + * GNU General Public License for more details.
 914 + *
 915 + * You should have received a copy of the GNU General Public License
 916 + * along with this program; if not, write to the Free Software
 917 + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 918 + */
 919 +
 920 +#include <linux/kernel.h>
 921 +#include <linux/module.h>
 922 +#include <linux/moduleparam.h>
 923 +#include <linux/init.h>
 924 +#include <linux/device.h>
 925 +#include <linux/platform_device.h>
 926 +#include <linux/string.h>
 927 +#include <linux/err.h>
 928 +#include <linux/fs.h>
 929 +#include <linux/delay.h>
 930 +#include <linux/bitrev.h>
 931 +#include <linux/fpgadl.h>
 932 +
 933 +#include <asm/gpio.h> /* For ioremap() */
 934 +
 935 +#define MODULE_NAME "fpgadl_par"
 936 +#define MODULE_VERSION_STR "v1.0"
 937 +
 938 +/* Define this to enable verbose debug messages */
 939 +#define FPGADL_PAR_DEBUG 1
 940 +
 941 +/* Module parameters */
 942 +static unsigned int fpgadl_par_debug;
 943 +EXPORT_SYMBOL_GPL(fpgadl_par_debug);
 944 +module_param_named(debug, fpgadl_par_debug, int, 0644);
 945 +
 946 +#ifdef FPGADL_PAR_DEBUG
 947 +#define INFOMSG(fmt, args...) \
 948 +do { \
 949 +  printk(KERN_INFO "%s: "fmt"\n", MODULE_NAME, ## args); } while (0)
 950 +#define DBGMSG(fmt, args...) \
 951 +do { if (fpgadl_par_debug > 0) \
 952 +  printk(KERN_DEBUG "%s: "fmt"\n", MODULE_NAME, ## args); } while (0)
 953 +#define DBGMSG_ENTER() \
 954 +  DBGMSG("%s() enter", __func__);
 955 +#define DBGMSG_LEAVE() \
 956 +  DBGMSG("%s() leave", __func__);
 957 +#else
 958 +#define INFOMSG(fmt, args...) do {} while (0)
 959 +#define DBGMSG(fmt, args...) do {} while (0)
 960 +#define DBGMSG_ENTER() do {} while (0)
 961 +#define DBGMSG_LEAVE() do {} while (0)
 962 +#endif
 963 +
 964 +#define FAILMSG(fmt, args...) \
 965 +do { \
 966 +  printk(KERN_ERR "%s: "fmt"\n", MODULE_NAME, ## args); } while (0)
 967 +
 968 +struct fpgadl_par_dev_t {
 969 +       char devname[32];
 970 +       enum {
 971 +               FPGADL_PAR_DEV_STATE_STRUCT_ALLOCATED,
 972 +               FPGADL_PAR_DEV_STATE_HAVE_IOREMAP,
 973 +               FPGADL_PAR_DEV_STATE_FPGADL_DEV_REGISTERED,
 974 +       } state;
 975 +       u8 *selectmap;
 976 +       struct fpgadl_device fpgadl_dev;
 977 +};
 978 +
 979 +#define MAX_FPGADL_PAR_DEV 5
 980 +
 981 +static int fpgadl_par_dev_count;
 982 +
 983 +/*
 984 + * Writes a byte of data to the FPGA using the SelectMAP
 985 + * interface. The FPGA_SELECT_MAP_REG address is within
 986 + * the FPGA address space (CS3), and when we write a byte
 987 + * to that address, the CCLK line will be toggled.
 988 + */
 989 +static int selectmap_write_byte(struct fpgadl_device *fpgadl_dev,
 990 +                               u8 *data, int size)
 991 +{
 992 +       int k;
 993 +       struct fpgadl_par_dev_t *fpgadl_par_dev;
 994 +
 995 +       fpgadl_par_dev = (struct fpgadl_par_dev_t *) fpgadl_dev->devdata;
 996 +
 997 +       for (k = 0; k < size; k++)
 998 +               fpgadl_par_dev->selectmap[0] = bitrev8(data[k]);
 999 +
1000 +       return 0;
1001 +}
1002 +
1003 +static void fpgadl_par_cleanup(struct fpgadl_par_dev_t *dev)
1004 +{
1005 +       DBGMSG("fpgadl_par_cleanup");
1006 +
1007 +       if (!dev)
1008 +               return;
1009 +
1010 +       switch (dev->state) {
1011 +       case FPGADL_PAR_DEV_STATE_FPGADL_DEV_REGISTERED:
1012 +               fpgadl_unregister_device(&dev->fpgadl_dev);
1013 +       case FPGADL_PAR_DEV_STATE_HAVE_IOREMAP:
1014 +               iounmap(dev->selectmap);
1015 +       case FPGADL_PAR_DEV_STATE_STRUCT_ALLOCATED:
1016 +               kfree(dev);
1017 +               break;
1018 +       }
1019 +}
1020 +
1021 +static int __devinit fpgadl_par_probe(struct platform_device *pdev)
1022 +{
1023 +       int len;
1024 +       int res;
1025 +       struct fpgadl_par_dev_t *dev = NULL;
1026 +       const struct resource *selectmap_res;
1027 +
1028 +       DBGMSG("fpgadl_par_probe()");
1029 +
1030 +       if (fpgadl_par_dev_count == MAX_FPGADL_PAR_DEV) {
1031 +               FAILMSG("Maximum number of devices reached (%d)",
1032 +                       fpgadl_par_dev_count);
1033 +               res = -ENODEV;
1034 +               goto error;
1035 +       }
1036 +
1037 +       DBGMSG("  device %d", fpgadl_par_dev_count);
1038 +
1039 +       dev = kzalloc(sizeof(*dev), GFP_KERNEL);
1040 +       if (!dev) {
1041 +               FAILMSG("Failed to allocate device structure");
1042 +               res = -ENOMEM;
1043 +               goto error;
1044 +       }
1045 +       /* Set some default values. */
1046 +       dev->state = FPGADL_PAR_DEV_STATE_STRUCT_ALLOCATED;
1047 +
1048 +       if (!pdev->dev.platform_data) {
1049 +               FAILMSG("Error getting platform data");
1050 +               res = -ENODEV;
1051 +               goto error;
1052 +       }
1053 +       dev->fpgadl_dev.pdata = pdev->dev.platform_data;
1054 +       pdev->dev.driver_data = dev; /* Private driver data */
1055 +
1056 +       /* Assign virtual addresses to SELECTMAP I/O memory regions. */
1057 +       selectmap_res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
1058 +                                                    "selectmap");
1059 +       if (!selectmap_res) {
1060 +               FAILMSG("Error getting selectmap ressource");
1061 +               res = -ENODEV;
1062 +               goto error;
1063 +       }
1064 +       len = selectmap_res->end - selectmap_res->start;
1065 +       dev->selectmap = ioremap(selectmap_res->start, len);
1066 +       if (!dev->selectmap) {
1067 +               FAILMSG("Can't remap selectmap register");
1068 +               res = -ENXIO;
1069 +               goto error;
1070 +       }
1071 +       dev->state = FPGADL_PAR_DEV_STATE_HAVE_IOREMAP;
1072 +
1073 +       dev->fpgadl_dev.write_byte = selectmap_write_byte;
1074 +       sprintf(dev->devname, "fpgadl_par%d", fpgadl_par_dev_count);
1075 +       DBGMSG("  NAME = %s", dev->devname);
1076 +       dev->fpgadl_dev.name = dev->devname;
1077 +       dev->fpgadl_dev.devdata = dev; /* For our write_byte() callback */
1078 +       res = fpgadl_register_device(&dev->fpgadl_dev);
1079 +       if (res < 0) {
1080 +               FAILMSG("Error registering fpgadl_par device");
1081 +               goto error;
1082 +       }
1083 +       dev->state = FPGADL_PAR_DEV_STATE_FPGADL_DEV_REGISTERED;
1084 +
1085 +       fpgadl_par_dev_count++;
1086 +
1087 +       return 0;
1088 +
1089 +error:
1090 +       fpgadl_par_cleanup(dev);
1091 +       return res;
1092 +}
1093 +
1094 +static int __devexit fpgadl_par_remove(struct platform_device *pdev)
1095 +{
1096 +       struct fpgadl_par_dev_t *dev = platform_get_drvdata(pdev);
1097 +
1098 +       DBGMSG("fpgadl_par_remove()");
1099 +
1100 +       fpgadl_par_cleanup(dev);
1101 +
1102 +       return 0;
1103 +}
1104 +
1105 +static struct fpgadl_driver fpgadl_par_driver = {
1106 +       .version = MODULE_VERSION_STR,
1107 +       .module  = THIS_MODULE,
1108 +       .driver = {
1109 +               .name = "fpgadl_par",
1110 +       },
1111 +};
1112 +
1113 +static struct platform_driver fpgadl_platform_driver = {
1114 +       .driver         = {
1115 +               .name   = MODULE_NAME,
1116 +               .owner  = THIS_MODULE,
1117 +       },
1118 +       .remove = fpgadl_par_remove,
1119 +};
1120 +
1121 +static int __init fpgadl_par_init(void)
1122 +{
1123 +       int res;
1124 +
1125 +       DBGMSG("fpgadl_par_init()");
1126 +
1127 +       /* Register with the driver core. */
1128 +       res = fpgadl_register_driver(&fpgadl_par_driver);
1129 +       if (res) {
1130 +               FAILMSG("Can't register fpgadl parallel driver");
1131 +               return res;
1132 +       }
1133 +
1134 +       /* The probe function will be called for each platform device declared
1135 +        * in board setup code. */
1136 +       res = platform_driver_probe(&fpgadl_platform_driver,
1137 +                                   fpgadl_par_probe);
1138 +       if (res) {
1139 +               FAILMSG("platform_driver_probe() failed");
1140 +               return res;
1141 +       }
1142 +
1143 +       return 0;
1144 +}
1145 +module_init(fpgadl_par_init);
1146 +
1147 +static void __exit fpgadl_par_exit(void)
1148 +{
1149 +       DBGMSG("fpgadl_par_exit()");
1150 +       platform_driver_unregister(&fpgadl_platform_driver);
1151 +       fpgadl_unregister_driver(&fpgadl_par_driver);
1152 +}
1153 +module_exit(fpgadl_par_exit);
1154 +
1155 +MODULE_AUTHOR("Hugo Villeneuve <hvilleneuve@lyrtech.com>");
1156 +MODULE_DESCRIPTION("FPGA parallel programming driver");
1157 +MODULE_LICENSE("GPL");
1158 diff --git a/drivers/misc/fpgadl_ser.c b/drivers/misc/fpgadl_ser.c
1159 new file mode 100644
1160 index 0000000..01ca5e0
1161 --- /dev/null
1162 +++ b/drivers/misc/fpgadl_ser.c
1163 @@ -0,0 +1,244 @@
1164 +/*
1165 + * fpgadl_ser.c - FPGA serial programming driver
1166 + *
1167 + * Copyright (C) 2008 Lyrtech <www.lyrtech.com>
1168 + *
1169 + * Based on SH SCI SPI interface
1170 + *   Copyright (c) 2008 Magnus Damm
1171 + *
1172 + * This program is free software; you can redistribute it and/or modify
1173 + * it under the terms of the GNU General Public License as published by
1174 + * the Free Software Foundation; either version 2 of the License, or
1175 + * (at your option) any later version.
1176 + *
1177 + * This program is distributed in the hope that it will be useful,
1178 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
1179 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
1180 + * GNU General Public License for more details.
1181 + *
1182 + * You should have received a copy of the GNU General Public License
1183 + * along with this program; if not, write to the Free Software
1184 + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
1185 + */
1186 +
1187 +#include <linux/kernel.h>
1188 +#include <linux/module.h>
1189 +#include <linux/moduleparam.h>
1190 +#include <linux/init.h>
1191 +#include <linux/device.h>
1192 +#include <linux/platform_device.h>
1193 +#include <linux/spi/spi.h>
1194 +#include <linux/fpgadl.h>
1195 +
1196 +#define MODULE_NAME "fpgadl_ser"
1197 +#define MODULE_VERSION_STR "v1.0"
1198 +
1199 +/* Define this to enable verbose debug messages */
1200 +#define FPGADL_SER_DEBUG 1
1201 +
1202 +/* Module parameters */
1203 +static unsigned int fpgadl_ser_debug;
1204 +EXPORT_SYMBOL_GPL(fpgadl_ser_debug);
1205 +module_param_named(debug, fpgadl_ser_debug, int, 0644);
1206 +
1207 +#ifdef FPGADL_SER_DEBUG
1208 +#define INFOMSG(fmt, args...) \
1209 +do { \
1210 +  printk(KERN_INFO "%s: "fmt"\n", MODULE_NAME, ## args); } while (0)
1211 +#define DBGMSG(fmt, args...) \
1212 +do { if (fpgadl_ser_debug > 0) \
1213 +  printk(KERN_DEBUG "%s: "fmt"\n", MODULE_NAME, ## args); } while (0)
1214 +#define DBGMSG_ENTER() \
1215 +  DBGMSG("%s() enter", __func__);
1216 +#define DBGMSG_LEAVE() \
1217 +  DBGMSG("%s() leave", __func__);
1218 +#else
1219 +#define INFOMSG(fmt, args...) do {} while (0)
1220 +#define DBGMSG(fmt, args...) do {} while (0)
1221 +#define DBGMSG_ENTER() do {} while (0)
1222 +#define DBGMSG_LEAVE() do {} while (0)
1223 +#endif
1224 +
1225 +#define FAILMSG(fmt, args...) \
1226 +do { \
1227 +  printk(KERN_ERR "%s: "fmt"\n", MODULE_NAME, ## args); } while (0)
1228 +
1229 +struct fpgadl_ser_dev_t {
1230 +       char devname[32];
1231 +       enum {
1232 +               FPGADL_SER_DEV_STATE_STRUCT_ALLOCATED,
1233 +               FPGADL_SER_DEV_STATE_SPI_SETUP,
1234 +               FPGADL_SER_DEV_STATE_FPGADL_DEV_REGISTERED,
1235 +       } state;
1236 +       struct spi_transfer t;
1237 +       struct spi_message m;
1238 +       struct spi_device *spi;
1239 +       struct fpgadl_device fpgadl_dev;
1240 +};
1241 +
1242 +#define MAX_FPGADL_SER_DEV 5
1243 +
1244 +static int fpgadl_ser_dev_count;
1245 +
1246 +static int fpgadl_ser_write_byte(struct fpgadl_device *fpgadl_dev,
1247 +                                  u8 *data, int size)
1248 +{
1249 +       int status;
1250 +       struct fpgadl_ser_dev_t *fpgadl_ser_dev;
1251 +
1252 +       fpgadl_ser_dev = (struct fpgadl_ser_dev_t *) fpgadl_dev->devdata;
1253 +
1254 +       if (!data) {
1255 +               FAILMSG("NULL data pointer");
1256 +               return -EFAULT;
1257 +       }
1258 +
1259 +       spi_message_init(&fpgadl_ser_dev->m);
1260 +       fpgadl_ser_dev->t.tx_buf = data;
1261 +       fpgadl_ser_dev->t.len = size;
1262 +       spi_message_add_tail(&fpgadl_ser_dev->t, &fpgadl_ser_dev->m);
1263 +
1264 +       status = spi_sync(fpgadl_ser_dev->spi, &fpgadl_ser_dev->m);
1265 +       if (status < 0)
1266 +               FAILMSG("spi_sync() failed (%d)", status);
1267 +
1268 +       return status;
1269 +}
1270 +
1271 +static void fpgadl_ser_cleanup(struct fpgadl_ser_dev_t *dev)
1272 +{
1273 +       DBGMSG_ENTER();
1274 +
1275 +       if (!dev)
1276 +               return;
1277 +
1278 +       switch (dev->state) {
1279 +       case FPGADL_SER_DEV_STATE_FPGADL_DEV_REGISTERED:
1280 +               fpgadl_unregister_device(&dev->fpgadl_dev);
1281 +       case FPGADL_SER_DEV_STATE_SPI_SETUP:
1282 +       case FPGADL_SER_DEV_STATE_STRUCT_ALLOCATED:
1283 +               kfree(dev);
1284 +               break;
1285 +       }
1286 +}
1287 +
1288 +static int __devinit fpgadl_ser_probe(struct spi_device *spi)
1289 +{
1290 +       int res;
1291 +       struct fpgadl_ser_dev_t *dev = NULL;
1292 +
1293 +       DBGMSG_ENTER();
1294 +
1295 +       if (fpgadl_ser_dev_count == MAX_FPGADL_SER_DEV) {
1296 +               FAILMSG("Maximum number of devices reached (%d)",
1297 +                       fpgadl_ser_dev_count);
1298 +               res = -ENODEV;
1299 +               goto error;
1300 +       }
1301 +
1302 +       DBGMSG("  device %d", fpgadl_ser_dev_count);
1303 +
1304 +       dev = kzalloc(sizeof(*dev), GFP_KERNEL);
1305 +       if (!dev) {
1306 +               FAILMSG("Failed to allocate device structure");
1307 +               res = -ENOMEM;
1308 +               goto error;
1309 +       }
1310 +       /* Set some default values. */
1311 +       dev->state = FPGADL_SER_DEV_STATE_STRUCT_ALLOCATED;
1312 +
1313 +       DBGMSG("  SPI mode = %d", spi->mode);
1314 +
1315 +       if (!spi->dev.platform_data) {
1316 +               FAILMSG("Error getting platform data");
1317 +               res = -ENODEV;
1318 +               goto error;
1319 +       }
1320 +       dev->fpgadl_dev.pdata = spi->dev.platform_data;
1321 +       spi->dev.driver_data = dev; /* Private driver data */
1322 +
1323 +       spi->bits_per_word = 8; /* Size of Tx and Rx transfers. */
1324 +       res = spi_setup(spi);
1325 +       if (res < 0) {
1326 +               FAILMSG("Error setting-up SPI");
1327 +               goto error;
1328 +       }
1329 +       dev->spi = spi;
1330 +       dev->state = FPGADL_SER_DEV_STATE_SPI_SETUP;
1331 +
1332 +       dev->fpgadl_dev.write_byte = fpgadl_ser_write_byte;
1333 +       sprintf(dev->devname, "fpgadl_ser%d", fpgadl_ser_dev_count);
1334 +       DBGMSG("  NAME = %s", dev->devname);
1335 +       dev->fpgadl_dev.name = dev->devname;
1336 +       dev->fpgadl_dev.devdata = dev; /* For our write_byte() callback */
1337 +       res = fpgadl_register_device(&dev->fpgadl_dev);
1338 +       if (res < 0) {
1339 +               FAILMSG("Error registering fpgadl_ser device");
1340 +               goto error;
1341 +       }
1342 +       dev->state = FPGADL_SER_DEV_STATE_FPGADL_DEV_REGISTERED;
1343 +
1344 +       fpgadl_ser_dev_count++;
1345 +
1346 +       return 0;
1347 +
1348 +error:
1349 +       fpgadl_ser_cleanup(dev);
1350 +       return res;
1351 +}
1352 +
1353 +static int __devexit fpgadl_ser_remove(struct spi_device *spi)
1354 +{
1355 +       struct fpgadl_ser_dev_t *dev = spi_get_drvdata(spi);
1356 +
1357 +       DBGMSG_ENTER();
1358 +       fpgadl_ser_cleanup(dev);
1359 +       return 0;
1360 +}
1361 +
1362 +static struct spi_driver fpgadl_ser_spi_driver = {
1363 +       .driver = {
1364 +               .name   = MODULE_NAME,
1365 +               .bus    = &spi_bus_type,
1366 +               .owner  = THIS_MODULE,
1367 +       },
1368 +       .probe          = fpgadl_ser_probe,
1369 +       .remove         = fpgadl_ser_remove,
1370 +};
1371 +
1372 +static struct fpgadl_driver fpgadl_ser_driver = {
1373 +       .version = MODULE_VERSION_STR,
1374 +       .module  = THIS_MODULE,
1375 +       .driver = {
1376 +               .name = "fpgadl_ser",
1377 +       },
1378 +};
1379 +
1380 +static int __init fpgadl_ser_init(void)
1381 +{
1382 +       int res;
1383 +
1384 +       DBGMSG_ENTER();
1385 +
1386 +       /* Register with the driver core. */
1387 +       res = fpgadl_register_driver(&fpgadl_ser_driver);
1388 +       if (res) {
1389 +               FAILMSG("Can't register fpgadl serial driver");
1390 +               return res;
1391 +       }
1392 +
1393 +       return spi_register_driver(&fpgadl_ser_spi_driver);
1394 +}
1395 +module_init(fpgadl_ser_init);
1396 +
1397 +static void __exit fpgadl_ser_exit(void)
1398 +{
1399 +       DBGMSG_ENTER();
1400 +       spi_unregister_driver(&fpgadl_ser_spi_driver);
1401 +       fpgadl_unregister_driver(&fpgadl_ser_driver);
1402 +}
1403 +module_exit(fpgadl_ser_exit);
1404 +
1405 +MODULE_DESCRIPTION("FPGA serial programming driver");
1406 +MODULE_AUTHOR("Hugo Villeneuve");
1407 +MODULE_LICENSE("GPL");
1408 diff --git a/include/linux/fpgadl.h b/include/linux/fpgadl.h
1409 new file mode 100644
1410 index 0000000..27d83f1
1411 --- /dev/null
1412 +++ b/include/linux/fpgadl.h
1413 @@ -0,0 +1,96 @@
1414 +/*
1415 + * FPGA bitstream load header file.
1416 + *
1417 + * Copyright (C) 2008 Lyrtech <www.lyrtech.com>
1418 + *
1419 + * This program is free software; you can redistribute it and/or modify
1420 + * it under the terms of the GNU General Public License as published by
1421 + * the Free Software Foundation; either version 2 of the License, or
1422 + * (at your option) any later version.
1423 + *
1424 + * This program is distributed in the hope that it will be useful,
1425 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
1426 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
1427 + * GNU General Public License for more details.
1428 + *
1429 + * You should have received a copy of the GNU General Public License
1430 + * along with this program; if not, write to the Free Software
1431 + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
1432 + */
1433 +
1434 +#ifndef FPGADL_H
1435 +#define FPGADL_H 1
1436 +
1437 +#include <linux/miscdevice.h>
1438 +
1439 +/* FPGA device-specific informations and functions. */
1440 +struct fpgadl_pdata_t {
1441 +       enum {
1442 +               FPGA_VENDOR_XILINX,
1443 +               FPGA_VENDOR_ALTERA,
1444 +       } fpga_vendor;
1445 +       enum {
1446 +               FPGA_FAMILY_XILINX_XC3S,
1447 +               FPGA_FAMILY_XILINX_XC4V,
1448 +       } fpga_family;
1449 +       ssize_t payload_full_size;
1450 +       u8 program_b;
1451 +       u8 init_b;
1452 +       u8 done;
1453 +       char *bitstream_name;
1454 +       int check_init_low; /* Set to 1 to check that the INIT pin is low during
1455 +                            * programming. Normally, we should check if INIT_B
1456 +                            * is low during configuration, indicating a
1457 +                            * configuration error. But this may cause problems
1458 +                            * for bitstreams where the INIT_B pin is used as a
1459 +                            * GPIO after configuration. */
1460 +};
1461 +
1462 +struct fpgadl_driver {
1463 +       char *version;
1464 +       struct module *module;
1465 +       struct device_driver driver;
1466 +       struct driver_attribute version_attr;
1467 +};
1468 +
1469 +struct fpgadl_device {
1470 +       int id;
1471 +       char *name;
1472 +       enum {
1473 +               FPGADL_DEV_STATE_START,
1474 +               FPGADL_DEV_STATE_DEVICE_REGISTERED,
1475 +               FPGADL_DEV_STATE_GPIO_REGISTERED,
1476 +               FPGADL_DEV_STATE_CHAR_DEV_REGISTERED,
1477 +       } state;
1478 +       int bitstream_buffer_allocated;
1479 +       u8 *bitstream_data;
1480 +       size_t bitstream_length;
1481 +       size_t bitstream_max_size;
1482 +       int bitstream_mode;
1483 +       int bitstream_loaded;
1484 +       int (*write_byte)(struct fpgadl_device *, u8 *, int);
1485 +       void *devdata; /* Pointer to interface-specific (SPI/PAR) device */
1486 +       struct miscdevice miscdev;
1487 +       struct fpgadl_driver *driver;
1488 +       struct fpgadl_pdata_t *pdata;
1489 +       struct device dev;
1490 +};
1491 +
1492 +/* Bitstream types. */
1493 +#define BITSTREAM_MODE_UNKNOWN 0
1494 +#define BITSTREAM_MODE_FULL    1
1495 +#define BITSTREAM_MODE_PARTIAL 2
1496 +
1497 +extern struct bus_type fpgadl_bus_type;
1498 +
1499 +#define to_fpgadl_driver(drv) container_of(drv, struct fpgadl_driver, driver);
1500 +
1501 +extern int fpgadl_register_driver(struct fpgadl_driver *drv);
1502 +extern void fpgadl_unregister_driver(struct fpgadl_driver *drv);
1503 +
1504 +extern int fpgadl_register_device(struct fpgadl_device *fpgadldev);
1505 +extern void fpgadl_unregister_device(struct fpgadl_device *fpgadldev);
1506 +
1507 +int fpgadl_is_bitstream_loaded(const char *name);
1508 +
1509 +#endif /* FPGADL_H */
1510 --
1511 1.5.4.5
1512