0d5a047cb58022600e39d53ad5e599f832ffb6fc
[openembedded.git] /
1 From 00cd18c8b6bd6b7f6c627d2b1284ca8f98f1fda4 Mon Sep 17 00:00:00 2001
2 From: Sergio Aguirre <saaguirre@ti.com>
3 Date: Thu, 15 Jul 2010 23:43:20 -0500
4 Subject: [PATCH 62/75] omap3beagle: camera: Prepare 24MHz xclk for mt9t112
5
6 Adjust calculations of timings based on # of EXTCLK cycles.
7
8 Also, set default requested framerate to 30 fps.
9
10 Signed-off-by: Sergio Aguirre <saaguirre@ti.com>
11 ---
12  arch/arm/mach-omap2/board-omap3beagle-camera.c |   16 ++++++++--------
13  1 files changed, 8 insertions(+), 8 deletions(-)
14
15 diff --git a/arch/arm/mach-omap2/board-omap3beagle-camera.c b/arch/arm/mach-omap2/board-omap3beagle-camera.c
16 index 75622bf..520e1d8 100644
17 --- a/arch/arm/mach-omap2/board-omap3beagle-camera.c
18 +++ b/arch/arm/mach-omap2/board-omap3beagle-camera.c
19 @@ -264,7 +264,7 @@ static struct omap34xxcam_hw_config mt9t112_hwc = {
20         .dev_type               = OMAP34XXCAM_SLAVE_SENSOR,
21         .u.sensor.sensor_isp    = 0,
22         .u.sensor.capture_mem   = MT9T112_BIGGEST_FRAME_BYTE_SIZE,
23 -       .u.sensor.ival_default  = { 1, 10 },
24 +       .u.sensor.ival_default  = { 1, 30 },
25  };
26  #endif
27  
28 @@ -331,24 +331,24 @@ static int mt9t112_power_set(struct v4l2_int_device *s, enum v4l2_power power)
29                 mdelay(50);
30  
31                 /* Enable EXTCLK */
32 -               isp_set_xclk(vdev->cam->isp, MT9T112_CLK_MIN, CAM_USE_XCLKA);
33 +               isp_set_xclk(vdev->cam->isp, 24000000, CAM_USE_XCLKA);
34  
35                 /*
36 -                * Wait at least 70 CLK cycles (w/EXTCLK = 6MHz, or CLK_MIN):
37 -                * ((1000000 * 70) / 6000000) = aprox 12 us.
38 +                * Wait at least 70 CLK cycles (w/EXTCLK = 24MHz):
39 +                * ((1000000 * 70) / 24000000) = aprox 2.91 us.
40                  */
41  
42 -               udelay(12);
43 +               udelay(3);
44  
45                 /* Set RESET_BAR to 1 */
46                 gpio_set_value(LEOPARD_RESET_GPIO, 1);
47  
48                 /*
49 -                * Wait at least 100 CLK cycles (w/EXTCLK = 6MHz, or CLK_MIN):
50 -                * ((1000000 * 100) / 6000000) = aprox 17 us.
51 +                * Wait at least 100 CLK cycles (w/EXTCLK = 24MHz):
52 +                * ((1000000 * 100) / 24000000) = aprox 4.16 us.
53                  */
54  
55 -               udelay(17);
56 +               udelay(5);
57  
58                 break;
59  
60 -- 
61 1.6.6.1
62