packages/linux/linux-ezx-2.6.21/patches/pxa27x-udc-support.2.patch

   1 diff --git a/drivers/usb/gadget/Kconfig b/drivers/usb/gadget/Kconfig
   2 index 4097a86..5d3ea6e 100644
   3 --- a/drivers/usb/gadget/Kconfig
   4 +++ b/drivers/usb/gadget/Kconfig
   5 @@ -111,6 +111,24 @@ config USB_PXA2XX
   6         default USB_GADGET
   7         select USB_GADGET_SELECTED
   8
   9 +config USB_GADGET_PXA27X
  10 +       boolean "PXA 27x"
  11 +       depends on ARCH_PXA && PXA27x
  12 +       help
  13 +          Intel's PXA 27x series XScale processors include an integrated
  14 +          full speed USB 1.1 device controller.
  15 +
  16 +          Say "y" to link the driver statically, or "m" to build a
  17 +          dynamically linked module called "pxa2xx_udc" and force all
  18 +          gadget drivers to also be dynamically linked.
  19 +
  20 +
  21 +config USB_PXA27X
  22 +       tristate
  23 +       depends on USB_GADGET_PXA27X
  24 +       default USB_GADGET
  25 +       select USB_GADGET_SELECTED
  26 +
  27  # if there's only one gadget driver, using only two bulk endpoints,
  28  # don't waste memory for the other endpoints
  29  config USB_PXA2XX_SMALL
  30 diff --git a/drivers/usb/gadget/Makefile b/drivers/usb/gadget/Makefile
  31 index e71e086..7e508a6 100644
  32 --- a/drivers/usb/gadget/Makefile
  33 +++ b/drivers/usb/gadget/Makefile
  34 @@ -4,6 +4,7 @@
  35  obj-$(CONFIG_USB_DUMMY_HCD)    += dummy_hcd.o
  36  obj-$(CONFIG_USB_NET2280)      += net2280.o
  37  obj-$(CONFIG_USB_PXA2XX)       += pxa2xx_udc.o
  38 +obj-$(CONFIG_USB_PXA27X)       += pxa27x_udc.o
  39  obj-$(CONFIG_USB_GOKU)         += goku_udc.o
  40  obj-$(CONFIG_USB_OMAP)         += omap_udc.o
  41  obj-$(CONFIG_USB_LH7A40X)      += lh7a40x_udc.o
  42 diff --git a/drivers/usb/gadget/epautoconf.c b/drivers/usb/gadget/epautoconf.c
  43 index f28af06..e7d72ff 100644
  44 --- a/drivers/usb/gadget/epautoconf.c
  45 +++ b/drivers/usb/gadget/epautoconf.c
  46 @@ -230,7 +230,8 @@ find_ep (struct usb_gadget *gadget, const char *name)
  47   */
  48  struct usb_ep * __devinit usb_ep_autoconfig (
  49         struct usb_gadget               *gadget,
  50 -       struct usb_endpoint_descriptor  *desc
  51 +       struct usb_endpoint_descriptor  *desc,
  52 +       int config, int interface, int alt
  53  )
  54  {
  55         struct usb_ep   *ep;
  56 @@ -238,6 +239,11 @@ struct usb_ep * __devinit usb_ep_autoconfig (
  57
  58         type = desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK;
  59
  60 +       /* If have ep_alloc() function use it! */
  61 +       if (gadget->ops->ep_alloc)
  62 +               return gadget->ops->ep_alloc(gadget, desc,
  63 +                                            config, interface, alt);
  64 +
  65         /* First, apply chip-specific "best usage" knowledge.
  66          * This might make a good usb_gadget_ops hook ...
  67          */
  68 diff --git a/drivers/usb/gadget/ether.c b/drivers/usb/gadget/ether.c
  69 index 04e6b85..bc6de31 100644
  70 --- a/drivers/usb/gadget/ether.c
  71 +++ b/drivers/usb/gadget/ether.c
  72 @@ -258,10 +258,6 @@ MODULE_PARM_DESC(host_addr, "Host Ethernet Address");
  73  #define        DEV_CONFIG_CDC
  74  #endif
  75
  76 -#ifdef CONFIG_USB_GADGET_PXA27X
  77 -#define DEV_CONFIG_CDC
  78 -#endif
  79 -
  80  #ifdef CONFIG_USB_GADGET_S3C2410
  81  #define DEV_CONFIG_CDC
  82  #endif
  83 @@ -294,6 +290,10 @@ MODULE_PARM_DESC(host_addr, "Host Ethernet Address");
  84  #define        DEV_CONFIG_SUBSET
  85  #endif
  86
  87 +#ifdef CONFIG_USB_GADGET_PXA27X
  88 +#define DEV_CONFIG_SUBSET
  89 +#endif
  90 +
  91  #ifdef CONFIG_USB_GADGET_SA1100
  92  /* use non-CDC for backwards compatibility */
  93  #define        DEV_CONFIG_SUBSET
  94 @@ -2309,6 +2309,9 @@ eth_bind (struct usb_gadget *gadget)
  95                  * non-CDC to be compatible with ARM Linux-2.4 "usb-eth".
  96                  */
  97                 cdc = 0;
  98 +       } else if (gadget_is_pxa27x(gadget)) {
  99 +               /* hardware can't write zlps */
 100 +               zlp = 0;
 101         }
 102
 103         gcnum = usb_gadget_controller_number (gadget);
 104 @@ -2375,7 +2378,22 @@ eth_bind (struct usb_gadget *gadget)
 105
 106         /* all we really need is bulk IN/OUT */
 107         usb_ep_autoconfig_reset (gadget);
 108 -       in_ep = usb_ep_autoconfig (gadget, &fs_source_desc);
 109 +#ifdef CONFIG_USB_ETH_RNDIS
 110 +       in_ep = usb_ep_autoconfig (gadget, &fs_source_desc,
 111 +                               DEV_RNDIS_CONFIG_VALUE,
 112 +                               (int)rndis_data_intf.bInterfaceNumber,
 113 +                               (int)rndis_data_intf.bAlternateSetting);
 114 +#elif  defined(DEV_CONFIG_CDC)
 115 +       in_ep = usb_ep_autoconfig (gadget, &fs_source_desc,
 116 +                               DEV_CONFIG_VALUE,
 117 +                               (int)data_intf.bInterfaceNumber,
 118 +                               (int)data_intf.bAlternateSetting);
 119 +#elif  defined(DEV_CONFIG_SUBSET)
 120 +       in_ep = usb_ep_autoconfig (gadget, &fs_source_desc,
 121 +                               DEV_CONFIG_VALUE,
 122 +                               (int)subset_data_intf.bInterfaceNumber,
 123 +                               (int)subset_data_intf.bAlternateSetting);
 124 +#endif /* CONFIG_USB_ETH_RNDIS */
 125         if (!in_ep) {
 126  autoconf_fail:
 127                 dev_err (&gadget->dev,
 128 @@ -2385,7 +2403,22 @@ autoconf_fail:
 129         }
 130         in_ep->driver_data = in_ep;     /* claim */
 131
 132 -       out_ep = usb_ep_autoconfig (gadget, &fs_sink_desc);
 133 +#ifdef CONFIG_USB_ETH_RNDIS
 134 +       out_ep = usb_ep_autoconfig (gadget, &fs_sink_desc,
 135 +                       DEV_RNDIS_CONFIG_VALUE,
 136 +                       (int)rndis_data_intf.bInterfaceNumber,
 137 +                       (int)rndis_data_intf.bAlternateSetting);
 138 +#elif  defined(DEV_CONFIG_CDC)
 139 +       out_ep = usb_ep_autoconfig (gadget, &fs_sink_desc,
 140 +                       DEV_CONFIG_VALUE,
 141 +                       (int)data_intf.bInterfaceNumber,
 142 +                       (int)data_intf.bAlternateSetting);
 143 +#elif  defined(DEV_CONFIG_SUBSET)
 144 +       out_ep = usb_ep_autoconfig (gadget, &fs_sink_desc,
 145 +                       DEV_CONFIG_VALUE,
 146 +                       (int)subset_data_intf.bInterfaceNumber,
 147 +                       (int)subset_data_intf.bAlternateSetting);
 148 +#endif /* CONFIG_USB_ETH_RNDIS */
 149         if (!out_ep)
 150                 goto autoconf_fail;
 151         out_ep->driver_data = out_ep;   /* claim */
 152 @@ -2395,7 +2428,17 @@ autoconf_fail:
 153          * Since some hosts expect one, try to allocate one anyway.
 154          */
 155         if (cdc || rndis) {
 156 -               status_ep = usb_ep_autoconfig (gadget, &fs_status_desc);
 157 +#ifdef CONFIG_USB_ETH_RNDIS
 158 +               status_ep = usb_ep_autoconfig (gadget, &fs_status_desc,
 159 +                       DEV_RNDIS_CONFIG_VALUE,
 160 +                       (int)rndis_control_intf.bInterfaceNumber,
 161 +                       (int)rndis_control_intf.bAlternateSetting);
 162 +#elif  defined(DEV_CONFIG_CDC)
 163 +               status_ep = usb_ep_autoconfig (gadget, &fs_status_desc,
 164 +                       DEV_CONFIG_VALUE,
 165 +                       (int)control_intf.bInterfaceNumber,
 166 +                       (int)control_intf.bAlternateSetting);
 167 +#endif /* CONFIG_USB_ETH_RNDIS */
 168                 if (status_ep) {
 169                         status_ep->driver_data = status_ep;     /* claim */
 170                 } else if (rndis) {
 171 @@ -2403,13 +2446,14 @@ autoconf_fail:
 172                                 "can't run RNDIS on %s\n",
 173                                 gadget->name);
 174                         return -ENODEV;
 175 +               }
 176  #ifdef DEV_CONFIG_CDC
 177                 /* pxa25x only does CDC subset; often used with RNDIS */
 178 -               } else if (cdc) {
 179 +               else if (cdc) {
 180                         control_intf.bNumEndpoints = 0;
 181                         /* FIXME remove endpoint from descriptor list */
 182 -#endif
 183                 }
 184 +#endif
 185         }
 186  #endif
 187
 188 diff --git a/drivers/usb/gadget/file_storage.c b/drivers/usb/gadget/file_storage.c
 189 index c6b6479..6af5fdd 100644
 190 --- a/drivers/usb/gadget/file_storage.c
 191 +++ b/drivers/usb/gadget/file_storage.c
 192 @@ -3920,20 +3920,20 @@ static int __init fsg_bind(struct usb_gadget *gadget)
 193
 194         /* Find all the endpoints we will use */
 195         usb_ep_autoconfig_reset(gadget);
 196 -       ep = usb_ep_autoconfig(gadget, &fs_bulk_in_desc);
 197 +       ep = usb_ep_autoconfig(gadget, &fs_bulk_in_desc, 0, 0, 0);
 198         if (!ep)
 199                 goto autoconf_fail;
 200         ep->driver_data = fsg;          // claim the endpoint
 201         fsg->bulk_in = ep;
 202
 203 -       ep = usb_ep_autoconfig(gadget, &fs_bulk_out_desc);
 204 +       ep = usb_ep_autoconfig(gadget, &fs_bulk_out_desc, 0, 0, 0);
 205         if (!ep)
 206                 goto autoconf_fail;
 207         ep->driver_data = fsg;          // claim the endpoint
 208         fsg->bulk_out = ep;
 209
 210         if (transport_is_cbi()) {
 211 -               ep = usb_ep_autoconfig(gadget, &fs_intr_in_desc);
 212 +               ep = usb_ep_autoconfig(gadget, &fs_intr_in_desc, 0, 0, 0);
 213                 if (!ep)
 214                         goto autoconf_fail;
 215                 ep->driver_data = fsg;          // claim the endpoint
 216 diff --git a/drivers/usb/gadget/gadget_chips.h b/drivers/usb/gadget/gadget_chips.h
 217 index 2e3d662..f3b3291 100644
 218 --- a/drivers/usb/gadget/gadget_chips.h
 219 +++ b/drivers/usb/gadget/gadget_chips.h
 220 @@ -177,5 +177,7 @@ static inline int usb_gadget_controller_number(struct usb_gadget *gadget)
 221                 return 0x17;
 222         else if (gadget_is_husb2dev(gadget))
 223                 return 0x18;
 224 +       else if (gadget_is_pxa27x(gadget))
 225 +               return 0x19;
 226         return -ENOENT;
 227  }
 228 diff --git a/drivers/usb/gadget/gmidi.c b/drivers/usb/gadget/gmidi.c
 229 index d08a8d0..d51feb2 100644
 230 --- a/drivers/usb/gadget/gmidi.c
 231 +++ b/drivers/usb/gadget/gmidi.c
 232 @@ -1204,7 +1204,7 @@ static int __devinit gmidi_bind(struct usb_gadget *gadget)
 233          * but there may also be important quirks to address.
 234          */
 235         usb_ep_autoconfig_reset(gadget);
 236 -       in_ep = usb_ep_autoconfig(gadget, &bulk_in_desc);
 237 +       in_ep = usb_ep_autoconfig(gadget, &bulk_in_desc, 0, 0, 0);
 238         if (!in_ep) {
 239  autoconf_fail:
 240                 printk(KERN_ERR "%s: can't autoconfigure on %s\n",
 241 @@ -1214,7 +1214,7 @@ autoconf_fail:
 242         EP_IN_NAME = in_ep->name;
 243         in_ep->driver_data = in_ep;     /* claim */
 244
 245 -       out_ep = usb_ep_autoconfig(gadget, &bulk_out_desc);
 246 +       out_ep = usb_ep_autoconfig(gadget, &bulk_out_desc, 0, 0, 0);
 247         if (!out_ep) {
 248                 goto autoconf_fail;
 249         }
 250 diff --git a/drivers/usb/gadget/pxa27x_udc.c b/drivers/usb/gadget/pxa27x_udc.c
 251 new file mode 100644
 252 index 0000000..d89ecc5
 253 --- /dev/null
 254 +++ b/drivers/usb/gadget/pxa27x_udc.c
 255 @@ -0,0 +1,2354 @@
 256 +/*
 257 + * linux/drivers/usb/gadget/pxa27x_udc.c
 258 + * Intel PXA2xx and IXP4xx on-chip full speed USB device controllers
 259 + *
 260 + * Copyright (C) 2002 Intrinsyc, Inc. (Frank Becker)
 261 + * Copyright (C) 2003 Robert Schwebel, Pengutronix
 262 + * Copyright (C) 2003 Benedikt Spranger, Pengutronix
 263 + * Copyright (C) 2003 David Brownell
 264 + * Copyright (C) 2003 Joshua Wise
 265 + * Copyright (C) 2004 Intel Corporation
 266 + * Copyright (C) 2007 Rodolfo Giometti <giometti@linux.it>
 267 + *
 268 + * This program is free software; you can redistribute it and/or modify
 269 + * it under the terms of the GNU General Public License as published by
 270 + * the Free Software Foundation; either version 2 of the License, or
 271 + * (at your option) any later version.
 272 + *
 273 + * This program is distributed in the hope that it will be useful,
 274 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
 275 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 276 + * GNU General Public License for more details.
 277 + *
 278 + * You should have received a copy of the GNU General Public License
 279 + * along with this program; if not, write to the Free Software
 280 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 281 + *
 282 + */
 283 +
 284 +#undef DEBUG
 285 +/* #define     VERBOSE DBG_VERBOSE */
 286 +
 287 +#include <linux/module.h>
 288 +#include <linux/kernel.h>
 289 +#include <linux/ioport.h>
 290 +#include <linux/types.h>
 291 +#include <linux/version.h>
 292 +#include <linux/errno.h>
 293 +#include <linux/delay.h>
 294 +#include <linux/sched.h>
 295 +#include <linux/slab.h>
 296 +#include <linux/init.h>
 297 +#include <linux/timer.h>
 298 +#include <linux/list.h>
 299 +#include <linux/interrupt.h>
 300 +#include <linux/proc_fs.h>
 301 +#include <linux/mm.h>
 302 +#include <linux/device.h>
 303 +#include <linux/dma-mapping.h>
 304 +#include <linux/platform_device.h>
 305 +
 306 +#include <asm/byteorder.h>
 307 +#include <asm/dma.h>
 308 +#include <asm/io.h>
 309 +#include <asm/irq.h>
 310 +#include <asm/system.h>
 311 +#include <asm/mach-types.h>
 312 +#include <asm/unaligned.h>
 313 +#include <asm/hardware.h>
 314 +#include <asm/arch/pxa-regs.h>
 315 +
 316 +#include <linux/usb/ch9.h>
 317 +#include <linux/usb_gadget.h>
 318 +
 319 +#include <asm/arch/udc.h>
 320 +
 321 +
 322 +/*
 323 + * This driver handles the USB Device Controller (UDC) in Intel's PXA 27x
 324 + * series processors.
 325 + * Such controller drivers work with a gadget driver.  The gadget driver
 326 + * returns descriptors, implements configuration and data protocols used
 327 + * by the host to interact with this device, and allocates endpoints to
 328 + * the different protocol interfaces.  The controller driver virtualizes
 329 + * usb hardware so that the gadget drivers will be more portable.
 330 + *
 331 + * This UDC hardware wants to implement a bit too much USB protocol, so
 332 + * it constrains the sorts of USB configuration change events that work.
 333 + * The errata for these chips are misleading; some "fixed" bugs from
 334 + * pxa250 a0/a1 b0/b1/b2 sure act like they're still there.
 335 + */
 336 +
 337 +#define        DRIVER_VERSION  "08-Feb-2007"
 338 +#define        DRIVER_DESC     "PXA 27x USB Device Controller driver"
 339 +
 340 +
 341 +static const char driver_name [] = "pxa27x_udc";
 342 +
 343 +static const char ep0name [] = "ep0";
 344 +
 345 +
 346 +#undef USE_DMA
 347 +#undef DISABLE_TEST_MODE
 348 +
 349 +#ifdef CONFIG_PROC_FS
 350 +#define        UDC_PROC_FILE
 351 +#endif
 352 +
 353 +#include "pxa27x_udc.h"
 354 +
 355 +#ifdef CONFIG_EMBEDDED
 356 +/* few strings, and little code to use them */
 357 +#undef DEBUG
 358 +#undef UDC_PROC_FILE
 359 +#endif
 360 +
 361 +#ifdef USE_DMA
 362 +static int use_dma = 1;
 363 +module_param(use_dma, bool, 0);
 364 +MODULE_PARM_DESC (use_dma, "true to use dma");
 365 +
 366 +static void dma_nodesc_handler (int dmach, void *_ep);
 367 +static void kick_dma(struct pxa27x_ep *ep, struct pxa27x_request *req);
 368 +
 369 +#define        DMASTR " (dma support)"
 370 +
 371 +#else  /* !USE_DMA */
 372 +#define        DMASTR " (pio only)"
 373 +#endif
 374 +
 375 +#ifdef CONFIG_USB_PXA27X_SMALL
 376 +#define SIZE_STR       " (small)"
 377 +#else
 378 +#define SIZE_STR       ""
 379 +#endif
 380 +
 381 +#ifdef DISABLE_TEST_MODE
 382 +/* (mode == 0) == no undocumented chip tweaks
 383 + * (mode & 1)  == double buffer bulk IN
 384 + * (mode & 2)  == double buffer bulk OUT
 385 + * ... so mode = 3 (or 7, 15, etc) does it for both
 386 + */
 387 +static ushort fifo_mode = 0;
 388 +module_param(fifo_mode, ushort, 0);
 389 +MODULE_PARM_DESC (fifo_mode, "pxa27x udc fifo mode");
 390 +#endif
 391 +
 392 +#define UDCISR0_IR0     0x3
 393 +#define UDCISR_INT_MASK         (UDC_INT_FIFOERROR | UDC_INT_PACKETCMP)
 394 +#define UDCICR_INT_MASK         UDCISR_INT_MASK
 395 +
 396 +#define UDCCSR_MASK    (UDCCSR_FST | UDCCSR_DME)
 397 +/* ---------------------------------------------------------------------------
 398 + *     endpoint related parts of the api to the usb controller hardware,
 399 + *     used by gadget driver; and the inner talker-to-hardware core.
 400 + * ---------------------------------------------------------------------------
 401 + */
 402 +
 403 +static void pxa27x_ep_fifo_flush (struct usb_ep *ep);
 404 +static void nuke (struct pxa27x_ep *, int status);
 405 +
 406 +static void pio_irq_enable(int ep_num)
 407 +{
 408 +        if (ep_num < 16)
 409 +                UDCICR0 |= 3 << (ep_num * 2);
 410 +        else {
 411 +                ep_num -= 16;
 412 +                UDCICR1 |= 3 << (ep_num * 2);
 413 +       }
 414 +}
 415 +
 416 +static void pio_irq_disable(int ep_num)
 417 +{
 418 +        ep_num &= 0xf;
 419 +        if (ep_num < 16)
 420 +                UDCICR0 &= ~(3 << (ep_num * 2));
 421 +        else {
 422 +                ep_num -= 16;
 423 +                UDCICR1 &= ~(3 << (ep_num * 2));
 424 +        }
 425 +}
 426 +
 427 +/* The UDCCR reg contains mask and interrupt status bits,
 428 + * so using '|=' isn't safe as it may ack an interrupt.
 429 + */
 430 +#define UDCCR_MASK_BITS         (UDCCR_OEN | UDCCR_UDE)
 431 +
 432 +static inline void udc_set_mask_UDCCR(int mask)
 433 +{
 434 +       UDCCR = (UDCCR & UDCCR_MASK_BITS) | (mask & UDCCR_MASK_BITS);
 435 +}
 436 +
 437 +static inline void udc_clear_mask_UDCCR(int mask)
 438 +{
 439 +       UDCCR = (UDCCR & UDCCR_MASK_BITS) & ~(mask & UDCCR_MASK_BITS);
 440 +}
 441 +
 442 +static inline void udc_ack_int_UDCCR(int mask)
 443 +{
 444 +       /* udccr contains the bits we dont want to change */
 445 +       __u32 udccr = UDCCR & UDCCR_MASK_BITS;
 446 +
 447 +       UDCCR = udccr | (mask & ~UDCCR_MASK_BITS);
 448 +}
 449 +
 450 +/*
 451 + * endpoint enable/disable
 452 + *
 453 + * we need to verify the descriptors used to enable endpoints.  since pxa27x
 454 + * endpoint configurations are fixed, and are pretty much always enabled,
 455 + * there's not a lot to manage here.
 456 + *
 457 + * because pxa27x can't selectively initialize bulk (or interrupt) endpoints,
 458 + * (resetting endpoint halt and toggle), SET_INTERFACE is unusable except
 459 + * for a single interface (with only the default altsetting) and for gadget
 460 + * drivers that don't halt endpoints (not reset by set_interface).  that also
 461 + * means that if you use ISO, you must violate the USB spec rule that all
 462 + * iso endpoints must be in non-default altsettings.
 463 + */
 464 +static int pxa27x_ep_enable (struct usb_ep *_ep,
 465 +               const struct usb_endpoint_descriptor *desc)
 466 +{
 467 +       struct pxa27x_ep        *ep;
 468 +       struct pxa27x_udc       *dev;
 469 +
 470 +       ep = container_of (_ep, struct pxa27x_ep, ep);
 471 +       if (!_ep || !desc || _ep->name == ep0name
 472 +                       || desc->bDescriptorType != USB_DT_ENDPOINT
 473 +                       || ep->fifo_size < le16_to_cpu(desc->wMaxPacketSize)) {
 474 +               DMSG("%s, bad ep or descriptor\n", __FUNCTION__);
 475 +               return -EINVAL;
 476 +       }
 477 +
 478 +       /* xfer types must match, except that interrupt ~= bulk */
 479 +       if( ep->ep_type != USB_ENDPOINT_XFER_BULK
 480 +                       && desc->bmAttributes != USB_ENDPOINT_XFER_INT) {
 481 +               DMSG("%s, %s type mismatch\n", __FUNCTION__, _ep->name);
 482 +               return -EINVAL;
 483 +       }
 484 +
 485 +       /* hardware _could_ do smaller, but driver doesn't */
 486 +       if ((desc->bmAttributes == USB_ENDPOINT_XFER_BULK
 487 +                               && le16_to_cpu (desc->wMaxPacketSize)
 488 +                                               != BULK_FIFO_SIZE)
 489 +                       || !desc->wMaxPacketSize) {
 490 +               DMSG("%s, bad %s maxpacket\n", __FUNCTION__, _ep->name);
 491 +               return -ERANGE;
 492 +       }
 493 +
 494 +       dev = ep->dev;
 495 +       if (!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN) {
 496 +               DMSG("%s, bogus device state\n", __FUNCTION__);
 497 +               return -ESHUTDOWN;
 498 +       }
 499 +
 500 +       ep->desc = desc;
 501 +       ep->dma = -1;
 502 +       ep->stopped = 0;
 503 +       ep->pio_irqs = ep->dma_irqs = 0;
 504 +       ep->ep.maxpacket = le16_to_cpu (desc->wMaxPacketSize);
 505 +
 506 +       /* flush fifo (mostly for OUT buffers) */
 507 +       pxa27x_ep_fifo_flush (_ep);
 508 +
 509 +       /* ... reset halt state too, if we could ... */
 510 +
 511 +#ifdef USE_DMA
 512 +       /* for (some) bulk and ISO endpoints, try to get a DMA channel and
 513 +        * bind it to the endpoint.  otherwise use PIO.
 514 +        */
 515 +       DMSG("%s: called attributes=%d\n", __FUNCTION__, ep->ep_type);
 516 +       switch (ep->ep_type) {
 517 +       case USB_ENDPOINT_XFER_ISOC:
 518 +               if (le16_to_cpu(desc->wMaxPacketSize) % 32)
 519 +                       break;
 520 +               // fall through
 521 +       case USB_ENDPOINT_XFER_BULK:
 522 +               if (!use_dma || !ep->reg_drcmr)
 523 +                       break;
 524 +               ep->dma = pxa_request_dma ((char *)_ep->name,
 525 +                               (le16_to_cpu (desc->wMaxPacketSize) > 64)
 526 +                                       ? DMA_PRIO_MEDIUM /* some iso */
 527 +                                       : DMA_PRIO_LOW,
 528 +                               dma_nodesc_handler, ep);
 529 +               if (ep->dma >= 0) {
 530 +                       *ep->reg_drcmr = DRCMR_MAPVLD | ep->dma;
 531 +                       DMSG("%s using dma%d\n", _ep->name, ep->dma);
 532 +               }
 533 +       default:
 534 +               break;
 535 +       }
 536 +#endif
 537 +       DBG(DBG_VERBOSE, "enabled %s\n", _ep->name);
 538 +       return 0;
 539 +}
 540 +
 541 +static int pxa27x_ep_disable (struct usb_ep *_ep)
 542 +{
 543 +       struct pxa27x_ep        *ep;
 544 +
 545 +       ep = container_of (_ep, struct pxa27x_ep, ep);
 546 +       if (!_ep || !ep->desc) {
 547 +               DMSG("%s, %s not enabled\n", __FUNCTION__,
 548 +                       _ep ? ep->ep.name : NULL);
 549 +               return -EINVAL;
 550 +       }
 551 +       nuke (ep, -ESHUTDOWN);
 552 +
 553 +#ifdef USE_DMA
 554 +       if (ep->dma >= 0) {
 555 +               *ep->reg_drcmr = 0;
 556 +               pxa_free_dma (ep->dma);
 557 +               ep->dma = -1;
 558 +       }
 559 +#endif
 560 +
 561 +       /* flush fifo (mostly for IN buffers) */
 562 +       pxa27x_ep_fifo_flush (_ep);
 563 +
 564 +       ep->desc = 0;
 565 +       ep->stopped = 1;
 566 +
 567 +       DBG(DBG_VERBOSE, "%s disabled\n", _ep->name);
 568 +       return 0;
 569 +}
 570 +
 571 +/*-------------------------------------------------------------------------*/
 572 +
 573 +/* for the pxa27x, these can just wrap kmalloc/kfree.  gadget drivers
 574 + * must still pass correctly initialized endpoints, since other controller
 575 + * drivers may care about how it's currently set up (dma issues etc).
 576 + */
 577 +
 578 +/*
 579 + *     pxa27x_ep_alloc_request - allocate a request data structure
 580 + */
 581 +static struct usb_request *
 582 +pxa27x_ep_alloc_request (struct usb_ep *_ep, unsigned int gfp_flags)
 583 +{
 584 +       struct pxa27x_request *req;
 585 +
 586 +       req = kmalloc (sizeof *req, gfp_flags);
 587 +       if (!req)
 588 +               return 0;
 589 +
 590 +       memset (req, 0, sizeof *req);
 591 +       INIT_LIST_HEAD (&req->queue);
 592 +       return &req->req;
 593 +}
 594 +
 595 +
 596 +/*
 597 + *     pxa27x_ep_free_request - deallocate a request data structure
 598 + */
 599 +static void
 600 +pxa27x_ep_free_request (struct usb_ep *_ep, struct usb_request *_req)
 601 +{
 602 +       struct pxa27x_request *req;
 603 +
 604 +       req = container_of(_req, struct pxa27x_request, req);
 605 +       WARN_ON (!list_empty (&req->queue));
 606 +       kfree(req);
 607 +}
 608 +
 609 +
 610 +/* PXA cache needs flushing with DMA I/O (it's dma-incoherent), but there's
 611 + * no device-affinity and the heap works perfectly well for i/o buffers.
 612 + * It wastes much less memory than dma_alloc_coherent() would, and even
 613 + * prevents cacheline (32 bytes wide) sharing problems.
 614 + */
 615 +static void *
 616 +pxa27x_ep_alloc_buffer(struct usb_ep *_ep, unsigned bytes,
 617 +       dma_addr_t *dma, unsigned int gfp_flags)
 618 +{
 619 +       char                    *retval;
 620 +
 621 +       retval = kmalloc (bytes, gfp_flags & ~(__GFP_DMA|__GFP_HIGHMEM));
 622 +       if (retval)
 623 +               *dma = virt_to_bus (retval);
 624 +       return retval;
 625 +}
 626 +
 627 +static void
 628 +pxa27x_ep_free_buffer(struct usb_ep *_ep, void *buf, dma_addr_t dma,
 629 +               unsigned bytes)
 630 +{
 631 +       kfree (buf);
 632 +}
 633 +
 634 +/*-------------------------------------------------------------------------*/
 635 +
 636 +/*
 637 + *     done - retire a request; caller blocked irqs
 638 + */
 639 +static void done(struct pxa27x_ep *ep, struct pxa27x_request *req, int status)
 640 +{
 641 +       list_del_init(&req->queue);
 642 +       if (likely (req->req.status == -EINPROGRESS))
 643 +               req->req.status = status;
 644 +       else
 645 +               status = req->req.status;
 646 +
 647 +       if (status && status != -ESHUTDOWN)
 648 +               DBG(DBG_VERBOSE, "complete %s req %p stat %d len %u/%u\n",
 649 +                       ep->ep.name, &req->req, status,
 650 +                       req->req.actual, req->req.length);
 651 +
 652 +       /* don't modify queue heads during completion callback */
 653 +       req->req.complete(&ep->ep, &req->req);
 654 +}
 655 +
 656 +
 657 +static inline void ep0_idle (struct pxa27x_udc *dev)
 658 +{
 659 +       dev->ep0state = EP0_IDLE;
 660 +       LED_EP0_OFF;
 661 +}
 662 +
 663 +static int
 664 +write_packet(volatile u32 *uddr, struct pxa27x_request *req, unsigned max)
 665 +{
 666 +       u32             *buf;
 667 +       int     length, count, remain;
 668 +
 669 +       buf = (u32*)(req->req.buf + req->req.actual);
 670 +       prefetch(buf);
 671 +
 672 +       /* how big will this packet be? */
 673 +       length = min(req->req.length - req->req.actual, max);
 674 +       req->req.actual += length;
 675 +
 676 +       remain = length & 0x3;
 677 +       count = length & ~(0x3);
 678 +
 679 +       while (likely(count)) {
 680 +               *uddr = *buf++;
 681 +               count -= 4;
 682 +       }
 683 +
 684 +       if (remain) {
 685 +               volatile u8* reg=(u8*)uddr;
 686 +               char *rd =(u8*)buf;
 687 +
 688 +               while (remain--) {
 689 +                       *reg=*rd++;
 690 +               }
 691 +       }
 692 +
 693 +       return length;
 694 +}
 695 +
 696 +/*
 697 + * write to an IN endpoint fifo, as many packets as possible.
 698 + * irqs will use this to write the rest later.
 699 + * caller guarantees at least one packet buffer is ready (or a zlp).
 700 + */
 701 +static int
 702 +write_fifo (struct pxa27x_ep *ep, struct pxa27x_request *req)
 703 +{
 704 +       unsigned                max;
 705 +
 706 +       max = le16_to_cpu(ep->desc->wMaxPacketSize);
 707 +       do {
 708 +               int     count;
 709 +               int             is_last, is_short;
 710 +
 711 +               count = write_packet(ep->reg_udcdr, req, max);
 712 +
 713 +               /* last packet is usually short (or a zlp) */
 714 +               if (unlikely (count != max))
 715 +                       is_last = is_short = 1;
 716 +               else {
 717 +                       if (likely(req->req.length != req->req.actual)
 718 +                                       || req->req.zero)
 719 +                               is_last = 0;
 720 +                       else
 721 +                               is_last = 1;
 722 +                       /* interrupt/iso maxpacket may not fill the fifo */
 723 +                       is_short = unlikely (max < ep->fifo_size);
 724 +               }
 725 +
 726 +               DMSG("wrote %s count:%d bytes%s%s %d left %p\n",
 727 +                       ep->ep.name, count,
 728 +                       is_last ? "/L" : "", is_short ? "/S" : "",
 729 +                       req->req.length - req->req.actual, &req->req);
 730 +
 731 +               /* let loose that packet. maybe try writing another one,
 732 +                * double buffering might work.  TSP, TPC, and TFS
 733 +                * bit values are the same for all normal IN endpoints.
 734 +                */
 735 +               *ep->reg_udccsr = UDCCSR_PC;
 736 +               if (is_short)
 737 +                       *ep->reg_udccsr = UDCCSR_SP;
 738 +
 739 +               /* requests complete when all IN data is in the FIFO */
 740 +               if (is_last) {
 741 +                       done (ep, req, 0);
 742 +                       if (list_empty(&ep->queue) || unlikely(ep->dma >= 0)) {
 743 +                               pio_irq_disable (ep->ep_num);
 744 +#ifdef USE_DMA
 745 +                               /* unaligned data and zlps couldn't use dma */
 746 +                               if (unlikely(!list_empty(&ep->queue))) {
 747 +                                       req = list_entry(ep->queue.next,
 748 +                                               struct pxa27x_request, queue);
 749 +                                       kick_dma(ep,req);
 750 +                                       return 0;
 751 +                               }
 752 +#endif
 753 +                       }
 754 +                       return 1;
 755 +               }
 756 +
 757 +               // TODO experiment: how robust can fifo mode tweaking be?
 758 +               // double buffering is off in the default fifo mode, which
 759 +               // prevents TFS from being set here.
 760 +
 761 +       } while (*ep->reg_udccsr & UDCCSR_FS);
 762 +       return 0;
 763 +}
 764 +
 765 +/* caller asserts req->pending (ep0 irq status nyet cleared); starts
 766 + * ep0 data stage.  these chips want very simple state transitions.
 767 + */
 768 +static inline
 769 +void ep0start(struct pxa27x_udc *dev, u32 flags, const char *tag)
 770 +{
 771 +       UDCCSR0 = flags|UDCCSR0_SA|UDCCSR0_OPC;
 772 +       UDCISR0 = UDCICR_INT(0, UDC_INT_FIFOERROR | UDC_INT_PACKETCMP);
 773 +       dev->req_pending = 0;
 774 +       DBG(DBG_VERY_NOISY, "%s %s, %02x/%02x\n",
 775 +               __FUNCTION__, tag, UDCCSR0, flags);
 776 +}
 777 +
 778 +static int
 779 +write_ep0_fifo (struct pxa27x_ep *ep, struct pxa27x_request *req)
 780 +{
 781 +       unsigned        count;
 782 +       int             is_short;
 783 +
 784 +       count = write_packet(&UDCDR0, req, EP0_FIFO_SIZE);
 785 +       ep->dev->stats.write.bytes += count;
 786 +
 787 +       /* last packet "must be" short (or a zlp) */
 788 +       is_short = (count != EP0_FIFO_SIZE);
 789 +
 790 +       DBG(DBG_VERY_NOISY, "ep0in %d bytes %d left %p\n", count,
 791 +               req->req.length - req->req.actual, &req->req);
 792 +
 793 +       if (unlikely (is_short)) {
 794 +               if (ep->dev->req_pending)
 795 +                       ep0start(ep->dev, UDCCSR0_IPR, "short IN");
 796 +               else
 797 +                       UDCCSR0 = UDCCSR0_IPR;
 798 +
 799 +               count = req->req.length;
 800 +               done (ep, req, 0);
 801 +               ep0_idle(ep->dev);
 802 +#if 0
 803 +               /* This seems to get rid of lost status irqs in some cases:
 804 +                * host responds quickly, or next request involves config
 805 +                * change automagic, or should have been hidden, or ...
 806 +                *
 807 +                * FIXME get rid of all udelays possible...
 808 +                */
 809 +               if (count >= EP0_FIFO_SIZE) {
 810 +                       count = 100;
 811 +                       do {
 812 +                               if ((UDCCSR0 & UDCCSR0_OPC) != 0) {
 813 +                                       /* clear OPC, generate ack */
 814 +                                       UDCCSR0 = UDCCSR0_OPC;
 815 +                                       break;
 816 +                               }
 817 +                               count--;
 818 +                               udelay(1);
 819 +                       } while (count);
 820 +               }
 821 +#endif
 822 +       } else if (ep->dev->req_pending)
 823 +               ep0start(ep->dev, 0, "IN");
 824 +       return is_short;
 825 +}
 826 +
 827 +
 828 +/*
 829 + * read_fifo -  unload packet(s) from the fifo we use for usb OUT
 830 + * transfers and put them into the request.  caller should have made
 831 + * sure there's at least one packet ready.
 832 + *
 833 + * returns true if the request completed because of short packet or the
 834 + * request buffer having filled (and maybe overran till end-of-packet).
 835 + */
 836 +static int
 837 +read_fifo (struct pxa27x_ep *ep, struct pxa27x_request *req)
 838 +{
 839 +       for (;;) {
 840 +               u32             *buf;
 841 +               int     bufferspace, count, is_short;
 842 +
 843 +               /* make sure there's a packet in the FIFO.*/
 844 +               if (unlikely ((*ep->reg_udccsr & UDCCSR_PC) == 0))
 845 +                       break;
 846 +               buf =(u32*) (req->req.buf + req->req.actual);
 847 +               prefetchw(buf);
 848 +               bufferspace = req->req.length - req->req.actual;
 849 +
 850 +               /* read all bytes from this packet */
 851 +               if (likely (*ep->reg_udccsr & UDCCSR_BNE)) {
 852 +                       count = 0x3ff & *ep->reg_udcbcr;
 853 +                       req->req.actual += min (count, bufferspace);
 854 +               } else /* zlp */
 855 +                       count = 0;
 856 +
 857 +               is_short = (count < ep->ep.maxpacket);
 858 +               DMSG("read %s udccsr:%02x, count:%d bytes%s req %p %d/%d\n",
 859 +                       ep->ep.name, *ep->reg_udccsr, count,
 860 +                       is_short ? "/S" : "",
 861 +                       &req->req, req->req.actual, req->req.length);
 862 +
 863 +//             dump_regs(ep->ep_num );
 864 +               count = min(count, bufferspace);
 865 +               while (likely (count > 0)) {
 866 +                       *buf++ = *ep->reg_udcdr;
 867 +                       count -= 4;
 868 +               }
 869 +               DMSG("Buf:0x%p\n", req->req.buf);
 870 +
 871 +               *ep->reg_udccsr =  UDCCSR_PC;
 872 +               /* RPC/RSP/RNE could now reflect the other packet buffer */
 873 +
 874 +               /* completion */
 875 +               if (is_short || req->req.actual == req->req.length) {
 876 +                       done (ep, req, 0);
 877 +                       if (list_empty(&ep->queue))
 878 +                               pio_irq_disable (ep->ep_num);
 879 +                       return 1;
 880 +               }
 881 +
 882 +               /* finished that packet.  the next one may be waiting... */
 883 +       }
 884 +       return 0;
 885 +}
 886 +
 887 +/*
 888 + * special ep0 version of the above.  no UBCR0 or double buffering; status
 889 + * handshaking is magic.  most device protocols don't need control-OUT.
 890 + * CDC vendor commands (and RNDIS), mass storage CB/CBI, and some other
 891 + * protocols do use them.
 892 + */
 893 +static int
 894 +read_ep0_fifo (struct pxa27x_ep *ep, struct pxa27x_request *req)
 895 +{
 896 +       u32             *buf, word;
 897 +       unsigned        bufferspace;
 898 +
 899 +       buf = (u32*) (req->req.buf + req->req.actual);
 900 +       bufferspace = req->req.length - req->req.actual;
 901 +
 902 +       while (UDCCSR0 & UDCCSR0_RNE) {
 903 +               word = UDCDR0;
 904 +
 905 +               if (unlikely (bufferspace == 0)) {
 906 +                       /* this happens when the driver's buffer
 907 +                        * is smaller than what the host sent.
 908 +                        * discard the extra data.
 909 +                        */
 910 +                       if (req->req.status != -EOVERFLOW)
 911 +                               DMSG("%s overflow\n", ep->ep.name);
 912 +                       req->req.status = -EOVERFLOW;
 913 +               } else {
 914 +                       *buf++ = word;
 915 +                       req->req.actual += 4;
 916 +                       bufferspace -= 4;
 917 +               }
 918 +       }
 919 +
 920 +       UDCCSR0 = UDCCSR0_OPC ;
 921 +
 922 +       /* completion */
 923 +       if (req->req.actual >= req->req.length)
 924 +               return 1;
 925 +
 926 +       /* finished that packet.  the next one may be waiting... */
 927 +       return 0;
 928 +}
 929 +
 930 +#ifdef USE_DMA
 931 +
 932 +#define        MAX_IN_DMA      ((DCMD_LENGTH + 1) - BULK_FIFO_SIZE)
 933 +static void kick_dma(struct pxa27x_ep *ep, struct pxa27x_request *req)
 934 +{
 935 +       u32     dcmd = 0;
 936 +       u32     len = req->req.length;
 937 +       u32     buf = req->req.dma;
 938 +       u32     fifo = io_v2p ((u32)ep->reg_udcdr);
 939 +
 940 +       buf += req->req.actual;
 941 +       len -= req->req.actual;
 942 +       ep->dma_con = 0;
 943 +
 944 +       DMSG("%s: req:0x%p length:%d, actual:%d dma:%d\n",
 945 +                       __FUNCTION__, &req->req, req->req.length,
 946 +                       req->req.actual,ep->dma);
 947 +
 948 +       /* no-descriptor mode can be simple for bulk-in, iso-in, iso-out */
 949 +       DCSR(ep->dma) = DCSR_NODESC;
 950 +       if (buf & 0x3)
 951 +               DALGN |= 1 << ep->dma;
 952 +       else
 953 +               DALGN &= ~(1 << ep->dma);
 954 +
 955 +       if (ep->dir_in) {
 956 +               DSADR(ep->dma) = buf;
 957 +               DTADR(ep->dma) = fifo;
 958 +               if (len > MAX_IN_DMA) {
 959 +                       len= MAX_IN_DMA;
 960 +                       ep->dma_con =1 ;
 961 +               } else if (len >= ep->ep.maxpacket) {
 962 +                       if ((ep->dma_con = (len % ep->ep.maxpacket) != 0))
 963 +                               len = ep->ep.maxpacket;
 964 +               }
 965 +                dcmd = len | DCMD_BURST32 | DCMD_WIDTH4 | DCMD_ENDIRQEN
 966 +                       | DCMD_FLOWTRG | DCMD_INCSRCADDR;
 967 +       } else {
 968 +               DSADR(ep->dma) = fifo;
 969 +               DTADR(ep->dma) = buf;
 970 +               dcmd = len | DCMD_BURST32 | DCMD_WIDTH4 | DCMD_ENDIRQEN
 971 +                       | DCMD_FLOWSRC | DCMD_INCTRGADDR;
 972 +       }
 973 +       *ep->reg_udccsr = UDCCSR_DME;
 974 +       DCMD(ep->dma) = dcmd;
 975 +       DCSR(ep->dma) =  DCSR_NODESC | DCSR_EORIRQEN \
 976 +                               | ((ep->dir_in) ? DCSR_STOPIRQEN : 0);
 977 +       *ep->reg_drcmr = ep->dma | DRCMR_MAPVLD;
 978 +       DCSR(ep->dma) |= DCSR_RUN;
 979 +}
 980 +
 981 +static void cancel_dma(struct pxa27x_ep *ep)
 982 +{
 983 +       struct pxa27x_request   *req;
 984 +       u32                     tmp;
 985 +
 986 +       if (DCSR(ep->dma) == 0 || list_empty(&ep->queue))
 987 +               return;
 988 +
 989 +       DMSG("hehe dma:%d,dcsr:0x%x\n", ep->dma, DCSR(ep->dma));
 990 +       DCSR(ep->dma) = 0;
 991 +       while ((DCSR(ep->dma) & DCSR_STOPSTATE) == 0)
 992 +               cpu_relax();
 993 +
 994 +       req = list_entry(ep->queue.next, struct pxa27x_request, queue);
 995 +       tmp = DCMD(ep->dma) & DCMD_LENGTH;
 996 +       req->req.actual = req->req.length - tmp;
 997 +
 998 +       /* the last tx packet may be incomplete, so flush the fifo.
 999 +        * FIXME correct req.actual if we can
1000 +        */
1001 +       *ep->reg_udccsr = UDCCSR_FEF;
1002 +}
1003 +
1004 +static void dma_nodesc_handler(int dmach, void *_ep, struct pt_regs *r)
1005 +{
1006 +       struct pxa27x_ep        *ep = _ep;
1007 +       struct pxa27x_request   *req, *req_next;
1008 +       u32                     dcsr, tmp, completed;
1009 +
1010 +       local_irq_disable();
1011 +
1012 +       req = list_entry(ep->queue.next, struct pxa27x_request, queue);
1013 +
1014 +       DMSG("%s, buf:0x%p\n",__FUNCTION__, req->req.buf);
1015 +
1016 +       ep->dma_irqs++;
1017 +       ep->dev->stats.irqs++;
1018 +       HEX_DISPLAY(ep->dev->stats.irqs);
1019 +
1020 +       completed = 0;
1021 +
1022 +       dcsr = DCSR(dmach);
1023 +       DCSR(ep->dma) &= ~DCSR_RUN;
1024 +
1025 +       if (dcsr & DCSR_BUSERR) {
1026 +               DCSR(dmach) = DCSR_BUSERR;
1027 +               printk(KERN_ERR " Buss Error\n");
1028 +               req->req.status = -EIO;
1029 +               completed = 1;
1030 +       } else if (dcsr & DCSR_ENDINTR) {
1031 +               DCSR(dmach) = DCSR_ENDINTR;
1032 +               if (ep->dir_in) {
1033 +                       tmp = req->req.length - req->req.actual;
1034 +                       /* Last packet is a short one*/
1035 +                       if ( tmp < ep->ep.maxpacket) {
1036 +                               int count = 0;
1037 +
1038 +                               *ep->reg_udccsr = UDCCSR_SP | \
1039 +                                       (*ep->reg_udccsr & UDCCSR_MASK);
1040 +                               /*Wait for packet out */
1041 +                               while( (count++ < 10000) && \
1042 +                                       !(*ep->reg_udccsr & UDCCSR_FS));
1043 +                               if (count >= 10000)
1044 +                                       DMSG("Failed to send packet\n");
1045 +                               else
1046 +                                       DMSG("%s: short packet sent len:%d,"
1047 +                                       "length:%d,actual:%d\n", __FUNCTION__,
1048 +                                       tmp, req->req.length, req->req.actual);
1049 +                               req->req.actual = req->req.length;
1050 +                               completed = 1;
1051 +                       /* There are still packets to transfer */
1052 +                       } else if ( ep->dma_con) {
1053 +                               DMSG("%s: more packets,length:%d,actual:%d\n",
1054 +                                        __FUNCTION__,req->req.length,
1055 +                                        req->req.actual);
1056 +                               req->req.actual += ep->ep.maxpacket;
1057 +                               completed = 0;
1058 +                       } else {
1059 +                               DMSG("%s: no more packets,length:%d,"
1060 +                                       "actual:%d\n", __FUNCTION__,
1061 +                                       req->req.length, req->req.actual);
1062 +                               req->req.actual = req->req.length;
1063 +                               completed = 1;
1064 +                       }
1065 +               } else {
1066 +                       req->req.actual = req->req.length;
1067 +                       completed = 1;
1068 +               }
1069 +       } else if (dcsr & DCSR_EORINTR) { //Only happened in OUT DMA
1070 +               int remain,udccsr ;
1071 +
1072 +               DCSR(dmach) = DCSR_EORINTR;
1073 +               remain = DCMD(dmach) & DCMD_LENGTH;
1074 +               req->req.actual = req->req.length - remain;
1075 +
1076 +               udccsr = *ep->reg_udccsr;
1077 +               if (udccsr & UDCCSR_SP) {
1078 +                       *ep->reg_udccsr = UDCCSR_PC | (udccsr & UDCCSR_MASK);
1079 +                       completed = 1;
1080 +               }
1081 +               DMSG("%s: length:%d actual:%d\n",
1082 +                               __FUNCTION__, req->req.length, req->req.actual);
1083 +       } else
1084 +               DMSG("%s: Others dma:%d DCSR:0x%x DCMD:0x%x\n",
1085 +                               __FUNCTION__, dmach, DCSR(dmach), DCMD(dmach));
1086 +
1087 +       if (likely(completed)) {
1088 +               if (req->queue.next != &ep->queue) {
1089 +                       req_next = list_entry(req->queue.next,
1090 +                                       struct pxa27x_request, queue);
1091 +                       kick_dma(ep, req_next);
1092 +               }
1093 +               done(ep, req, 0);
1094 +       } else {
1095 +               kick_dma(ep, req);
1096 +       }
1097 +
1098 +       local_irq_enable();
1099 +}
1100 +
1101 +#endif
1102 +/*-------------------------------------------------------------------------*/
1103 +
1104 +static int
1105 +pxa27x_ep_queue(struct usb_ep *_ep, struct usb_request *_req, unsigned int gfp_flags)
1106 +{
1107 +       struct pxa27x_ep        *ep;
1108 +       struct pxa27x_request   *req;
1109 +       struct pxa27x_udc       *dev;
1110 +       unsigned long           flags;
1111 +
1112 +       req = container_of(_req, struct pxa27x_request, req);
1113 +       if (unlikely (!_req || !_req->complete || !_req->buf||
1114 +                       !list_empty(&req->queue))) {
1115 +               DMSG("%s, bad params\n", __FUNCTION__);
1116 +               return -EINVAL;
1117 +       }
1118 +
1119 +       ep = container_of(_ep, struct pxa27x_ep, ep);
1120 +       if (unlikely (!_ep || (!ep->desc && ep->ep.name != ep0name))) {
1121 +               DMSG("%s, bad ep\n", __FUNCTION__);
1122 +               return -EINVAL;
1123 +       }
1124 +
1125 +       DMSG("%s, ep point %d is queue\n", __FUNCTION__, ep->ep_num);
1126 +
1127 +       dev = ep->dev;
1128 +       if (unlikely (!dev->driver
1129 +                       || dev->gadget.speed == USB_SPEED_UNKNOWN)) {
1130 +               DMSG("%s, bogus device state\n", __FUNCTION__);
1131 +               return -ESHUTDOWN;
1132 +       }
1133 +
1134 +       /* iso is always one packet per request, that's the only way
1135 +        * we can report per-packet status.  that also helps with dma.
1136 +        */
1137 +       if (unlikely (ep->ep_type == USB_ENDPOINT_XFER_ISOC
1138 +                       && req->req.length > le16_to_cpu
1139 +                                               (ep->desc->wMaxPacketSize)))
1140 +               return -EMSGSIZE;
1141 +
1142 +#ifdef USE_DMA
1143 +       /* FIXME: caller may already have done the dma mapping */
1144 +       if (ep->dma >= 0) {
1145 +               _req->dma = dma_map_single(dev->dev, _req->buf, _req->length,
1146 +                       (ep->dir_in) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
1147 +       }
1148 +#endif
1149 +
1150 +       DBG(DBG_NOISY, "%s queue req %p, len %d buf %p\n",
1151 +            _ep->name, _req, _req->length, _req->buf);
1152 +
1153 +       local_irq_save(flags);
1154 +
1155 +       _req->status = -EINPROGRESS;
1156 +       _req->actual = 0;
1157 +
1158 +       /* kickstart this i/o queue? */
1159 +       if (list_empty(&ep->queue) && !ep->stopped) {
1160 +               if (ep->desc == 0 /* ep0 */) {
1161 +                       unsigned        length = _req->length;
1162 +
1163 +                       switch (dev->ep0state) {
1164 +                       case EP0_IN_DATA_PHASE:
1165 +                               dev->stats.write.ops++;
1166 +                               if (write_ep0_fifo(ep, req))
1167 +                                       req = 0;
1168 +                               break;
1169 +
1170 +                       case EP0_OUT_DATA_PHASE:
1171 +                               dev->stats.read.ops++;
1172 +                               if (dev->req_pending)
1173 +                                       ep0start(dev, UDCCSR0_IPR, "OUT");
1174 +                               if (length == 0 || ((UDCCSR0 & UDCCSR0_RNE) != 0
1175 +                                               && read_ep0_fifo(ep, req))) {
1176 +                                       ep0_idle(dev);
1177 +                                       done(ep, req, 0);
1178 +                                       req = 0;
1179 +                               }
1180 +                               break;
1181 +                       case EP0_NO_ACTION:
1182 +                               ep0_idle(dev);
1183 +                               req=0;
1184 +                               break;
1185 +                       default:
1186 +                               DMSG("ep0 i/o, odd state %d\n", dev->ep0state);
1187 +                               local_irq_restore (flags);
1188 +                               return -EL2HLT;
1189 +                       }
1190 +#ifdef USE_DMA
1191 +               /* either start dma or prime pio pump */
1192 +               } else if (ep->dma >= 0) {
1193 +                       kick_dma(ep, req);
1194 +#endif
1195 +               /* can the FIFO can satisfy the request immediately? */
1196 +               } else if (ep->dir_in
1197 +                               && (*ep->reg_udccsr & UDCCSR_FS) != 0
1198 +                               && write_fifo(ep, req)) {
1199 +                       req = 0;
1200 +               } else if ((*ep->reg_udccsr & UDCCSR_FS) != 0
1201 +                               && read_fifo(ep, req)) {
1202 +                       req = 0;
1203 +               }
1204 +               DMSG("req:%p,ep->desc:%p,ep->dma:%d\n", req, ep->desc, ep->dma);
1205 +               if (likely (req && ep->desc) && ep->dma < 0)
1206 +                       pio_irq_enable(ep->ep_num);
1207 +       }
1208 +
1209 +       /* pio or dma irq handler advances the queue. */
1210 +       if (likely (req != 0))
1211 +               list_add_tail(&req->queue, &ep->queue);
1212 +       local_irq_restore(flags);
1213 +
1214 +       return 0;
1215 +}
1216 +
1217 +
1218 +/*
1219 + *     nuke - dequeue ALL requests
1220 + */
1221 +static void nuke(struct pxa27x_ep *ep, int status)
1222 +{
1223 +       struct pxa27x_request *req;
1224 +
1225 +       /* called with irqs blocked */
1226 +#ifdef USE_DMA
1227 +       if (ep->dma >= 0 && !ep->stopped)
1228 +               cancel_dma(ep);
1229 +#endif
1230 +       while (!list_empty(&ep->queue)) {
1231 +               req = list_entry(ep->queue.next, struct pxa27x_request, queue);
1232 +               done(ep, req, status);
1233 +       }
1234 +       if (ep->desc)
1235 +               pio_irq_disable (ep->ep_num);
1236 +}
1237 +
1238 +
1239 +/* dequeue JUST ONE request */
1240 +static int pxa27x_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
1241 +{
1242 +       struct pxa27x_ep        *ep;
1243 +       struct pxa27x_request   *req;
1244 +       unsigned long           flags;
1245 +
1246 +       ep = container_of(_ep, struct pxa27x_ep, ep);
1247 +       if (!_ep || ep->ep.name == ep0name)
1248 +               return -EINVAL;
1249 +
1250 +       local_irq_save(flags);
1251 +
1252 +       /* make sure it's actually queued on this endpoint */
1253 +       list_for_each_entry (req, &ep->queue, queue) {
1254 +               if (&req->req == _req)
1255 +                       break;
1256 +       }
1257 +       if (&req->req != _req) {
1258 +               local_irq_restore(flags);
1259 +               return -EINVAL;
1260 +       }
1261 +
1262 +#ifdef USE_DMA
1263 +       if (ep->dma >= 0 && ep->queue.next == &req->queue && !ep->stopped) {
1264 +               cancel_dma(ep);
1265 +               done(ep, req, -ECONNRESET);
1266 +               /* restart i/o */
1267 +               if (!list_empty(&ep->queue)) {
1268 +                       req = list_entry(ep->queue.next,
1269 +                                       struct pxa27x_request, queue);
1270 +                       kick_dma(ep, req);
1271 +               }
1272 +       } else
1273 +#endif
1274 +               done(ep, req, -ECONNRESET);
1275 +
1276 +       local_irq_restore(flags);
1277 +       return 0;
1278 +}
1279 +
1280 +/*-------------------------------------------------------------------------*/
1281 +
1282 +static int pxa27x_ep_set_halt(struct usb_ep *_ep, int value)
1283 +{
1284 +       struct pxa27x_ep        *ep;
1285 +       unsigned long           flags;
1286 +
1287 +       DMSG("%s is called\n", __FUNCTION__);
1288 +       ep = container_of(_ep, struct pxa27x_ep, ep);
1289 +       if (unlikely (!_ep
1290 +                       || (!ep->desc && ep->ep.name != ep0name))
1291 +                       || ep->ep_type == USB_ENDPOINT_XFER_ISOC) {
1292 +               DMSG("%s, bad ep\n", __FUNCTION__);
1293 +               return -EINVAL;
1294 +       }
1295 +       if (value == 0) {
1296 +               /* this path (reset toggle+halt) is needed to implement
1297 +                * SET_INTERFACE on normal hardware.  but it can't be
1298 +                * done from software on the PXA UDC, and the hardware
1299 +                * forgets to do it as part of SET_INTERFACE automagic.
1300 +                */
1301 +               DMSG("only host can clear %s halt\n", _ep->name);
1302 +               return -EROFS;
1303 +       }
1304 +
1305 +       local_irq_save(flags);
1306 +
1307 +       if (ep->dir_in  && ((*ep->reg_udccsr & UDCCSR_FS) == 0
1308 +                          || !list_empty(&ep->queue))) {
1309 +               local_irq_restore(flags);
1310 +               return -EAGAIN;
1311 +       }
1312 +
1313 +       /* FST bit is the same for control, bulk in, bulk out, interrupt in */
1314 +       *ep->reg_udccsr = UDCCSR_FST|UDCCSR_FEF;
1315 +
1316 +       /* ep0 needs special care */
1317 +       if (!ep->desc) {
1318 +               start_watchdog(ep->dev);
1319 +               ep->dev->req_pending = 0;
1320 +               ep->dev->ep0state = EP0_STALL;
1321 +               LED_EP0_OFF;
1322 +
1323 +       /* and bulk/intr endpoints like dropping stalls too */
1324 +       } else {
1325 +               unsigned i;
1326 +               for (i = 0; i < 1000; i += 20) {
1327 +                       if (*ep->reg_udccsr & UDCCSR_SST)
1328 +                               break;
1329 +                       udelay(20);
1330 +               }
1331 +       }
1332 +       local_irq_restore(flags);
1333 +
1334 +       DBG(DBG_VERBOSE, "%s halt\n", _ep->name);
1335 +       return 0;
1336 +}
1337 +
1338 +static int pxa27x_ep_fifo_status(struct usb_ep *_ep)
1339 +{
1340 +       struct pxa27x_ep        *ep;
1341 +
1342 +       ep = container_of(_ep, struct pxa27x_ep, ep);
1343 +       if (!_ep) {
1344 +               DMSG("%s, bad ep\n", __FUNCTION__);
1345 +               return -ENODEV;
1346 +       }
1347 +       /* pxa can't report unclaimed bytes from IN fifos */
1348 +       if (ep->dir_in)
1349 +               return -EOPNOTSUPP;
1350 +       if (ep->dev->gadget.speed == USB_SPEED_UNKNOWN
1351 +                       || (*ep->reg_udccsr & UDCCSR_FS) == 0)
1352 +               return 0;
1353 +       else
1354 +               return (*ep->reg_udcbcr & 0xfff) + 1;
1355 +}
1356 +
1357 +static void pxa27x_ep_fifo_flush(struct usb_ep *_ep)
1358 +{
1359 +       struct pxa27x_ep        *ep;
1360 +
1361 +       ep = container_of(_ep, struct pxa27x_ep, ep);
1362 +       if (!_ep || ep->ep.name == ep0name || !list_empty(&ep->queue)) {
1363 +               DMSG("%s, bad ep\n", __FUNCTION__);
1364 +               return;
1365 +       }
1366 +
1367 +       /* toggle and halt bits stay unchanged */
1368 +
1369 +       /* for OUT, just read and discard the FIFO contents. */
1370 +       if (!ep->dir_in) {
1371 +               while (((*ep->reg_udccsr) & UDCCSR_BNE) != 0)
1372 +                       (void) *ep->reg_udcdr;
1373 +               return;
1374 +       }
1375 +
1376 +       /* most IN status is the same, but ISO can't stall */
1377 +       *ep->reg_udccsr = UDCCSR_PC|UDCCSR_FST|UDCCSR_TRN
1378 +               | (ep->ep_type == USB_ENDPOINT_XFER_ISOC)
1379 +                       ? 0 : UDCCSR_SST;
1380 +}
1381 +
1382 +
1383 +static struct usb_ep_ops pxa27x_ep_ops = {
1384 +       .enable         = pxa27x_ep_enable,
1385 +       .disable        = pxa27x_ep_disable,
1386 +
1387 +       .alloc_request  = pxa27x_ep_alloc_request,
1388 +       .free_request   = pxa27x_ep_free_request,
1389 +
1390 +       .alloc_buffer   = pxa27x_ep_alloc_buffer,
1391 +       .free_buffer    = pxa27x_ep_free_buffer,
1392 +
1393 +       .queue          = pxa27x_ep_queue,
1394 +       .dequeue        = pxa27x_ep_dequeue,
1395 +
1396 +       .set_halt       = pxa27x_ep_set_halt,
1397 +       .fifo_status    = pxa27x_ep_fifo_status,
1398 +       .fifo_flush     = pxa27x_ep_fifo_flush,
1399 +};
1400 +
1401 +
1402 +/* ---------------------------------------------------------------------------
1403 + *     device-scoped parts of the api to the usb controller hardware
1404 + * ---------------------------------------------------------------------------
1405 + */
1406 +
1407 +static inline void validate_fifo_size(struct pxa27x_ep *pxa_ep, u8 bmAttributes)
1408 +{
1409 +       switch (bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) {
1410 +       case USB_ENDPOINT_XFER_CONTROL:
1411 +               pxa_ep->fifo_size = EP0_FIFO_SIZE;
1412 +               break;
1413 +       case USB_ENDPOINT_XFER_ISOC:
1414 +               pxa_ep->fifo_size = ISO_FIFO_SIZE;
1415 +               break;
1416 +       case USB_ENDPOINT_XFER_BULK:
1417 +               pxa_ep->fifo_size = BULK_FIFO_SIZE;
1418 +               break;
1419 +       case USB_ENDPOINT_XFER_INT:
1420 +               pxa_ep->fifo_size = INT_FIFO_SIZE;
1421 +               break;
1422 +       default:
1423 +               break;
1424 +       }
1425 +}
1426 +
1427 +#define NAME_SIZE 18
1428 +struct usb_ep* pxa27x_ep_alloc(struct usb_gadget *gadget, struct usb_endpoint_descriptor *desc, int config, int interface, int alt)
1429 +{
1430 +       u32 tmp ;
1431 +       unsigned i;
1432 +       char* name;
1433 +       struct usb_ep * ep = NULL;
1434 +       struct pxa27x_ep *pxa_ep = NULL;
1435 +       struct pxa27x_udc *dev = the_controller;
1436 +
1437 +       DMSG("pxa27x_config_ep is called\n");
1438 +       DMSG(" usb endpoint descriptor is:\n"
1439 +               "       bLength:%d\n"
1440 +               "       bDescriptorType:%x\n"
1441 +               "       bEndpointAddress:%x\n"
1442 +               "       bmAttributes:%x\n"
1443 +               "       wMaxPacketSize:%d\n",
1444 +               desc->bLength,
1445 +               desc->bDescriptorType,desc->bEndpointAddress,
1446 +               desc->bmAttributes,desc->wMaxPacketSize);
1447 +
1448 +       for (i = 1; i < UDC_EP_NUM; i++) {
1449 +               if(!dev->ep[i].assigned) {
1450 +                       pxa_ep = &dev->ep[i];
1451 +                       pxa_ep->assigned = 1;
1452 +                       pxa_ep->ep_num = i;
1453 +                       break;
1454 +               }
1455 +       }
1456 +       if (unlikely(i == UDC_EP_NUM)) {
1457 +               printk(KERN_ERR __FILE__ ": Failed to find a spare endpoint\n");
1458 +               return ep;
1459 +       }
1460 +
1461 +
1462 +       ep = &pxa_ep->ep;
1463 +
1464 +       pxa_ep->dev = dev;
1465 +       pxa_ep->desc = desc;
1466 +       pxa_ep->pio_irqs = pxa_ep->dma_irqs = 0;
1467 +       pxa_ep->dma = -1;
1468 +
1469 +       if (!(desc->bEndpointAddress & 0xF))
1470 +               desc->bEndpointAddress |= i;
1471 +
1472 +       if (!(desc->wMaxPacketSize)) {
1473 +               validate_fifo_size(pxa_ep, desc->bmAttributes);
1474 +               desc->wMaxPacketSize = pxa_ep->fifo_size;
1475 +       } else
1476 +               pxa_ep->fifo_size = desc->wMaxPacketSize;
1477 +
1478 +       pxa_ep->dir_in = (desc->bEndpointAddress & USB_DIR_IN) ? 1 : 0;
1479 +       pxa_ep->ep_type = desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK;
1480 +       pxa_ep->stopped = 1;
1481 +       pxa_ep->dma_con = 0;
1482 +       pxa_ep->config = config;
1483 +       pxa_ep->interface = interface;
1484 +       pxa_ep->aisn = alt;
1485 +
1486 +       pxa_ep->reg_udccsr = &UDCCSR0 + i;
1487 +       pxa_ep->reg_udcbcr = &UDCBCR0 + i;
1488 +       pxa_ep->reg_udcdr = &UDCDR0 + i ;
1489 +       pxa_ep->reg_udccr = &UDCCRA - 1 + i;
1490 +#ifdef USE_DMA
1491 +       pxa_ep->reg_drcmr = &DRCMR24 + i;
1492 +#endif
1493 +
1494 +       DMSG("udccsr=0x%8x, udcbcr=0x%8x, udcdr=0x%8x,"
1495 +                       "udccr0=0x%8x\n",
1496 +                       (unsigned)pxa_ep->reg_udccsr,
1497 +                       (unsigned)pxa_ep->reg_udcbcr,
1498 +                       (unsigned)pxa_ep->reg_udcdr,
1499 +                       (unsigned)pxa_ep->reg_udccr);
1500 +
1501 +       /* Configure UDCCR */
1502 +       tmp = 0;
1503 +       tmp |= (pxa_ep->config << UDCCONR_CN_S) & UDCCONR_CN;
1504 +#if 0
1505 +       tmp |= (pxa_ep->interface << UDCCONR_IN_S) & UDCCONR_IN;
1506 +       tmp |= (pxa_ep->aisn << UDCCONR_AISN_S) & UDCCONR_AISN;
1507 +#else
1508 +       tmp |= (0 << UDCCONR_IN_S) & UDCCONR_IN;
1509 +       tmp |= (0 << UDCCONR_AISN_S) & UDCCONR_AISN;
1510 +#endif
1511 +       tmp |= (desc->bEndpointAddress << UDCCONR_EN_S) & UDCCONR_EN;
1512 +       tmp |= (pxa_ep->ep_type << UDCCONR_ET_S) & UDCCONR_ET;
1513 +       tmp |= (pxa_ep->dir_in) ? UDCCONR_ED : 0;
1514 +       tmp |= (min(pxa_ep->fifo_size,  (unsigned)desc->wMaxPacketSize) \
1515 +                       << UDCCONR_MPS_S ) & UDCCONR_MPS;
1516 +       tmp |= UDCCONR_DE | UDCCONR_EE;
1517 +//     tmp |= UDCCONR_EE;
1518 +
1519 +       *pxa_ep->reg_udccr = tmp;
1520 +
1521 +#ifdef USE_DMA
1522 +       /* Only BULK use DMA */
1523 +       if ((pxa_ep->ep_type & USB_ENDPOINT_XFERTYPE_MASK)\
1524 +                       == USB_ENDPOINT_XFER_BULK)
1525 +               *pxa_ep->reg_udccsr = UDCCSR_DME;
1526 +#endif
1527 +
1528 +       DMSG("UDCCR: 0x%p is 0x%x\n", pxa_ep->reg_udccr,*pxa_ep->reg_udccr);
1529 +
1530 +       /* Fill ep name*/
1531 +       name = kmalloc(NAME_SIZE, GFP_KERNEL);
1532 +       if (!name) {
1533 +               printk(KERN_ERR "%s: Error\n", __FUNCTION__);
1534 +               return NULL;
1535 +       }
1536 +
1537 +       switch (pxa_ep->ep_type) {
1538 +       case USB_ENDPOINT_XFER_BULK:
1539 +               sprintf(name, "Bulk-%s-%d", (pxa_ep->dir_in ? "in":"out"), i);
1540 +               break;
1541 +       case USB_ENDPOINT_XFER_INT:
1542 +               sprintf(name, "Interrupt-%s-%d", (pxa_ep->dir_in ? \
1543 +                               "in":"out"), i);
1544 +               break;
1545 +       default:
1546 +               sprintf(name, "endpoint-%s-%d", (pxa_ep->dir_in ? \
1547 +                               "in":"out"), i);
1548 +               break;
1549 +       }
1550 +       ep->name = name;
1551 +
1552 +       ep->ops = &pxa27x_ep_ops;
1553 +       ep->maxpacket = min((ushort)pxa_ep->fifo_size, desc->wMaxPacketSize);
1554 +
1555 +       list_add_tail (&ep->ep_list, &gadget->ep_list);
1556 +       return ep;
1557 +}
1558 +
1559 +static int pxa27x_udc_get_frame(struct usb_gadget *_gadget)
1560 +{
1561 +       return (UDCFNR & 0x3FF);
1562 +}
1563 +
1564 +static int pxa27x_udc_wakeup(struct usb_gadget *_gadget)
1565 +{
1566 +       /* host may not have enabled remote wakeup */
1567 +       if ((UDCCR & UDCCR_DWRE) == 0)
1568 +               return -EHOSTUNREACH;
1569 +       udc_set_mask_UDCCR(UDCCR_UDR);
1570 +       return 0;
1571 +}
1572 +
1573 +static const struct usb_gadget_ops pxa27x_udc_ops = {
1574 +       .ep_alloc        = pxa27x_ep_alloc,
1575 +       .get_frame       = pxa27x_udc_get_frame,
1576 +       .wakeup          = pxa27x_udc_wakeup,
1577 +       // current versions must always be self-powered
1578 +};
1579 +
1580 +
1581 +/*-------------------------------------------------------------------------*/
1582 +
1583 +#ifdef UDC_PROC_FILE
1584 +
1585 +static const char proc_node_name [] = "driver/udc";
1586 +
1587 +static int
1588 +udc_proc_read(char *page, char **start, off_t off, int count,
1589 +               int *eof, void *_dev)
1590 +{
1591 +       char                    *buf = page;
1592 +       struct pxa27x_udc       *dev = _dev;
1593 +       char                    *next = buf;
1594 +       unsigned                size = count;
1595 +       unsigned long           flags;
1596 +       int                     i, t;
1597 +       u32                     tmp;
1598 +
1599 +       if (off != 0)
1600 +               return 0;
1601 +
1602 +       local_irq_save(flags);
1603 +
1604 +       /* basic device status */
1605 +       t = scnprintf(next, size, DRIVER_DESC "\n"
1606 +               "%s version: %s\nGadget driver: %s\n",
1607 +               driver_name, DRIVER_VERSION SIZE_STR DMASTR,
1608 +               dev->driver ? dev->driver->driver.name : "(none)");
1609 +       size -= t;
1610 +       next += t;
1611 +
1612 +       /* registers for device and ep0 */
1613 +       t = scnprintf(next, size,
1614 +               "uicr %02X.%02X, usir %02X.%02x, ufnr %02X\n",
1615 +               UDCICR1, UDCICR0, UDCISR1, UDCISR0, UDCFNR);
1616 +       size -= t;
1617 +       next += t;
1618 +
1619 +       tmp = UDCCR;
1620 +       t = scnprintf(next, size,"udccr %02X =%s%s%s%s%s%s%s%s%s%s, con=%d,inter=%d,altinter=%d\n", tmp,
1621 +               (tmp & UDCCR_OEN) ? " oen":"",
1622 +               (tmp & UDCCR_AALTHNP) ? " aalthnp":"",
1623 +               (tmp & UDCCR_AHNP) ? " rem" : "",
1624 +               (tmp & UDCCR_BHNP) ? " rstir" : "",
1625 +               (tmp & UDCCR_DWRE) ? " dwre" : "",
1626 +               (tmp & UDCCR_SMAC) ? " smac" : "",
1627 +               (tmp & UDCCR_EMCE) ? " emce" : "",
1628 +               (tmp & UDCCR_UDR) ? " udr" : "",
1629 +               (tmp & UDCCR_UDA) ? " uda" : "",
1630 +               (tmp & UDCCR_UDE) ? " ude" : "",
1631 +               (tmp & UDCCR_ACN) >> UDCCR_ACN_S,
1632 +               (tmp & UDCCR_AIN) >> UDCCR_AIN_S,
1633 +               (tmp & UDCCR_AAISN)>> UDCCR_AAISN_S );
1634 +
1635 +       size -= t;
1636 +       next += t;
1637 +
1638 +       tmp = UDCCSR0;
1639 +       t = scnprintf(next, size,
1640 +               "udccsr0 %02X =%s%s%s%s%s%s%s\n", tmp,
1641 +               (tmp & UDCCSR0_SA) ? " sa" : "",
1642 +               (tmp & UDCCSR0_RNE) ? " rne" : "",
1643 +               (tmp & UDCCSR0_FST) ? " fst" : "",
1644 +               (tmp & UDCCSR0_SST) ? " sst" : "",
1645 +               (tmp & UDCCSR0_DME) ? " dme" : "",
1646 +               (tmp & UDCCSR0_IPR) ? " ipr" : "",
1647 +               (tmp & UDCCSR0_OPC) ? " opc" : "");
1648 +       size -= t;
1649 +       next += t;
1650 +
1651 +       if (!dev->driver)
1652 +               goto done;
1653 +
1654 +       t = scnprintf(next, size, "ep0 IN %lu/%lu, OUT %lu/%lu\nirqs %lu\n\n",
1655 +               dev->stats.write.bytes, dev->stats.write.ops,
1656 +               dev->stats.read.bytes, dev->stats.read.ops,
1657 +               dev->stats.irqs);
1658 +       size -= t;
1659 +       next += t;
1660 +
1661 +       /* dump endpoint queues */
1662 +       for (i = 0; i < UDC_EP_NUM; i++) {
1663 +               struct pxa27x_ep        *ep = &dev->ep [i];
1664 +               struct pxa27x_request   *req;
1665 +               int                     t;
1666 +
1667 +               if (i != 0) {
1668 +                       const struct usb_endpoint_descriptor    *d;
1669 +
1670 +                       d = ep->desc;
1671 +                       if (!d)
1672 +                               continue;
1673 +                       tmp = *dev->ep [i].reg_udccsr;
1674 +                       t = scnprintf(next, size,
1675 +                               "%s max %d %s udccs %02x udccr:0x%x\n",
1676 +                               ep->ep.name, le16_to_cpu (d->wMaxPacketSize),
1677 +                               (ep->dma >= 0) ? "dma" : "pio", tmp,
1678 +                               *dev->ep[i].reg_udccr);
1679 +                       /* TODO translate all five groups of udccs bits! */
1680 +
1681 +               } else /* ep0 should only have one transfer queued */
1682 +                       t = scnprintf(next, size, "ep0 max 16 pio irqs %lu\n",
1683 +                               ep->pio_irqs);
1684 +               if (t <= 0 || t > size)
1685 +                       goto done;
1686 +               size -= t;
1687 +               next += t;
1688 +
1689 +               if (list_empty(&ep->queue)) {
1690 +                       t = scnprintf(next, size, "\t(nothing queued)\n");
1691 +                       if (t <= 0 || t > size)
1692 +                               goto done;
1693 +                       size -= t;
1694 +                       next += t;
1695 +                       continue;
1696 +               }
1697 +               list_for_each_entry(req, &ep->queue, queue) {
1698 +#ifdef USE_DMA
1699 +                       if (ep->dma >= 0 && req->queue.prev == &ep->queue)
1700 +                               t = scnprintf(next, size,
1701 +                                       "\treq %p len %d/%d "
1702 +                                       "buf %p (dma%d dcmd %08x)\n",
1703 +                                       &req->req, req->req.actual,
1704 +                                       req->req.length, req->req.buf,
1705 +                                       ep->dma, DCMD(ep->dma)
1706 +                                       // low 13 bits == bytes-to-go
1707 +                                       );
1708 +                       else
1709 +#endif
1710 +                               t = scnprintf(next, size,
1711 +                                       "\treq %p len %d/%d buf %p\n",
1712 +                                       &req->req, req->req.actual,
1713 +                                       req->req.length, req->req.buf);
1714 +                       if (t <= 0 || t > size)
1715 +                               goto done;
1716 +                       size -= t;
1717 +                       next += t;
1718 +               }
1719 +       }
1720 +
1721 +done:
1722 +       local_irq_restore(flags);
1723 +       *eof = 1;
1724 +       return count - size;
1725 +}
1726 +
1727 +#define create_proc_files() \
1728 +       create_proc_read_entry(proc_node_name, 0, NULL, udc_proc_read, dev)
1729 +#define remove_proc_files() \
1730 +       remove_proc_entry(proc_node_name, NULL)
1731 +
1732 +#else  /* !UDC_PROC_FILE */
1733 +#define create_proc_files() do {} while (0)
1734 +#define remove_proc_files() do {} while (0)
1735 +
1736 +#endif /* UDC_PROC_FILE */
1737 +
1738 +/* "function" sysfs attribute */
1739 +static ssize_t
1740 +show_function (struct device *_dev, struct device_attribute *attr, char *buf)
1741 +{
1742 +       struct pxa27x_udc       *dev = dev_get_drvdata (_dev);
1743 +
1744 +       if (!dev->driver
1745 +                       || !dev->driver->function
1746 +                       || strlen (dev->driver->function) > PAGE_SIZE)
1747 +               return 0;
1748 +       return scnprintf (buf, PAGE_SIZE, "%s\n", dev->driver->function);
1749 +}
1750 +static DEVICE_ATTR (function, S_IRUGO, show_function, NULL);
1751 +
1752 +/*-------------------------------------------------------------------------*/
1753 +
1754 +/*
1755 + *     udc_disable - disable USB device controller
1756 + */
1757 +static void udc_disable(struct pxa27x_udc *dev)
1758 +{
1759 +       UDCICR0 = UDCICR1 = 0x00000000;
1760 +
1761 +       udc_clear_mask_UDCCR(UDCCR_UDE);
1762 +
1763 +        /* Disable clock for USB device */
1764 +       pxa_set_cken(CKEN11_USB, 0);
1765 +
1766 +       ep0_idle (dev);
1767 +       dev->gadget.speed = USB_SPEED_UNKNOWN;
1768 +
1769 +       if (dev->mach->gpio_pullup)
1770 +               GPCR(dev->mach->gpio_pullup) = GPIO_bit(dev->mach->gpio_pullup);
1771 +       if (dev->mach->udc_command)
1772 +               dev->mach->udc_command(PXA2XX_UDC_CMD_DISCONNECT);
1773 +
1774 +       make_usb_disappear();
1775 +}
1776 +
1777 +
1778 +/*
1779 + *     udc_reinit - initialize software state
1780 + */
1781 +static void udc_reinit(struct pxa27x_udc *dev)
1782 +{
1783 +       u32     i;
1784 +
1785 +       dev->ep0state = EP0_IDLE;
1786 +
1787 +       /* basic endpoint records init */
1788 +       for (i = 0; i < UDC_EP_NUM; i++) {
1789 +               struct pxa27x_ep *ep = &dev->ep[i];
1790 +
1791 +               ep->stopped = 0;
1792 +               ep->pio_irqs = ep->dma_irqs = 0;
1793 +       }
1794 +       dev->configuration = 0;
1795 +       dev->interface = 0;
1796 +       dev->alternate = 0;
1797 +       /* the rest was statically initialized, and is read-only */
1798 +}
1799 +
1800 +/* until it's enabled, this UDC should be completely invisible
1801 + * to any USB host.
1802 + */
1803 +static void udc_enable (struct pxa27x_udc *dev)
1804 +{
1805 +       udc_clear_mask_UDCCR(UDCCR_UDE);
1806 +
1807 +        /* Enable clock for USB device */
1808 +       pxa_set_cken(CKEN11_USB, 1);
1809 +
1810 +       UDCICR0 = UDCICR1 = 0;
1811 +
1812 +       ep0_idle(dev);
1813 +       dev->gadget.speed = USB_SPEED_FULL;
1814 +       dev->stats.irqs = 0;
1815 +
1816 +       udc_set_mask_UDCCR(UDCCR_UDE);
1817 +       udelay (2);
1818 +       if (UDCCR & UDCCR_EMCE)
1819 +       {
1820 +               printk(KERN_ERR ": There are error in configuration, udc disabled\n");
1821 +       }
1822 +
1823 +       /* caller must be able to sleep in order to cope
1824 +        * with startup transients.
1825 +        */
1826 +       msleep(100);
1827 +
1828 +       /* enable suspend/resume and reset irqs */
1829 +       UDCICR1 = UDCICR1_IECC | UDCICR1_IERU | UDCICR1_IESU | UDCICR1_IERS;
1830 +
1831 +       /* enable ep0 irqs */
1832 +       UDCICR0 = UDCICR_INT(0,UDCICR_INT_MASK);
1833 +#if 0
1834 +       for(i=1; i < UDC_EP_NUM; i++) {
1835 +               if (dev->ep[i].assigned)
1836 +                       pio_irq_enable(i);
1837 +       }
1838 +#endif
1839 +
1840 +       if (dev->mach->gpio_pullup)
1841 +               GPSR(dev->mach->gpio_pullup) = GPIO_bit(dev->mach->gpio_pullup);
1842 +       if (dev->mach->udc_command)
1843 +               dev->mach->udc_command(PXA2XX_UDC_CMD_CONNECT);
1844 +
1845 +       /* FIXME */
1846 +       let_usb_appear();
1847 +}
1848 +
1849 +
1850 +/* when a driver is successfully registered, it will receive
1851 + * control requests including set_configuration(), which enables
1852 + * non-control requests.  then usb traffic follows until a
1853 + * disconnect is reported.  then a host may connect again, or
1854 + * the driver might get unbound.
1855 + */
1856 +int usb_gadget_register_driver(struct usb_gadget_driver *driver)
1857 +{
1858 +       struct pxa27x_udc       *dev = the_controller;
1859 +       int                     retval;
1860 +
1861 +       DMSG("dev=0x%x, driver=0x%x, speed=%d, "
1862 +                       "bind=0x%x, unbind=0x%x, disconnect=0x%x, setup=0x%x\n",
1863 +                       (unsigned)dev, (unsigned)driver, driver->speed,
1864 +                       (unsigned)driver->bind, (unsigned)driver->unbind,
1865 +                       (unsigned)driver->disconnect, (unsigned)driver->setup);
1866 +
1867 +       if (!driver     || driver->speed != USB_SPEED_FULL
1868 +                       || !driver->bind
1869 +                       || !driver->unbind
1870 +                       || !driver->disconnect
1871 +                       || !driver->setup)
1872 +               return -EINVAL;
1873 +       if (!dev)
1874 +               return -ENODEV;
1875 +       if (dev->driver)
1876 +               return -EBUSY;
1877 +
1878 +       /* first hook up the driver ... */
1879 +       dev->driver = driver;
1880 +       dev->gadget.dev.driver = &driver->driver;
1881 +
1882 +       device_add(&dev->gadget.dev);
1883 +       retval = driver->bind(&dev->gadget);
1884 +       if (retval) {
1885 +               DMSG("bind to driver %s --> error %d\n",
1886 +                               driver->driver.name, retval);
1887 +               device_del (&dev->gadget.dev);
1888 +
1889 +               dev->driver = 0;
1890 +               dev->gadget.dev.driver = 0;
1891 +               return retval;
1892 +       }
1893 +       device_create_file(dev->dev, &dev_attr_function);
1894 +
1895 +       /* ... then enable host detection and ep0; and we're ready
1896 +        * for set_configuration as well as eventual disconnect.
1897 +        * NOTE:  this shouldn't power up until later.
1898 +        */
1899 +       DMSG("registered gadget driver '%s'\n", driver->driver.name);
1900 +       udc_enable(dev);
1901 +       dump_state(dev);
1902 +       return 0;
1903 +}
1904 +EXPORT_SYMBOL(usb_gadget_register_driver);
1905 +
1906 +static void
1907 +stop_activity(struct pxa27x_udc *dev, struct usb_gadget_driver *driver)
1908 +{
1909 +       int i;
1910 +
1911 +       DMSG("Trace path 1\n");
1912 +       /* don't disconnect drivers more than once */
1913 +       if (dev->gadget.speed == USB_SPEED_UNKNOWN)
1914 +               driver = 0;
1915 +       dev->gadget.speed = USB_SPEED_UNKNOWN;
1916 +
1917 +       /* prevent new request submissions, kill any outstanding requests  */
1918 +       for (i = 0; i < UDC_EP_NUM; i++) {
1919 +               struct pxa27x_ep *ep = &dev->ep[i];
1920 +
1921 +               ep->stopped = 1;
1922 +               nuke(ep, -ESHUTDOWN);
1923 +       }
1924 +       del_timer_sync(&dev->timer);
1925 +
1926 +       /* report disconnect; the driver is already quiesced */
1927 +       if (driver)
1928 +               driver->disconnect(&dev->gadget);
1929 +
1930 +       /* re-init driver-visible data structures */
1931 +       udc_reinit(dev);
1932 +}
1933 +
1934 +int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
1935 +{
1936 +       struct pxa27x_udc       *dev = the_controller;
1937 +
1938 +       if (!dev)
1939 +               return -ENODEV;
1940 +       if (!driver || driver != dev->driver)
1941 +               return -EINVAL;
1942 +
1943 +       local_irq_disable();
1944 +       udc_disable(dev);
1945 +       stop_activity(dev, driver);
1946 +       local_irq_enable();
1947 +
1948 +       driver->unbind(&dev->gadget);
1949 +       dev->driver = 0;
1950 +
1951 +       device_del (&dev->gadget.dev);
1952 +       device_remove_file(dev->dev, &dev_attr_function);
1953 +
1954 +       DMSG("unregistered gadget driver '%s'\n", driver->driver.name);
1955 +       dump_state(dev);
1956 +       return 0;
1957 +}
1958 +EXPORT_SYMBOL(usb_gadget_unregister_driver);
1959 +
1960 +#ifndef        enable_disconnect_irq
1961 +#define        enable_disconnect_irq()         do {} while (0)
1962 +#define        disable_disconnect_irq()        do {} while (0)
1963 +#endif
1964 +
1965 +
1966 +/*-------------------------------------------------------------------------*/
1967 +
1968 +static inline void clear_ep_state (struct pxa27x_udc *dev)
1969 +{
1970 +       unsigned i;
1971 +
1972 +       /* hardware SET_{CONFIGURATION,INTERFACE} automagic resets endpoint
1973 +        * fifos, and pending transactions mustn't be continued in any case.
1974 +        */
1975 +       for (i = 1; i < UDC_EP_NUM; i++)
1976 +               nuke(&dev->ep[i], -ECONNABORTED);
1977 +}
1978 +
1979 +static void udc_watchdog(unsigned long _dev)
1980 +{
1981 +       struct pxa27x_udc       *dev = (void *)_dev;
1982 +
1983 +       local_irq_disable();
1984 +       if (dev->ep0state == EP0_STALL
1985 +                       && (UDCCSR0 & UDCCSR0_FST) == 0
1986 +                       && (UDCCSR0 & UDCCSR0_SST) == 0) {
1987 +               UDCCSR0 = UDCCSR0_FST|UDCCSR0_FTF;
1988 +               DBG(DBG_VERBOSE, "ep0 re-stall\n");
1989 +               start_watchdog(dev);
1990 +       }
1991 +       local_irq_enable();
1992 +}
1993 +
1994 +static void handle_ep0 (struct pxa27x_udc *dev)
1995 +{
1996 +       u32                     udccsr0 = UDCCSR0;
1997 +       struct pxa27x_ep        *ep = &dev->ep [0];
1998 +       struct pxa27x_request   *req;
1999 +       union {
2000 +               struct usb_ctrlrequest  r;
2001 +               u8                      raw [8];
2002 +               u32                     word [2];
2003 +       } u;
2004 +
2005 +       if (list_empty(&ep->queue))
2006 +               req = 0;
2007 +       else
2008 +               req = list_entry(ep->queue.next, struct pxa27x_request, queue);
2009 +
2010 +       /* clear stall status */
2011 +       if (udccsr0 & UDCCSR0_SST) {
2012 +               nuke(ep, -EPIPE);
2013 +               UDCCSR0 = UDCCSR0_SST;
2014 +               del_timer(&dev->timer);
2015 +               ep0_idle(dev);
2016 +       }
2017 +
2018 +       /* previous request unfinished?  non-error iff back-to-back ... */
2019 +       if ((udccsr0 & UDCCSR0_SA) != 0 && dev->ep0state != EP0_IDLE) {
2020 +               nuke(ep, 0);
2021 +               del_timer(&dev->timer);
2022 +               ep0_idle(dev);
2023 +       }
2024 +
2025 +       switch (dev->ep0state) {
2026 +       case EP0_NO_ACTION:
2027 +               printk(KERN_INFO"%s: Busy\n", __FUNCTION__);
2028 +               /*Fall through */
2029 +       case EP0_IDLE:
2030 +               /* late-breaking status? */
2031 +               udccsr0 = UDCCSR0;
2032 +
2033 +               /* start control request? */
2034 +               if (likely((udccsr0 & (UDCCSR0_OPC|UDCCSR0_SA|UDCCSR0_RNE))
2035 +                               == (UDCCSR0_OPC|UDCCSR0_SA|UDCCSR0_RNE))) {
2036 +                       int i;
2037 +
2038 +                       nuke (ep, -EPROTO);
2039 +                       /* read SETUP packet */
2040 +                       for (i = 0; i < 2; i++) {
2041 +                               if (unlikely(!(UDCCSR0 & UDCCSR0_RNE))) {
2042 +bad_setup:
2043 +                                       DMSG("SETUP %d!\n", i);
2044 +                                       goto stall;
2045 +                               }
2046 +                               u.word [i] =  UDCDR0;
2047 +                       }
2048 +                       if (unlikely((UDCCSR0 & UDCCSR0_RNE) != 0))
2049 +                               goto bad_setup;
2050 +
2051 +                       le16_to_cpus (&u.r.wValue);
2052 +                       le16_to_cpus (&u.r.wIndex);
2053 +                       le16_to_cpus (&u.r.wLength);
2054 +
2055 +                       LED_EP0_ON;
2056 +
2057 +                       DBG(DBG_VERBOSE, "SETUP %02x.%02x v%04x i%04x l%04x\n",
2058 +                               u.r.bRequestType, u.r.bRequest,
2059 +                               u.r.wValue, u.r.wIndex, u.r.wLength);
2060 +                       /* cope with automagic for some standard requests. */
2061 +                       dev->req_std = (u.r.bRequestType & USB_TYPE_MASK)
2062 +                                               == USB_TYPE_STANDARD;
2063 +                       dev->req_config = 0;
2064 +                       dev->req_pending = 1;
2065 +#if 0
2066 +                       switch (u.r.bRequest) {
2067 +                       /* hardware was supposed to hide this */
2068 +                       case USB_REQ_SET_CONFIGURATION:
2069 +                       case USB_REQ_SET_INTERFACE:
2070 +                       case USB_REQ_SET_ADDRESS:
2071 +                               printk(KERN_ERR "Should not come here\n");
2072 +                               break;
2073 +                       }
2074 +
2075 +#endif
2076 +                       if (u.r.bRequestType & USB_DIR_IN)
2077 +                               dev->ep0state = EP0_IN_DATA_PHASE;
2078 +                       else
2079 +                               dev->ep0state = EP0_OUT_DATA_PHASE;
2080 +                       i = dev->driver->setup(&dev->gadget, &u.r);
2081 +
2082 +                       if (i < 0) {
2083 +                               /* hardware automagic preventing STALL... */
2084 +                               if (dev->req_config) {
2085 +                                       /* hardware sometimes neglects to tell
2086 +                                        * tell us about config change events,
2087 +                                        * so later ones may fail...
2088 +                                        */
2089 +                                       WARN("config change %02x fail %d?\n",
2090 +                                               u.r.bRequest, i);
2091 +                                       return;
2092 +                                       /* TODO experiment:  if has_cfr,
2093 +                                        * hardware didn't ACK; maybe we
2094 +                                        * could actually STALL!
2095 +                                        */
2096 +                               }
2097 +                               DBG(DBG_VERBOSE, "protocol STALL, "
2098 +                                       "%02x err %d\n", UDCCSR0, i);
2099 +stall:
2100 +                               /* the watchdog timer helps deal with cases
2101 +                                * where udc seems to clear FST wrongly, and
2102 +                                * then NAKs instead of STALLing.
2103 +                                */
2104 +                               ep0start(dev, UDCCSR0_FST|UDCCSR0_FTF, "stall");
2105 +                               start_watchdog(dev);
2106 +                               dev->ep0state = EP0_STALL;
2107 +                               LED_EP0_OFF;
2108 +
2109 +                       /* deferred i/o == no response yet */
2110 +                       } else if (dev->req_pending) {
2111 +                               if (likely(dev->ep0state == EP0_IN_DATA_PHASE
2112 +                                               || dev->req_std || u.r.wLength))
2113 +                                       ep0start(dev, 0, "defer");
2114 +                               else
2115 +                                       ep0start(dev, UDCCSR0_IPR, "defer/IPR");
2116 +                       }
2117 +
2118 +                       /* expect at least one data or status stage irq */
2119 +                       return;
2120 +
2121 +               } else {
2122 +                       /* some random early IRQ:
2123 +                        * - we acked FST
2124 +                        * - IPR cleared
2125 +                        * - OPC got set, without SA (likely status stage)
2126 +                        */
2127 +                       UDCCSR0 = udccsr0 & (UDCCSR0_SA|UDCCSR0_OPC);
2128 +               }
2129 +               break;
2130 +       case EP0_IN_DATA_PHASE:                 /* GET_DESCRIPTOR etc */
2131 +               if (udccsr0 & UDCCSR0_OPC) {
2132 +                       UDCCSR0 = UDCCSR0_OPC|UDCCSR0_FTF;
2133 +                       DBG(DBG_VERBOSE, "ep0in premature status\n");
2134 +                       if (req)
2135 +                               done(ep, req, 0);
2136 +                       ep0_idle(dev);
2137 +               } else /* irq was IPR clearing */ {
2138 +                       if (req) {
2139 +                               /* this IN packet might finish the request */
2140 +                               (void) write_ep0_fifo(ep, req);
2141 +                       } /* else IN token before response was written */
2142 +               }
2143 +               break;
2144 +       case EP0_OUT_DATA_PHASE:                /* SET_DESCRIPTOR etc */
2145 +               if (udccsr0 & UDCCSR0_OPC) {
2146 +                       if (req) {
2147 +                               /* this OUT packet might finish the request */
2148 +                               if (read_ep0_fifo(ep, req))
2149 +                                       done(ep, req, 0);
2150 +                               /* else more OUT packets expected */
2151 +                       } /* else OUT token before read was issued */
2152 +               } else /* irq was IPR clearing */ {
2153 +                       DBG(DBG_VERBOSE, "ep0out premature status\n");
2154 +                       if (req)
2155 +                               done(ep, req, 0);
2156 +                       ep0_idle(dev);
2157 +               }
2158 +               break;
2159 +       case EP0_STALL:
2160 +               UDCCSR0 = UDCCSR0_FST;
2161 +               break;
2162 +               }
2163 +       UDCISR0 = UDCISR_INT(0, UDCISR_INT_MASK);
2164 +}
2165 +
2166 +
2167 +static void handle_ep(struct pxa27x_ep *ep)
2168 +{
2169 +       struct pxa27x_request   *req;
2170 +       int                     completed;
2171 +       u32                     udccsr=0;
2172 +
2173 +       DMSG("%s is called\n", __FUNCTION__);
2174 +       do {
2175 +               completed = 0;
2176 +               if (likely (!list_empty(&ep->queue))) {
2177 +                       req = list_entry(ep->queue.next,
2178 +                                       struct pxa27x_request, queue);
2179 +               } else
2180 +                       req = 0;
2181 +
2182 +//             udccsr = *ep->reg_udccsr;
2183 +               DMSG("%s: req:%p, udcisr0:0x%x udccsr %p:0x%x\n", __FUNCTION__,
2184 +                               req, UDCISR0, ep->reg_udccsr, *ep->reg_udccsr);
2185 +               if (unlikely(ep->dir_in)) {
2186 +                       udccsr = (UDCCSR_SST | UDCCSR_TRN) & *ep->reg_udccsr;
2187 +                       if (unlikely (udccsr))
2188 +                               *ep->reg_udccsr = udccsr;
2189 +
2190 +                       if (req && likely ((*ep->reg_udccsr & UDCCSR_FS) != 0))
2191 +                               completed = write_fifo(ep, req);
2192 +
2193 +               } else {
2194 +                       udccsr = (UDCCSR_SST | UDCCSR_TRN) & *ep->reg_udccsr;
2195 +                       if (unlikely(udccsr))
2196 +                               *ep->reg_udccsr = udccsr;
2197 +
2198 +                       /* fifos can hold packets, ready for reading... */
2199 +                       if (likely(req)) {
2200 +                               completed = read_fifo(ep, req);
2201 +                       } else {
2202 +                               pio_irq_disable (ep->ep_num);
2203 +                               *ep->reg_udccsr = UDCCSR_FEF;
2204 +                               DMSG("%s: no req for out data\n",
2205 +                                               __FUNCTION__);
2206 +                       }
2207 +               }
2208 +               ep->pio_irqs++;
2209 +       } while (completed);
2210 +}
2211 +
2212 +static void pxa27x_change_configuration (struct pxa27x_udc *dev)
2213 +{
2214 +       struct usb_ctrlrequest req ;
2215 +
2216 +       req.bRequestType = 0;
2217 +       req.bRequest = USB_REQ_SET_CONFIGURATION;
2218 +       req.wValue = dev->configuration;
2219 +       req.wIndex = 0;
2220 +       req.wLength = 0;
2221 +
2222 +       dev->ep0state = EP0_NO_ACTION;
2223 +       dev->driver->setup(&dev->gadget, &req);
2224 +
2225 +}
2226 +
2227 +static void pxa27x_change_interface (struct pxa27x_udc *dev)
2228 +{
2229 +       struct usb_ctrlrequest  req;
2230 +
2231 +       req.bRequestType = USB_RECIP_INTERFACE;
2232 +       req.bRequest = USB_REQ_SET_INTERFACE;
2233 +       req.wValue = dev->alternate;
2234 +       req.wIndex = dev->interface;
2235 +       req.wLength = 0;
2236 +
2237 +       dev->ep0state = EP0_NO_ACTION;
2238 +       dev->driver->setup(&dev->gadget, &req);
2239 +}
2240 +
2241 +/*
2242 + *     pxa27x_udc_irq - interrupt handler
2243 + *
2244 + * avoid delays in ep0 processing. the control handshaking isn't always
2245 + * under software control (pxa250c0 and the pxa255 are better), and delays
2246 + * could cause usb protocol errors.
2247 + */
2248 +static irqreturn_t pxa27x_udc_irq(int irq, void *_dev)
2249 +{
2250 +       struct pxa27x_udc       *dev = _dev;
2251 +       int                     handled;
2252 +
2253 +       dev->stats.irqs++;
2254 +       HEX_DISPLAY(dev->stats.irqs);
2255 +
2256 +       DBG(DBG_VERBOSE, "Interrupt, UDCISR0:0x%08x, UDCISR1:0x%08x, "
2257 +                       "UDCCR:0x%08x\n", UDCISR0, UDCISR1, UDCCR);
2258 +
2259 +       do {
2260 +               u32 udcir = UDCISR1 & 0xF8000000;
2261 +
2262 +               handled = 0;
2263 +
2264 +               /* SUSpend Interrupt Request */
2265 +               if (unlikely(udcir & UDCISR1_IRSU)) {
2266 +                       UDCISR1 = UDCISR1_IRSU;
2267 +                       handled = 1;
2268 +                       DBG(DBG_VERBOSE, "USB suspend\n");
2269 +                       if (dev->gadget.speed != USB_SPEED_UNKNOWN
2270 +                                       && dev->driver
2271 +                                       && dev->driver->suspend)
2272 +                               dev->driver->suspend(&dev->gadget);
2273 +                       ep0_idle (dev);
2274 +               }
2275 +
2276 +               /* RESume Interrupt Request */
2277 +               if (unlikely(udcir & UDCISR1_IRRU)) {
2278 +                       UDCISR1 = UDCISR1_IRRU;
2279 +                       handled = 1;
2280 +                       DBG(DBG_VERBOSE, "USB resume\n");
2281 +
2282 +                       if (dev->gadget.speed != USB_SPEED_UNKNOWN
2283 +                                       && dev->driver
2284 +                                       && dev->driver->resume)
2285 +                               dev->driver->resume(&dev->gadget);
2286 +               }
2287 +
2288 +               if (unlikely(udcir & UDCISR1_IRCC)) {
2289 +                       unsigned config, interface, alternate;
2290 +
2291 +                       handled = 1;
2292 +                       DBG(DBG_VERBOSE, "USB SET_CONFIGURATION or "
2293 +                               "SET_INTERFACE command received\n");
2294 +
2295 +                       UDCCR |= UDCCR_SMAC;
2296 +
2297 +                       config = (UDCCR & UDCCR_ACN) >> UDCCR_ACN_S;
2298 +
2299 +                       if (dev->configuration != config) {
2300 +                               dev->configuration = config;
2301 +                               pxa27x_change_configuration(dev) ;
2302 +                       }
2303 +
2304 +                       interface =  (UDCCR & UDCCR_AIN) >> UDCCR_AIN_S;
2305 +                       alternate = (UDCCR & UDCCR_AAISN) >> UDCCR_AAISN_S;
2306 +
2307 +                       if ( (dev->configuration != interface) || \
2308 +                                       (dev->alternate != alternate)){
2309 +                               dev->interface = config;
2310 +                               dev->alternate = alternate;
2311 +                               pxa27x_change_interface(dev);
2312 +                       }
2313 +
2314 +                       UDCISR1 = UDCISR1_IRCC;
2315 +                       DMSG("%s: con:%d,inter:%d,alt:%d\n",
2316 +                               __FUNCTION__, config,interface, alternate);
2317 +               }
2318 +
2319 +               /* ReSeT Interrupt Request - USB reset */
2320 +               if (unlikely(udcir & UDCISR1_IRRS)) {
2321 +                       UDCISR1 = UDCISR1_IRRS;
2322 +                       handled = 1;
2323 +
2324 +                       if ((UDCCR & UDCCR_UDA) == 0) {
2325 +                               DBG(DBG_VERBOSE, "SB reset start\n");
2326 +
2327 +                               /* reset driver and endpoints,
2328 +                                * in case that's not yet done
2329 +                                */
2330 +                               stop_activity (dev, dev->driver);
2331 +
2332 +                       }
2333 +                       INFO("USB reset\n");
2334 +                       dev->gadget.speed = USB_SPEED_FULL;
2335 +                       memset(&dev->stats, 0, sizeof dev->stats);
2336 +
2337 +               } else {
2338 +                       u32     udcisr0 = UDCISR0 ;
2339 +                       u32     udcisr1 = UDCISR1 & 0xFFFF;
2340 +                       int     i;
2341 +
2342 +                       if (unlikely (!udcisr0 && !udcisr1))
2343 +                               continue;
2344 +
2345 +                       DBG(DBG_VERY_NOISY, "irq %02x.%02x\n", udcisr1,udcisr0);
2346 +
2347 +                       /* control traffic */
2348 +                       if (udcisr0 & UDCISR0_IR0) {
2349 +                               dev->ep[0].pio_irqs++;
2350 +                               handle_ep0(dev);
2351 +                               handled = 1;
2352 +                       }
2353 +
2354 +                       udcisr0 >>= 2;
2355 +                       /* endpoint data transfers */
2356 +                       for (i = 1; udcisr0!=0 && i < 16; udcisr0>>=2,i++) {
2357 +                               UDCISR0 = UDCISR_INT(i, UDCISR_INT_MASK);
2358 +
2359 +                               if (udcisr0 & UDC_INT_FIFOERROR)
2360 +                                       printk(KERN_ERR" Endpoint %d Fifo error\n", i);
2361 +                               if (udcisr0 & UDC_INT_PACKETCMP) {
2362 +                                       handle_ep(&dev->ep[i]);
2363 +                                       handled = 1;
2364 +                               }
2365 +
2366 +                       }
2367 +
2368 +                       for (i = 0; udcisr1!=0 && i < 8; udcisr1 >>= 2, i++) {
2369 +                               UDCISR1 = UDCISR_INT(i, UDCISR_INT_MASK);
2370 +
2371 +                               if (udcisr1 & UDC_INT_FIFOERROR) {
2372 +                                       printk(KERN_ERR" Endpoint %d fifo error\n", (i+16));
2373 +                               }
2374 +
2375 +                               if (udcisr1 & UDC_INT_PACKETCMP) {
2376 +                                       handle_ep(&dev->ep[i+16]);
2377 +                                       handled = 1;
2378 +                               }
2379 +                       }
2380 +               }
2381 +
2382 +               /* we could also ask for 1 msec SOF (SIR) interrupts */
2383 +
2384 +       } while (handled);
2385 +       return IRQ_HANDLED;
2386 +}
2387 +
2388 +static void udc_init_ep(struct pxa27x_udc *dev)
2389 +{
2390 +       int i;
2391 +
2392 +       INIT_LIST_HEAD (&dev->gadget.ep_list);
2393 +       INIT_LIST_HEAD (&dev->gadget.ep0->ep_list);
2394 +
2395 +       for (i = 0; i < UDC_EP_NUM; i++) {
2396 +               struct pxa27x_ep *ep = &dev->ep[i];
2397 +
2398 +               ep->dma = -1;
2399 +               if (i != 0) {
2400 +                       memset(ep, 0, sizeof(*ep));
2401 +               }
2402 +               INIT_LIST_HEAD (&ep->queue);
2403 +       }
2404 +}
2405 +
2406 +/*-------------------------------------------------------------------------*/
2407 +
2408 +static void nop_release (struct device *dev)
2409 +{
2410 +       DMSG("%s %s\n", __FUNCTION__, dev->bus_id);
2411 +}
2412 +
2413 +/* this uses load-time allocation and initialization (instead of
2414 + * doing it at run-time) to save code, eliminate fault paths, and
2415 + * be more obviously correct.
2416 + */
2417 +static struct pxa27x_udc memory = {
2418 +       .gadget = {
2419 +               .ops            = &pxa27x_udc_ops,
2420 +               .ep0            = &memory.ep[0].ep,
2421 +               .name           = driver_name,
2422 +               .dev = {
2423 +                       .bus_id         = "gadget",
2424 +                       .release        = nop_release,
2425 +               },
2426 +       },
2427 +
2428 +       /* control endpoint */
2429 +       .ep[0] = {
2430 +               .ep = {
2431 +                       .name           = ep0name,
2432 +                       .ops            = &pxa27x_ep_ops,
2433 +                       .maxpacket      = EP0_FIFO_SIZE,
2434 +               },
2435 +               .dev            = &memory,
2436 +               .reg_udccsr     = &UDCCSR0,
2437 +               .reg_udcdr      = &UDCDR0,
2438 +       }
2439 +};
2440 +
2441 +#define CP15R0_VENDOR_MASK     0xffffe000
2442 +
2443 +#define CP15R0_XSCALE_VALUE    0x69054000      /* intel/arm/xscale */
2444 +
2445 +/*
2446 + *     probe - binds to the platform device
2447 + */
2448 +static int pxa27x_udc_probe(struct platform_device *pdev)
2449 +{
2450 +       struct device *dev = &pdev->dev;
2451 +       struct pxa27x_udc *udc = &memory;
2452 +       int retval;
2453 +       u32 chiprev;
2454 +
2455 +       /* insist on Intel/ARM/XScale */
2456 +       asm("mrc%? p15, 0, %0, c0, c0" : "=r" (chiprev));
2457 +       if ((chiprev & CP15R0_VENDOR_MASK) != CP15R0_XSCALE_VALUE) {
2458 +               printk(KERN_ERR "%s: not XScale!\n", driver_name);
2459 +               return -ENODEV;
2460 +       }
2461 +       /* other non-static parts of init */
2462 +       udc->dev = dev;
2463 +       udc->mach = dev->platform_data;
2464 +
2465 +       /* FIXME */
2466 +       if (udc->mach->gpio_pullup)
2467 +               pxa_gpio_mode((udc->mach->gpio_pullup & GPIO_MD_MASK_NR) | \
2468 +                                       GPIO_OUT | GPIO_DFLT_HIGH);
2469 +
2470 +       init_timer(&udc->timer);
2471 +       udc->timer.function = udc_watchdog;
2472 +       udc->timer.data = (unsigned long) udc;
2473 +
2474 +       device_initialize(&udc->gadget.dev);
2475 +       udc->gadget.dev.parent = dev;
2476 +       udc->gadget.dev.dma_mask = dev->dma_mask;
2477 +
2478 +       the_controller = udc;
2479 +       dev_set_drvdata(dev, udc);
2480 +
2481 +       udc_disable(udc);
2482 +       udc_init_ep(udc);
2483 +       udc_reinit(udc);
2484 +
2485 +       /* irq setup after old hardware state is cleaned up */
2486 +       retval = request_irq(IRQ_USB, pxa27x_udc_irq,
2487 +                       SA_INTERRUPT, driver_name, udc);
2488 +       if (retval != 0) {
2489 +               printk(KERN_ERR "%s: can't get irq %i, err %d\n",
2490 +                       driver_name, IRQ_USB, retval);
2491 +               return -EBUSY;
2492 +       }
2493 +       udc->got_irq = 1;
2494 +
2495 +       create_proc_files();
2496 +
2497 +       return 0;
2498 +}
2499 +
2500 +static int pxa27x_udc_remove(struct platform_device *pdev)
2501 +{
2502 +       struct device *dev = &pdev->dev;
2503 +       struct pxa27x_udc *udc = dev->driver_data;
2504 +
2505 +       udc_disable(udc);
2506 +       remove_proc_files();
2507 +       usb_gadget_unregister_driver(udc->driver);
2508 +
2509 +       if (udc->got_irq) {
2510 +               free_irq(IRQ_USB, udc);
2511 +               udc->got_irq = 0;
2512 +       }
2513 +       if (machine_is_lubbock() && udc->got_disc) {
2514 +               free_irq(LUBBOCK_USB_DISC_IRQ, udc);
2515 +               udc->got_disc = 0;
2516 +       }
2517 +       dev_set_drvdata(dev, 0);
2518 +       the_controller = 0;
2519 +       return 0;
2520 +}
2521 +
2522 +#ifdef CONFIG_PM
2523 +static int pxa27x_udc_suspend(struct platform_device *pdev, pm_message_t state)
2524 +{
2525 +       struct device *dev = &pdev->dev;
2526 +       struct pxa27x_udc *udc = dev->driver_data;
2527 +       int i;
2528 +
2529 +       DMSG("%s will go into SUSPEND_POWER_DOWN\n", __FUNCTION__);
2530 +       udc->udccsr0 = UDCCSR0;
2531 +       for(i=1; (i<UDC_EP_NUM); i++) {
2532 +               if (udc->ep[i].assigned) {
2533 +                       struct pxa27x_ep *ep = &udc->ep[i];
2534 +
2535 +                       ep->udccsr_value = *ep->reg_udccsr;
2536 +                       ep->udccr_value = *ep->reg_udccr;
2537 +                       DMSG("EP%d, udccsr:0x%x, udccr:0x%x\n",
2538 +                               i, *ep->reg_udccsr, *ep->reg_udccr);
2539 +               }
2540 +       }
2541 +
2542 +       udc_clear_mask_UDCCR(UDCCR_UDE);
2543 +       pxa_set_cken(CKEN11_USB, 0);
2544 +
2545 +       return 0;
2546 +}
2547 +
2548 +static int pxa27x_udc_resume(struct platform_device *pdev)
2549 +{
2550 +       struct device *dev = &pdev->dev;
2551 +       struct pxa27x_udc *udc = dev->driver_data;
2552 +       int i;
2553 +
2554 +       DMSG("%s: udc resume\n", __FUNCTION__);
2555 +
2556 +       UDCCSR0 = udc->udccsr0 & (UDCCSR0_FST | UDCCSR0_DME);
2557 +       for (i=1; i < UDC_EP_NUM; i++) {
2558 +               if (udc->ep[i].assigned) {
2559 +                       struct pxa27x_ep *ep = &udc->ep[i];
2560 +
2561 +                       *ep->reg_udccsr = ep->udccsr_value;
2562 +                       *ep->reg_udccr = ep->udccr_value;
2563 +                       DMSG("EP%d, udccsr:0x%x, udccr:0x%x\n",
2564 +                               i, *ep->reg_udccsr, *ep->reg_udccr);
2565 +               }
2566 +       }
2567 +       udc_enable(udc);
2568 +       /* OTGPH bit is set when sleep mode is entered.
2569 +        * it indicates that OTG pad is retaining its state.
2570 +        * Upon exit from sleep mode and before clearing OTGPH,
2571 +        * Software must configure the USB OTG pad, UDC, and UHC
2572 +        * to the state they were in before entering sleep mode.*/
2573 +       PSSR  |= PSSR_OTGPH;
2574 +
2575 +       return 0;
2576 +}
2577 +#else
2578 +#define pxa27x_udc_suspend     NULL
2579 +#define pxa27x_udc_resume      NULL
2580 +#endif
2581 +
2582 +/*-------------------------------------------------------------------------*/
2583 +
2584 +static struct platform_driver pxa27x_udc_driver = {
2585 +       .probe          = pxa27x_udc_probe,
2586 +       .remove         = pxa27x_udc_remove,
2587 +       .suspend        = pxa27x_udc_suspend,
2588 +       .resume         = pxa27x_udc_resume,
2589 +       .driver         = {
2590 +               .name           = "pxa2xx-udc",
2591 +       },
2592 +};
2593 +
2594 +static int __init udc_init(void)
2595 +{
2596 +       printk(KERN_INFO "%s: version %s\n", driver_name, DRIVER_VERSION);
2597 +       return platform_driver_register(&pxa27x_udc_driver);
2598 +}
2599 +module_init(udc_init);
2600 +
2601 +static void __exit udc_exit(void)
2602 +{
2603 +       platform_driver_unregister(&pxa27x_udc_driver);
2604 +}
2605 +module_exit(udc_exit);
2606 +
2607 +MODULE_DESCRIPTION(DRIVER_DESC);
2608 +MODULE_AUTHOR("Frank Becker, Robert Schwebel, David Brownell");
2609 +MODULE_LICENSE("GPL");
2610 diff --git a/drivers/usb/gadget/pxa27x_udc.h b/drivers/usb/gadget/pxa27x_udc.h
2611 new file mode 100644
2612 index 0000000..c4b72a2
2613 --- /dev/null
2614 +++ b/drivers/usb/gadget/pxa27x_udc.h
2615 @@ -0,0 +1,329 @@
2616 +/*
2617 + * linux/drivers/usb/gadget/pxa27x_udc.h
2618 + * Intel PXA27x on-chip full speed USB device controller
2619 + *
2620 + * Copyright (C) 2003 Robert Schwebel <r.schwebel@pengutronix.de>, Pengutronix
2621 + * Copyright (C) 2003 David Brownell
2622 + * Copyright (C) 2004 Intel Corporation
2623 + *
2624 + * This program is free software; you can redistribute it and/or modify
2625 + * it under the terms of the GNU General Public License as published by
2626 + * the Free Software Foundation; either version 2 of the License, or
2627 + * (at your option) any later version.
2628 + *
2629 + * This program is distributed in the hope that it will be useful,
2630 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
2631 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
2632 + * GNU General Public License for more details.
2633 + *
2634 + * You should have received a copy of the GNU General Public License
2635 + * along with this program; if not, write to the Free Software
2636 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
2637 + */
2638 +
2639 +#ifndef __LINUX_USB_GADGET_PXA27X_H
2640 +#define __LINUX_USB_GADGET_PXA27X_H
2641 +
2642 +#include <linux/types.h>
2643 +
2644 +struct pxa27x_udc;
2645 +
2646 +struct pxa27x_ep {
2647 +       struct usb_ep                           ep;
2648 +       struct pxa27x_udc                       *dev;
2649 +
2650 +       const struct usb_endpoint_descriptor    *desc;
2651 +       struct list_head                        queue;
2652 +       unsigned long                           pio_irqs;
2653 +       unsigned long                           dma_irqs;
2654 +
2655 +       int                                     dma;
2656 +       unsigned                                fifo_size;
2657 +       unsigned                                ep_num;
2658 +       unsigned                                ep_type;
2659 +
2660 +       unsigned                                stopped : 1;
2661 +       unsigned                                dma_con : 1;
2662 +       unsigned                                dir_in : 1;
2663 +       unsigned                                assigned : 1;
2664 +
2665 +       unsigned                                config;
2666 +       unsigned                                interface;
2667 +       unsigned                                aisn;
2668 +       /* UDCCSR = UDC Control/Status Register for this EP
2669 +        * UBCR = UDC Byte Count Remaining (contents of OUT fifo)
2670 +        * UDCDR = UDC Endpoint Data Register (the fifo)
2671 +        * UDCCR = UDC Endpoint Configuration Registers
2672 +        * DRCM = DMA Request Channel Map
2673 +        */
2674 +       volatile u32                            *reg_udccsr;
2675 +       volatile u32                            *reg_udcbcr;
2676 +       volatile u32                            *reg_udcdr;
2677 +       volatile u32                            *reg_udccr;
2678 +#ifdef USE_DMA
2679 +       volatile u32                            *reg_drcmr;
2680 +#define        drcmr(n)  .reg_drcmr = & DRCMR ## n ,
2681 +#else
2682 +#define        drcmr(n)
2683 +#endif
2684 +
2685 +#ifdef CONFIG_PM
2686 +       unsigned                                udccsr_value;
2687 +       unsigned                                udccr_value;
2688 +#endif
2689 +};
2690 +
2691 +struct pxa27x_request {
2692 +       struct usb_request                      req;
2693 +       struct list_head                        queue;
2694 +};
2695 +
2696 +enum ep0_state {
2697 +       EP0_IDLE,
2698 +       EP0_IN_DATA_PHASE,
2699 +       EP0_OUT_DATA_PHASE,
2700 +//     EP0_END_XFER,
2701 +       EP0_STALL,
2702 +       EP0_NO_ACTION
2703 +};
2704 +
2705 +#define EP0_FIFO_SIZE  ((unsigned)16)
2706 +#define BULK_FIFO_SIZE ((unsigned)64)
2707 +#define ISO_FIFO_SIZE  ((unsigned)256)
2708 +#define INT_FIFO_SIZE  ((unsigned)8)
2709 +
2710 +struct udc_stats {
2711 +       struct ep0stats {
2712 +               unsigned long           ops;
2713 +               unsigned long           bytes;
2714 +       } read, write;
2715 +       unsigned long                   irqs;
2716 +};
2717 +
2718 +#ifdef CONFIG_USB_PXA27X_SMALL
2719 +/* when memory's tight, SMALL config saves code+data.  */
2720 +//#undef       USE_DMA
2721 +//#define      UDC_EP_NUM      3
2722 +#endif
2723 +
2724 +#ifndef        UDC_EP_NUM
2725 +#define        UDC_EP_NUM      24
2726 +#endif
2727 +
2728 +struct pxa27x_udc {
2729 +       struct usb_gadget                       gadget;
2730 +       struct usb_gadget_driver                *driver;
2731 +
2732 +       enum ep0_state                          ep0state;
2733 +       struct udc_stats                        stats;
2734 +       unsigned                                got_irq : 1,
2735 +                                               got_disc : 1,
2736 +                                               has_cfr : 1,
2737 +                                               req_pending : 1,
2738 +                                               req_std : 1,
2739 +                                               req_config : 1;
2740 +
2741 +#define start_watchdog(dev) mod_timer(&dev->timer, jiffies + (HZ/200))
2742 +       struct timer_list                       timer;
2743 +
2744 +       struct device                           *dev;
2745 +       struct pxa2xx_udc_mach_info             *mach;
2746 +       u64                                     dma_mask;
2747 +       struct pxa27x_ep                        ep [UDC_EP_NUM];
2748 +
2749 +       unsigned                                configuration,
2750 +                                               interface,
2751 +                                               alternate;
2752 +#ifdef CONFIG_PM
2753 +       unsigned                                udccsr0;
2754 +#endif
2755 +};
2756 +
2757 +/*-------------------------------------------------------------------------*/
2758 +#if 0
2759 +#ifdef DEBUG
2760 +#define HEX_DISPLAY(n) do { \
2761 +       if (machine_is_mainstone())\
2762 +                { MST_LEDDAT1 = (n); } \
2763 +       } while(0)
2764 +
2765 +#define HEX_DISPLAY1(n)        HEX_DISPLAY(n)
2766 +
2767 +#define HEX_DISPLAY2(n)        do { \
2768 +       if (machine_is_mainstone()) \
2769 +               { MST_LEDDAT2 = (n); } \
2770 +       } while(0)
2771 +
2772 +#endif /* DEBUG */
2773 +#endif
2774 +/*-------------------------------------------------------------------------*/
2775 +
2776 +/* LEDs are only for debug */
2777 +#ifndef HEX_DISPLAY
2778 +#define HEX_DISPLAY(n)         do {} while(0)
2779 +#endif
2780 +
2781 +#ifndef LED_CONNECTED_ON
2782 +#define LED_CONNECTED_ON       do {} while(0)
2783 +#define LED_CONNECTED_OFF      do {} while(0)
2784 +#endif
2785 +#ifndef LED_EP0_ON
2786 +#define LED_EP0_ON             do {} while (0)
2787 +#define LED_EP0_OFF            do {} while (0)
2788 +#endif
2789 +
2790 +static struct pxa27x_udc *the_controller;
2791 +
2792 +/*-------------------------------------------------------------------------*/
2793 +
2794 +/* one GPIO should be used to detect host disconnect */
2795 +static inline int is_usb_connected(void)
2796 +{
2797 +       if (!the_controller->mach->udc_is_connected)
2798 +               return 1;
2799 +       return the_controller->mach->udc_is_connected();
2800 +}
2801 +
2802 +/* one GPIO should force the host to see this device (or not) */
2803 +static inline void make_usb_disappear(void)
2804 +{
2805 +       if (!the_controller->mach->udc_command)
2806 +               return;
2807 +       the_controller->mach->udc_command(PXA2XX_UDC_CMD_DISCONNECT);
2808 +}
2809 +
2810 +static inline void let_usb_appear(void)
2811 +{
2812 +       if (!the_controller->mach->udc_command)
2813 +               return;
2814 +       the_controller->mach->udc_command(PXA2XX_UDC_CMD_CONNECT);
2815 +}
2816 +
2817 +/*-------------------------------------------------------------------------*/
2818 +
2819 +/*
2820 + * Debugging support vanishes in non-debug builds.  DBG_NORMAL should be
2821 + * mostly silent during normal use/testing, with no timing side-effects.
2822 + */
2823 +#define DBG_NORMAL     1       /* error paths, device state transitions */
2824 +#define DBG_VERBOSE    2       /* add some success path trace info */
2825 +#define DBG_NOISY      3       /* ... even more: request level */
2826 +#define DBG_VERY_NOISY 4       /* ... even more: packet level */
2827 +
2828 +#ifdef DEBUG
2829 +
2830 +static const char *state_name[] = {
2831 +       "EP0_IDLE",
2832 +       "EP0_IN_DATA_PHASE", "EP0_OUT_DATA_PHASE",
2833 +       "EP0_END_XFER", "EP0_STALL"
2834 +};
2835 +
2836 +#define DMSG(stuff...) printk(KERN_ERR "udc: " stuff)
2837 +
2838 +#ifdef VERBOSE
2839 +#    define UDC_DEBUG DBG_VERBOSE
2840 +#else
2841 +#    define UDC_DEBUG DBG_NORMAL
2842 +#endif
2843 +
2844 +static void __attribute__ ((__unused__))
2845 +dump_udccr(const char *label)
2846 +{
2847 +       u32     udccr = UDCCR;
2848 +       DMSG("%s 0x%08x =%s%s%s%s%s%s%s%s%s%s, con=%d,inter=%d,altinter=%d\n",
2849 +               label, udccr,
2850 +               (udccr & UDCCR_OEN) ? " oen":"",
2851 +               (udccr & UDCCR_AALTHNP) ? " aalthnp":"",
2852 +               (udccr & UDCCR_AHNP) ? " rem" : "",
2853 +               (udccr & UDCCR_BHNP) ? " rstir" : "",
2854 +               (udccr & UDCCR_DWRE) ? " dwre" : "",
2855 +               (udccr & UDCCR_SMAC) ? " smac" : "",
2856 +               (udccr & UDCCR_EMCE) ? " emce" : "",
2857 +               (udccr & UDCCR_UDR) ? " udr" : "",
2858 +               (udccr & UDCCR_UDA) ? " uda" : "",
2859 +               (udccr & UDCCR_UDE) ? " ude" : "",
2860 +               (udccr & UDCCR_ACN) >> UDCCR_ACN_S,
2861 +               (udccr & UDCCR_AIN) >> UDCCR_AIN_S,
2862 +               (udccr & UDCCR_AAISN)>> UDCCR_AAISN_S );
2863 +}
2864 +
2865 +static void __attribute__ ((__unused__))
2866 +dump_udccsr0(const char *label)
2867 +{
2868 +       u32             udccsr0 = UDCCSR0;
2869 +
2870 +       DMSG("%s %s 0x%08x =%s%s%s%s%s%s%s\n",
2871 +               label, state_name[the_controller->ep0state], udccsr0,
2872 +               (udccsr0 & UDCCSR0_SA) ? " sa" : "",
2873 +               (udccsr0 & UDCCSR0_RNE) ? " rne" : "",
2874 +               (udccsr0 & UDCCSR0_FST) ? " fst" : "",
2875 +               (udccsr0 & UDCCSR0_SST) ? " sst" : "",
2876 +               (udccsr0 & UDCCSR0_DME) ? " dme" : "",
2877 +               (udccsr0 & UDCCSR0_IPR) ? " ipr" : "",
2878 +               (udccsr0 & UDCCSR0_OPC) ? " opr" : "");
2879 +}
2880 +
2881 +static void __attribute__ ((__unused__))
2882 +dump_state(struct pxa27x_udc *dev)
2883 +{
2884 +       unsigned        i;
2885 +
2886 +       DMSG("%s, udcicr %02X.%02X, udcsir %02X.%02x, udcfnr %02X\n",
2887 +               state_name[dev->ep0state],
2888 +               UDCICR1, UDCICR0, UDCISR1, UDCISR0, UDCFNR);
2889 +       dump_udccr("udccr");
2890 +
2891 +       if (!dev->driver) {
2892 +               DMSG("no gadget driver bound\n");
2893 +               return;
2894 +       } else
2895 +               DMSG("ep0 driver '%s'\n", dev->driver->driver.name);
2896 +
2897 +
2898 +       dump_udccsr0 ("udccsr0");
2899 +       DMSG("ep0 IN %lu/%lu, OUT %lu/%lu\n",
2900 +               dev->stats.write.bytes, dev->stats.write.ops,
2901 +               dev->stats.read.bytes, dev->stats.read.ops);
2902 +
2903 +       for (i = 1; i < UDC_EP_NUM; i++) {
2904 +               if (dev->ep [i].desc == 0)
2905 +                       continue;
2906 +               DMSG ("udccs%d = %02x\n", i, *dev->ep->reg_udccsr);
2907 +       }
2908 +}
2909 +
2910 +#if 0
2911 +static void dump_regs(u8 ep)
2912 +{
2913 +       DMSG("EP:%d UDCCSR:0x%08x UDCBCR:0x%08x\n UDCCR:0x%08x\n",
2914 +               ep,UDCCSN(ep), UDCBCN(ep), UDCCN(ep));
2915 +}
2916 +static void dump_req (struct pxa27x_request *req)
2917 +{
2918 +       struct usb_request *r = &req->req;
2919 +
2920 +       DMSG("%s: buf:0x%08x length:%d dma:0x%08x actual:%d\n",
2921 +                       __FUNCTION__, (unsigned)r->buf, r->length,
2922 +                       r->dma, r->actual);
2923 +}
2924 +#endif
2925 +
2926 +#else
2927 +
2928 +#define DMSG(stuff...)         do{}while(0)
2929 +
2930 +#define        dump_udccr(x)   do{}while(0)
2931 +#define        dump_udccsr0(x) do{}while(0)
2932 +#define        dump_state(x)   do{}while(0)
2933 +
2934 +#define UDC_DEBUG ((unsigned)0)
2935 +
2936 +#endif
2937 +
2938 +#define DBG(lvl, stuff...) do{if ((lvl) <= UDC_DEBUG) DMSG(stuff);}while(0)
2939 +
2940 +#define WARN(stuff...) printk(KERN_WARNING "udc: " stuff)
2941 +#define INFO(stuff...) printk(KERN_INFO "udc: " stuff)
2942 +
2943 +
2944 +#endif /* __LINUX_USB_GADGET_PXA27X_H */
2945 diff --git a/drivers/usb/gadget/serial.c b/drivers/usb/gadget/serial.c
2946 index e552668..971e491 100644
2947 --- a/drivers/usb/gadget/serial.c
2948 +++ b/drivers/usb/gadget/serial.c
2949 @@ -1378,20 +1378,20 @@ static int __init gs_bind(struct usb_gadget *gadget)
2950
2951         usb_ep_autoconfig_reset(gadget);
2952
2953 -       ep = usb_ep_autoconfig(gadget, &gs_fullspeed_in_desc);
2954 +       ep = usb_ep_autoconfig(gadget, &gs_fullspeed_in_desc, 0, 0, 0);
2955         if (!ep)
2956                 goto autoconf_fail;
2957         EP_IN_NAME = ep->name;
2958         ep->driver_data = ep;   /* claim the endpoint */
2959
2960 -       ep = usb_ep_autoconfig(gadget, &gs_fullspeed_out_desc);
2961 +       ep = usb_ep_autoconfig(gadget, &gs_fullspeed_out_desc, 0, 0, 0);
2962         if (!ep)
2963                 goto autoconf_fail;
2964         EP_OUT_NAME = ep->name;
2965         ep->driver_data = ep;   /* claim the endpoint */
2966
2967         if (use_acm) {
2968 -               ep = usb_ep_autoconfig(gadget, &gs_fullspeed_notify_desc);
2969 +               ep = usb_ep_autoconfig(gadget, &gs_fullspeed_notify_desc, 0, 0, 0);
2970                 if (!ep) {
2971                         printk(KERN_ERR "gs_bind: cannot run ACM on %s\n", gadget->name);
2972                         goto autoconf_fail;
2973 diff --git a/drivers/usb/gadget/zero.c b/drivers/usb/gadget/zero.c
2974 index 8c85e33..46ffe6c 100644
2975 --- a/drivers/usb/gadget/zero.c
2976 +++ b/drivers/usb/gadget/zero.c
2977 @@ -1155,7 +1155,7 @@ zero_bind (struct usb_gadget *gadget)
2978          * but there may also be important quirks to address.
2979          */
2980         usb_ep_autoconfig_reset (gadget);
2981 -       ep = usb_ep_autoconfig (gadget, &fs_source_desc);
2982 +       ep = usb_ep_autoconfig (gadget, &fs_source_desc, 0, 0, 0);
2983         if (!ep) {
2984  autoconf_fail:
2985                 printk (KERN_ERR "%s: can't autoconfigure on %s\n",
2986 @@ -1165,7 +1165,7 @@ autoconf_fail:
2987         EP_IN_NAME = ep->name;
2988         ep->driver_data = ep;   /* claim */
2989
2990 -       ep = usb_ep_autoconfig (gadget, &fs_sink_desc);
2991 +       ep = usb_ep_autoconfig (gadget, &fs_sink_desc, 0, 0, 0);
2992         if (!ep)
2993                 goto autoconf_fail;
2994         EP_OUT_NAME = ep->name;
2995 diff --git a/include/linux/usb_gadget.h b/include/linux/usb_gadget.h
2996 index e17186d..64c81fd 100644
2997 --- a/include/linux/usb_gadget.h
2998 +++ b/include/linux/usb_gadget.h
2999 @@ -445,10 +445,28 @@ usb_ep_fifo_flush (struct usb_ep *ep)
3000
3001  struct usb_gadget;
3002
3003 +/**
3004 + * struct usb_endpoint_config - possible configurations of a given endpoint
3005 + * @config: the configuration number
3006 + * @interface: the interface number
3007 + * @altinterface: the altinterface number
3008 + *
3009 + * Used as an array to pass information about the possible configurations
3010 + * of a given endpoint to the bus controller.
3011 + */
3012 +struct usb_endpoint_config {
3013 +       int     config;
3014 +       int     interface;
3015 +       int     altinterface;
3016 +};
3017 +
3018  /* the rest of the api to the controller hardware: device operations,
3019   * which don't involve endpoints (or i/o).
3020   */
3021  struct usb_gadget_ops {
3022 +       struct usb_ep*  (*ep_alloc)(struct usb_gadget *gadget,
3023 +                               struct usb_endpoint_descriptor *desc,
3024 +                               int config, int interface, int alt);
3025         int     (*get_frame)(struct usb_gadget *);
3026         int     (*wakeup)(struct usb_gadget *);
3027         int     (*set_selfpowered) (struct usb_gadget *, int is_selfpowered);
3028 @@ -872,7 +890,8 @@ int usb_gadget_config_buf(const struct usb_config_descriptor *config,
3029  /* utility wrapping a simple endpoint selection policy */
3030
3031  extern struct usb_ep *usb_ep_autoconfig (struct usb_gadget *,
3032 -                       struct usb_endpoint_descriptor *) __devinit;
3033 +                       struct usb_endpoint_descriptor *,
3034 +                       int, int, int) __devinit;
3035
3036  extern void usb_ep_autoconfig_reset (struct usb_gadget *) __devinit;
3037