packages/linux/linux-ezx-2.6.21/patches/ezx-pcap.patch

   1 Index: linux-2.6.21/arch/arm/mach-pxa/ezx-pcap.c
   2 ===================================================================
   3 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
   4 +++ linux-2.6.21/arch/arm/mach-pxa/ezx-pcap.c   2007-06-07 21:39:37.000000000 -0300
   5 @@ -0,0 +1,472 @@
   6 +/* Driver for Motorola PCAP2 as present in EZX phones
   7 + *
   8 + * This is both a SPI device driver for PCAP itself, as well as
   9 + * an IRQ demultiplexer for handling PCAP generated events such as
  10 + * headphone jack sense by downstream drivers.
  11 + *
  12 + * Copyright (C) 2006 Harald Welte <laforge@openezx.org>
  13 + * Copyright (C) 2007 Daniel Ribeiro <drwyrm@gmail.com>
  14 + *
  15 + */
  16 +
  17 +#include <linux/module.h>
  18 +#include <linux/kernel.h>
  19 +#include <linux/platform_device.h>
  20 +#include <linux/interrupt.h>
  21 +#include <linux/kernel_stat.h>
  22 +#include <linux/proc_fs.h>
  23 +
  24 +#include <asm/hardware.h>
  25 +#include <asm/mach-types.h>
  26 +
  27 +#include <asm/arch/ssp.h>
  28 +#include <asm/arch/pxa-regs.h>
  29 +#include <asm/arch/ezx-pcap.h>
  30 +#include <asm/arch/irqs.h>
  31 +#include <asm/mach/irq.h>
  32 +
  33 +#include "ezx.h"
  34 +
  35 +#if 0
  36 +#define DEBUGP(x, args...) printk(x, ## args)
  37 +#else
  38 +#define DEBUGP(x, args...)
  39 +#endif
  40 +
  41 +extern unsigned long ezx_ssp_pcap_putget(ulong);
  42 +
  43 +int ezx_pcap_write(u_int8_t reg_num, u_int32_t value)
  44 +{
  45 +       value &= SSP_PCAP_REGISTER_VALUE_MASK;
  46 +       value |= SSP_PCAP_REGISTER_WRITE_OP_BIT
  47 +               | (reg_num<<SSP_PCAP_REGISTER_ADDRESS_SHIFT);
  48 +
  49 +       local_irq_disable();
  50 +       ezx_ssp_pcap_putget(value);
  51 +       local_irq_enable();
  52 +
  53 +       DEBUGP("pcap write r%x: 0x%08x\n", reg_num, value);
  54 +       return 0;
  55 +}
  56 +EXPORT_SYMBOL_GPL(ezx_pcap_write);
  57 +
  58 +int ezx_pcap_read(u_int8_t reg_num, u_int32_t *value)
  59 +{
  60 +       u_int32_t frame = SSP_PCAP_REGISTER_READ_OP_BIT
  61 +               | (reg_num<<SSP_PCAP_REGISTER_ADDRESS_SHIFT);
  62 +
  63 +       local_irq_disable();
  64 +       *value = ezx_ssp_pcap_putget(frame);
  65 +       local_irq_enable();
  66 +
  67 +       DEBUGP("pcap read r%x:  0x%08x\n", reg_num, *value);
  68 +       return 0;
  69 +}
  70 +EXPORT_SYMBOL_GPL(ezx_pcap_read);
  71 +
  72 +int ezx_pcap_bit_set(u_int32_t sspPcapBit, u_int8_t to)
  73 +{
  74 +        int ret;
  75 +        u_int32_t tmp;
  76 +        u_int32_t bit = (sspPcapBit & SSP_PCAP_REGISTER_VALUE_MASK);
  77 +        u_int8_t reg_num = (sspPcapBit & SSP_PCAP_REGISTER_ADDRESS_MASK)
  78 +                                        >> SSP_PCAP_REGISTER_ADDRESS_SHIFT;
  79 +
  80 +        ret = ezx_pcap_read(reg_num, &tmp);
  81 +        if (ret < 0)
  82 +                return ret;
  83 +
  84 +        if (to == 0)
  85 +                tmp &= ~bit;
  86 +        else
  87 +                tmp |= bit;
  88 +
  89 +        return ezx_pcap_write(reg_num, tmp);
  90 +}
  91 +EXPORT_SYMBOL_GPL(ezx_pcap_bit_set);
  92 +
  93 +int ezx_pcap_read_bit(u_int32_t bit)
  94 +{
  95 +        int ret;
  96 +        u_int32_t tmp;
  97 +        u_int8_t reg_num = (bit & SSP_PCAP_REGISTER_ADDRESS_MASK)
  98 +                                        >> SSP_PCAP_REGISTER_ADDRESS_SHIFT;
  99 +
 100 +        ret = ezx_pcap_read(reg_num, &tmp);
 101 +        if (ret < 0)
 102 +                return ret;
 103 +
 104 +        return tmp & (bit & SSP_PCAP_REGISTER_VALUE_MASK);
 105 +}
 106 +EXPORT_SYMBOL_GPL(ezx_pcap_read_bit);
 107 +
 108 +/* /proc/pcap support */
 109 +#ifdef CONFIG_PROC_FS
 110 +
 111 +static struct proc_dir_entry *proc_pcap;
 112 +
 113 +char *pcap_registers[] = {
 114 +       "ISR\t", "MSR\t", "PSTAT\t", NULL, NULL, NULL, "VREG2\t", "VREG\t",
 115 +       "BATT_DAC", "ADC1\t", "ADC2\t", "AUD_CODEC", "AUD_RX_AMPS",
 116 +       "AUD_ST_DAC", NULL, NULL, NULL, NULL, NULL, NULL, "BUSCTRL\t",
 117 +       "PERIPH\t", NULL, NULL, "LOWPWR\t", NULL, "AUD_TX_AMPS", "GP\t",
 118 +       NULL, NULL, NULL, NULL, NULL
 119 +};
 120 +
 121 +static int pcap_read_proc(char *page, char **start, off_t off, int count,
 122 +                               int *eof, void *data_unused)
 123 +{
 124 +       int len = 0;
 125 +       u_int8_t r;
 126 +       u_int32_t v;
 127 +       off_t begin = 0;
 128 +
 129 +       for(r=0;r<32;r++) {
 130 +               if (pcap_registers[r] == NULL)
 131 +                       continue;
 132 +               ezx_pcap_read(r, &v);
 133 +               len += sprintf(page+len, "%s\t%08X\n", pcap_registers[r], v);
 134 +               if(len + begin > off + count)
 135 +                       goto done;
 136 +               if(len + begin < off) {
 137 +                       begin += len;
 138 +                       len = 0;
 139 +               }
 140 +       }
 141 +       *eof = 1;
 142 +done:
 143 +       if (off >= len+begin)
 144 +               return 0;
 145 +       *start = page + (off-begin);
 146 +       return ((count < begin+len-off) ? count : begin+len-off);
 147 +}
 148 +#endif
 149 +
 150 +void ezx_pcap_vibrator_level(u_int32_t value)
 151 +{
 152 +       u_int32_t tmp;
 153 +
 154 +       ezx_pcap_read(SSP_PCAP_ADJ_AUX_VREG_REGISTER, &tmp);
 155 +
 156 +       tmp &= (~SSP_PCAP_VIBRATOR_VOLTAGE_LEVEL_MASK);
 157 +       tmp |= value;
 158 +
 159 +       ezx_pcap_write(SSP_PCAP_ADJ_AUX_VREG_REGISTER, tmp);
 160 +}
 161 +EXPORT_SYMBOL_GPL(ezx_pcap_vibrator_level);
 162 +
 163 +static int __init pcap_init(void)
 164 +{
 165 +        /* initialize registers */
 166 +#warning FIXME: pcap_init still chip level
 167 +       /* implement a per board pcap init reg array? */
 168 +
 169 +       ezx_pcap_write(SSP_PCAP_ADJ_MSR_REGISTER, PCAP_MASK_ALL_INTERRUPT);
 170 +       ezx_pcap_write(SSP_PCAP_ADJ_ISR_REGISTER, PCAP_CLEAR_INTERRUPT_REGISTER);
 171 +
 172 +        ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_AUD_RX_AMPS_A1CTRL, 1);
 173 +//        ezx_pcap_vibrator_level(PCAP_VIBRATOR_VOLTAGE_LEVEL3);
 174 +
 175 +        /* set SW1 sleep to keep SW1 1.3v in sync mode */
 176 +        ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_LOWPWR_CTRL_SW1_MODE10, 0);
 177 +        ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_LOWPWR_CTRL_SW1_MODE11, 0);
 178 +        /*  SW1 active in sync mode */
 179 +        ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_LOWPWR_CTRL_SW1_MODE00, 1);
 180 +        ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_LOWPWR_CTRL_SW1_MODE01, 0);
 181 +        /*  at SW1 -core voltage to 1.30V   */
 182 +        ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_LOWPWR_CTRL_SW10_DVS, 1);
 183 +        ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_LOWPWR_CTRL_SW11_DVS, 1);
 184 +        ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_LOWPWR_CTRL_SW12_DVS, 1);
 185 +        ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_LOWPWR_CTRL_SW13_DVS, 0);
 186 +
 187 +        /* when STANDY2 PIN ACTIVE (high) set V3-- sram V8 -- pll off  */
 188 +        ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_VREG2_V3_STBY, 1);
 189 +        ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_VREG2_V3_LOWPWR, 0);
 190 +
 191 +        ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_VREG2_V8_STBY, 1);
 192 +        ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_VREG2_V8_LOWPWR, 0);
 193 +
 194 +        /* when STANDY2 PIN ACTIVE (high) set V4-- lcd only for e680 V6 ---
 195 +        * camera for e680 */
 196 +        ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_VREG2_V4_STBY, 1);
 197 +        ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_VREG2_V4_LOWPWR, 1);
 198 +
 199 +        ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_VREG2_V6_STBY, 1);
 200 +        ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_VREG2_V6_LOWPWR, 0);
 201 +
 202 +        /* set Vc to low power mode when AP sleep */
 203 +        //SSP_PCAP_bit_set( SSP_PCAP_ADJ_BIT_LOWPWR_CTRL_VC_STBY);
 204 +
 205 +        /* set VAUX2 to voltage 2.775V and low power mode when AP sleep */
 206 +        ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_AUX_VREG_VAUX2_1, 1);
 207 +        ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_AUX_VREG_VAUX2_0, 0);
 208 +        ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_LOWPWR_CTRL_VAUX2_STBY, 1);
 209 +        ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_LOWPWR_CTRL_VAUX2_LOWPWR, 1);
 210 +        ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_AUX_VREG_VAUX2_EN, 1);
 211 +
 212 +//     PGSR(GPIO34_TXENB) |= GPIO_bit(GPIO34_TXENB);
 213 +
 214 +       return 0;
 215 +}
 216 +/* MMC/SD specific functions */
 217 +
 218 +void ezx_pcap_mmcsd_voltage(u_int32_t bits)
 219 +{
 220 +        unsigned int tmp;
 221 +        ezx_pcap_read(SSP_PCAP_ADJ_AUX_VREG_REGISTER, &tmp);
 222 +#if defined(CONFIG_EZX_MCI_SD)
 223 +        tmp &= 0xffffff9f;      /* zero all vaux2 bits */
 224 +        tmp |= (bits & 0x3) << 5;
 225 +#elif defined(CONFIG_EZX_MCI_TF)
 226 +        tmp &= 0xfffff0ff;      /* zero all vaux3 bits */
 227 +        tmp |= (bits & 0xf) << 8;
 228 +#endif
 229 +        ezx_pcap_write(SSP_PCAP_ADJ_AUX_VREG_REGISTER, tmp);
 230 +}
 231 +EXPORT_SYMBOL(ezx_pcap_mmcsd_voltage);
 232 +
 233 +int ezx_pcap_mmcsd_power(int on)
 234 +{
 235 +       if (on > 0) on = 1;
 236 +       else on = 0;
 237 +#if defined(CONFIG_EZX_MCI_SD)
 238 +       return ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_AUX_VREG_VAUX2_EN, on);
 239 +#elif defined(CONFIG_EZX_MCI_TF)
 240 +       return ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_AUX_VREG_VAUX3_EN, on);
 241 +#endif
 242 +}
 243 +EXPORT_SYMBOL_GPL(ezx_pcap_mmcsd_power);
 244 +
 245 +/* IRQ Handling */
 246 +
 247 +/* Array indexed by BIT POSITION of PCAP register, returns IRQ number */
 248 +static unsigned int pcap2irq[] = {
 249 +        [0]     = EZX_IRQ_ADCDONE,
 250 +        [1]     = EZX_IRQ_TS,
 251 +        [2]     = 0, /* 1HZ */
 252 +        [3]     = 0, /* WH */
 253 +        [4]     = 0, /* WL */
 254 +        [5]     = 0, /* TODA */
 255 +        [6]     = EZX_IRQ_USB4V,
 256 +        [7]     = 0, /* ONOFF */
 257 +        [8]     = 0, /* ONOFF2 */
 258 +        [9]     = EZX_IRQ_USB1V,
 259 +        [10]    = 0, /* MOBPORT */
 260 +        [11]    = EZX_IRQ_MIC,
 261 +        [12]    = EZX_IRQ_HEADJACK,
 262 +        [13]    = 0, /* ST */
 263 +        [14]    = 0, /* PC */
 264 +        [15]    = 0, /* WARM */
 265 +        [16]    = 0, /* EOL */
 266 +        [17]    = 0, /* CLK */
 267 +        [18]    = 0, /* SYSRST */
 268 +        [19]    = 0,
 269 +        [20]    = EZX_IRQ_ADCDONE2,
 270 +        [21]    = 0, /* SOFTRESET */
 271 +        [22]    = 0, /* MNEXB */
 272 +};
 273 +
 274 +/* Array indexed by IRQ NUMBER, returns PCAP absolute value */
 275 +static unsigned int irq2pcap[] = {
 276 +        [EZX_IRQ_USB4V]         = SSP_PCAP_ADJ_BIT_ISR_USB4VI,
 277 +        [EZX_IRQ_USB1V]         = SSP_PCAP_ADJ_BIT_ISR_USB1VI,
 278 +        [EZX_IRQ_HEADJACK]      = SSP_PCAP_ADJ_BIT_ISR_A1I,
 279 +        [EZX_IRQ_MIC]           = SSP_PCAP_ADJ_BIT_ISR_MB2I,
 280 +        [EZX_IRQ_ADCDONE]       = SSP_PCAP_ADJ_BIT_ISR_ADCDONEI,
 281 +        [EZX_IRQ_TS]            = SSP_PCAP_ADJ_BIT_ISR_TSI,
 282 +        [EZX_IRQ_ADCDONE2]      = SSP_PCAP_ADJ_BIT_ISR_ADCDONE2I,
 283 +};
 284 +
 285 +static void pcap_ack_irq(unsigned int irq)
 286 +{
 287 +        DEBUGP("pcap_ack_irq: %u\n", irq);
 288 +        ezx_pcap_write(SSP_PCAP_ADJ_ISR_REGISTER, irq2pcap[irq]);
 289 +}
 290 +
 291 +static void pcap_mask_irq(unsigned int irq)
 292 +{
 293 +        u_int32_t reg;
 294 +
 295 +        DEBUGP("pcap_mask_irq: %u\n", irq);
 296 +
 297 +        /* this needs to be atomic... but we're not on SMP so it is */
 298 +        ezx_pcap_read(SSP_PCAP_ADJ_MSR_REGISTER, &reg);
 299 +        reg |= irq2pcap[irq];
 300 +        ezx_pcap_write(SSP_PCAP_ADJ_MSR_REGISTER, reg);
 301 +}
 302 +
 303 +static void pcap_unmask_irq(unsigned int irq)
 304 +{
 305 +        u_int32_t tmp;
 306 +        DEBUGP("pcap_unmask_irq: %u\n", irq);
 307 +
 308 +        /* this needs to be atomic... but we're not on SMP so it is */
 309 +        ezx_pcap_read(SSP_PCAP_ADJ_MSR_REGISTER, &tmp);
 310 +        tmp &= ~irq2pcap[irq];
 311 +        ezx_pcap_write(SSP_PCAP_ADJ_MSR_REGISTER, tmp);
 312 +}
 313 +
 314 +static struct irq_chip pcap_chip = {
 315 +        .ack    = pcap_ack_irq,
 316 +        .mask   = pcap_mask_irq,
 317 +        .unmask = pcap_unmask_irq,
 318 +};
 319 +
 320 +/* handler for interrupt received from PCAP via GPIO */
 321 +static void pcap_irq_demux_handler(unsigned int irq, struct irq_desc *desc)
 322 +{
 323 +        int i;
 324 +        const unsigned int cpu = smp_processor_id();
 325 +        u_int32_t reg, mask;
 326 +
 327 +       spin_lock(&desc->lock);
 328 +
 329 +        DEBUGP("pcap_irq_demux_handler(%u,,) entered\n", irq);
 330 +
 331 +        desc->status &= ~(IRQ_REPLAY | IRQ_WAITING);
 332 +
 333 +        if (unlikely(desc->status & IRQ_INPROGRESS)) {
 334 +               DEBUGP("irq busy, masking it off\n");
 335 +               desc->status |= (IRQ_PENDING | IRQ_MASKED);
 336 +               desc->chip->mask(irq);
 337 +               desc->chip->ack(irq);
 338 +               goto out_unlock;
 339 +       }
 340 +
 341 +        kstat_cpu(cpu).irqs[irq]++;
 342 +       desc->chip->ack(irq);
 343 +       desc->status |= IRQ_INPROGRESS;
 344 +
 345 +        do {
 346 +                if (unlikely((desc->status &
 347 +                               (IRQ_PENDING | IRQ_MASKED | IRQ_DISABLED)) ==
 348 +                               (IRQ_PENDING | IRQ_MASKED))) {
 349 +                        DEBUGP("dealing with pending IRQ, unmasking\n");
 350 +                        desc->chip->unmask(irq);
 351 +                       desc->status &= ~IRQ_MASKED;
 352 +                }
 353 +
 354 +               desc->status &= ~IRQ_PENDING;
 355 +
 356 +               ezx_pcap_read(SSP_PCAP_ADJ_ISR_REGISTER, &reg);
 357 +               ezx_pcap_read(SSP_PCAP_ADJ_MSR_REGISTER, &mask);
 358 +                DEBUGP("pcap_irq_demux_handler: ISR=0x%08x MSR=0x%08x\n", reg, mask);
 359 +
 360 +                for (i = ARRAY_SIZE(pcap2irq)-1; i >= 0; i--) {
 361 +                        unsigned int pirq = pcap2irq[i];
 362 +                        if (pirq == 0)
 363 +                                continue;
 364 +
 365 +                        if ((reg & (1 << i)) && !(mask & (1 << i))) {
 366 +                                struct irq_desc *subdesc;
 367 +                                DEBUGP("found irq %u\n", pirq);
 368 +                                subdesc = irq_desc + pirq;
 369 +
 370 +                               kstat_cpu(cpu).irqs[pirq]++;
 371 +                               subdesc->chip->ack(pirq);
 372 +
 373 +                               spin_unlock(&desc->lock);
 374 +                               handle_IRQ_event(pirq, subdesc->action);
 375 +                               spin_lock(&desc->lock);
 376 +                        }
 377 +                }
 378 +
 379 +        } while ((desc->status & (IRQ_PENDING | IRQ_DISABLED)) == IRQ_PENDING);
 380 +
 381 +        desc->status &= ~IRQ_INPROGRESS;
 382 +
 383 +out_unlock:
 384 +       spin_unlock(&desc->lock);
 385 +}
 386 +
 387 +static int ezx_pcap_remove(struct platform_device *pdev)
 388 +{
 389 +       int irq;
 390 +       DEBUGP("exz_pcap_remove entered\n");
 391 +
 392 +       set_irq_chained_handler(IRQ_GPIO1, NULL);
 393 +
 394 +       for (irq = EZX_IRQ(0); irq <= EZX_IRQ(6); irq++) {
 395 +               set_irq_chip(irq, NULL);
 396 +               set_irq_handler(irq, NULL);
 397 +               set_irq_flags(irq, 0);
 398 +       }
 399 +
 400 +       return 0;
 401 +}
 402 +
 403 +static int __init ezx_pcap_probe(struct platform_device *pdev)
 404 +{
 405 +       unsigned int irq;
 406 +       DEBUGP("ezx_pcap_probe entered\n");
 407 +
 408 +       pcap_init();
 409 +
 410 +       set_irq_type(IRQ_GPIO1, IRQT_RISING);
 411 +        /* set up interrupt demultiplexing code for PCAP2 irqs */
 412 +        for (irq = EZX_IRQ(0); irq <= EZX_IRQ(6); irq++) {
 413 +                set_irq_chip(irq, &pcap_chip);
 414 +                set_irq_handler(irq, handle_edge_irq);
 415 +                set_irq_flags(irq, IRQF_VALID);
 416 +        }
 417 +        set_irq_chained_handler(IRQ_GPIO1, pcap_irq_demux_handler);
 418 +
 419 +       printk("ezx-pcap: ssp driver registered\n");
 420 +
 421 +        return 0;
 422 +}
 423 +
 424 +static int ezx_pcap_suspend(struct platform_device *dev, pm_message_t state)
 425 +{
 426 +       DEBUGP("pcap suspend!\n");
 427 +        return 0;
 428 +}
 429 +
 430 +static int ezx_pcap_resume(struct platform_device *dev)
 431 +{
 432 +       DEBUGP("pcap resume!\n");
 433 +       /* ack all irqs */
 434 +       ezx_pcap_write(SSP_PCAP_ADJ_ISR_REGISTER, PCAP_CLEAR_INTERRUPT_REGISTER);
 435 +        return 0;
 436 +}
 437 +
 438 +static struct platform_driver ezxpcap_driver = {
 439 +       .probe          = ezx_pcap_probe,
 440 +       .remove         = ezx_pcap_remove,
 441 +       .suspend        = ezx_pcap_suspend,
 442 +       .resume         = ezx_pcap_resume,
 443 +       .driver         = {
 444 +               .name   = "ezx-pcap",
 445 +               .owner  = THIS_MODULE,
 446 +       },
 447 +};
 448 +
 449 +static int __init ezx_pcap_init(void)
 450 +{
 451 +       DEBUGP("ezx_pcap_init entered\n");
 452 +
 453 +#ifdef CONFIG_PROC_FS
 454 +       if((proc_pcap = create_proc_entry("pcap", 0, NULL)))
 455 +               proc_pcap->read_proc = pcap_read_proc;
 456 +#endif
 457 +
 458 +       return platform_driver_register(&ezxpcap_driver);
 459 +}
 460 +
 461 +static void __exit ezx_pcap_exit(void)
 462 +{
 463 +#ifdef CONFIG_PROC_FS
 464 +       if (proc_pcap)
 465 +               remove_proc_entry("pcap", NULL);
 466 +#endif
 467 +
 468 +       return platform_driver_unregister(&ezxpcap_driver);
 469 +}
 470 +
 471 +module_init(ezx_pcap_init);
 472 +module_exit(ezx_pcap_exit);
 473 +
 474 +MODULE_LICENSE("GPL");
 475 +MODULE_AUTHOR("Harald Welte");
 476 +MODULE_DESCRIPTION("SPI Driver for Motorola PCAP2");
 477 +
 478 Index: linux-2.6.21/include/asm-arm/arch-pxa/ezx-pcap.h
 479 ===================================================================
 480 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
 481 +++ linux-2.6.21/include/asm-arm/arch-pxa/ezx-pcap.h    2007-06-03 11:14:40.000000000 -0300
 482 @@ -0,0 +1,665 @@
 483 +/* (c) Copyright Motorola Beijing 2002 all rights reserved.
 484 +
 485 +       Project Name  : EZX
 486 +       Project No.   :
 487 +       Title         :
 488 +       File Name     :
 489 +       Description   :
 490 +
 491 +       ************** REVISION HISTORY **********************************************
 492 +       Date          Author                    Reference
 493 +       ========     ==========         ==========================
 494 +       2002-07-01   weiqiang lin               create
 495 +*/
 496 +#ifndef SSP_PCAP_H
 497 +#define SSP_PCAP_H
 498 +
 499 +#define SSP_vibrate_start_command()                SSP_PCAP_bit_set(SSP_PCAP_ADJ_BIT_AUX_VREG_V_VIB_EN); \
 500 +                                                   SSP_PCAP_bit_set(SSP_PCAP_ADJ_BIT_AUX_VREG_V_VIB_EN)
 501 +
 502 +#define SSP_vibrate_stop_command()                 SSP_PCAP_bit_clean(SSP_PCAP_ADJ_BIT_AUX_VREG_V_VIB_EN); \
 503 +                                                   SSP_PCAP_bit_clean(SSP_PCAP_ADJ_BIT_AUX_VREG_V_VIB_EN)
 504 +
 505 +#define SSP_PCAP_REGISTER_VALUE_LENGTH            16
 506 +
 507 +#define SSP_PCAP_REGISTER_WRITE_OP_BIT            0x80000000
 508 +#define SSP_PCAP_REGISTER_READ_OP_BIT             0x00000000
 509 +
 510 +#define SSP_PCAP_REGISTER_VALUE_UP_WORD_MASK      0xffff0000
 511 +#define SSP_PCAP_REGISTER_VALUE_DOWN_WORD_MASK    0x0000ffff
 512 +
 513 +#define SSP_PCAP_REGISTER_VALUE_MASK              0x01ffffff
 514 +#define SSP_PCAP_REGISTER_VALUE_MASK              0x01ffffff
 515 +#define SSP_PCAP_REGISTER_ADDRESS_MASK            0x7c000000
 516 +#define SSP_PCAP_REGISTER_ADDRESS_SHIFT           26
 517 +#define SSP_PCAP_REGISTER_NUMBER                  32
 518 +
 519 +#define SSP_PCAP_ADC_START_VALUE_SET_MASK                  0xfffffc00
 520 +#define SSP_PCAP_ADC_START_VALUE                           0x000001dd
 521 +
 522 +
 523 +#define SSP_PCAP_PHONE_CDC_CLOCK_MASK                      0x000001c0
 524 +#define SSP_PCAP_STEREO_SAMPLE_RATE_MASK                   0x00000f00
 525 +#define SSP_PCAP_STEREO_BCLK_TIME_SLOT_MASK                0x00018000
 526 +#define SSP_PCAP_STEREO_CLOCK_MASK                         0x0000001c
 527 +#define SSP_PCAP_DIGITAL_AUDIO_MODE_MASK                   0x00006000
 528 +#define SSP_PCAP_TOUCH_PANEL_POSITION_DETECT_MODE_MASK     0x000e0000
 529 +#define SSP_PCAP_MONO_PGA_MASK                             0x00180000
 530 +
 531 +#define SSP_PCAP_VIBRATOR_VOLTAGE_LEVEL_MASK               0x00300000
 532 +
 533 +#define SSP_PCAP_AUDIO_IN_GAIN_MASK                        0x0000001f
 534 +#define SSP_PCAP_AUDIO_IN_GAIN_SHIFT                       0
 535 +#define SSP_PCAP_AUDIO_OUT_GAIN_MASK                       0x0001e000
 536 +#define SSP_PCAP_AUDIO_OUT_GAIN_SHIFT                      13
 537 +
 538 +
 539 +#define SSP_PCAP_ADD1_VALUE_MASK                           0x000003ff
 540 +#define SSP_PCAP_ADD1_VALUE_SHIFT                          0
 541 +#define SSP_PCAP_ADD2_VALUE_MASK                           0x000ffc00
 542 +#define SSP_PCAP_ADD2_VALUE_SHIFT                          10
 543 +
 544 +
 545 +#define PCAP_AUDIO_IN_GAIN_MAX_VALUE                       31
 546 +#define PCAP_AUDIO_OUT_GAIN_MAX_VALUE                      15
 547 +
 548 +#define PCAP_CLEAR_INTERRUPT_REGISTER                      0x00141fdf
 549 +#define PCAP_MASK_ALL_INTERRUPT                            0x0013ffff
 550 +
 551 +#define SSP_PCAP_TS_KEEPER_TIMER                           100      /* 1 second */
 552 +#define START_ADC_DELAY_TIMER                              1991     /* 540 us */
 553 +
 554 +#define   SSP_SEND_PM_ALART_INTERVAL                    1000 *HZ/1000                 /* 1 second */
 555 +#define   SSP_SEND_MSG_USB_ACCESSORY_INFO_DEBOUNCE      200 *HZ/1000                 /*  200ms   */
 556 +
 557 +struct ssp_interrupt_info
 558 +{
 559 +    u32 type;
 560 +    u32 status;
 561 +    void* privdata;
 562 +};
 563 +
 564 +#ifndef U8
 565 +#define U8    unsigned char
 566 +#endif
 567 +
 568 +#ifndef U32
 569 +#define U32    unsigned long
 570 +#endif
 571 +
 572 +#ifndef U16
 573 +#define U16    unsigned short
 574 +#endif
 575 +
 576 +#ifndef P_U16
 577 +#define P_U16    U16*
 578 +#endif
 579 +
 580 +#ifndef P_U32
 581 +#define P_U32    U32*
 582 +#endif
 583 +
 584 +#define SSP_SELECT_BUFFER     (volatile unsigned long *)(0xf4000000)
 585 +
 586 +#define SSP_SR_RNE        0x00000008
 587 +#define SSP_PCAP_BASE     0x00001000
 588 +/************************ STRUCTURES, ENUMS, AND TYPEDEFS **************************/
 589 +typedef enum accessoryStatus
 590 +{
 591 +        ACCESSORY_DEVICE_STATUS_DETACHED             = 0,
 592 +        ACCESSORY_DEVICE_STATUS_ATTACHED                ,
 593 +        ACCESSORY_DEVICE_STATUS_UNKNOW             =0x000000ff
 594 +}ACCESSORY_DEVICE_STATUS;
 595 +
 596 +typedef enum accessoryType
 597 +{
 598 +        ACCESSORY_DEVICE_NONE               = 0,
 599 +        ACCESSORY_DEVICE_SERIAL_PORT        ,
 600 +        ACCESSORY_DEVICE_USB_PORT           ,
 601 +        ACCESSORY_DEVICE_UNKNOW             =0x000000ff
 602 +}ACCESSORY_TYPE;
 603 +
 604 +typedef enum pcapReturnStatus
 605 +{
 606 +       SSP_PCAP_SUCCESS                    = 0,
 607 +       SSP_PCAP_ERROR_REGISTER             = SSP_PCAP_BASE+1,
 608 +       SSP_PCAP_ERROR_VALUE                = SSP_PCAP_BASE+2,
 609 +
 610 +       SSP_PCAP_NOT_RUN                    = SSP_PCAP_BASE+0xff
 611 +}SSP_PCAP_STATUS;
 612 +
 613 +typedef enum pcapPortType
 614 +{
 615 +        SSP_PCAP_SERIAL_PORT                = 0x00000000,
 616 +        SSP_PCAP_LOW_USB_PORT               = 0x00000001,
 617 +        SSP_PCAP_HIGH_USB_PORT              = 0x00000002,
 618 +        SSP_PCAP_UNKNOW_PORT                = 0x000000ff
 619 +}SSP_PCAP_PORT_TYPE;
 620 +
 621 +typedef enum pcapInitDriverType
 622 +{
 623 +        SSP_PCAP_TS_OPEN                    = 0x00000000,
 624 +        SSP_PCAP_AUDIO_OPEN                 = 0x00000001,
 625 +        SSP_PCAP_UNKNOW_DRIVER_OPEN         = 0x000000ff
 626 +}SSP_PCAP_INIT_DRIVER_TYPE;
 627 +
 628 +
 629 +typedef enum pcapReturnBitStatus
 630 +{
 631 +       SSP_PCAP_BIT_ZERO                   = 0x00000000,
 632 +       SSP_PCAP_BIT_ONE                    = 0x00000001,
 633 +       SSP_PCAP_BIT_ERROR                  = 0xff000000
 634 +}SSP_PCAP_BIT_STATUS;
 635 +
 636 +typedef enum pcapCDCClkType
 637 +{
 638 +       PCAP_CDC_CLK_IN_13M0                  = 0x00000000,
 639 +       PCAP_CDC_CLK_IN_15M36                 = 0x00000040,
 640 +       PCAP_CDC_CLK_IN_16M8                  = 0x00000080,
 641 +       PCAP_CDC_CLK_IN_19M44                 = 0x000000c0,
 642 +       PCAP_CDC_CLK_IN_26M0                  = 0x00000100
 643 +}PHONE_CDC_CLOCK_TYPE;
 644 +
 645 +typedef enum pcapST_SR
 646 +{
 647 +       PCAP_ST_SAMPLE_RATE_8K                = 0x00000000,
 648 +       PCAP_ST_SAMPLE_RATE_11K               = 0x00000100,
 649 +       PCAP_ST_SAMPLE_RATE_12K               = 0x00000200,
 650 +       PCAP_ST_SAMPLE_RATE_16K               = 0x00000300,
 651 +       PCAP_ST_SAMPLE_RATE_22K               = 0x00000400,
 652 +       PCAP_ST_SAMPLE_RATE_24K               = 0x00000500,
 653 +       PCAP_ST_SAMPLE_RATE_32K               = 0x00000600,
 654 +       PCAP_ST_SAMPLE_RATE_44K               = 0x00000700,
 655 +       PCAP_ST_SAMPLE_RATE_48K               = 0x00000800
 656 +}ST_SAMPLE_RATE_TYPE;
 657 +
 658 +typedef enum pcapST_BCLK
 659 +{
 660 +       PCAP_ST_BCLK_SLOT_16                  = 0x00000000,
 661 +       PCAP_ST_BCLK_SLOT_8                   = 0x00008000,
 662 +       PCAP_ST_BCLK_SLOT_4                   = 0x00010000,
 663 +       PCAP_ST_BCLK_SLOT_2                   = 0x00018000,
 664 +}ST_BCLK_TIME_SLOT_TYPE;
 665 +
 666 +typedef enum pcapST_CLK
 667 +{
 668 +       PCAP_ST_CLK_PLL_CLK_IN_13M0           = 0x00000000,
 669 +       PCAP_ST_CLK_PLL_CLK_IN_15M36          = 0x00000004,
 670 +       PCAP_ST_CLK_PLL_CLK_IN_16M8           = 0x00000008,
 671 +       PCAP_ST_CLK_PLL_CLK_IN_19M44          = 0x0000000c,
 672 +       PCAP_ST_CLK_PLL_CLK_IN_26M0           = 0x00000010,
 673 +       PCAP_ST_CLK_PLL_CLK_IN_EXT_MCLK       = 0x00000014,
 674 +       PCAP_ST_CLK_PLL_CLK_IN_FSYNC          = 0x00000018,
 675 +       PCAP_ST_CLK_PLL_CLK_IN_BITCLK         = 0x0000001c
 676 +}ST_CLK_TYPE;
 677 +
 678 +typedef enum pcapDigitalAudioInterfaceMode
 679 +{
 680 +       PCAP_DIGITAL_AUDIO_INTERFACE_NORMAL   = 0x00000000,
 681 +       PCAP_DIGITAL_AUDIO_INTERFACE_NETWORK  = 0x00002000,
 682 +       PCAP_DIGITAL_AUDIO_INTERFACE_I2S      = 0x00004000
 683 +}DIG_AUD_MODE_TYPE;
 684 +
 685 +typedef enum pcapMono
 686 +{
 687 +       PCAP_MONO_PGA_R_L_STEREO             = 0x00000000,
 688 +       PCAP_MONO_PGA_RL                     = 0x00080000,
 689 +       PCAP_MONO_PGA_RL_3DB                 = 0x00100000,
 690 +       PCAP_MONO_PGA_RL_6DB                 = 0x00180000
 691 +}MONO_TYPE;
 692 +
 693 +typedef enum pcapVibratorVoltageLevel
 694 +{
 695 +       PCAP_VIBRATOR_VOLTAGE_LEVEL0         = 0x00000000,
 696 +       PCAP_VIBRATOR_VOLTAGE_LEVEL1         = 0x00100000,
 697 +       PCAP_VIBRATOR_VOLTAGE_LEVEL2         = 0x00200000,
 698 +       PCAP_VIBRATOR_VOLTAGE_LEVEL3         = 0x00300000
 699 +}VibratorVoltageLevel_TYPE;
 700 +
 701 +typedef enum pcapTouchScreenMode
 702 +{
 703 +       PCAP_TS_POSITION_X_MEASUREMENT       = 0x00000000,
 704 +       PCAP_TS_POSITION_XY_MEASUREMENT      = 0x00020000,
 705 +       PCAP_TS_PRESSURE_MEASUREMENT         = 0x00040000,
 706 +       PCAP_TS_PLATE_X_MEASUREMENT          = 0x00060000,
 707 +       PCAP_TS_PLATE_Y_MEASUREMENT          = 0x00080000,
 708 +       PCAP_TS_STANDBY_MODE                 = 0x000a0000,
 709 +       PCAP_TS_NONTS_MODE                   = 0x000c0000
 710 +}TOUCH_SCREEN_DETECT_TYPE;
 711 +
 712 +typedef enum pcapADJRegister
 713 +{
 714 +       SSP_PCAP_ADJ_ISR_REGISTER           = 0x00,
 715 +       SSP_PCAP_ADJ_MSR_REGISTER           = 0x01,
 716 +       SSP_PCAP_ADJ_PSTAT_REGISTER         = 0x02,
 717 +       SSP_PCAP_ADJ_VREG2_REGISTER         = 0x06,
 718 +       SSP_PCAP_ADJ_AUX_VREG_REGISTER      = 0x07,
 719 +       SSP_PCAP_ADJ_BATT_DAC_REGISTER      = 0x08,
 720 +       SSP_PCAP_ADJ_ADC1_REGISTER          = 0x09,
 721 +       SSP_PCAP_ADJ_ADC2_REGISTER          = 0x0a,
 722 +       SSP_PCAP_ADJ_AUD_CODEC_REGISTER     = 0x0b,
 723 +       SSP_PCAP_ADJ_AUD_RX_AMPS_REGISTER   = 0x0c,
 724 +       SSP_PCAP_ADJ_ST_DAC_REGISTER        = 0x0d,
 725 +       SSP_PCAP_ADJ_BUSCTRL_REGISTER       = 0x14,
 726 +       SSP_PCAP_ADJ_PERIPH_REGISTER        = 0x15,
 727 +       SSP_PCAP_ADJ_LOWPWR_CTRL_REGISTER   = 0x18,
 728 +       SSP_PCAP_ADJ_TX_AUD_AMPS_REGISTER   = 0x1a,
 729 +       SSP_PCAP_ADJ_GP_REG_REGISTER        = 0x1b
 730 +}SSP_PCAP_SECONDARY_PROCESSOR_REGISTER;
 731 +
 732 +typedef enum pcapADJBit_SetType
 733 +{
 734 +       SSP_PCAP_ADJ_BIT_ISR_ADCDONEI               = 0x00000001,
 735 +       SSP_PCAP_ADJ_BIT_ISR_TSI                    = 0x00000002,
 736 +       SSP_PCAP_ADJ_BIT_ISR_1HZI                   = 0x00000004,
 737 +       SSP_PCAP_ADJ_BIT_ISR_WHI                    = 0x00000008,
 738 +       SSP_PCAP_ADJ_BIT_ISR_WLI                    = 0x00000010,
 739 +       SSP_PCAP_ADJ_BIT_ISR_TODAI                  = 0x00000020,
 740 +       SSP_PCAP_ADJ_BIT_ISR_USB4VI                 = 0x00000040,
 741 +       SSP_PCAP_ADJ_BIT_ISR_ONOFFI                 = 0x00000080,
 742 +       SSP_PCAP_ADJ_BIT_ISR_ONOFF2I                = 0x00000100,
 743 +       SSP_PCAP_ADJ_BIT_ISR_USB1VI                 = 0x00000200,
 744 +       SSP_PCAP_ADJ_BIT_ISR_MOBPORTI               = 0x00000400,
 745 +       SSP_PCAP_ADJ_BIT_ISR_MB2I                   = 0x00000800,
 746 +       SSP_PCAP_ADJ_BIT_ISR_A1I                    = 0x00001000,
 747 +       SSP_PCAP_ADJ_BIT_ISR_STI                    = 0x00002000,
 748 +       SSP_PCAP_ADJ_BIT_ISR_PCI                    = 0x00004000,
 749 +       SSP_PCAP_ADJ_BIT_ISR_WARMI                  = 0x00008000,
 750 +       SSP_PCAP_ADJ_BIT_ISR_EOLI                   = 0x00010000,
 751 +       SSP_PCAP_ADJ_BIT_ISR_CLKI                   = 0x00020000,
 752 +       SSP_PCAP_ADJ_BIT_ISR_SYS_RSTI               = 0x00040000,
 753 +       SSP_PCAP_ADJ_BIT_ISR_ADCDONE2I              = 0x00100000,
 754 +       SSP_PCAP_ADJ_BIT_ISR_SOFT_RESETI            = 0x00200000,
 755 +       SSP_PCAP_ADJ_BIT_ISR_MNEXBI                 = 0x00400000,
 756 +
 757 +       SSP_PCAP_ADJ_BIT_MSR_ADCDONEM               = 0x04000001,
 758 +       SSP_PCAP_ADJ_BIT_MSR_TSM                    = 0x04000002,
 759 +       SSP_PCAP_ADJ_BIT_MSR_1HZM                   = 0x04000004,
 760 +       SSP_PCAP_ADJ_BIT_MSR_WHM                    = 0x04000008,
 761 +       SSP_PCAP_ADJ_BIT_MSR_WLM                    = 0x04000010,
 762 +       SSP_PCAP_ADJ_BIT_MSR_TODAM                  = 0x04000020,
 763 +       SSP_PCAP_ADJ_BIT_MSR_USB4VM                 = 0x04000040,
 764 +       SSP_PCAP_ADJ_BIT_MSR_ONOFFM                 = 0x04000080,
 765 +       SSP_PCAP_ADJ_BIT_MSR_ONOFF2M                = 0x04000100,
 766 +       SSP_PCAP_ADJ_BIT_MSR_USB1VM                 = 0x04000200,
 767 +       SSP_PCAP_ADJ_BIT_MSR_MOBPORTM               = 0x04000400,
 768 +       SSP_PCAP_ADJ_BIT_MSR_MB2M                   = 0x04000800,
 769 +       SSP_PCAP_ADJ_BIT_MSR_A1M                    = 0x04001000,
 770 +       SSP_PCAP_ADJ_BIT_MSR_STM                    = 0x04002000,
 771 +       SSP_PCAP_ADJ_BIT_MSR_PCM                    = 0x04004000,
 772 +       SSP_PCAP_ADJ_BIT_MSR_WARMM                  = 0x04008000,
 773 +       SSP_PCAP_ADJ_BIT_MSR_EOLM                   = 0x04010000,
 774 +       SSP_PCAP_ADJ_BIT_MSR_CLKM                   = 0x04020000,
 775 +       SSP_PCAP_ADJ_BIT_MSR_SYS_RSTM               = 0x04040000,
 776 +       SSP_PCAP_ADJ_BIT_MSR_ADCDONE2M              = 0x04100000,
 777 +       SSP_PCAP_ADJ_BIT_MSR_SOFT_RESETM            = 0x04200000,
 778 +       SSP_PCAP_ADJ_BIT_MSR_MNEXBM                 = 0x04400000,
 779 +
 780 +       SSP_PCAP_ADJ_BIT_PSTAT_USBDET_4V            = 0x08000040,
 781 +       SSP_PCAP_ADJ_BIT_PSTAT_ONOFFSNS             = 0x08000080,
 782 +       SSP_PCAP_ADJ_BIT_PSTAT_ONOFFSNS2            = 0x08000100,
 783 +       SSP_PCAP_ADJ_BIT_PSTAT_USBDET_1V            = 0x08000200,
 784 +       SSP_PCAP_ADJ_BIT_PSTAT_MOBSENSB             = 0x08000400,
 785 +       SSP_PCAP_ADJ_BIT_PSTAT_MB2SNS               = 0x08000800,
 786 +       SSP_PCAP_ADJ_BIT_PSTAT_A1SNS                = 0x08001000,
 787 +       SSP_PCAP_ADJ_BIT_PSTAT_MSTB                 = 0x08002000,
 788 +       SSP_PCAP_ADJ_BIT_PSTAT_EOL_STAT             = 0x08010000,
 789 +       SSP_PCAP_ADJ_BIT_PSTAT_CLK_STAT             = 0x08020000,
 790 +       SSP_PCAP_ADJ_BIT_PSTAT_SYS_RST              = 0x08040000,
 791 +       SSP_PCAP_ADJ_BIT_PSTAT_BATTFBSNS            = 0x08080000,
 792 +       SSP_PCAP_ADJ_BIT_PSTAT_BATT_DET_IN_SNS      = 0x08200000,
 793 +       SSP_PCAP_ADJ_BIT_PSTAT_MNEXBSNS             = 0x08400000,
 794 +       SSP_PCAP_ADJ_BIT_PSTAT_WARM_SYS_RST         = 0x08800000,
 795 +
 796 +       SSP_PCAP_ADJ_BIT_VREG2_V1_STBY              = 0x18000001,
 797 +       SSP_PCAP_ADJ_BIT_VREG2_V2_STBY              = 0x18000002,
 798 +       SSP_PCAP_ADJ_BIT_VREG2_V3_STBY              = 0x18000004,
 799 +       SSP_PCAP_ADJ_BIT_VREG2_V4_STBY              = 0x18000008,
 800 +       SSP_PCAP_ADJ_BIT_VREG2_V5_STBY              = 0x18000010,
 801 +       SSP_PCAP_ADJ_BIT_VREG2_V6_STBY              = 0x18000020,
 802 +       SSP_PCAP_ADJ_BIT_VREG2_V7_STBY              = 0x18000040,
 803 +       SSP_PCAP_ADJ_BIT_VREG2_V8_STBY              = 0x18000080,
 804 +       SSP_PCAP_ADJ_BIT_VREG2_V9_STBY              = 0x18000100,
 805 +       SSP_PCAP_ADJ_BIT_VREG2_V10_STBY             = 0x18000200,
 806 +       SSP_PCAP_ADJ_BIT_VREG2_V1_LOWPWR            = 0x18000400,
 807 +       SSP_PCAP_ADJ_BIT_VREG2_V2_LOWPWR            = 0x18000800,
 808 +       SSP_PCAP_ADJ_BIT_VREG2_V3_LOWPWR            = 0x18001000,
 809 +       SSP_PCAP_ADJ_BIT_VREG2_V4_LOWPWR            = 0x18002000,
 810 +       SSP_PCAP_ADJ_BIT_VREG2_V5_LOWPWR            = 0x18004000,
 811 +       SSP_PCAP_ADJ_BIT_VREG2_V6_LOWPWR            = 0x18008000,
 812 +       SSP_PCAP_ADJ_BIT_VREG2_V7_LOWPWR            = 0x18010000,
 813 +       SSP_PCAP_ADJ_BIT_VREG2_V8_LOWPWR            = 0x18020000,
 814 +       SSP_PCAP_ADJ_BIT_VREG2_V9_LOWPWR            = 0x18040000,
 815 +       SSP_PCAP_ADJ_BIT_VREG2_V10_LOWPWR           = 0x18080000,
 816 +
 817 +       SSP_PCAP_ADJ_BIT_AUX_VREG_VAUX1_EN          = 0x1c000002,
 818 +       SSP_PCAP_ADJ_BIT_AUX_VREG_VAUX1_0           = 0x1c000004,
 819 +       SSP_PCAP_ADJ_BIT_AUX_VREG_VAUX1_1           = 0x1c000008,
 820 +       SSP_PCAP_ADJ_BIT_AUX_VREG_VAUX2_EN          = 0x1c000010,
 821 +       SSP_PCAP_ADJ_BIT_AUX_VREG_VAUX2_0           = 0x1c000020,
 822 +       SSP_PCAP_ADJ_BIT_AUX_VREG_VAUX2_1           = 0x1c000040,
 823 +       SSP_PCAP_ADJ_BIT_AUX_VREG_VAUX3_EN          = 0x1c000080,
 824 +       SSP_PCAP_ADJ_BIT_AUX_VREG_VAUX3_0           = 0x1c000100,
 825 +       SSP_PCAP_ADJ_BIT_AUX_VREG_VAUX3_1           = 0x1c000200,
 826 +       SSP_PCAP_ADJ_BIT_AUX_VREG_VAUX3_2           = 0x1c000400,
 827 +       SSP_PCAP_ADJ_BIT_AUX_VREG_VAUX3_3           = 0x1c000800,
 828 +       SSP_PCAP_ADJ_BIT_AUX_VREG_VAUX4_EN          = 0x1c001000,
 829 +       SSP_PCAP_ADJ_BIT_AUX_VREG_VAUX4_0           = 0x1c002000,
 830 +       SSP_PCAP_ADJ_BIT_AUX_VREG_VAUX4_1           = 0x1c004000,
 831 +       SSP_PCAP_ADJ_BIT_AUX_VREG_VSIM2_EN          = 0x1c010000,
 832 +       SSP_PCAP_ADJ_BIT_AUX_VREG_VSIM_EN           = 0x1c020000,
 833 +       SSP_PCAP_ADJ_BIT_AUX_VREG_VSIM_0            = 0x1c040000,
 834 +       SSP_PCAP_ADJ_BIT_AUX_VREG_V_VIB_EN          = 0x1c080000,
 835 +       SSP_PCAP_ADJ_BIT_AUX_VREG_V_VIB_0           = 0x1c100000,
 836 +       SSP_PCAP_ADJ_BIT_AUX_VREG_V_VIB_1           = 0x1c200000,
 837 +       SSP_PCAP_ADJ_BIT_AUX_VREG_VAUX1_STBY        = 0x1c400000,
 838 +       SSP_PCAP_ADJ_BIT_AUX_VREG_VAUX1_LOWPWR      = 0x1c800000,
 839 +       SSP_PCAP_ADJ_BIT_AUX_VREG_SW3_STBY          = 0x1d000000,
 840 +
 841 +       SSP_PCAP_ADJ_BIT_BATT_DAC_DAC0              = 0x20000001,
 842 +       SSP_PCAP_ADJ_BIT_BATT_DAC_DAC1              = 0x20000002,
 843 +       SSP_PCAP_ADJ_BIT_BATT_DAC_DAC2              = 0x20000004,
 844 +       SSP_PCAP_ADJ_BIT_BATT_DAC_DAC3              = 0x20000008,
 845 +       SSP_PCAP_ADJ_BIT_BATT_DAC_DAC4              = 0x20000010,
 846 +       SSP_PCAP_ADJ_BIT_BATT_DAC_DAC5              = 0x20000020,
 847 +       SSP_PCAP_ADJ_BIT_BATT_DAC_DAC6              = 0x20000040,
 848 +       SSP_PCAP_ADJ_BIT_BATT_DAC_DAC7              = 0x20000080,
 849 +       SSP_PCAP_ADJ_BIT_BATT_DAC_B_FDBK            = 0x20000100,
 850 +       SSP_PCAP_ADJ_BIT_BATT_DAC_EXT_ISENSE        = 0x20000200,
 851 +       SSP_PCAP_ADJ_BIT_BATT_DAC_V_COIN0           = 0x20000400,
 852 +       SSP_PCAP_ADJ_BIT_BATT_DAC_V_COIN1           = 0x20000800,
 853 +       SSP_PCAP_ADJ_BIT_BATT_DAC_V_COIN2           = 0x20001000,
 854 +       SSP_PCAP_ADJ_BIT_BATT_DAC_V_COIN3           = 0x20002000,
 855 +       SSP_PCAP_ADJ_BIT_BATT_DAC_I_COIN            = 0x20004000,
 856 +       SSP_PCAP_ADJ_BIT_BATT_DAC_COIN_CH_EN        = 0x20008000,
 857 +       SSP_PCAP_ADJ_BIT_BATT_DAC_EOL_SEL0          = 0x20020000,
 858 +       SSP_PCAP_ADJ_BIT_BATT_DAC_EOL_SEL1          = 0x20040000,
 859 +       SSP_PCAP_ADJ_BIT_BATT_DAC_EOL_SEL2          = 0x20080000,
 860 +       SSP_PCAP_ADJ_BIT_BATT_DAC_EOL_CMP_EN        = 0x20100000,
 861 +       SSP_PCAP_ADJ_BIT_BATT_DAC_BATT_DET_EN       = 0x20200000,
 862 +       SSP_PCAP_ADJ_BIT_BATT_DAC_THERMBIAS_CTRL    = 0x20400000,
 863 +
 864 +       SSP_PCAP_ADJ_BIT_ADC1_ADEN                  = 0x24000001,
 865 +       SSP_PCAP_ADJ_BIT_ADC1_RAND                  = 0x24000002,
 866 +       SSP_PCAP_ADJ_BIT_ADC1_AD_SEL1               = 0x24000004,
 867 +       SSP_PCAP_ADJ_BIT_ADC1_AD_SEL2               = 0x24000008,
 868 +       SSP_PCAP_ADJ_BIT_ADC1_ADA10                 = 0x24000010,
 869 +       SSP_PCAP_ADJ_BIT_ADC1_ADA11                 = 0x24000020,
 870 +       SSP_PCAP_ADJ_BIT_ADC1_ADA12                 = 0x24000040,
 871 +       SSP_PCAP_ADJ_BIT_ADC1_ADA20                 = 0x24000080,
 872 +       SSP_PCAP_ADJ_BIT_ADC1_ADA21                 = 0x24000100,
 873 +       SSP_PCAP_ADJ_BIT_ADC1_ADA22                 = 0x24000200,
 874 +       SSP_PCAP_ADJ_BIT_ADC1_ATO0                  = 0x24000400,
 875 +       SSP_PCAP_ADJ_BIT_ADC1_ATO1                  = 0x24000800,
 876 +       SSP_PCAP_ADJ_BIT_ADC1_ATO2                  = 0x24001000,
 877 +       SSP_PCAP_ADJ_BIT_ADC1_ATO3                  = 0x24002000,
 878 +       SSP_PCAP_ADJ_BIT_ADC1_ATOX                  = 0x24004000,
 879 +       SSP_PCAP_ADJ_BIT_ADC1_MTR1                  = 0x24008000,
 880 +       SSP_PCAP_ADJ_BIT_ADC1_MTR2                  = 0x24010000,
 881 +       SSP_PCAP_ADJ_BIT_ADC1_TS_M0                 = 0x24020000,
 882 +       SSP_PCAP_ADJ_BIT_ADC1_TS_M1                 = 0x24040000,
 883 +       SSP_PCAP_ADJ_BIT_ADC1_TS_M2                 = 0x24080000,
 884 +       SSP_PCAP_ADJ_BIT_ADC1_TS_REF_LOWPWR         = 0x24100000,
 885 +       SSP_PCAP_ADJ_BIT_ADC1_TS_REFENB             = 0x24200000,
 886 +       SSP_PCAP_ADJ_BIT_ADC1_BATT_I_POLARITY       = 0x24400000,
 887 +       SSP_PCAP_ADJ_BIT_ADC1_BATT_I_ADC            = 0x24800000,
 888 +
 889 +       SSP_PCAP_ADJ_BIT_ADC2_ADD10                 = 0x28000001,
 890 +       SSP_PCAP_ADJ_BIT_ADC2_ADD11                 = 0x28000002,
 891 +       SSP_PCAP_ADJ_BIT_ADC2_ADD12                 = 0x28000004,
 892 +       SSP_PCAP_ADJ_BIT_ADC2_ADD13                 = 0x28000008,
 893 +       SSP_PCAP_ADJ_BIT_ADC2_ADD14                 = 0x28000010,
 894 +       SSP_PCAP_ADJ_BIT_ADC2_ADD15                 = 0x28000020,
 895 +       SSP_PCAP_ADJ_BIT_ADC2_ADD16                 = 0x28000040,
 896 +       SSP_PCAP_ADJ_BIT_ADC2_ADD17                 = 0x28000080,
 897 +       SSP_PCAP_ADJ_BIT_ADC2_ADD18                 = 0x28000100,
 898 +       SSP_PCAP_ADJ_BIT_ADC2_ADD19                 = 0x28000200,
 899 +       SSP_PCAP_ADJ_BIT_ADC2_ADD20                 = 0x28000400,
 900 +       SSP_PCAP_ADJ_BIT_ADC2_ADD21                 = 0x28000800,
 901 +       SSP_PCAP_ADJ_BIT_ADC2_ADD22                 = 0x28001000,
 902 +       SSP_PCAP_ADJ_BIT_ADC2_ADD23                 = 0x28002000,
 903 +       SSP_PCAP_ADJ_BIT_ADC2_ADD24                 = 0x28004000,
 904 +       SSP_PCAP_ADJ_BIT_ADC2_ADD25                 = 0x28008000,
 905 +       SSP_PCAP_ADJ_BIT_ADC2_ADD26                 = 0x28010000,
 906 +       SSP_PCAP_ADJ_BIT_ADC2_ADD27                 = 0x28020000,
 907 +       SSP_PCAP_ADJ_BIT_ADC2_ADD28                 = 0x28040000,
 908 +       SSP_PCAP_ADJ_BIT_ADC2_ADD29                 = 0x28080000,
 909 +       SSP_PCAP_ADJ_BIT_ADC2_ADINC1                = 0x28100000,
 910 +       SSP_PCAP_ADJ_BIT_ADC2_ADINC2                = 0x28200000,
 911 +       SSP_PCAP_ADJ_BIT_ADC2_ASC                   = 0x28400000,
 912 +
 913 +       SSP_PCAP_ADJ_BIT_AUD_CODEC_AUDIHPF          = 0x2c000001,
 914 +       SSP_PCAP_ADJ_BIT_AUD_CODEC_SMB              = 0x2c000002,
 915 +       SSP_PCAP_ADJ_BIT_AUD_CODEC_AUDOHPF          = 0x2c000004,
 916 +       SSP_PCAP_ADJ_BIT_AUD_CODEC_CD_TS            = 0x2c000008,
 917 +       SSP_PCAP_ADJ_BIT_AUD_CODEC_DLM              = 0x2c000010,
 918 +       SSP_PCAP_ADJ_BIT_AUD_CODEC_ADITH            = 0x2c000020,
 919 +       SSP_PCAP_ADJ_BIT_AUD_CODEC_CDC_CLK0         = 0x2c000040,
 920 +       SSP_PCAP_ADJ_BIT_AUD_CODEC_CDC_CLK1         = 0x2c000080,
 921 +       SSP_PCAP_ADJ_BIT_AUD_CODEC_CDC_CLK2         = 0x2c000100,
 922 +       SSP_PCAP_ADJ_BIT_AUD_CODEC_CLK_INV          = 0x2c000200,
 923 +       SSP_PCAP_ADJ_BIT_AUD_CODEC_FS_INV           = 0x2c000400,
 924 +       SSP_PCAP_ADJ_BIT_AUD_CODEC_DF_RESET         = 0x2c000800,
 925 +       SSP_PCAP_ADJ_BIT_AUD_CODEC_CDC_EN           = 0x2c001000,
 926 +       SSP_PCAP_ADJ_BIT_AUD_CODEC_CDC_CLK_EN       = 0x2c002000,
 927 +       SSP_PCAP_ADJ_BIT_AUD_CODEC_FS_8K_16K        = 0x2c004000,
 928 +       SSP_PCAP_ADJ_BIT_AUD_CODEC_DIG_AUD_IN       = 0x2c008000,
 929 +       SSP_PCAP_ADJ_BIT_AUD_CODEC_CLK_IN_SEL       = 0x2c010000,
 930 +       SSP_PCAP_ADJ_BIT_AUD_CODEC_MIC2_MUX         = 0x2c020000,
 931 +       SSP_PCAP_ADJ_BIT_AUD_CODEC_MIC2IG0          = 0x2c040000,
 932 +       SSP_PCAP_ADJ_BIT_AUD_CODEC_MIC2IG1          = 0x2c080000,
 933 +       SSP_PCAP_ADJ_BIT_AUD_CODEC_MIC2IG2          = 0x2c100000,
 934 +       SSP_PCAP_ADJ_BIT_AUD_CODEC_MIC2IG3          = 0x2c200000,
 935 +       SSP_PCAP_ADJ_BIT_AUD_CODEC_MIC2IG4          = 0x2c400000,
 936 +       SSP_PCAP_ADJ_BIT_AUD_CODEC_MIC2IG_PRI_ADJ   = 0x2c800000,
 937 +       SSP_PCAP_ADJ_BIT_AUD_CODEC_CDC_PRI_ADJ      = 0x2c200000,
 938 +
 939 +       SSP_PCAP_ADJ_BIT_AUD_RX_AMPS_A1_EN          = 0x30000001,
 940 +       SSP_PCAP_ADJ_BIT_AUD_RX_AMPS_A2_EN          = 0x30000002,
 941 +       SSP_PCAP_ADJ_BIT_AUD_RX_AMPS_A4_EN          = 0x30000010,
 942 +       SSP_PCAP_ADJ_BIT_AUD_RX_AMPS_ARIGHT_EN      = 0x30000020,
 943 +       SSP_PCAP_ADJ_BIT_AUD_RX_AMPS_ALEFT_EN       = 0x30000040,
 944 +       SSP_PCAP_ADJ_BIT_AUD_RX_AMPS_CD_BYP         = 0x30000080,
 945 +       SSP_PCAP_ADJ_BIT_AUD_RX_AMPS_CDC_SW         = 0x30000100,
 946 +       SSP_PCAP_ADJ_BIT_AUD_RX_AMPS_ST_DAC_SW      = 0x30000200,
 947 +       SSP_PCAP_ADJ_BIT_AUD_RX_AMPS_PGA_IN_SW      = 0x30000400,
 948 +       SSP_PCAP_ADJ_BIT_AUD_RX_AMPS_PGA_R_EN       = 0x30000800,
 949 +       SSP_PCAP_ADJ_BIT_AUD_RX_AMPS_PGA_L_EN       = 0x30001000,
 950 +       SSP_PCAP_ADJ_BIT_AUD_RX_AMPS_AUDOG0         = 0x30002000,
 951 +       SSP_PCAP_ADJ_BIT_AUD_RX_AMPS_AUDOG1         = 0x30004000,
 952 +       SSP_PCAP_ADJ_BIT_AUD_RX_AMPS_AUDOG2         = 0x30008000,
 953 +       SSP_PCAP_ADJ_BIT_AUD_RX_AMPS_AUDOG3         = 0x30010000,
 954 +       SSP_PCAP_ADJ_BIT_AUD_RX_AMPS_A1CTRL         = 0x30020000,
 955 +       SSP_PCAP_ADJ_BIT_AUD_RX_AMPS_MONO0          = 0x30080000,
 956 +       SSP_PCAP_ADJ_BIT_AUD_RX_AMPS_MONO1          = 0x30100000,
 957 +       SSP_PCAP_ADJ_BIT_AUD_RX_AMPS_AUDOG_PRI_ADJ  = 0x30200000,
 958 +       SSP_PCAP_ADJ_BIT_AUD_RX_AMPS_MONO_PRI_ADJ   = 0x30400000,
 959 +       SSP_PCAP_ADJ_BIT_AUD_RX_AMPS_RX_PRI_ADJ0    = 0x30800000,
 960 +       SSP_PCAP_ADJ_BIT_AUD_RX_AMPS_RX_PRI_ADJ1    = 0x31000000,
 961 +
 962 +       SSP_PCAP_ADJ_BIT_ST_DAC_SMB_ST_DAC          = 0x34000001,
 963 +       SSP_PCAP_ADJ_BIT_ST_DAC_STDET_EN            = 0x34000002,
 964 +       SSP_PCAP_ADJ_BIT_ST_DAC_ST_CLK0             = 0x34000004,
 965 +       SSP_PCAP_ADJ_BIT_ST_DAC_ST_CLK1             = 0x34000008,
 966 +       SSP_PCAP_ADJ_BIT_ST_DAC_ST_CLK2             = 0x34000010,
 967 +       SSP_PCAP_ADJ_BIT_ST_DAC_ST_CLK_EN           = 0x34000020,
 968 +       SSP_PCAP_ADJ_BIT_ST_DAC_DF_RESET_ST_DAC     = 0x34000040,
 969 +       SSP_PCAP_ADJ_BIT_ST_DAC_ST_DAC_EN           = 0x34000080,
 970 +       SSP_PCAP_ADJ_BIT_ST_DAC_SR0                 = 0x34000100,
 971 +       SSP_PCAP_ADJ_BIT_ST_DAC_SR1                 = 0x34000200,
 972 +       SSP_PCAP_ADJ_BIT_ST_DAC_SR2                 = 0x34000400,
 973 +       SSP_PCAP_ADJ_BIT_ST_DAC_SR3                 = 0x34000800,
 974 +       SSP_PCAP_ADJ_BIT_ST_DAC_DIG_AUD_IN_ST_DAC   = 0x34001000,
 975 +       SSP_PCAP_ADJ_BIT_ST_DAC_DIG_AUD_FS0         = 0x34002000,
 976 +       SSP_PCAP_ADJ_BIT_ST_DAC_DIG_AUD_FS1         = 0x34004000,
 977 +       SSP_PCAP_ADJ_BIT_ST_DAC_BCLK0               = 0x34008000,
 978 +       SSP_PCAP_ADJ_BIT_ST_DAC_BCLK1               = 0x34010000,
 979 +       SSP_PCAP_ADJ_BIT_ST_DAC_ST_CLK_INV          = 0x34020000,
 980 +       SSP_PCAP_ADJ_BIT_ST_DAC_ST_FS_INV           = 0x34040000,
 981 +       SSP_PCAP_ADJ_BIT_ST_DAC_ST_DAC_CLK_IN_SEL   = 0x34080000,
 982 +       SSP_PCAP_ADJ_BIT_ST_DAC_ST_DAC_PRI_ADJ      = 0x35000000,
 983 +
 984 +       SSP_PCAP_ADJ_BIT_BUSCTRL_FSENB              = 0x50000001,
 985 +       SSP_PCAP_ADJ_BIT_BUSCTRL_USB_SUSPEND        = 0x50000002,
 986 +       SSP_PCAP_ADJ_BIT_BUSCTRL_USB_PU             = 0x50000004,
 987 +       SSP_PCAP_ADJ_BIT_BUSCTRL_USB_PD             = 0x50000008,
 988 +       SSP_PCAP_ADJ_BIT_BUSCTRL_VUSB_EN            = 0x50000010,
 989 +       SSP_PCAP_ADJ_BIT_BUSCTRL_USB_PS             = 0x50000020,
 990 +       SSP_PCAP_ADJ_BIT_BUSCTRL_VUSB_MSTR_EN       = 0x50000040,
 991 +       SSP_PCAP_ADJ_BIT_BUSCTRL_VBUS_PD_ENB        = 0x50000080,
 992 +       SSP_PCAP_ADJ_BIT_BUSCTRL_CURRLIM            = 0x50000100,
 993 +       SSP_PCAP_ADJ_BIT_BUSCTRL_RS232ENB           = 0x50000200,
 994 +       SSP_PCAP_ADJ_BIT_BUSCTRL_RS232_DIR          = 0x50000400,
 995 +       SSP_PCAP_ADJ_BIT_BUSCTRL_SE0_CONN           = 0x50000800,
 996 +       SSP_PCAP_ADJ_BIT_BUSCTRL_USB_PDM            = 0x50001000,
 997 +       SSP_PCAP_ADJ_BIT_BUSCTRL_BUS_PRI_ADJ        = 0x51000000,
 998 +
 999 +       SSP_PCAP_ADJ_BIT_PERIPH_BL_CTRL0            = 0x54000001,
1000 +       SSP_PCAP_ADJ_BIT_PERIPH_BL_CTRL1            = 0x54000002,
1001 +       SSP_PCAP_ADJ_BIT_PERIPH_BL_CTRL2            = 0x54000004,
1002 +       SSP_PCAP_ADJ_BIT_PERIPH_BL_CTRL3            = 0x54000008,
1003 +       SSP_PCAP_ADJ_BIT_PERIPH_BL_CTRL4            = 0x54000010,
1004 +       SSP_PCAP_ADJ_BIT_PERIPH_LEDR_EN             = 0x54000020,
1005 +       SSP_PCAP_ADJ_BIT_PERIPH_LEDG_EN             = 0x54000040,
1006 +       SSP_PCAP_ADJ_BIT_PERIPH_LEDR_CTRL0          = 0x54000080,
1007 +       SSP_PCAP_ADJ_BIT_PERIPH_LEDR_CTRL1          = 0x54000100,
1008 +       SSP_PCAP_ADJ_BIT_PERIPH_LEDR_CTRL2          = 0x54000200,
1009 +       SSP_PCAP_ADJ_BIT_PERIPH_LEDR_CTRL3          = 0x54000400,
1010 +       SSP_PCAP_ADJ_BIT_PERIPH_LEDG_CTRL0          = 0x54000800,
1011 +       SSP_PCAP_ADJ_BIT_PERIPH_LEDG_CTRL1          = 0x54001000,
1012 +       SSP_PCAP_ADJ_BIT_PERIPH_LEDG_CTRL2          = 0x54002000,
1013 +       SSP_PCAP_ADJ_BIT_PERIPH_LEDG_CTRL3          = 0x54004000,
1014 +       SSP_PCAP_ADJ_BIT_PERIPH_LEDR_I0             = 0x54008000,
1015 +       SSP_PCAP_ADJ_BIT_PERIPH_LEDR_I1             = 0x54010000,
1016 +       SSP_PCAP_ADJ_BIT_PERIPH_LEDG_I0             = 0x54020000,
1017 +       SSP_PCAP_ADJ_BIT_PERIPH_LEDG_I1             = 0x54040000,
1018 +       SSP_PCAP_ADJ_BIT_PERIPH_SKIP                = 0x54080000,
1019 +       SSP_PCAP_ADJ_BIT_PERIPH_BL2_CTRL0           = 0x54100000,
1020 +       SSP_PCAP_ADJ_BIT_PERIPH_BL2_CTRL1           = 0x54200000,
1021 +       SSP_PCAP_ADJ_BIT_PERIPH_BL2_CTRL2           = 0x54400000,
1022 +       SSP_PCAP_ADJ_BIT_PERIPH_BL2_CTRL3           = 0x54800000,
1023 +       SSP_PCAP_ADJ_BIT_PERIPH_BL2_CTRL4           = 0x55000000,
1024 +
1025 +       SSP_PCAP_ADJ_BIT_LOWPWR_CTRL_VAUX2_STBY     = 0x60000001,
1026 +       SSP_PCAP_ADJ_BIT_LOWPWR_CTRL_VAUX2_LOWPWR   = 0x60000002,
1027 +       SSP_PCAP_ADJ_BIT_LOWPWR_CTRL_VAUX3_STBY     = 0x60000004,
1028 +       SSP_PCAP_ADJ_BIT_LOWPWR_CTRL_VAUX3_LOWPWR   = 0x60000008,
1029 +       SSP_PCAP_ADJ_BIT_LOWPWR_CTRL_VAUX4_STBY     = 0x60000010,
1030 +       SSP_PCAP_ADJ_BIT_LOWPWR_CTRL_VAUX4_LOWPWR   = 0x60000020,
1031 +       SSP_PCAP_ADJ_BIT_LOWPWR_CTRL_VSIM_LOWPWR    = 0x60000040,
1032 +       SSP_PCAP_ADJ_BIT_LOWPWR_CTRL_VSIM2_LOWPWR   = 0x60000080,
1033 +       SSP_PCAP_ADJ_BIT_LOWPWR_CTRL_SW1_MODE00     = 0x60000100,
1034 +       SSP_PCAP_ADJ_BIT_LOWPWR_CTRL_SW1_MODE01     = 0x60000200,
1035 +       SSP_PCAP_ADJ_BIT_LOWPWR_CTRL_SW1_MODE10     = 0x60000400,
1036 +       SSP_PCAP_ADJ_BIT_LOWPWR_CTRL_SW1_MODE11     = 0x60000800,
1037 +       SSP_PCAP_ADJ_BIT_LOWPWR_CTRL_SW10_DVS       = 0x60001000,
1038 +       SSP_PCAP_ADJ_BIT_LOWPWR_CTRL_SW11_DVS       = 0x60002000,
1039 +       SSP_PCAP_ADJ_BIT_LOWPWR_CTRL_SW12_DVS       = 0x60004000,
1040 +       SSP_PCAP_ADJ_BIT_LOWPWR_CTRL_SW13_DVS       = 0x60008000,
1041 +       SSP_PCAP_ADJ_BIT_LOWPWR_CTRL_SW2_MODE00     = 0x60010000,
1042 +       SSP_PCAP_ADJ_BIT_LOWPWR_CTRL_SW2_MODE01     = 0x60020000,
1043 +       SSP_PCAP_ADJ_BIT_LOWPWR_CTRL_SW2_MODE10     = 0x60040000,
1044 +       SSP_PCAP_ADJ_BIT_LOWPWR_CTRL_SW2_MODE11     = 0x60080000,
1045 +       SSP_PCAP_ADJ_BIT_LOWPWR_CTRL_SW20_DVS       = 0x60100000,
1046 +       SSP_PCAP_ADJ_BIT_LOWPWR_CTRL_SW21_DVS       = 0x60200000,
1047 +       SSP_PCAP_ADJ_BIT_LOWPWR_CTRL_SW22_DVS       = 0x60400000,
1048 +       SSP_PCAP_ADJ_BIT_LOWPWR_CTRL_SW23_DVS       = 0x60800000,
1049 +       SSP_PCAP_ADJ_BIT_LOWPWR_CTRL_VC_STBY        = 0x61000000,
1050 +
1051 +       SSP_PCAP_ADJ_BIT_TX_AUD_AMPS_AUDIG0         = 0x68000001,
1052 +       SSP_PCAP_ADJ_BIT_TX_AUD_AMPS_AUDIG1         = 0x68000002,
1053 +       SSP_PCAP_ADJ_BIT_TX_AUD_AMPS_AUDIG2         = 0x68000004,
1054 +       SSP_PCAP_ADJ_BIT_TX_AUD_AMPS_AUDIG3         = 0x68000008,
1055 +       SSP_PCAP_ADJ_BIT_TX_AUD_AMPS_AUDIG4         = 0x68000010,
1056 +       SSP_PCAP_ADJ_BIT_TX_AUD_AMPS_A3_EN          = 0x68000020,
1057 +       SSP_PCAP_ADJ_BIT_TX_AUD_AMPS_A3_MUX         = 0x68000040,
1058 +       SSP_PCAP_ADJ_BIT_TX_AUD_AMPS_A5_EN          = 0x68000080,
1059 +       SSP_PCAP_ADJ_BIT_TX_AUD_AMPS_A5_MUX         = 0x68000100,
1060 +       SSP_PCAP_ADJ_BIT_TX_AUD_AMPS_EXT_MIC_MUX    = 0x68000200,
1061 +       SSP_PCAP_ADJ_BIT_TX_AUD_AMPS_MB_ON2         = 0x68000400,
1062 +       SSP_PCAP_ADJ_BIT_TX_AUD_AMPS_MB_ON1         = 0x68000800,
1063 +       SSP_PCAP_ADJ_BIT_TX_AUD_AMPS_A1ID_TX        = 0x68001000,
1064 +       SSP_PCAP_ADJ_BIT_TX_AUD_AMPS_A1_CONFIG      = 0x68002000,
1065 +       SSP_PCAP_ADJ_BIT_TX_AUD_AMPS_AHS_CONFIG     = 0x68004000,
1066 +       SSP_PCAP_ADJ_BIT_TX_AUD_AMPS_A2_CONFIG      = 0x68008000,
1067 +       SSP_PCAP_ADJ_BIT_TX_AUD_AMPS_AUDIO_LOWPWR   = 0x68080000,
1068 +       SSP_PCAP_ADJ_BIT_TX_AUD_AMPS_AUDIO_STBY     = 0x68100000,
1069 +       SSP_PCAP_ADJ_BIT_TX_AUD_AMPS_V2_EN_2        = 0x68200000,
1070 +       SSP_PCAP_ADJ_BIT_TX_AUD_AMPS_AUDIG_PRI_ADJ  = 0x68400000,
1071 +       SSP_PCAP_ADJ_BIT_TX_AUD_AMPS_TX_PRI_ADJ0    = 0x68800000,
1072 +       SSP_PCAP_ADJ_BIT_TX_AUD_AMPS_TX_PRI_ADJ1    = 0x69000000,
1073 +
1074 +       SSP_PCAP_ADJ_BIT_SYS_RST_CLR                = 0x6c000001,
1075 +       SSP_PCAP_ADJ_BIT_SYS_RST_MODE0              = 0x6c000002,
1076 +       SSP_PCAP_ADJ_BIT_SYS_RST_MODE1              = 0x6c000004,
1077 +       SSP_PCAP_ADJ_BIT_SYS_VFLASH_0               = 0x6c000008,
1078 +       SSP_PCAP_ADJ_BIT_SYS_VFLASH_1               = 0x6c000010,
1079 +       SSP_PCAP_ADJ_BIT_SYS_MID_SELECT             = 0x6c000020,
1080 +       SSP_PCAP_ADJ_BIT_SYS_MID_FET                = 0x6c000040,
1081 +       SSP_PCAP_ADJ_BIT_SYS_MAIN_LOW               = 0x6c000080,
1082 +       SSP_PCAP_ADJ_BIT_SYS_BATTFB_DIS             = 0x6c000100,
1083 +       SSP_PCAP_ADJ_BIT_SYS_GP_REG9                = 0x6c000200,
1084 +       SSP_PCAP_ADJ_BIT_SYS_GP_REG10               = 0x6c000400,
1085 +       SSP_PCAP_ADJ_BIT_SYS_GP_REG11               = 0x6c000800,
1086 +       SSP_PCAP_ADJ_BIT_SYS_GP_REG12               = 0x6c001000,
1087 +       SSP_PCAP_ADJ_BIT_SYS_GP_REG13               = 0x6c002000,
1088 +       SSP_PCAP_ADJ_BIT_SYS_GP_REG14               = 0x6c004000,
1089 +       SSP_PCAP_ADJ_BIT_SYS_GP_REG15               = 0x6c008000,
1090 +       SSP_PCAP_ADJ_BIT_SYS_GP_REG16               = 0x6c010000,
1091 +       SSP_PCAP_ADJ_BIT_SYS_GP_REG17               = 0x6c020000,
1092 +       SSP_PCAP_ADJ_BIT_SYS_GP_REG18               = 0x6c040000,
1093 +       SSP_PCAP_ADJ_BIT_SYS_GP_REG19               = 0x6c080000,
1094 +       SSP_PCAP_ADJ_BIT_SYS_GP_REG20               = 0x6c100000,
1095 +       SSP_PCAP_ADJ_BIT_SYS_GP_REG21               = 0x6c200000,
1096 +       SSP_PCAP_ADJ_BIT_SYS_GP_REG22               = 0x6c400000,
1097 +       SSP_PCAP_ADJ_BIT_SYS_GP_REG23               = 0x6c800000,
1098 +       SSP_PCAP_ADJ_BIT_SYS_GP_REG24               = 0x6d000000
1099 +
1100 +}SSP_PCAP_SECONDARY_PROCESSOR_REGISTER_BIT_TYPE;
1101 +
1102 +/************************ FUNCTION PROTOTYPES **************************************/
1103 +extern void ssp_pcap_init(void);
1104 +extern void ssp_pcap_release(void);
1105 +
1106 +extern void ssp_pcap_open(SSP_PCAP_INIT_DRIVER_TYPE portType);
1107 +extern void ssp_pcap_close(void);
1108 +
1109 +extern void ssp_pcap_intoSleep_callBack(void);
1110 +extern void ssp_pcap_wakeUp_callBack(void);
1111 +
1112 +
1113 +extern SSP_PCAP_STATUS SSP_PCAP_write_data_to_PCAP(SSP_PCAP_SECONDARY_PROCESSOR_REGISTER ssp_pcap_register,U32 ssp_pcap_register_value);
1114 +extern SSP_PCAP_STATUS SSP_PCAP_read_data_from_PCAP(SSP_PCAP_SECONDARY_PROCESSOR_REGISTER ssp_pcap_register,P_U32 p_ssp_pcap_register_value);
1115 +
1116 +extern SSP_PCAP_STATUS SSP_PCAP_bit_set(SSP_PCAP_SECONDARY_PROCESSOR_REGISTER_BIT_TYPE ssp_pcap_bit ) ;
1117 +extern SSP_PCAP_STATUS SSP_PCAP_bit_clean(SSP_PCAP_SECONDARY_PROCESSOR_REGISTER_BIT_TYPE ssp_pcap_bit ) ;
1118 +extern SSP_PCAP_BIT_STATUS SSP_PCAP_get_bit_from_buffer(SSP_PCAP_SECONDARY_PROCESSOR_REGISTER_BIT_TYPE ssp_pcap_bit ) ;
1119 +extern SSP_PCAP_BIT_STATUS SSP_PCAP_get_bit_from_PCAP(SSP_PCAP_SECONDARY_PROCESSOR_REGISTER_BIT_TYPE ssp_pcap_bit ) ;
1120 +extern U32 SSP_PCAP_get_register_value_from_buffer(SSP_PCAP_SECONDARY_PROCESSOR_REGISTER ssp_pcap_register ) ;
1121 +
1122 +extern SSP_PCAP_STATUS SSP_PCAP_TSI_mode_set(TOUCH_SCREEN_DETECT_TYPE mode_Type );
1123 +extern SSP_PCAP_STATUS SSP_PCAP_TSI_start_XY_read(void);
1124 +extern SSP_PCAP_STATUS SSP_PCAP_TSI_get_XY_value(P_U16 p_x,P_U16 p_y);
1125 +extern SSP_PCAP_STATUS SSP_PCAP_CDC_CLK_set(PHONE_CDC_CLOCK_TYPE clkType);
1126 +
1127 +extern SSP_PCAP_STATUS SSP_PCAP_CDC_SR_set(ST_SAMPLE_RATE_TYPE srType);
1128 +extern SSP_PCAP_STATUS SSP_PCAP_BCLK_set(ST_BCLK_TIME_SLOT_TYPE bclkType);
1129 +extern SSP_PCAP_STATUS SSP_PCAP_STCLK_set(ST_CLK_TYPE stClkType);
1130 +extern SSP_PCAP_STATUS SSP_PCAP_DIG_AUD_FS_set(DIG_AUD_MODE_TYPE fsType);
1131 +extern SSP_PCAP_STATUS SSP_PCAP_AUDIG_set(U32 audioInGain);
1132 +extern SSP_PCAP_STATUS SSP_PCAP_MONO_set(MONO_TYPE monoType);
1133 +extern SSP_PCAP_STATUS SSP_PCAP_AUDOG_set(U32 audioOutGain);
1134 +
1135 +extern SSP_PCAP_STATUS SSP_PCAP_V_VIB_level_set(VibratorVoltageLevel_TYPE VIBLevelType);
1136 +extern SSP_PCAP_STATUS SSP_PCAP_configure_USB_UART_transeiver(SSP_PCAP_PORT_TYPE portType);
1137 +extern SSP_PCAP_BIT_STATUS SSP_PCAP_get_audio_in_status(void);
1138 +
1139 +/* for log */
1140 +extern void pcap_log_add_pure_data(u8* pData,u32 len);
1141 +extern void pcap_log_add_data(u8* pData,u32 len);
1142 +
1143 +/* screen lock on/off handler */
1144 +extern void ssp_pcap_screenlock_lock(u32 data);
1145 +extern void ssp_pcap_screenlock_unlock(u32 data);
1146 +
1147 +#endif
1148 Index: linux-2.6.21/include/asm-arm/arch-pxa/irqs.h
1149 ===================================================================
1150 --- linux-2.6.21.orig/include/asm-arm/arch-pxa/irqs.h   2007-06-03 02:17:12.000000000 -0300
1151 +++ linux-2.6.21/include/asm-arm/arch-pxa/irqs.h        2007-06-03 11:14:40.000000000 -0300
1152 @@ -176,7 +176,8 @@
1153  #define NR_IRQS                        (IRQ_LOCOMO_SPI_TEND + 1)
1154  #elif defined(CONFIG_ARCH_LUBBOCK) || \
1155        defined(CONFIG_MACH_LOGICPD_PXA270) || \
1156 -      defined(CONFIG_MACH_MAINSTONE)
1157 +      defined(CONFIG_MACH_MAINSTONE) || \
1158 +      defined(CONFIG_PXA_EZX)
1159  #define NR_IRQS                        (IRQ_BOARD_END)
1160  #else
1161  #define NR_IRQS                        (IRQ_BOARD_START)
1162 @@ -222,3 +223,13 @@
1163  #define IRQ_LOCOMO_GPIO_BASE   (IRQ_BOARD_START + 1)
1164  #define IRQ_LOCOMO_LT_BASE     (IRQ_BOARD_START + 2)
1165  #define IRQ_LOCOMO_SPI_BASE    (IRQ_BOARD_START + 3)
1166 +
1167 +/* EZX Interrupts (CONFIG_EZX) */
1168 +#define EZX_IRQ(x)             (IRQ_BOARD_START + (x))
1169 +#define EZX_IRQ_USB4V          EZX_IRQ(0) /* EMU */
1170 +#define EZX_IRQ_USB1V          EZX_IRQ(1) /* EMU */
1171 +#define EZX_IRQ_HEADJACK       EZX_IRQ(2) /* Audio connector */
1172 +#define EZX_IRQ_MIC            EZX_IRQ(3) /* Audio connector */
1173 +#define EZX_IRQ_ADCDONE        EZX_IRQ(4)
1174 +#define EZX_IRQ_TS             EZX_IRQ(5) /* TS touch */
1175 +#define EZX_IRQ_ADCDONE2       EZX_IRQ(6) /* TS x/y ADC ready */
1176 Index: linux-2.6.21/arch/arm/mach-pxa/ezx.c
1177 ===================================================================
1178 --- linux-2.6.21.orig/arch/arm/mach-pxa/ezx.c   2007-06-03 11:14:40.000000000 -0300
1179 +++ linux-2.6.21/arch/arm/mach-pxa/ezx.c        2007-06-09 14:57:44.000000000 -0300
1180 @@ -131,11 +131,30 @@
1181         .resource       = ezxbp_resources,
1182  };
1183
1184 +/* PCAP */
1185 +static struct resource ezxpcap_resources[] = {
1186 +       [0] = {
1187 +               .start          = IRQ_GPIO1,
1188 +               .end            = IRQ_GPIO1,
1189 +               .flags          = IORESOURCE_IRQ,
1190 +       },
1191 +};
1192 +
1193 +struct platform_device ezxpcap_device = {
1194 +       .name           = "ezx-pcap",
1195 +       .id             = -1,
1196 +       .dev            = {
1197 +               .parent         = &ezxssp_device.dev,
1198 +       },
1199 +       .num_resources  = ARRAY_SIZE(ezxpcap_resources),
1200 +       .resource       = ezxpcap_resources,
1201 +};
1202
1203
1204  static struct platform_device *devices[] __initdata = {
1205         &ezxssp_device,
1206         &ezxbp_device,
1207 +       &ezxpcap_device,
1208  };
1209
1210  /* PM */
1211 Index: linux-2.6.21/arch/arm/mach-pxa/Kconfig
1212 ===================================================================
1213 --- linux-2.6.21.orig/arch/arm/mach-pxa/Kconfig 2007-06-03 11:14:40.000000000 -0300
1214 +++ linux-2.6.21/arch/arm/mach-pxa/Kconfig      2007-06-09 14:57:46.000000000 -0300
1215 @@ -105,6 +105,15 @@
1216  config EZX_BP
1217         bool "BP Control code for EZX Platform"
1218
1219 +config EZX_PCAP
1220 +       bool "PCAP Support"
1221 +
1222 +config EZX_MCI_SD
1223 +       bool
1224 +
1225 +config EZX_MCI_TF
1226 +       bool
1227 +
1228  endif
1229
1230  endmenu
1231 Index: linux-2.6.21/arch/arm/mach-pxa/Makefile
1232 ===================================================================
1233 --- linux-2.6.21.orig/arch/arm/mach-pxa/Makefile        2007-06-03 11:14:40.000000000 -0300
1234 +++ linux-2.6.21/arch/arm/mach-pxa/Makefile     2007-06-09 14:57:44.000000000 -0300
1235 @@ -25,6 +25,7 @@
1236  obj-$(CONFIG_PXA_EZX_A1200)    += ezx-a1200.o
1237  obj-$(CONFIG_PXA_EZX_E6)       += ezx-e6.o
1238  obj-$(CONFIG_EZX_BP)           += ezx-bp.o
1239 +obj-$(CONFIG_EZX_PCAP)         += ezx-pcap.o
1240
1241  # Support for blinky lights
1242  led-y := leds.o