packages/linux/linux-ezx-2.6.20.7/ezx-pcap.patch

   1 Index: linux-2.6.20.7/arch/arm/mach-pxa/ezx-pcap.c
   2 ===================================================================
   3 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
   4 +++ linux-2.6.20.7/arch/arm/mach-pxa/ezx-pcap.c 2007-04-21 08:26:37.000000000 -0300
   5 @@ -0,0 +1,411 @@
   6 +/* Driver for Motorola PCAP2 as present in EZX phones
   7 + *
   8 + * This is both a SPI device driver for PCAP itself, as well as
   9 + * an IRQ demultiplexer for handling PCAP generated events such as
  10 + * headphone jack sense by downstream drivers.
  11 + *
  12 + * (C) 2006 by Harald Welte <laforge@openezx.org>
  13 + *
  14 + * 2007, April - Daniel Ribeiro <drwyrm@gmail.com>
  15 + *                     Altered to work with corgi's SSP code.
  16 + *                     Fixed irq handling routine.
  17 + */
  18 +
  19 +#include <linux/module.h>
  20 +#include <linux/kernel.h>
  21 +#include <linux/platform_device.h>
  22 +#include <linux/interrupt.h>
  23 +#include <linux/kernel_stat.h>
  24 +
  25 +#include <asm/hardware.h>
  26 +#include <asm/mach-types.h>
  27 +
  28 +#include <asm/arch/ssp.h>
  29 +#include <asm/arch/pxa-regs.h>
  30 +#include <asm/arch/ezx-pcap.h>
  31 +#include <asm/arch/irqs.h>
  32 +#include <asm/mach/irq.h>
  33 +
  34 +#include "ezx.h"
  35 +
  36 +#if 0
  37 +#define DEBUGP(x, args...) printk(x, ## args)
  38 +#else
  39 +#define DEBUGP(x, args...)
  40 +#endif
  41 +
  42 +extern unsigned long ezx_ssp_pcap_putget(ulong);
  43 +
  44 +int ezx_pcap_write(u_int8_t reg_num, u_int32_t value)
  45 +{
  46 +       value &= SSP_PCAP_REGISTER_VALUE_MASK;
  47 +       value |= SSP_PCAP_REGISTER_WRITE_OP_BIT
  48 +               | (reg_num<<SSP_PCAP_REGISTER_ADDRESS_SHIFT);
  49 +
  50 +       local_irq_disable();
  51 +       ezx_ssp_pcap_putget(value);
  52 +       local_irq_enable();
  53 +
  54 +       DEBUGP("pcap write r%x: 0x%08x\n", reg_num, value);
  55 +       return 0;
  56 +}
  57 +EXPORT_SYMBOL_GPL(ezx_pcap_write);
  58 +
  59 +int ezx_pcap_read(u_int8_t reg_num, u_int32_t *value)
  60 +{
  61 +       u_int32_t frame = SSP_PCAP_REGISTER_READ_OP_BIT
  62 +               | (reg_num<<SSP_PCAP_REGISTER_ADDRESS_SHIFT);
  63 +
  64 +       local_irq_disable();
  65 +       *value = ezx_ssp_pcap_putget(frame);
  66 +       local_irq_enable();
  67 +
  68 +       DEBUGP("pcap read r%x:  0x%08x\n", reg_num, *value);
  69 +       return 0;
  70 +}
  71 +EXPORT_SYMBOL_GPL(ezx_pcap_read);
  72 +
  73 +int ezx_pcap_bit_set(u_int32_t sspPcapBit, u_int8_t to)
  74 +{
  75 +        int ret;
  76 +        u_int32_t tmp;
  77 +        u_int32_t bit = (sspPcapBit & SSP_PCAP_REGISTER_VALUE_MASK);
  78 +        u_int8_t reg_num = (sspPcapBit & SSP_PCAP_REGISTER_ADDRESS_MASK)
  79 +                                        >> SSP_PCAP_REGISTER_ADDRESS_SHIFT;
  80 +
  81 +        ret = ezx_pcap_read(reg_num, &tmp);
  82 +        if (ret < 0)
  83 +                return ret;
  84 +
  85 +        if (to == 0)
  86 +                tmp &= ~bit;
  87 +        else
  88 +                tmp |= bit;
  89 +
  90 +        return ezx_pcap_write(reg_num, tmp);
  91 +}
  92 +EXPORT_SYMBOL_GPL(ezx_pcap_bit_set);
  93 +
  94 +int ezx_pcap_read_bit(u_int32_t bit)
  95 +{
  96 +        int ret;
  97 +        u_int32_t tmp;
  98 +        u_int8_t reg_num = (bit & SSP_PCAP_REGISTER_ADDRESS_MASK)
  99 +                                        >> SSP_PCAP_REGISTER_ADDRESS_SHIFT;
 100 +
 101 +        ret = ezx_pcap_read(reg_num, &tmp);
 102 +        if (ret < 0)
 103 +                return ret;
 104 +
 105 +        return tmp & (bit & SSP_PCAP_REGISTER_VALUE_MASK);
 106 +}
 107 +EXPORT_SYMBOL_GPL(ezx_pcap_read_bit);
 108 +
 109 +
 110 +static int ezx_pcap_vibrator_level(u_int32_t bit)
 111 +{
 112 +        /* FIXME */
 113 +       return 0;
 114 +}
 115 +EXPORT_SYMBOL_GPL(ezx_pcap_vibrator_level);
 116 +
 117 +
 118 +static int pcap_init(void)
 119 +{
 120 +        /* initialize registers */
 121 +        /* FIXME: this should be board-level, not chip-level */
 122 +       /* implement a per board pcap init reg array? */
 123 +
 124 +       ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_ISR_USB4VI, 1);
 125 +        ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_MSR_USB4VM, 0);
 126 +        ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_ISR_USB1VI, 1);
 127 +        ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_MSR_USB1VM, 0);
 128 +       // disable all interrupts
 129 +       //ezx_pcap_write(SSP_PCAP_ADJ_MSR_REGISTER, 0x03ffffff);
 130 +
 131 +        ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_AUD_RX_AMPS_A1CTRL, 1);
 132 +        ezx_pcap_vibrator_level(PCAP_VIBRATOR_VOLTAGE_LEVEL3);
 133 +        ezx_pcap_vibrator_level(PCAP_VIBRATOR_VOLTAGE_LEVEL3);
 134 +
 135 +        /* set SW1 sleep to keep SW1 1.3v in sync mode */
 136 +        ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_LOWPWR_CTRL_SW1_MODE10, 0);
 137 +        ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_LOWPWR_CTRL_SW1_MODE11, 0);
 138 +        /*  SW1 active in sync mode */
 139 +        ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_LOWPWR_CTRL_SW1_MODE00, 1);
 140 +        ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_LOWPWR_CTRL_SW1_MODE01, 0);
 141 +        /*  at SW1 -core voltage to 1.30V   */
 142 +        ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_LOWPWR_CTRL_SW10_DVS, 1);
 143 +        ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_LOWPWR_CTRL_SW11_DVS, 1);
 144 +        ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_LOWPWR_CTRL_SW12_DVS, 1);
 145 +        ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_LOWPWR_CTRL_SW13_DVS, 0);
 146 +
 147 +        /* when STANDY2 PIN ACTIVE (high) set V3-- sram V8 -- pll off  */
 148 +        ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_VREG2_V3_STBY, 1);
 149 +        ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_VREG2_V3_LOWPWR, 0);
 150 +
 151 +        ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_VREG2_V8_STBY, 1);
 152 +        ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_VREG2_V8_LOWPWR, 0);
 153 +
 154 +        /* when STANDY2 PIN ACTIVE (high) set V4-- lcd only for e680 V6 ---
 155 +        * camera for e680 */
 156 +        ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_VREG2_V4_STBY, 1);
 157 +        ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_VREG2_V4_LOWPWR, 1);
 158 +
 159 +        ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_VREG2_V6_STBY, 1);
 160 +        ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_VREG2_V6_LOWPWR, 0);
 161 +
 162 +        /* set Vc to low power mode when AP sleep */
 163 +        //SSP_PCAP_bit_set( SSP_PCAP_ADJ_BIT_LOWPWR_CTRL_VC_STBY);
 164 +
 165 +        /* set VAUX2 to voltage 2.775V and low power mode when AP sleep */
 166 +        ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_AUX_VREG_VAUX2_1, 1);
 167 +        ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_AUX_VREG_VAUX2_0, 0);
 168 +        ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_LOWPWR_CTRL_VAUX2_STBY, 1);
 169 +        ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_LOWPWR_CTRL_VAUX2_LOWPWR, 1);
 170 +        ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_AUX_VREG_VAUX2_EN, 1);
 171 +
 172 +       PGSR(GPIO34_TXENB) |= GPIO_bit(GPIO34_TXENB);
 173 +
 174 +       return 0;
 175 +}
 176 +/* MMC/SD specific functions */
 177 +
 178 +void ezx_pcap_mmcsd_voltage(u_int32_t bits)
 179 +{
 180 +        unsigned int tmp;
 181 +        ezx_pcap_read(SSP_PCAP_ADJ_AUX_VREG_REGISTER, &tmp);
 182 +#if defined(CONFIG_PXA_EZX_E680)
 183 +        tmp &= 0xffffff9f;      /* zero all vaux2 bits */
 184 +        tmp |= (bits & 0x3) << 5;
 185 +#elif defined(CONFIG_PXA_EZX_A780)
 186 +        tmp &= 0xfffff0ff;      /* zero all vaux3 bits */
 187 +        tmp |= (bits & 0xf) << 8;
 188 +#endif
 189 +        ezx_pcap_write(SSP_PCAP_ADJ_AUX_VREG_REGISTER, tmp);
 190 +}
 191 +EXPORT_SYMBOL(ezx_pcap_mmcsd_voltage);
 192 +
 193 +int ezx_pcap_mmcsd_power(int on)
 194 +{
 195 +        if (on) {
 196 +#if defined(CONFIG_PXA_EZX_E680)
 197 +                return ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_AUX_VREG_VAUX2_EN, 1);
 198 +#else
 199 +                return ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_AUX_VREG_VAUX3_EN, 1);
 200 +#endif
 201 +        } else {
 202 +#if defined(CONFIG_PXA_EZX_E680)
 203 +                return ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_AUX_VREG_VAUX2_EN, 0);
 204 +#else
 205 +                return ezx_pcap_bit_set(SSP_PCAP_ADJ_BIT_AUX_VREG_VAUX3_EN, 0);
 206 +#endif
 207 +        }
 208 +}
 209 +EXPORT_SYMBOL_GPL(ezx_pcap_mmcsd_power);
 210 +
 211 +/* IRQ Handling */
 212 +
 213 +/* Array indexed by BIT POSITION of PCAP register, returns IRQ number */
 214 +static unsigned int pcap2irq[] = {
 215 +        [0]     = EZX_IRQ_ADCDONE,
 216 +        [1]     = EZX_IRQ_TS,
 217 +        [2]     = 0, /* 1HZ */
 218 +        [3]     = 0, /* WI */
 219 +        [4]     = 0, /* WI */
 220 +        [5]     = 0, /* TODA */
 221 +        [6]     = EZX_IRQ_USB4V,
 222 +        [7]     = 0, /* ONOFF */
 223 +        [8]     = 0, /* ONOFF2 */
 224 +        [9]     = EZX_IRQ_USB1V,
 225 +        [10]    = 0, /* MOBPORT */
 226 +        [11]    = EZX_IRQ_MIC,
 227 +        [12]    = EZX_IRQ_HEADJACK,
 228 +        [13]    = 0, /* ST */
 229 +        [14]    = 0, /* PC */
 230 +        [15]    = 0, /* WARM */
 231 +        [16]    = 0, /* EOL */
 232 +        [17]    = 0, /* CLK */
 233 +        [18]    = 0, /* SYS_RST */
 234 +        [19]    = 0,
 235 +        [20]    = EZX_IRQ_ADCDONE2,
 236 +        [21]    = 0, /* SOFT_RESET */
 237 +        [22]    = 0, /* MNEXB */
 238 +};
 239 +
 240 +/* Array indexed by IRQ NUMBER, returns PCAP absolute value */
 241 +static unsigned int irq2pcap[] = {
 242 +        [EZX_IRQ_ADCDONE]       = SSP_PCAP_ADJ_BIT_ISR_ADCDONEI,
 243 +        [EZX_IRQ_TS]            = SSP_PCAP_ADJ_BIT_ISR_TSI,
 244 +        [EZX_IRQ_USB4V]         = SSP_PCAP_ADJ_BIT_ISR_USB4VI,
 245 +        [EZX_IRQ_USB1V]         = SSP_PCAP_ADJ_BIT_ISR_USB1VI,
 246 +        [EZX_IRQ_HEADJACK]      = SSP_PCAP_ADJ_BIT_ISR_A1I,
 247 +        [EZX_IRQ_MIC]           = SSP_PCAP_ADJ_BIT_ISR_MB2I,
 248 +        [EZX_IRQ_ADCDONE2]      = SSP_PCAP_ADJ_BIT_ISR_ADCDONE2I,
 249 +};
 250 +
 251 +static void pcap_ack_irq(unsigned int irq)
 252 +{
 253 +        DEBUGP("pcap_ack_irq: %u\n", irq);
 254 +        ezx_pcap_write(SSP_PCAP_ADJ_ISR_REGISTER, irq2pcap[irq]);
 255 +}
 256 +
 257 +static void pcap_mask_irq(unsigned int irq)
 258 +{
 259 +        u_int32_t reg;
 260 +
 261 +        DEBUGP("pcap_mask_irq: %u\n", irq);
 262 +
 263 +        /* this needs to be atomic... but we're not on SMP so it is */
 264 +        ezx_pcap_read(SSP_PCAP_ADJ_MSR_REGISTER, &reg);
 265 +        reg |= irq2pcap[irq];
 266 +        ezx_pcap_write(SSP_PCAP_ADJ_MSR_REGISTER, reg);
 267 +}
 268 +
 269 +static void pcap_unmask_irq(unsigned int irq)
 270 +{
 271 +        u_int32_t tmp;
 272 +        DEBUGP("pcap_unmask_irq: %u\n", irq);
 273 +
 274 +        /* this needs to be atomic... but we're not on SMP so it is */
 275 +        ezx_pcap_read(SSP_PCAP_ADJ_MSR_REGISTER, &tmp);
 276 +        tmp &= ~irq2pcap[irq];
 277 +        ezx_pcap_write(SSP_PCAP_ADJ_MSR_REGISTER, tmp);
 278 +}
 279 +
 280 +static struct irq_chip pcap_chip = {
 281 +        .ack    = pcap_ack_irq,
 282 +        .mask   = pcap_mask_irq,
 283 +        .unmask = pcap_unmask_irq,
 284 +};
 285 +
 286 +/* handler for interrupt received from PCAP via GPIO */
 287 +static void pcap_irq_demux_handler(unsigned int irq, struct irq_desc *desc)
 288 +{
 289 +        int i;
 290 +        const unsigned int cpu = smp_processor_id();
 291 +        u_int32_t reg;
 292 +
 293 +        DEBUGP("pcap_irq_demux_handler(%u,,) entered\n", irq);
 294 +
 295 +       spin_lock(&desc->lock);
 296 +
 297 +        desc->status &= ~(IRQ_REPLAY | IRQ_WAITING);
 298 +
 299 +        if (unlikely(desc->status & IRQ_INPROGRESS)) {
 300 +               DEBUGP("irq busy, masking it off\n");
 301 +               desc->status |= (IRQ_PENDING | IRQ_MASKED);
 302 +               desc->chip->mask(irq);
 303 +               desc->chip->ack(irq);
 304 +               goto out_unlock;
 305 +       }
 306 +
 307 +        kstat_cpu(cpu).irqs[irq]++;
 308 +       desc->status |= IRQ_INPROGRESS;
 309 +
 310 +        do {
 311 +                if (unlikely((desc->status &
 312 +                               (IRQ_PENDING | IRQ_MASKED | IRQ_DISABLED)) ==
 313 +                               (IRQ_PENDING | IRQ_MASKED))) {
 314 +                        DEBUGP("dealing with pending IRQ, unmasking\n");
 315 +                        desc->chip->unmask(irq);
 316 +                       desc->status &= ~IRQ_MASKED;
 317 +                }
 318 +
 319 +               desc->status &= ~IRQ_PENDING;
 320 +               spin_unlock(&desc->lock);
 321 +
 322 +                ezx_pcap_read(SSP_PCAP_ADJ_ISR_REGISTER, &reg);
 323 +                DEBUGP("pcap_irq_demux_handler: ISR=0x%08x\n", reg);
 324 +
 325 +                for (i = ARRAY_SIZE(pcap2irq)-1; i >= 0; i--) {
 326 +                        unsigned int pirq = pcap2irq[i];
 327 +                        if (pirq == 0)
 328 +                                continue;
 329 +
 330 +                        if (reg & (1 << i)) {
 331 +                                struct irq_desc *subdesc;
 332 +                                DEBUGP("found irq %u\n", pirq);
 333 +                                subdesc = irq_desc + pirq;
 334 +
 335 +                               // acknowledge pcap irq
 336 +                               // do just one pcap irq each time
 337 +                               subdesc->chip->ack(pirq);
 338 +                               i = 0;
 339 +
 340 +                               handle_IRQ_event(pirq, subdesc->action);
 341 +                        }
 342 +                }
 343 +               spin_lock(&desc->lock);
 344 +
 345 +        } while ((desc->status & (IRQ_PENDING | IRQ_DISABLED)) == IRQ_PENDING);
 346 +
 347 +        desc->status &= ~IRQ_INPROGRESS;
 348 +
 349 +out_unlock:
 350 +       spin_unlock(&desc->lock);
 351 +}
 352 +
 353 +static int ezx_pcap_remove(struct platform_device *pdev)
 354 +{
 355 +       int irq;
 356 +       DEBUGP("exz_pcap_remove entered\n");
 357 +
 358 +       set_irq_chained_handler(IRQ_GPIO1, NULL);
 359 +
 360 +       for (irq = EZX_IRQ(0); irq <= EZX_IRQ(6); irq++) {
 361 +               set_irq_chip(irq, NULL);
 362 +               set_irq_handler(irq, NULL);
 363 +               set_irq_flags(irq, 0);
 364 +       }
 365 +
 366 +       return 0;
 367 +}
 368 +
 369 +static int __init ezx_pcap_probe(struct platform_device *pdev)
 370 +{
 371 +       unsigned int irq;
 372 +       DEBUGP("ezx_pcap_probe entered\n");
 373 +
 374 +       pcap_init();
 375 +
 376 +       set_irq_type(IRQ_GPIO1, IRQT_RISING);
 377 +        /* set up interrupt demultiplexing code for PCAP2 irqs */
 378 +        for (irq = EZX_IRQ(0); irq <= EZX_IRQ(6); irq++) {
 379 +                set_irq_chip(irq, &pcap_chip);
 380 +                set_irq_handler(irq, handle_edge_irq);
 381 +                set_irq_flags(irq, IRQF_VALID);
 382 +        }
 383 +        set_irq_chained_handler(IRQ_GPIO1, pcap_irq_demux_handler);
 384 +
 385 +       printk("PCAP2 SSP driver registered.\n");
 386 +
 387 +        return 0;
 388 +}
 389 +
 390 +static struct platform_driver ezxpcap_driver = {
 391 +       .probe          = ezx_pcap_probe,
 392 +       .remove         = ezx_pcap_remove,
 393 +       .driver         = {
 394 +               .name   = "ezx-pcap",
 395 +               .owner  = THIS_MODULE,
 396 +       },
 397 +};
 398 +
 399 +static int __init ezx_pcap_init(void)
 400 +{
 401 +       DEBUGP("ezx_pcap_init entered\n");
 402 +       return platform_driver_register(&ezxpcap_driver);
 403 +}
 404 +
 405 +static void __exit ezx_pcap_exit(void)
 406 +{
 407 +       return platform_driver_unregister(&ezxpcap_driver);
 408 +}
 409 +
 410 +module_init(ezx_pcap_init);
 411 +module_exit(ezx_pcap_exit);
 412 +
 413 +MODULE_LICENSE("GPL");
 414 +MODULE_AUTHOR("Harald Welte");
 415 +MODULE_DESCRIPTION("SPI Driver for Motorola PCAP2");
 416 +
 417 Index: linux-2.6.20.7/include/asm-arm/arch-pxa/ezx-pcap.h
 418 ===================================================================
 419 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
 420 +++ linux-2.6.20.7/include/asm-arm/arch-pxa/ezx-pcap.h  2007-04-21 08:26:37.000000000 -0300
 421 @@ -0,0 +1,665 @@
 422 +/* (c) Copyright Motorola Beijing 2002 all rights reserved.
 423 +
 424 +       Project Name  : EZX
 425 +       Project No.   :
 426 +       Title         :
 427 +       File Name     :
 428 +       Description   :
 429 +
 430 +       ************** REVISION HISTORY **********************************************
 431 +       Date          Author                    Reference
 432 +       ========     ==========         ==========================
 433 +       2002-07-01   weiqiang lin               create
 434 +*/
 435 +#ifndef SSP_PCAP_H
 436 +#define SSP_PCAP_H
 437 +
 438 +#define SSP_vibrate_start_command()                SSP_PCAP_bit_set(SSP_PCAP_ADJ_BIT_AUX_VREG_V_VIB_EN); \
 439 +                                                   SSP_PCAP_bit_set(SSP_PCAP_ADJ_BIT_AUX_VREG_V_VIB_EN)
 440 +
 441 +#define SSP_vibrate_stop_command()                 SSP_PCAP_bit_clean(SSP_PCAP_ADJ_BIT_AUX_VREG_V_VIB_EN); \
 442 +                                                   SSP_PCAP_bit_clean(SSP_PCAP_ADJ_BIT_AUX_VREG_V_VIB_EN)
 443 +
 444 +#define SSP_PCAP_REGISTER_VALUE_LENGTH            16
 445 +
 446 +#define SSP_PCAP_REGISTER_WRITE_OP_BIT            0x80000000
 447 +#define SSP_PCAP_REGISTER_READ_OP_BIT             0x00000000
 448 +
 449 +#define SSP_PCAP_REGISTER_VALUE_UP_WORD_MASK      0xffff0000
 450 +#define SSP_PCAP_REGISTER_VALUE_DOWN_WORD_MASK    0x0000ffff
 451 +
 452 +#define SSP_PCAP_REGISTER_VALUE_MASK              0x01ffffff
 453 +#define SSP_PCAP_REGISTER_VALUE_MASK              0x01ffffff
 454 +#define SSP_PCAP_REGISTER_ADDRESS_MASK            0x7c000000
 455 +#define SSP_PCAP_REGISTER_ADDRESS_SHIFT           26
 456 +#define SSP_PCAP_REGISTER_NUMBER                  32
 457 +
 458 +#define SSP_PCAP_ADC_START_VALUE_SET_MASK                  0xfffffc00
 459 +#define SSP_PCAP_ADC_START_VALUE                           0x000001dd
 460 +
 461 +
 462 +#define SSP_PCAP_PHONE_CDC_CLOCK_MASK                      0x000001c0
 463 +#define SSP_PCAP_STEREO_SAMPLE_RATE_MASK                   0x00000f00
 464 +#define SSP_PCAP_STEREO_BCLK_TIME_SLOT_MASK                0x00018000
 465 +#define SSP_PCAP_STEREO_CLOCK_MASK                         0x0000001c
 466 +#define SSP_PCAP_DIGITAL_AUDIO_MODE_MASK                   0x00006000
 467 +#define SSP_PCAP_TOUCH_PANEL_POSITION_DETECT_MODE_MASK     0x000e0000
 468 +#define SSP_PCAP_MONO_PGA_MASK                             0x00180000
 469 +
 470 +#define SSP_PCAP_VIBRATOR_VOLTAGE_LEVEL_MASK               0x00300000
 471 +
 472 +#define SSP_PCAP_AUDIO_IN_GAIN_MASK                        0x0000001f
 473 +#define SSP_PCAP_AUDIO_IN_GAIN_SHIFT                       0
 474 +#define SSP_PCAP_AUDIO_OUT_GAIN_MASK                       0x0001e000
 475 +#define SSP_PCAP_AUDIO_OUT_GAIN_SHIFT                      13
 476 +
 477 +
 478 +#define SSP_PCAP_ADD1_VALUE_MASK                           0x000003ff
 479 +#define SSP_PCAP_ADD1_VALUE_SHIFT                          0
 480 +#define SSP_PCAP_ADD2_VALUE_MASK                           0x000ffc00
 481 +#define SSP_PCAP_ADD2_VALUE_SHIFT                          10
 482 +
 483 +
 484 +#define PCAP_AUDIO_IN_GAIN_MAX_VALUE                       31
 485 +#define PCAP_AUDIO_OUT_GAIN_MAX_VALUE                      15
 486 +
 487 +#define PCAP_CLEAR_INTERRUPT_REGISTER                      0x00141fdf
 488 +#define PCAP_MASK_ALL_INTERRUPT                            0x0013ffff
 489 +
 490 +#define SSP_PCAP_TS_KEEPER_TIMER                           100      /* 1 second */
 491 +#define START_ADC_DELAY_TIMER                              1991     /* 540 us */
 492 +
 493 +#define   SSP_SEND_PM_ALART_INTERVAL                    1000 *HZ/1000                 /* 1 second */
 494 +#define   SSP_SEND_MSG_USB_ACCESSORY_INFO_DEBOUNCE      200 *HZ/1000                 /*  200ms   */
 495 +
 496 +struct ssp_interrupt_info
 497 +{
 498 +    u32 type;
 499 +    u32 status;
 500 +    void* privdata;
 501 +};
 502 +
 503 +#ifndef U8
 504 +#define U8    unsigned char
 505 +#endif
 506 +
 507 +#ifndef U32
 508 +#define U32    unsigned long
 509 +#endif
 510 +
 511 +#ifndef U16
 512 +#define U16    unsigned short
 513 +#endif
 514 +
 515 +#ifndef P_U16
 516 +#define P_U16    U16*
 517 +#endif
 518 +
 519 +#ifndef P_U32
 520 +#define P_U32    U32*
 521 +#endif
 522 +
 523 +#define SSP_SELECT_BUFFER     (volatile unsigned long *)(0xf4000000)
 524 +
 525 +#define SSP_SR_RNE        0x00000008
 526 +#define SSP_PCAP_BASE     0x00001000
 527 +/************************ STRUCTURES, ENUMS, AND TYPEDEFS **************************/
 528 +typedef enum accessoryStatus
 529 +{
 530 +        ACCESSORY_DEVICE_STATUS_DETACHED             = 0,
 531 +        ACCESSORY_DEVICE_STATUS_ATTACHED                ,
 532 +        ACCESSORY_DEVICE_STATUS_UNKNOW             =0x000000ff
 533 +}ACCESSORY_DEVICE_STATUS;
 534 +
 535 +typedef enum accessoryType
 536 +{
 537 +        ACCESSORY_DEVICE_NONE               = 0,
 538 +        ACCESSORY_DEVICE_SERIAL_PORT        ,
 539 +        ACCESSORY_DEVICE_USB_PORT           ,
 540 +        ACCESSORY_DEVICE_UNKNOW             =0x000000ff
 541 +}ACCESSORY_TYPE;
 542 +
 543 +typedef enum pcapReturnStatus
 544 +{
 545 +       SSP_PCAP_SUCCESS                    = 0,
 546 +       SSP_PCAP_ERROR_REGISTER             = SSP_PCAP_BASE+1,
 547 +       SSP_PCAP_ERROR_VALUE                = SSP_PCAP_BASE+2,
 548 +
 549 +       SSP_PCAP_NOT_RUN                    = SSP_PCAP_BASE+0xff
 550 +}SSP_PCAP_STATUS;
 551 +
 552 +typedef enum pcapPortType
 553 +{
 554 +        SSP_PCAP_SERIAL_PORT                = 0x00000000,
 555 +        SSP_PCAP_LOW_USB_PORT               = 0x00000001,
 556 +        SSP_PCAP_HIGH_USB_PORT              = 0x00000002,
 557 +        SSP_PCAP_UNKNOW_PORT                = 0x000000ff
 558 +}SSP_PCAP_PORT_TYPE;
 559 +
 560 +typedef enum pcapInitDriverType
 561 +{
 562 +        SSP_PCAP_TS_OPEN                    = 0x00000000,
 563 +        SSP_PCAP_AUDIO_OPEN                 = 0x00000001,
 564 +        SSP_PCAP_UNKNOW_DRIVER_OPEN         = 0x000000ff
 565 +}SSP_PCAP_INIT_DRIVER_TYPE;
 566 +
 567 +
 568 +typedef enum pcapReturnBitStatus
 569 +{
 570 +       SSP_PCAP_BIT_ZERO                   = 0x00000000,
 571 +       SSP_PCAP_BIT_ONE                    = 0x00000001,
 572 +       SSP_PCAP_BIT_ERROR                  = 0xff000000
 573 +}SSP_PCAP_BIT_STATUS;
 574 +
 575 +typedef enum pcapCDCClkType
 576 +{
 577 +       PCAP_CDC_CLK_IN_13M0                  = 0x00000000,
 578 +       PCAP_CDC_CLK_IN_15M36                 = 0x00000040,
 579 +       PCAP_CDC_CLK_IN_16M8                  = 0x00000080,
 580 +       PCAP_CDC_CLK_IN_19M44                 = 0x000000c0,
 581 +       PCAP_CDC_CLK_IN_26M0                  = 0x00000100
 582 +}PHONE_CDC_CLOCK_TYPE;
 583 +
 584 +typedef enum pcapST_SR
 585 +{
 586 +       PCAP_ST_SAMPLE_RATE_8K                = 0x00000000,
 587 +       PCAP_ST_SAMPLE_RATE_11K               = 0x00000100,
 588 +       PCAP_ST_SAMPLE_RATE_12K               = 0x00000200,
 589 +       PCAP_ST_SAMPLE_RATE_16K               = 0x00000300,
 590 +       PCAP_ST_SAMPLE_RATE_22K               = 0x00000400,
 591 +       PCAP_ST_SAMPLE_RATE_24K               = 0x00000500,
 592 +       PCAP_ST_SAMPLE_RATE_32K               = 0x00000600,
 593 +       PCAP_ST_SAMPLE_RATE_44K               = 0x00000700,
 594 +       PCAP_ST_SAMPLE_RATE_48K               = 0x00000800
 595 +}ST_SAMPLE_RATE_TYPE;
 596 +
 597 +typedef enum pcapST_BCLK
 598 +{
 599 +       PCAP_ST_BCLK_SLOT_16                  = 0x00000000,
 600 +       PCAP_ST_BCLK_SLOT_8                   = 0x00008000,
 601 +       PCAP_ST_BCLK_SLOT_4                   = 0x00010000,
 602 +       PCAP_ST_BCLK_SLOT_2                   = 0x00018000,
 603 +}ST_BCLK_TIME_SLOT_TYPE;
 604 +
 605 +typedef enum pcapST_CLK
 606 +{
 607 +       PCAP_ST_CLK_PLL_CLK_IN_13M0           = 0x00000000,
 608 +       PCAP_ST_CLK_PLL_CLK_IN_15M36          = 0x00000004,
 609 +       PCAP_ST_CLK_PLL_CLK_IN_16M8           = 0x00000008,
 610 +       PCAP_ST_CLK_PLL_CLK_IN_19M44          = 0x0000000c,
 611 +       PCAP_ST_CLK_PLL_CLK_IN_26M0           = 0x00000010,
 612 +       PCAP_ST_CLK_PLL_CLK_IN_EXT_MCLK       = 0x00000014,
 613 +       PCAP_ST_CLK_PLL_CLK_IN_FSYNC          = 0x00000018,
 614 +       PCAP_ST_CLK_PLL_CLK_IN_BITCLK         = 0x0000001c
 615 +}ST_CLK_TYPE;
 616 +
 617 +typedef enum pcapDigitalAudioInterfaceMode
 618 +{
 619 +       PCAP_DIGITAL_AUDIO_INTERFACE_NORMAL   = 0x00000000,
 620 +       PCAP_DIGITAL_AUDIO_INTERFACE_NETWORK  = 0x00002000,
 621 +       PCAP_DIGITAL_AUDIO_INTERFACE_I2S      = 0x00004000
 622 +}DIG_AUD_MODE_TYPE;
 623 +
 624 +typedef enum pcapMono
 625 +{
 626 +       PCAP_MONO_PGA_R_L_STEREO             = 0x00000000,
 627 +       PCAP_MONO_PGA_RL                     = 0x00080000,
 628 +       PCAP_MONO_PGA_RL_3DB                 = 0x00100000,
 629 +       PCAP_MONO_PGA_RL_6DB                 = 0x00180000
 630 +}MONO_TYPE;
 631 +
 632 +typedef enum pcapVibratorVoltageLevel
 633 +{
 634 +       PCAP_VIBRATOR_VOLTAGE_LEVEL0         = 0x00000000,
 635 +       PCAP_VIBRATOR_VOLTAGE_LEVEL1         = 0x00100000,
 636 +       PCAP_VIBRATOR_VOLTAGE_LEVEL2         = 0x00200000,
 637 +       PCAP_VIBRATOR_VOLTAGE_LEVEL3         = 0x00300000
 638 +}VibratorVoltageLevel_TYPE;
 639 +
 640 +typedef enum pcapTouchScreenMode
 641 +{
 642 +       PCAP_TS_POSITION_X_MEASUREMENT       = 0x00000000,
 643 +       PCAP_TS_POSITION_XY_MEASUREMENT      = 0x00020000,
 644 +       PCAP_TS_PRESSURE_MEASUREMENT         = 0x00040000,
 645 +       PCAP_TS_PLATE_X_MEASUREMENT          = 0x00060000,
 646 +       PCAP_TS_PLATE_Y_MEASUREMENT          = 0x00080000,
 647 +       PCAP_TS_STANDBY_MODE                 = 0x000a0000,
 648 +       PCAP_TS_NONTS_MODE                   = 0x000c0000
 649 +}TOUCH_SCREEN_DETECT_TYPE;
 650 +
 651 +typedef enum pcapADJRegister
 652 +{
 653 +       SSP_PCAP_ADJ_ISR_REGISTER           = 0x00,
 654 +       SSP_PCAP_ADJ_MSR_REGISTER           = 0x01,
 655 +       SSP_PCAP_ADJ_PSTAT_REGISTER         = 0x02,
 656 +       SSP_PCAP_ADJ_VREG2_REGISTER         = 0x06,
 657 +       SSP_PCAP_ADJ_AUX_VREG_REGISTER      = 0x07,
 658 +       SSP_PCAP_ADJ_BATT_DAC_REGISTER      = 0x08,
 659 +       SSP_PCAP_ADJ_ADC1_REGISTER          = 0x09,
 660 +       SSP_PCAP_ADJ_ADC2_REGISTER          = 0x0a,
 661 +       SSP_PCAP_ADJ_AUD_CODEC_REGISTER     = 0x0b,
 662 +       SSP_PCAP_ADJ_AUD_RX_AMPS_REGISTER   = 0x0c,
 663 +       SSP_PCAP_ADJ_ST_DAC_REGISTER        = 0x0d,
 664 +       SSP_PCAP_ADJ_BUSCTRL_REGISTER       = 0x14,
 665 +       SSP_PCAP_ADJ_PERIPH_REGISTER        = 0x15,
 666 +       SSP_PCAP_ADJ_LOWPWR_CTRL_REGISTER   = 0x18,
 667 +       SSP_PCAP_ADJ_TX_AUD_AMPS_REGISTER   = 0x1a,
 668 +       SSP_PCAP_ADJ_GP_REG_REGISTER        = 0x1b
 669 +}SSP_PCAP_SECONDARY_PROCESSOR_REGISTER;
 670 +
 671 +typedef enum pcapADJBit_SetType
 672 +{
 673 +       SSP_PCAP_ADJ_BIT_ISR_ADCDONEI               = 0x00000001,
 674 +       SSP_PCAP_ADJ_BIT_ISR_TSI                    = 0x00000002,
 675 +       SSP_PCAP_ADJ_BIT_ISR_1HZI                   = 0x00000004,
 676 +       SSP_PCAP_ADJ_BIT_ISR_WHI                    = 0x00000008,
 677 +       SSP_PCAP_ADJ_BIT_ISR_WLI                    = 0x00000010,
 678 +       SSP_PCAP_ADJ_BIT_ISR_TODAI                  = 0x00000020,
 679 +       SSP_PCAP_ADJ_BIT_ISR_USB4VI                 = 0x00000040,
 680 +       SSP_PCAP_ADJ_BIT_ISR_ONOFFI                 = 0x00000080,
 681 +       SSP_PCAP_ADJ_BIT_ISR_ONOFF2I                = 0x00000100,
 682 +       SSP_PCAP_ADJ_BIT_ISR_USB1VI                 = 0x00000200,
 683 +       SSP_PCAP_ADJ_BIT_ISR_MOBPORTI               = 0x00000400,
 684 +       SSP_PCAP_ADJ_BIT_ISR_MB2I                   = 0x00000800,
 685 +       SSP_PCAP_ADJ_BIT_ISR_A1I                    = 0x00001000,
 686 +       SSP_PCAP_ADJ_BIT_ISR_STI                    = 0x00002000,
 687 +       SSP_PCAP_ADJ_BIT_ISR_PCI                    = 0x00004000,
 688 +       SSP_PCAP_ADJ_BIT_ISR_WARMI                  = 0x00008000,
 689 +       SSP_PCAP_ADJ_BIT_ISR_EOLI                   = 0x00010000,
 690 +       SSP_PCAP_ADJ_BIT_ISR_CLKI                   = 0x00020000,
 691 +       SSP_PCAP_ADJ_BIT_ISR_SYS_RSTI               = 0x00040000,
 692 +       SSP_PCAP_ADJ_BIT_ISR_ADCDONE2I              = 0x00100000,
 693 +       SSP_PCAP_ADJ_BIT_ISR_SOFT_RESETI            = 0x00200000,
 694 +       SSP_PCAP_ADJ_BIT_ISR_MNEXBI                 = 0x00400000,
 695 +
 696 +       SSP_PCAP_ADJ_BIT_MSR_ADCDONEM               = 0x04000001,
 697 +       SSP_PCAP_ADJ_BIT_MSR_TSM                    = 0x04000002,
 698 +       SSP_PCAP_ADJ_BIT_MSR_1HZM                   = 0x04000004,
 699 +       SSP_PCAP_ADJ_BIT_MSR_WHM                    = 0x04000008,
 700 +       SSP_PCAP_ADJ_BIT_MSR_WLM                    = 0x04000010,
 701 +       SSP_PCAP_ADJ_BIT_MSR_TODAM                  = 0x04000020,
 702 +       SSP_PCAP_ADJ_BIT_MSR_USB4VM                 = 0x04000040,
 703 +       SSP_PCAP_ADJ_BIT_MSR_ONOFFM                 = 0x04000080,
 704 +       SSP_PCAP_ADJ_BIT_MSR_ONOFF2M                = 0x04000100,
 705 +       SSP_PCAP_ADJ_BIT_MSR_USB1VM                 = 0x04000200,
 706 +       SSP_PCAP_ADJ_BIT_MSR_MOBPORTM               = 0x04000400,
 707 +       SSP_PCAP_ADJ_BIT_MSR_MB2M                   = 0x04000800,
 708 +       SSP_PCAP_ADJ_BIT_MSR_A1M                    = 0x04001000,
 709 +       SSP_PCAP_ADJ_BIT_MSR_STM                    = 0x04002000,
 710 +       SSP_PCAP_ADJ_BIT_MSR_PCM                    = 0x04004000,
 711 +       SSP_PCAP_ADJ_BIT_MSR_WARMM                  = 0x04008000,
 712 +       SSP_PCAP_ADJ_BIT_MSR_EOLM                   = 0x04010000,
 713 +       SSP_PCAP_ADJ_BIT_MSR_CLKM                   = 0x04020000,
 714 +       SSP_PCAP_ADJ_BIT_MSR_SYS_RSTM               = 0x04040000,
 715 +       SSP_PCAP_ADJ_BIT_MSR_ADCDONE2M              = 0x04100000,
 716 +       SSP_PCAP_ADJ_BIT_MSR_SOFT_RESETM            = 0x04200000,
 717 +       SSP_PCAP_ADJ_BIT_MSR_MNEXBM                 = 0x04400000,
 718 +
 719 +       SSP_PCAP_ADJ_BIT_PSTAT_USBDET_4V            = 0x08000040,
 720 +       SSP_PCAP_ADJ_BIT_PSTAT_ONOFFSNS             = 0x08000080,
 721 +       SSP_PCAP_ADJ_BIT_PSTAT_ONOFFSNS2            = 0x08000100,
 722 +       SSP_PCAP_ADJ_BIT_PSTAT_USBDET_1V            = 0x08000200,
 723 +       SSP_PCAP_ADJ_BIT_PSTAT_MOBSENSB             = 0x08000400,
 724 +       SSP_PCAP_ADJ_BIT_PSTAT_MB2SNS               = 0x08000800,
 725 +       SSP_PCAP_ADJ_BIT_PSTAT_A1SNS                = 0x08001000,
 726 +       SSP_PCAP_ADJ_BIT_PSTAT_MSTB                 = 0x08002000,
 727 +       SSP_PCAP_ADJ_BIT_PSTAT_EOL_STAT             = 0x08010000,
 728 +       SSP_PCAP_ADJ_BIT_PSTAT_CLK_STAT             = 0x08020000,
 729 +       SSP_PCAP_ADJ_BIT_PSTAT_SYS_RST              = 0x08040000,
 730 +       SSP_PCAP_ADJ_BIT_PSTAT_BATTFBSNS            = 0x08080000,
 731 +       SSP_PCAP_ADJ_BIT_PSTAT_BATT_DET_IN_SNS      = 0x08200000,
 732 +       SSP_PCAP_ADJ_BIT_PSTAT_MNEXBSNS             = 0x08400000,
 733 +       SSP_PCAP_ADJ_BIT_PSTAT_WARM_SYS_RST         = 0x08800000,
 734 +
 735 +       SSP_PCAP_ADJ_BIT_VREG2_V1_STBY              = 0x18000001,
 736 +       SSP_PCAP_ADJ_BIT_VREG2_V2_STBY              = 0x18000002,
 737 +       SSP_PCAP_ADJ_BIT_VREG2_V3_STBY              = 0x18000004,
 738 +       SSP_PCAP_ADJ_BIT_VREG2_V4_STBY              = 0x18000008,
 739 +       SSP_PCAP_ADJ_BIT_VREG2_V5_STBY              = 0x18000010,
 740 +       SSP_PCAP_ADJ_BIT_VREG2_V6_STBY              = 0x18000020,
 741 +       SSP_PCAP_ADJ_BIT_VREG2_V7_STBY              = 0x18000040,
 742 +       SSP_PCAP_ADJ_BIT_VREG2_V8_STBY              = 0x18000080,
 743 +       SSP_PCAP_ADJ_BIT_VREG2_V9_STBY              = 0x18000100,
 744 +       SSP_PCAP_ADJ_BIT_VREG2_V10_STBY             = 0x18000200,
 745 +       SSP_PCAP_ADJ_BIT_VREG2_V1_LOWPWR            = 0x18000400,
 746 +       SSP_PCAP_ADJ_BIT_VREG2_V2_LOWPWR            = 0x18000800,
 747 +       SSP_PCAP_ADJ_BIT_VREG2_V3_LOWPWR            = 0x18001000,
 748 +       SSP_PCAP_ADJ_BIT_VREG2_V4_LOWPWR            = 0x18002000,
 749 +       SSP_PCAP_ADJ_BIT_VREG2_V5_LOWPWR            = 0x18004000,
 750 +       SSP_PCAP_ADJ_BIT_VREG2_V6_LOWPWR            = 0x18008000,
 751 +       SSP_PCAP_ADJ_BIT_VREG2_V7_LOWPWR            = 0x18010000,
 752 +       SSP_PCAP_ADJ_BIT_VREG2_V8_LOWPWR            = 0x18020000,
 753 +       SSP_PCAP_ADJ_BIT_VREG2_V9_LOWPWR            = 0x18040000,
 754 +       SSP_PCAP_ADJ_BIT_VREG2_V10_LOWPWR           = 0x18080000,
 755 +
 756 +       SSP_PCAP_ADJ_BIT_AUX_VREG_VAUX1_EN          = 0x1c000002,
 757 +       SSP_PCAP_ADJ_BIT_AUX_VREG_VAUX1_0           = 0x1c000004,
 758 +       SSP_PCAP_ADJ_BIT_AUX_VREG_VAUX1_1           = 0x1c000008,
 759 +       SSP_PCAP_ADJ_BIT_AUX_VREG_VAUX2_EN          = 0x1c000010,
 760 +       SSP_PCAP_ADJ_BIT_AUX_VREG_VAUX2_0           = 0x1c000020,
 761 +       SSP_PCAP_ADJ_BIT_AUX_VREG_VAUX2_1           = 0x1c000040,
 762 +       SSP_PCAP_ADJ_BIT_AUX_VREG_VAUX3_EN          = 0x1c000080,
 763 +       SSP_PCAP_ADJ_BIT_AUX_VREG_VAUX3_0           = 0x1c000100,
 764 +       SSP_PCAP_ADJ_BIT_AUX_VREG_VAUX3_1           = 0x1c000200,
 765 +       SSP_PCAP_ADJ_BIT_AUX_VREG_VAUX3_2           = 0x1c000400,
 766 +       SSP_PCAP_ADJ_BIT_AUX_VREG_VAUX3_3           = 0x1c000800,
 767 +       SSP_PCAP_ADJ_BIT_AUX_VREG_VAUX4_EN          = 0x1c001000,
 768 +       SSP_PCAP_ADJ_BIT_AUX_VREG_VAUX4_0           = 0x1c002000,
 769 +       SSP_PCAP_ADJ_BIT_AUX_VREG_VAUX4_1           = 0x1c004000,
 770 +       SSP_PCAP_ADJ_BIT_AUX_VREG_VSIM2_EN          = 0x1c010000,
 771 +       SSP_PCAP_ADJ_BIT_AUX_VREG_VSIM_EN           = 0x1c020000,
 772 +       SSP_PCAP_ADJ_BIT_AUX_VREG_VSIM_0            = 0x1c040000,
 773 +       SSP_PCAP_ADJ_BIT_AUX_VREG_V_VIB_EN          = 0x1c080000,
 774 +       SSP_PCAP_ADJ_BIT_AUX_VREG_V_VIB_0           = 0x1c100000,
 775 +       SSP_PCAP_ADJ_BIT_AUX_VREG_V_VIB_1           = 0x1c200000,
 776 +       SSP_PCAP_ADJ_BIT_AUX_VREG_VAUX1_STBY        = 0x1c400000,
 777 +       SSP_PCAP_ADJ_BIT_AUX_VREG_VAUX1_LOWPWR      = 0x1c800000,
 778 +       SSP_PCAP_ADJ_BIT_AUX_VREG_SW3_STBY          = 0x1d000000,
 779 +
 780 +       SSP_PCAP_ADJ_BIT_BATT_DAC_DAC0              = 0x20000001,
 781 +       SSP_PCAP_ADJ_BIT_BATT_DAC_DAC1              = 0x20000002,
 782 +       SSP_PCAP_ADJ_BIT_BATT_DAC_DAC2              = 0x20000004,
 783 +       SSP_PCAP_ADJ_BIT_BATT_DAC_DAC3              = 0x20000008,
 784 +       SSP_PCAP_ADJ_BIT_BATT_DAC_DAC4              = 0x20000010,
 785 +       SSP_PCAP_ADJ_BIT_BATT_DAC_DAC5              = 0x20000020,
 786 +       SSP_PCAP_ADJ_BIT_BATT_DAC_DAC6              = 0x20000040,
 787 +       SSP_PCAP_ADJ_BIT_BATT_DAC_DAC7              = 0x20000080,
 788 +       SSP_PCAP_ADJ_BIT_BATT_DAC_B_FDBK            = 0x20000100,
 789 +       SSP_PCAP_ADJ_BIT_BATT_DAC_EXT_ISENSE        = 0x20000200,
 790 +       SSP_PCAP_ADJ_BIT_BATT_DAC_V_COIN0           = 0x20000400,
 791 +       SSP_PCAP_ADJ_BIT_BATT_DAC_V_COIN1           = 0x20000800,
 792 +       SSP_PCAP_ADJ_BIT_BATT_DAC_V_COIN2           = 0x20001000,
 793 +       SSP_PCAP_ADJ_BIT_BATT_DAC_V_COIN3           = 0x20002000,
 794 +       SSP_PCAP_ADJ_BIT_BATT_DAC_I_COIN            = 0x20004000,
 795 +       SSP_PCAP_ADJ_BIT_BATT_DAC_COIN_CH_EN        = 0x20008000,
 796 +       SSP_PCAP_ADJ_BIT_BATT_DAC_EOL_SEL0          = 0x20020000,
 797 +       SSP_PCAP_ADJ_BIT_BATT_DAC_EOL_SEL1          = 0x20040000,
 798 +       SSP_PCAP_ADJ_BIT_BATT_DAC_EOL_SEL2          = 0x20080000,
 799 +       SSP_PCAP_ADJ_BIT_BATT_DAC_EOL_CMP_EN        = 0x20100000,
 800 +       SSP_PCAP_ADJ_BIT_BATT_DAC_BATT_DET_EN       = 0x20200000,
 801 +       SSP_PCAP_ADJ_BIT_BATT_DAC_THERMBIAS_CTRL    = 0x20400000,
 802 +
 803 +       SSP_PCAP_ADJ_BIT_ADC1_ADEN                  = 0x24000001,
 804 +       SSP_PCAP_ADJ_BIT_ADC1_RAND                  = 0x24000002,
 805 +       SSP_PCAP_ADJ_BIT_ADC1_AD_SEL1               = 0x24000004,
 806 +       SSP_PCAP_ADJ_BIT_ADC1_AD_SEL2               = 0x24000008,
 807 +       SSP_PCAP_ADJ_BIT_ADC1_ADA10                 = 0x24000010,
 808 +       SSP_PCAP_ADJ_BIT_ADC1_ADA11                 = 0x24000020,
 809 +       SSP_PCAP_ADJ_BIT_ADC1_ADA12                 = 0x24000040,
 810 +       SSP_PCAP_ADJ_BIT_ADC1_ADA20                 = 0x24000080,
 811 +       SSP_PCAP_ADJ_BIT_ADC1_ADA21                 = 0x24000100,
 812 +       SSP_PCAP_ADJ_BIT_ADC1_ADA22                 = 0x24000200,
 813 +       SSP_PCAP_ADJ_BIT_ADC1_ATO0                  = 0x24000400,
 814 +       SSP_PCAP_ADJ_BIT_ADC1_ATO1                  = 0x24000800,
 815 +       SSP_PCAP_ADJ_BIT_ADC1_ATO2                  = 0x24001000,
 816 +       SSP_PCAP_ADJ_BIT_ADC1_ATO3                  = 0x24002000,
 817 +       SSP_PCAP_ADJ_BIT_ADC1_ATOX                  = 0x24004000,
 818 +       SSP_PCAP_ADJ_BIT_ADC1_MTR1                  = 0x24008000,
 819 +       SSP_PCAP_ADJ_BIT_ADC1_MTR2                  = 0x24010000,
 820 +       SSP_PCAP_ADJ_BIT_ADC1_TS_M0                 = 0x24020000,
 821 +       SSP_PCAP_ADJ_BIT_ADC1_TS_M1                 = 0x24040000,
 822 +       SSP_PCAP_ADJ_BIT_ADC1_TS_M2                 = 0x24080000,
 823 +       SSP_PCAP_ADJ_BIT_ADC1_TS_REF_LOWPWR         = 0x24100000,
 824 +       SSP_PCAP_ADJ_BIT_ADC1_TS_REFENB             = 0x24200000,
 825 +       SSP_PCAP_ADJ_BIT_ADC1_BATT_I_POLARITY       = 0x24400000,
 826 +       SSP_PCAP_ADJ_BIT_ADC1_BATT_I_ADC            = 0x24800000,
 827 +
 828 +       SSP_PCAP_ADJ_BIT_ADC2_ADD10                 = 0x28000001,
 829 +       SSP_PCAP_ADJ_BIT_ADC2_ADD11                 = 0x28000002,
 830 +       SSP_PCAP_ADJ_BIT_ADC2_ADD12                 = 0x28000004,
 831 +       SSP_PCAP_ADJ_BIT_ADC2_ADD13                 = 0x28000008,
 832 +       SSP_PCAP_ADJ_BIT_ADC2_ADD14                 = 0x28000010,
 833 +       SSP_PCAP_ADJ_BIT_ADC2_ADD15                 = 0x28000020,
 834 +       SSP_PCAP_ADJ_BIT_ADC2_ADD16                 = 0x28000040,
 835 +       SSP_PCAP_ADJ_BIT_ADC2_ADD17                 = 0x28000080,
 836 +       SSP_PCAP_ADJ_BIT_ADC2_ADD18                 = 0x28000100,
 837 +       SSP_PCAP_ADJ_BIT_ADC2_ADD19                 = 0x28000200,
 838 +       SSP_PCAP_ADJ_BIT_ADC2_ADD20                 = 0x28000400,
 839 +       SSP_PCAP_ADJ_BIT_ADC2_ADD21                 = 0x28000800,
 840 +       SSP_PCAP_ADJ_BIT_ADC2_ADD22                 = 0x28001000,
 841 +       SSP_PCAP_ADJ_BIT_ADC2_ADD23                 = 0x28002000,
 842 +       SSP_PCAP_ADJ_BIT_ADC2_ADD24                 = 0x28004000,
 843 +       SSP_PCAP_ADJ_BIT_ADC2_ADD25                 = 0x28008000,
 844 +       SSP_PCAP_ADJ_BIT_ADC2_ADD26                 = 0x28010000,
 845 +       SSP_PCAP_ADJ_BIT_ADC2_ADD27                 = 0x28020000,
 846 +       SSP_PCAP_ADJ_BIT_ADC2_ADD28                 = 0x28040000,
 847 +       SSP_PCAP_ADJ_BIT_ADC2_ADD29                 = 0x28080000,
 848 +       SSP_PCAP_ADJ_BIT_ADC2_ADINC1                = 0x28100000,
 849 +       SSP_PCAP_ADJ_BIT_ADC2_ADINC2                = 0x28200000,
 850 +       SSP_PCAP_ADJ_BIT_ADC2_ASC                   = 0x28400000,
 851 +
 852 +       SSP_PCAP_ADJ_BIT_AUD_CODEC_AUDIHPF          = 0x2c000001,
 853 +       SSP_PCAP_ADJ_BIT_AUD_CODEC_SMB              = 0x2c000002,
 854 +       SSP_PCAP_ADJ_BIT_AUD_CODEC_AUDOHPF          = 0x2c000004,
 855 +       SSP_PCAP_ADJ_BIT_AUD_CODEC_CD_TS            = 0x2c000008,
 856 +       SSP_PCAP_ADJ_BIT_AUD_CODEC_DLM              = 0x2c000010,
 857 +       SSP_PCAP_ADJ_BIT_AUD_CODEC_ADITH            = 0x2c000020,
 858 +       SSP_PCAP_ADJ_BIT_AUD_CODEC_CDC_CLK0         = 0x2c000040,
 859 +       SSP_PCAP_ADJ_BIT_AUD_CODEC_CDC_CLK1         = 0x2c000080,
 860 +       SSP_PCAP_ADJ_BIT_AUD_CODEC_CDC_CLK2         = 0x2c000100,
 861 +       SSP_PCAP_ADJ_BIT_AUD_CODEC_CLK_INV          = 0x2c000200,
 862 +       SSP_PCAP_ADJ_BIT_AUD_CODEC_FS_INV           = 0x2c000400,
 863 +       SSP_PCAP_ADJ_BIT_AUD_CODEC_DF_RESET         = 0x2c000800,
 864 +       SSP_PCAP_ADJ_BIT_AUD_CODEC_CDC_EN           = 0x2c001000,
 865 +       SSP_PCAP_ADJ_BIT_AUD_CODEC_CDC_CLK_EN       = 0x2c002000,
 866 +       SSP_PCAP_ADJ_BIT_AUD_CODEC_FS_8K_16K        = 0x2c004000,
 867 +       SSP_PCAP_ADJ_BIT_AUD_CODEC_DIG_AUD_IN       = 0x2c008000,
 868 +       SSP_PCAP_ADJ_BIT_AUD_CODEC_CLK_IN_SEL       = 0x2c010000,
 869 +       SSP_PCAP_ADJ_BIT_AUD_CODEC_MIC2_MUX         = 0x2c020000,
 870 +       SSP_PCAP_ADJ_BIT_AUD_CODEC_MIC2IG0          = 0x2c040000,
 871 +       SSP_PCAP_ADJ_BIT_AUD_CODEC_MIC2IG1          = 0x2c080000,
 872 +       SSP_PCAP_ADJ_BIT_AUD_CODEC_MIC2IG2          = 0x2c100000,
 873 +       SSP_PCAP_ADJ_BIT_AUD_CODEC_MIC2IG3          = 0x2c200000,
 874 +       SSP_PCAP_ADJ_BIT_AUD_CODEC_MIC2IG4          = 0x2c400000,
 875 +       SSP_PCAP_ADJ_BIT_AUD_CODEC_MIC2IG_PRI_ADJ   = 0x2c800000,
 876 +       SSP_PCAP_ADJ_BIT_AUD_CODEC_CDC_PRI_ADJ      = 0x2c200000,
 877 +
 878 +       SSP_PCAP_ADJ_BIT_AUD_RX_AMPS_A1_EN          = 0x30000001,
 879 +       SSP_PCAP_ADJ_BIT_AUD_RX_AMPS_A2_EN          = 0x30000002,
 880 +       SSP_PCAP_ADJ_BIT_AUD_RX_AMPS_A4_EN          = 0x30000010,
 881 +       SSP_PCAP_ADJ_BIT_AUD_RX_AMPS_ARIGHT_EN      = 0x30000020,
 882 +       SSP_PCAP_ADJ_BIT_AUD_RX_AMPS_ALEFT_EN       = 0x30000040,
 883 +       SSP_PCAP_ADJ_BIT_AUD_RX_AMPS_CD_BYP         = 0x30000080,
 884 +       SSP_PCAP_ADJ_BIT_AUD_RX_AMPS_CDC_SW         = 0x30000100,
 885 +       SSP_PCAP_ADJ_BIT_AUD_RX_AMPS_ST_DAC_SW      = 0x30000200,
 886 +       SSP_PCAP_ADJ_BIT_AUD_RX_AMPS_PGA_IN_SW      = 0x30000400,
 887 +       SSP_PCAP_ADJ_BIT_AUD_RX_AMPS_PGA_R_EN       = 0x30000800,
 888 +       SSP_PCAP_ADJ_BIT_AUD_RX_AMPS_PGA_L_EN       = 0x30001000,
 889 +       SSP_PCAP_ADJ_BIT_AUD_RX_AMPS_AUDOG0         = 0x30002000,
 890 +       SSP_PCAP_ADJ_BIT_AUD_RX_AMPS_AUDOG1         = 0x30004000,
 891 +       SSP_PCAP_ADJ_BIT_AUD_RX_AMPS_AUDOG2         = 0x30008000,
 892 +       SSP_PCAP_ADJ_BIT_AUD_RX_AMPS_AUDOG3         = 0x30010000,
 893 +       SSP_PCAP_ADJ_BIT_AUD_RX_AMPS_A1CTRL         = 0x30020000,
 894 +       SSP_PCAP_ADJ_BIT_AUD_RX_AMPS_MONO0          = 0x30080000,
 895 +       SSP_PCAP_ADJ_BIT_AUD_RX_AMPS_MONO1          = 0x30100000,
 896 +       SSP_PCAP_ADJ_BIT_AUD_RX_AMPS_AUDOG_PRI_ADJ  = 0x30200000,
 897 +       SSP_PCAP_ADJ_BIT_AUD_RX_AMPS_MONO_PRI_ADJ   = 0x30400000,
 898 +       SSP_PCAP_ADJ_BIT_AUD_RX_AMPS_RX_PRI_ADJ0    = 0x30800000,
 899 +       SSP_PCAP_ADJ_BIT_AUD_RX_AMPS_RX_PRI_ADJ1    = 0x31000000,
 900 +
 901 +       SSP_PCAP_ADJ_BIT_ST_DAC_SMB_ST_DAC          = 0x34000001,
 902 +       SSP_PCAP_ADJ_BIT_ST_DAC_STDET_EN            = 0x34000002,
 903 +       SSP_PCAP_ADJ_BIT_ST_DAC_ST_CLK0             = 0x34000004,
 904 +       SSP_PCAP_ADJ_BIT_ST_DAC_ST_CLK1             = 0x34000008,
 905 +       SSP_PCAP_ADJ_BIT_ST_DAC_ST_CLK2             = 0x34000010,
 906 +       SSP_PCAP_ADJ_BIT_ST_DAC_ST_CLK_EN           = 0x34000020,
 907 +       SSP_PCAP_ADJ_BIT_ST_DAC_DF_RESET_ST_DAC     = 0x34000040,
 908 +       SSP_PCAP_ADJ_BIT_ST_DAC_ST_DAC_EN           = 0x34000080,
 909 +       SSP_PCAP_ADJ_BIT_ST_DAC_SR0                 = 0x34000100,
 910 +       SSP_PCAP_ADJ_BIT_ST_DAC_SR1                 = 0x34000200,
 911 +       SSP_PCAP_ADJ_BIT_ST_DAC_SR2                 = 0x34000400,
 912 +       SSP_PCAP_ADJ_BIT_ST_DAC_SR3                 = 0x34000800,
 913 +       SSP_PCAP_ADJ_BIT_ST_DAC_DIG_AUD_IN_ST_DAC   = 0x34001000,
 914 +       SSP_PCAP_ADJ_BIT_ST_DAC_DIG_AUD_FS0         = 0x34002000,
 915 +       SSP_PCAP_ADJ_BIT_ST_DAC_DIG_AUD_FS1         = 0x34004000,
 916 +       SSP_PCAP_ADJ_BIT_ST_DAC_BCLK0               = 0x34008000,
 917 +       SSP_PCAP_ADJ_BIT_ST_DAC_BCLK1               = 0x34010000,
 918 +       SSP_PCAP_ADJ_BIT_ST_DAC_ST_CLK_INV          = 0x34020000,
 919 +       SSP_PCAP_ADJ_BIT_ST_DAC_ST_FS_INV           = 0x34040000,
 920 +       SSP_PCAP_ADJ_BIT_ST_DAC_ST_DAC_CLK_IN_SEL   = 0x34080000,
 921 +       SSP_PCAP_ADJ_BIT_ST_DAC_ST_DAC_PRI_ADJ      = 0x35000000,
 922 +
 923 +       SSP_PCAP_ADJ_BIT_BUSCTRL_FSENB              = 0x50000001,
 924 +       SSP_PCAP_ADJ_BIT_BUSCTRL_USB_SUSPEND        = 0x50000002,
 925 +       SSP_PCAP_ADJ_BIT_BUSCTRL_USB_PU             = 0x50000004,
 926 +       SSP_PCAP_ADJ_BIT_BUSCTRL_USB_PD             = 0x50000008,
 927 +       SSP_PCAP_ADJ_BIT_BUSCTRL_VUSB_EN            = 0x50000010,
 928 +       SSP_PCAP_ADJ_BIT_BUSCTRL_USB_PS             = 0x50000020,
 929 +       SSP_PCAP_ADJ_BIT_BUSCTRL_VUSB_MSTR_EN       = 0x50000040,
 930 +       SSP_PCAP_ADJ_BIT_BUSCTRL_VBUS_PD_ENB        = 0x50000080,
 931 +       SSP_PCAP_ADJ_BIT_BUSCTRL_CURRLIM            = 0x50000100,
 932 +       SSP_PCAP_ADJ_BIT_BUSCTRL_RS232ENB           = 0x50000200,
 933 +       SSP_PCAP_ADJ_BIT_BUSCTRL_RS232_DIR          = 0x50000400,
 934 +       SSP_PCAP_ADJ_BIT_BUSCTRL_SE0_CONN           = 0x50000800,
 935 +       SSP_PCAP_ADJ_BIT_BUSCTRL_USB_PDM            = 0x50001000,
 936 +       SSP_PCAP_ADJ_BIT_BUSCTRL_BUS_PRI_ADJ        = 0x51000000,
 937 +
 938 +       SSP_PCAP_ADJ_BIT_PERIPH_BL_CTRL0            = 0x54000001,
 939 +       SSP_PCAP_ADJ_BIT_PERIPH_BL_CTRL1            = 0x54000002,
 940 +       SSP_PCAP_ADJ_BIT_PERIPH_BL_CTRL2            = 0x54000004,
 941 +       SSP_PCAP_ADJ_BIT_PERIPH_BL_CTRL3            = 0x54000008,
 942 +       SSP_PCAP_ADJ_BIT_PERIPH_BL_CTRL4            = 0x54000010,
 943 +       SSP_PCAP_ADJ_BIT_PERIPH_LEDR_EN             = 0x54000020,
 944 +       SSP_PCAP_ADJ_BIT_PERIPH_LEDG_EN             = 0x54000040,
 945 +       SSP_PCAP_ADJ_BIT_PERIPH_LEDR_CTRL0          = 0x54000080,
 946 +       SSP_PCAP_ADJ_BIT_PERIPH_LEDR_CTRL1          = 0x54000100,
 947 +       SSP_PCAP_ADJ_BIT_PERIPH_LEDR_CTRL2          = 0x54000200,
 948 +       SSP_PCAP_ADJ_BIT_PERIPH_LEDR_CTRL3          = 0x54000400,
 949 +       SSP_PCAP_ADJ_BIT_PERIPH_LEDG_CTRL0          = 0x54000800,
 950 +       SSP_PCAP_ADJ_BIT_PERIPH_LEDG_CTRL1          = 0x54001000,
 951 +       SSP_PCAP_ADJ_BIT_PERIPH_LEDG_CTRL2          = 0x54002000,
 952 +       SSP_PCAP_ADJ_BIT_PERIPH_LEDG_CTRL3          = 0x54004000,
 953 +       SSP_PCAP_ADJ_BIT_PERIPH_LEDR_I0             = 0x54008000,
 954 +       SSP_PCAP_ADJ_BIT_PERIPH_LEDR_I1             = 0x54010000,
 955 +       SSP_PCAP_ADJ_BIT_PERIPH_LEDG_I0             = 0x54020000,
 956 +       SSP_PCAP_ADJ_BIT_PERIPH_LEDG_I1             = 0x54040000,
 957 +       SSP_PCAP_ADJ_BIT_PERIPH_SKIP                = 0x54080000,
 958 +       SSP_PCAP_ADJ_BIT_PERIPH_BL2_CTRL0           = 0x54100000,
 959 +       SSP_PCAP_ADJ_BIT_PERIPH_BL2_CTRL1           = 0x54200000,
 960 +       SSP_PCAP_ADJ_BIT_PERIPH_BL2_CTRL2           = 0x54400000,
 961 +       SSP_PCAP_ADJ_BIT_PERIPH_BL2_CTRL3           = 0x54800000,
 962 +       SSP_PCAP_ADJ_BIT_PERIPH_BL2_CTRL4           = 0x55000000,
 963 +
 964 +       SSP_PCAP_ADJ_BIT_LOWPWR_CTRL_VAUX2_STBY     = 0x60000001,
 965 +       SSP_PCAP_ADJ_BIT_LOWPWR_CTRL_VAUX2_LOWPWR   = 0x60000002,
 966 +       SSP_PCAP_ADJ_BIT_LOWPWR_CTRL_VAUX3_STBY     = 0x60000004,
 967 +       SSP_PCAP_ADJ_BIT_LOWPWR_CTRL_VAUX3_LOWPWR   = 0x60000008,
 968 +       SSP_PCAP_ADJ_BIT_LOWPWR_CTRL_VAUX4_STBY     = 0x60000010,
 969 +       SSP_PCAP_ADJ_BIT_LOWPWR_CTRL_VAUX4_LOWPWR   = 0x60000020,
 970 +       SSP_PCAP_ADJ_BIT_LOWPWR_CTRL_VSIM_LOWPWR    = 0x60000040,
 971 +       SSP_PCAP_ADJ_BIT_LOWPWR_CTRL_VSIM2_LOWPWR   = 0x60000080,
 972 +       SSP_PCAP_ADJ_BIT_LOWPWR_CTRL_SW1_MODE00     = 0x60000100,
 973 +       SSP_PCAP_ADJ_BIT_LOWPWR_CTRL_SW1_MODE01     = 0x60000200,
 974 +       SSP_PCAP_ADJ_BIT_LOWPWR_CTRL_SW1_MODE10     = 0x60000400,
 975 +       SSP_PCAP_ADJ_BIT_LOWPWR_CTRL_SW1_MODE11     = 0x60000800,
 976 +       SSP_PCAP_ADJ_BIT_LOWPWR_CTRL_SW10_DVS       = 0x60001000,
 977 +       SSP_PCAP_ADJ_BIT_LOWPWR_CTRL_SW11_DVS       = 0x60002000,
 978 +       SSP_PCAP_ADJ_BIT_LOWPWR_CTRL_SW12_DVS       = 0x60004000,
 979 +       SSP_PCAP_ADJ_BIT_LOWPWR_CTRL_SW13_DVS       = 0x60008000,
 980 +       SSP_PCAP_ADJ_BIT_LOWPWR_CTRL_SW2_MODE00     = 0x60010000,
 981 +       SSP_PCAP_ADJ_BIT_LOWPWR_CTRL_SW2_MODE01     = 0x60020000,
 982 +       SSP_PCAP_ADJ_BIT_LOWPWR_CTRL_SW2_MODE10     = 0x60040000,
 983 +       SSP_PCAP_ADJ_BIT_LOWPWR_CTRL_SW2_MODE11     = 0x60080000,
 984 +       SSP_PCAP_ADJ_BIT_LOWPWR_CTRL_SW20_DVS       = 0x60100000,
 985 +       SSP_PCAP_ADJ_BIT_LOWPWR_CTRL_SW21_DVS       = 0x60200000,
 986 +       SSP_PCAP_ADJ_BIT_LOWPWR_CTRL_SW22_DVS       = 0x60400000,
 987 +       SSP_PCAP_ADJ_BIT_LOWPWR_CTRL_SW23_DVS       = 0x60800000,
 988 +       SSP_PCAP_ADJ_BIT_LOWPWR_CTRL_VC_STBY        = 0x61000000,
 989 +
 990 +       SSP_PCAP_ADJ_BIT_TX_AUD_AMPS_AUDIG0         = 0x68000001,
 991 +       SSP_PCAP_ADJ_BIT_TX_AUD_AMPS_AUDIG1         = 0x68000002,
 992 +       SSP_PCAP_ADJ_BIT_TX_AUD_AMPS_AUDIG2         = 0x68000004,
 993 +       SSP_PCAP_ADJ_BIT_TX_AUD_AMPS_AUDIG3         = 0x68000008,
 994 +       SSP_PCAP_ADJ_BIT_TX_AUD_AMPS_AUDIG4         = 0x68000010,
 995 +       SSP_PCAP_ADJ_BIT_TX_AUD_AMPS_A3_EN          = 0x68000020,
 996 +       SSP_PCAP_ADJ_BIT_TX_AUD_AMPS_A3_MUX         = 0x68000040,
 997 +       SSP_PCAP_ADJ_BIT_TX_AUD_AMPS_A5_EN          = 0x68000080,
 998 +       SSP_PCAP_ADJ_BIT_TX_AUD_AMPS_A5_MUX         = 0x68000100,
 999 +       SSP_PCAP_ADJ_BIT_TX_AUD_AMPS_EXT_MIC_MUX    = 0x68000200,
1000 +       SSP_PCAP_ADJ_BIT_TX_AUD_AMPS_MB_ON2         = 0x68000400,
1001 +       SSP_PCAP_ADJ_BIT_TX_AUD_AMPS_MB_ON1         = 0x68000800,
1002 +       SSP_PCAP_ADJ_BIT_TX_AUD_AMPS_A1ID_TX        = 0x68001000,
1003 +       SSP_PCAP_ADJ_BIT_TX_AUD_AMPS_A1_CONFIG      = 0x68002000,
1004 +       SSP_PCAP_ADJ_BIT_TX_AUD_AMPS_AHS_CONFIG     = 0x68004000,
1005 +       SSP_PCAP_ADJ_BIT_TX_AUD_AMPS_A2_CONFIG      = 0x68008000,
1006 +       SSP_PCAP_ADJ_BIT_TX_AUD_AMPS_AUDIO_LOWPWR   = 0x68080000,
1007 +       SSP_PCAP_ADJ_BIT_TX_AUD_AMPS_AUDIO_STBY     = 0x68100000,
1008 +       SSP_PCAP_ADJ_BIT_TX_AUD_AMPS_V2_EN_2        = 0x68200000,
1009 +       SSP_PCAP_ADJ_BIT_TX_AUD_AMPS_AUDIG_PRI_ADJ  = 0x68400000,
1010 +       SSP_PCAP_ADJ_BIT_TX_AUD_AMPS_TX_PRI_ADJ0    = 0x68800000,
1011 +       SSP_PCAP_ADJ_BIT_TX_AUD_AMPS_TX_PRI_ADJ1    = 0x69000000,
1012 +
1013 +       SSP_PCAP_ADJ_BIT_SYS_RST_CLR                = 0x6c000001,
1014 +       SSP_PCAP_ADJ_BIT_SYS_RST_MODE0              = 0x6c000002,
1015 +       SSP_PCAP_ADJ_BIT_SYS_RST_MODE1              = 0x6c000004,
1016 +       SSP_PCAP_ADJ_BIT_SYS_VFLASH_0               = 0x6c000008,
1017 +       SSP_PCAP_ADJ_BIT_SYS_VFLASH_1               = 0x6c000010,
1018 +       SSP_PCAP_ADJ_BIT_SYS_MID_SELECT             = 0x6c000020,
1019 +       SSP_PCAP_ADJ_BIT_SYS_MID_FET                = 0x6c000040,
1020 +       SSP_PCAP_ADJ_BIT_SYS_MAIN_LOW               = 0x6c000080,
1021 +       SSP_PCAP_ADJ_BIT_SYS_BATTFB_DIS             = 0x6c000100,
1022 +       SSP_PCAP_ADJ_BIT_SYS_GP_REG9                = 0x6c000200,
1023 +       SSP_PCAP_ADJ_BIT_SYS_GP_REG10               = 0x6c000400,
1024 +       SSP_PCAP_ADJ_BIT_SYS_GP_REG11               = 0x6c000800,
1025 +       SSP_PCAP_ADJ_BIT_SYS_GP_REG12               = 0x6c001000,
1026 +       SSP_PCAP_ADJ_BIT_SYS_GP_REG13               = 0x6c002000,
1027 +       SSP_PCAP_ADJ_BIT_SYS_GP_REG14               = 0x6c004000,
1028 +       SSP_PCAP_ADJ_BIT_SYS_GP_REG15               = 0x6c008000,
1029 +       SSP_PCAP_ADJ_BIT_SYS_GP_REG16               = 0x6c010000,
1030 +       SSP_PCAP_ADJ_BIT_SYS_GP_REG17               = 0x6c020000,
1031 +       SSP_PCAP_ADJ_BIT_SYS_GP_REG18               = 0x6c040000,
1032 +       SSP_PCAP_ADJ_BIT_SYS_GP_REG19               = 0x6c080000,
1033 +       SSP_PCAP_ADJ_BIT_SYS_GP_REG20               = 0x6c100000,
1034 +       SSP_PCAP_ADJ_BIT_SYS_GP_REG21               = 0x6c200000,
1035 +       SSP_PCAP_ADJ_BIT_SYS_GP_REG22               = 0x6c400000,
1036 +       SSP_PCAP_ADJ_BIT_SYS_GP_REG23               = 0x6c800000,
1037 +       SSP_PCAP_ADJ_BIT_SYS_GP_REG24               = 0x6d000000
1038 +
1039 +}SSP_PCAP_SECONDARY_PROCESSOR_REGISTER_BIT_TYPE;
1040 +
1041 +/************************ FUNCTION PROTOTYPES **************************************/
1042 +extern void ssp_pcap_init(void);
1043 +extern void ssp_pcap_release(void);
1044 +
1045 +extern void ssp_pcap_open(SSP_PCAP_INIT_DRIVER_TYPE portType);
1046 +extern void ssp_pcap_close(void);
1047 +
1048 +extern void ssp_pcap_intoSleep_callBack(void);
1049 +extern void ssp_pcap_wakeUp_callBack(void);
1050 +
1051 +
1052 +extern SSP_PCAP_STATUS SSP_PCAP_write_data_to_PCAP(SSP_PCAP_SECONDARY_PROCESSOR_REGISTER ssp_pcap_register,U32 ssp_pcap_register_value);
1053 +extern SSP_PCAP_STATUS SSP_PCAP_read_data_from_PCAP(SSP_PCAP_SECONDARY_PROCESSOR_REGISTER ssp_pcap_register,P_U32 p_ssp_pcap_register_value);
1054 +
1055 +extern SSP_PCAP_STATUS SSP_PCAP_bit_set(SSP_PCAP_SECONDARY_PROCESSOR_REGISTER_BIT_TYPE ssp_pcap_bit ) ;
1056 +extern SSP_PCAP_STATUS SSP_PCAP_bit_clean(SSP_PCAP_SECONDARY_PROCESSOR_REGISTER_BIT_TYPE ssp_pcap_bit ) ;
1057 +extern SSP_PCAP_BIT_STATUS SSP_PCAP_get_bit_from_buffer(SSP_PCAP_SECONDARY_PROCESSOR_REGISTER_BIT_TYPE ssp_pcap_bit ) ;
1058 +extern SSP_PCAP_BIT_STATUS SSP_PCAP_get_bit_from_PCAP(SSP_PCAP_SECONDARY_PROCESSOR_REGISTER_BIT_TYPE ssp_pcap_bit ) ;
1059 +extern U32 SSP_PCAP_get_register_value_from_buffer(SSP_PCAP_SECONDARY_PROCESSOR_REGISTER ssp_pcap_register ) ;
1060 +
1061 +extern SSP_PCAP_STATUS SSP_PCAP_TSI_mode_set(TOUCH_SCREEN_DETECT_TYPE mode_Type );
1062 +extern SSP_PCAP_STATUS SSP_PCAP_TSI_start_XY_read(void);
1063 +extern SSP_PCAP_STATUS SSP_PCAP_TSI_get_XY_value(P_U16 p_x,P_U16 p_y);
1064 +extern SSP_PCAP_STATUS SSP_PCAP_CDC_CLK_set(PHONE_CDC_CLOCK_TYPE clkType);
1065 +
1066 +extern SSP_PCAP_STATUS SSP_PCAP_CDC_SR_set(ST_SAMPLE_RATE_TYPE srType);
1067 +extern SSP_PCAP_STATUS SSP_PCAP_BCLK_set(ST_BCLK_TIME_SLOT_TYPE bclkType);
1068 +extern SSP_PCAP_STATUS SSP_PCAP_STCLK_set(ST_CLK_TYPE stClkType);
1069 +extern SSP_PCAP_STATUS SSP_PCAP_DIG_AUD_FS_set(DIG_AUD_MODE_TYPE fsType);
1070 +extern SSP_PCAP_STATUS SSP_PCAP_AUDIG_set(U32 audioInGain);
1071 +extern SSP_PCAP_STATUS SSP_PCAP_MONO_set(MONO_TYPE monoType);
1072 +extern SSP_PCAP_STATUS SSP_PCAP_AUDOG_set(U32 audioOutGain);
1073 +
1074 +extern SSP_PCAP_STATUS SSP_PCAP_V_VIB_level_set(VibratorVoltageLevel_TYPE VIBLevelType);
1075 +extern SSP_PCAP_STATUS SSP_PCAP_configure_USB_UART_transeiver(SSP_PCAP_PORT_TYPE portType);
1076 +extern SSP_PCAP_BIT_STATUS SSP_PCAP_get_audio_in_status(void);
1077 +
1078 +/* for log */
1079 +extern void pcap_log_add_pure_data(u8* pData,u32 len);
1080 +extern void pcap_log_add_data(u8* pData,u32 len);
1081 +
1082 +/* screen lock on/off handler */
1083 +extern void ssp_pcap_screenlock_lock(u32 data);
1084 +extern void ssp_pcap_screenlock_unlock(u32 data);
1085 +
1086 +#endif
1087 Index: linux-2.6.20.7/include/asm-arm/arch-pxa/irqs.h
1088 ===================================================================
1089 --- linux-2.6.20.7.orig/include/asm-arm/arch-pxa/irqs.h 2007-04-21 08:26:32.000000000 -0300
1090 +++ linux-2.6.20.7/include/asm-arm/arch-pxa/irqs.h      2007-04-21 08:26:37.000000000 -0300
1091 @@ -176,7 +176,8 @@
1092  #define NR_IRQS                        (IRQ_LOCOMO_SPI_TEND + 1)
1093  #elif defined(CONFIG_ARCH_LUBBOCK) || \
1094        defined(CONFIG_MACH_LOGICPD_PXA270) || \
1095 -      defined(CONFIG_MACH_MAINSTONE)
1096 +      defined(CONFIG_MACH_MAINSTONE) || \
1097 +      defined(CONFIG_PXA_EZX)
1098  #define NR_IRQS                        (IRQ_BOARD_END)
1099  #else
1100  #define NR_IRQS                        (IRQ_BOARD_START)
1101 @@ -222,3 +223,16 @@
1102  #define IRQ_LOCOMO_GPIO_BASE   (IRQ_BOARD_START + 1)
1103  #define IRQ_LOCOMO_LT_BASE     (IRQ_BOARD_START + 2)
1104  #define IRQ_LOCOMO_SPI_BASE    (IRQ_BOARD_START + 3)
1105 +
1106 +/* EZX Interrupts (CONFIG_EZX) */
1107 +#define EZX_IRQ(x)             (IRQ_BOARD_START + (x))
1108 +#define EZX_IRQ_ADCDONE                EZX_IRQ(0)      /* PCAP */
1109 +#define EZX_IRQ_TS             EZX_IRQ(1)      /* PCAP */
1110 +#define EZX_IRQ_USB4V          EZX_IRQ(2)      /* PCAP */
1111 +#define EZX_IRQ_USB1V          EZX_IRQ(3)      /* PCAP */
1112 +#define EZX_IRQ_HEADJACK       EZX_IRQ(4)      /* PCAP */
1113 +#define EZX_IRQ_MIC            EZX_IRQ(5)      /* PCAP */
1114 +#define EZX_IRQ_ADCDONE2       EZX_IRQ(6)      /* PCAP */
1115 +#define EZX_IRQ_ONOFF          EZX_IRQ(7)
1116 +#define EZX_IRQ_ONOFF2         EZX_IRQ(8)
1117 +
1118 Index: linux-2.6.20.7/arch/arm/mach-pxa/Makefile
1119 ===================================================================
1120 --- linux-2.6.20.7.orig/arch/arm/mach-pxa/Makefile      2007-04-21 08:26:37.000000000 -0300
1121 +++ linux-2.6.20.7/arch/arm/mach-pxa/Makefile   2007-04-21 08:45:09.000000000 -0300
1122 @@ -18,7 +18,7 @@
1123  obj-$(CONFIG_MACH_AKITA)       += akita-ioexp.o
1124  obj-$(CONFIG_MACH_POODLE)      += poodle.o corgi_ssp.o
1125  obj-$(CONFIG_MACH_TOSA)         += tosa.o
1126 -obj-$(CONFIG_PXA_EZX)          += ezx.o ezx_lcd.o ezx_ssp.o
1127 +obj-$(CONFIG_PXA_EZX)          += ezx.o ezx_lcd.o ezx_ssp.o ezx-pcap.o
1128
1129  # Support for blinky lights
1130  led-y := leds.o
1131 Index: linux-2.6.20.7/arch/arm/mach-pxa/ezx.c
1132 ===================================================================
1133 --- linux-2.6.20.7.orig/arch/arm/mach-pxa/ezx.c 2007-04-21 08:26:37.000000000 -0300
1134 +++ linux-2.6.20.7/arch/arm/mach-pxa/ezx.c      2007-04-21 08:51:15.000000000 -0300
1135 @@ -73,6 +73,24 @@
1136         .clk_pcap       = 1,
1137  };
1138
1139 +/* PCAP */
1140 +static struct resource ezxpcap_resources[] = {
1141 +       [0] = {
1142 +               .start          = IRQ_GPIO1,
1143 +               .end            = IRQ_GPIO1,
1144 +               .flags          = IORESOURCE_IRQ,
1145 +       },
1146 +};
1147 +
1148 +struct platform_device ezxpcap_device = {
1149 +       .name           = "ezx-pcap",
1150 +       .id             = -1,
1151 +       .dev            = {
1152 +               .parent         = &ezxssp_device.dev,
1153 +       },
1154 +       .num_resources  = ARRAY_SIZE(ezxpcap_resources),
1155 +       .resource       = ezxpcap_resources,
1156 +};
1157
1158  /* OHCI Controller */
1159
1160 @@ -236,7 +254,7 @@
1161  };
1162
1163
1164 -static struct resource ezx_bp_resources[] = {
1165 +static struct resource ezxbp_resources[] = {
1166         [0] = {
1167                 .start          = GPIO_BP_RDY,
1168                 .end            = GPIO_BP_RDY,
1169 @@ -256,15 +274,15 @@
1170  #endif
1171  };
1172
1173 -static struct platform_device ezx_bp_device = {
1174 +static struct platform_device ezxbp_device = {
1175         .name           = "ezx-bp",
1176         .dev            = {
1177                 //.parent               =
1178                 //.platform_data        =
1179         },
1180         .id             = -1,
1181 -       .num_resources  = ARRAY_SIZE(ezx_bp_resources),
1182 -       .resource       = ezx_bp_resources,
1183 +       .num_resources  = ARRAY_SIZE(ezxbp_resources),
1184 +       .resource       = ezxbp_resources,
1185  };
1186
1187  static void __init ezx_init_gpio_irq(void)
1188 @@ -297,7 +315,8 @@
1189
1190  static struct platform_device *devices[] __initdata = {
1191         &ezxssp_device,
1192 -       &ezx_bp_device,
1193 +       &ezxpcap_device,
1194 +       &ezxbp_device,
1195  };
1196
1197  static void __init a780_init(void)