1 Index: linux-2.6.20.7/arch/arm/boot/compressed/head-xscale.S
2 ===================================================================
3 --- linux-2.6.20.7.orig/arch/arm/boot/compressed/head-xscale.S 2007-04-21 22:31:54.000000000 -0300
4 +++ linux-2.6.20.7/arch/arm/boot/compressed/head-xscale.S 2007-04-21 22:32:53.000000000 -0300
9 +#ifdef CONFIG_ARCH_EZX
10 + mov r7, #MACH_TYPE_EZX
12 Index: linux-2.6.20.7/arch/arm/mach-pxa/Kconfig
13 ===================================================================
14 --- linux-2.6.20.7.orig/arch/arm/mach-pxa/Kconfig 2007-04-21 22:31:54.000000000 -0300
15 +++ linux-2.6.20.7/arch/arm/mach-pxa/Kconfig 2007-04-22 01:33:15.000000000 -0300
17 bool "Keith und Koep Trizeps4 DIMM-Module"
21 + bool "Motorola EZX Platform"
34 + prompt "Select target EZX device"
37 + bool "Motorola E680 GSM Phone"
41 + bool "Motorola A780 GSM Phone"
45 + bool "Motorola E2 GSM Phone"
58 Enable support for PXA2xx SSP ports
61 Index: linux-2.6.20.7/arch/arm/mach-pxa/Makefile
62 ===================================================================
63 --- linux-2.6.20.7.orig/arch/arm/mach-pxa/Makefile 2007-04-21 22:31:54.000000000 -0300
64 +++ linux-2.6.20.7/arch/arm/mach-pxa/Makefile 2007-04-22 01:33:17.000000000 -0300
66 obj-$(CONFIG_MACH_AKITA) += akita-ioexp.o
67 obj-$(CONFIG_MACH_POODLE) += poodle.o corgi_ssp.o
68 obj-$(CONFIG_MACH_TOSA) += tosa.o
69 +obj-$(CONFIG_PXA_EZX) += ezx.o ezx_lcd.o ezx_ssp.o
71 # Support for blinky lights
73 Index: linux-2.6.20.7/arch/arm/mach-pxa/ezx.c
74 ===================================================================
75 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
76 +++ linux-2.6.20.7/arch/arm/mach-pxa/ezx.c 2007-04-22 01:33:17.000000000 -0300
79 + * linux/arch/arm/mach-ezx/a780.c
81 + * Support for the Motorola Ezx A780 Development Platform.
83 + * Author: Zhuang Xiaofan
84 + * Created: Nov 25, 2003
85 + * Copyright: Motorola Inc.
87 + * This program is free software; you can redistribute it and/or modify
88 + * it under the terms of the GNU General Public License version 2 as
89 + * published by the Free Software Foundation.
92 +#include <linux/init.h>
93 +#include <linux/major.h>
94 +#include <linux/fs.h>
95 +#include <linux/interrupt.h>
96 +#include <linux/sched.h>
97 +#include <linux/bitops.h>
98 +#include <linux/apm_bios.h>
99 +#include <linux/platform_device.h>
100 +#include <linux/input.h>
102 +#include <asm/types.h>
103 +#include <asm/setup.h>
104 +#include <asm/memory.h>
105 +#include <asm/mach-types.h>
106 +#include <asm/hardware.h>
107 +#include <asm/irq.h>
109 +#include <asm/mach/arch.h>
110 +#include <asm/mach/map.h>
111 +#include <asm/mach/irq.h>
113 +#include <asm/arch/ohci.h>
114 +#include <asm/arch/pxa-regs.h>
117 +#include "generic.h"
118 +#include <linux/tty.h>
119 +#include <linux/apm_bios.h>
122 +extern void usb_send_readurb(void);
123 +extern int ezx_ssp_set_machinfo(struct ezxssp_machinfo *);
124 +//FIXME extern void pm_do_poweroff(void);
127 +#define FIRST_STEP 2
129 +#define BP_RDY_TIMEOUT 0x000c0000
131 +/* check power down condition */
132 +inline void check_power_off(void)
134 + if (!(GPIO_is_high(GPIO_BB_WDI2))) {
136 +//FIXME pm_do_poweroff();
142 +struct platform_device ezxssp_device = {
147 +struct ezxssp_machinfo ezx_ssp_machinfo = {
149 + .cs_pcap = GPIO_SPI_CE,
154 +/* OHCI Controller */
156 +static int ezx_ohci_init(struct device *dev)
158 + /* for A780 support (connected with Neptune) */
159 + pxa_gpio_mode(GPIO30_USB_P3_2); /* GPIO30 - USB_P3_2/ICL_TXENB */
160 + pxa_gpio_mode(GPIO31_USB_P3_6); /* GPIO31 - USB_P3_6/ICL_VPOUT */
161 + pxa_gpio_mode(GPIO90_USB_P3_5); /* GPIO90 - USB_P3_5/ICL_VPIN */
162 + pxa_gpio_mode(GPIO91_USB_P3_1); /* GPIO91 - USB_P3_1/ICL_XRXD */
163 + pxa_gpio_mode(GPIO56_USB_P3_4); /* GPIO56 - USB_P3_4/ICL_VMOUT */
164 + pxa_gpio_mode(GPIO113_USB_P3_3);/* GPIO113 - USB_P3_3/ICL_VMIN */
165 + UP3OCR = 0x00000002;
167 + UHCHR = UHCHR & ~(UHCHR_SSEP2 | UHCHR_SSEP3 | UHCHR_SSE);
172 +static struct pxaohci_platform_data ezx_ohci_platform_data = {
173 + .port_mode = PMM_NPS_MODE,
174 + .init = ezx_ohci_init,
177 +static int step = FIRST_STEP;
178 +void handshake(void)
180 + /* step 1: check MCU_INT_SW or BP_RDY is low (now it is checked in apboot) */
182 + int timeout = BP_RDY_TIMEOUT;
184 + /* config MCU_INT_SW, BP_RDY as input */
185 + GPDR(GPIO_MCU_INT_SW) &= ~GPIO_bit(GPIO_MCU_INT_SW);
186 + GPDR(GPIO_BP_RDY) &= ~GPIO_bit(GPIO_BP_RDY);
188 + while ( timeout -- ) {
189 + if ( (!(GPIO_is_high(GPIO_MCU_INT_SW)))
190 + || (!(GPIO_is_high(GPIO_BP_RDY))) ) {
199 + /* step 2: wait BP_RDY is low */
201 + if (!(GPIO_is_high(GPIO_BP_RDY))) {
203 + /* config MCU_INT_SW as output */
204 + pxa_gpio_mode(GPIO_MCU_INT_SW | GPIO_OUT);
205 + clr_GPIO(GPIO_MCU_INT_SW);
211 + /* step 3: wait BP_RDY is high */
213 + if (GPIO_is_high(GPIO_BP_RDY)) {
215 + //FIXME delay_bklight();
216 + set_GPIO(GPIO_MCU_INT_SW);
222 +static unsigned long idle_limit = 0;
223 +int pm_handle_irq(int irq)
226 + //FIXME: extern unsigned long idle_limit;
227 + //FIXME: extern int can_idle, can_sleep;
228 + static unsigned long tmp_jiffy; /* for temporary store of jiffies */
231 + * if idle_limit is zero, never enter idle.
232 + * if not OS timer, reset idle timer count
234 + if (idle_limit == 0) {
235 + tmp_jiffy = jiffies;
239 + if (irq != IRQ_OST0) {
240 + tmp_jiffy = jiffies;
243 + } else if (jiffies > tmp_jiffy + idle_limit) {
246 + * I think this is enough to prevent from reentering here
247 + * due to jiffies will be stoped
249 + tmp_jiffy = jiffies;
251 + /* if pm idle timer expired, queue event */
252 + apm_queue_event(KRNL_PROC_INACT);
260 +irqreturn_t bp_wdi_intr(int irq, void *dev_id)
262 +//FIXME apm_queue_event(KRNL_BP_WDI);
263 + return IRQ_HANDLED;
266 +static struct irqaction bp_wdi_irq = {
268 + .handler = &bp_wdi_intr,
272 +int handshake_pass(void)
274 + return (step > LAST_STEP);
277 +static irqreturn_t bp_rdy_intr(int irq, void *dev_id)
279 + static int usbipc_ready = 0;
281 + if (!usbipc_ready) {
283 + if (handshake_pass()) {
284 + disable_irq(IRQ_GPIO(GPIO_BB_WDI2));
286 + /* set bp_rdy handle for usb ipc */
287 + set_irq_type(GPIO_BP_RDY, IRQT_FALLING);
291 + // FIXME usb_send_readurb();
294 + return IRQ_HANDLED;
297 +static struct irqaction bp_rdy_irq = {
299 + .handler = bp_rdy_intr,
302 +static irqreturn_t bp_wdi2_intr(int irq, void *dev_id)
305 +//FIXME pm_do_poweroff();
307 + return IRQ_HANDLED;
310 +static struct irqaction bp_wdi2_irq = {
312 + .handler = bp_wdi2_intr,
316 +static struct resource ezx_bp_resources[] = {
318 + .start = GPIO_BP_RDY,
319 + .end = GPIO_BP_RDY,
320 + .flags = IORESOURCE_IRQ,
323 + .start = GPIO_BB_WDI2,
324 + .end = GPIO_BB_WDI2,
325 + .flags = IORESOURCE_IRQ,
329 + .start = GPIO_BB_WDI,
330 + .end = GPIO_BB_WDI,
331 + .flags = IORESOURCE_IRQ,
336 +static struct platform_device ezx_bp_device = {
343 + .num_resources = ARRAY_SIZE(ezx_bp_resources),
344 + .resource = ezx_bp_resources,
347 +static void __init ezx_init_gpio_irq(void)
350 + set_irq_type(GPIO_BB_WDI, IRQT_FALLING);
351 + setup_irq(IRQ_GPIO(GPIO_BB_WDI), &bp_wdi_irq);
353 + set_irq_type(GPIO_BP_RDY, IRQT_BOTHEDGE);
354 + setup_irq(IRQ_GPIO(GPIO_BP_RDY), &bp_rdy_irq);
356 + set_irq_type(GPIO_BB_WDI2, IRQT_FALLING);
357 + setup_irq(IRQ_GPIO(GPIO_BB_WDI2), &bp_wdi2_irq);
360 +static void __init a780_init_irq(void)
364 + /* init ezx specfic gpio irq */
365 + ezx_init_gpio_irq();
369 + if (handshake_pass()) {
370 + disable_irq(IRQ_GPIO(GPIO_BP_RDY));
371 + disable_irq(IRQ_GPIO(GPIO_BB_WDI2));
375 +static struct platform_device *devices[] __initdata = {
380 +static void __init a780_init(void)
382 +//FIXME CKEN = CKEN9_OSTIMER | CKEN22_MEMC | CKEN5_STUART;
384 + ezx_ssp_set_machinfo(&ezx_ssp_machinfo);
386 + /* set BB_RESET PIN out put high */
387 + pxa_gpio_mode(GPIO_BB_RESET|GPIO_OUT);
388 + set_GPIO(GPIO_BB_RESET);
390 + pxa_gpio_mode(GPIO_ICL_FFRXD_MD);
391 + pxa_gpio_mode(GPIO_ICL_FFTXD_MD);
392 + pxa_gpio_mode(GPIO_ICL_FFCTS_MD);
393 + pxa_gpio_mode(GPIO_ICL_FFRTS_MD);
395 + pxa_gpio_mode(GPIO42_BTRXD_MD);
396 + pxa_gpio_mode(GPIO43_BTTXD_MD);
397 + pxa_gpio_mode(GPIO44_BTCTS_MD);
398 + pxa_gpio_mode(GPIO45_BTRTS_MD);
400 + /* clear EMU MUX1/MUX2 (low) to close the audio path to EMU */
401 + pxa_gpio_mode(GPIO_EMU_MUX1|GPIO_OUT);
402 + clr_GPIO(GPIO_EMU_MUX1);
403 + pxa_gpio_mode(GPIO_EMU_MUX2|GPIO_OUT);
404 + clr_GPIO(GPIO_EMU_MUX2);
406 +#if defined(CONFIG_PXA_EZX_E680)
407 + pxa_gpio_mode(GPIO46_STRXD_MD);
408 + pxa_gpio_mode(GPIO47_STTXD_MD);
410 + /* setup sleep mode values */
411 + PWER = 0xc000f803; // disable usb 0xdc00f803;
414 + // keypad wakeup (PKWR,PGSR3) should be in keypad.c
415 + PGSR0 = 0x00000010;
416 + PGSR1 = 0x02800000;
417 + PGSR2 = 0x00040000;
418 + PGSR3 = 0x00000000;
419 + PCFR = PCFR_DC_EN | PCFR_FS | PCFR_FP | PCFR_OPDE;
422 +#elif defined(CONFIG_PXA_EZX_A780)
424 + /* Standard UART */
425 + pxa_gpio_mode(GPIO46_STRXD_MD);
426 + pxa_gpio_mode(GPIO47_STTXD_MD);
428 + /* setup sleep mode values */
429 + PWER = 0xc0007803; // disable usb, GPIO15 NC
432 + // keypad wakeup (PKWR,PGSR3) should be in keypad.c
433 + PGSR0 = 0x00000010;
434 + PGSR1 = 0x02800000;
435 + PGSR2 = 0x00040000;
436 + PGSR3 = 0x00000008;
437 + PCFR = PCFR_DC_EN | PCFR_FS | PCFR_FP | PCFR_OPDE;
441 + pxa_set_ohci_info(&ezx_ohci_platform_data);
443 + platform_add_devices(devices, ARRAY_SIZE(devices));
447 +MACHINE_START(EZX, "Motorola Ezx Platform")
448 + /* Maintainer: Harald Welte <laforge@gnumonks.org> */
449 + .phys_io = 0x40000000,
450 + .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc,
451 + .boot_params = 0xa0000100,
452 + .map_io = pxa_map_io,
453 + .init_irq = a780_init_irq,
454 + .timer = &pxa_timer,
455 + .init_machine = a780_init,
457 Index: linux-2.6.20.7/include/asm-arm/arch-pxa/ezx.h
458 ===================================================================
459 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
460 +++ linux-2.6.20.7/include/asm-arm/arch-pxa/ezx.h 2007-04-21 22:32:53.000000000 -0300
463 + * linux/include/asm-arm/arch-pxa/ezx.h
465 + * Specific macro defines for Motorola Ezx Development Platform
467 + * Author: Zhuang Xiaofan
468 + * Created: Nov 25, 2003
469 + * Copyright: Motorola Inc.
471 + * This program is free software; you can redistribute it and/or modify
472 + * it under the terms of the GNU General Public License version 2 as
473 + * published by the Free Software Foundation.
476 +/* support E680 p3 and ealier PCB */
477 +//#define E680_P3_AND_EARLY
479 +#define GPIO_is_high(x) (GPLR(x) & GPIO_bit(x))
480 +#define set_GPIO(x) (GPSR(x) = GPIO_bit(x))
481 +#define clr_GPIO(x) (GPCR(x) = GPIO_bit(x))
484 + * Flags in memory for sleep use
486 +#define FLAG_ADDR PHYS_OFFSET
487 +#define RESUME_ADDR (PHYS_OFFSET + 4)
488 +#define BPSIG_ADDR (PHYS_OFFSET + 8)
490 +#define USER_OFF_FLAG 0x5a5a5a5a
491 +#define SLEEP_FLAG 0x6b6b6b6b
492 +#define OFF_FLAG 0x7c7c7c7c
493 +#define REFLASH_FLAG 0x0C1D2E3F
494 +#define PASS_THRU_FLAG 0x12345678
496 +#define WDI_FLAG 0xbb00dead
497 +#define NO_FLAG 0xaa00dead
500 + * GPIO control pin, have to change when hardware lock down
503 +#ifdef E680_P3_AND_EARLY
505 +/* shakehand with BP's PIN */
506 +#define GPIO_BP_RDY 0 /* BP_RDY */
507 +#define GPIO_BB_WDI 13 /* BB_WDI */
508 +#define GPIO_BB_WDI2 3 /* BB_WDI2 */
509 +#define GPIO_BB_RESET 57 /* BB_RESET */
510 +#define GPIO_MCU_INT_SW 115 /* MCU_INT_SW */
511 +#define GPIO_TC_MM_EN 89 /* TC_MM_EN */
513 +/* control PCAP direct PIN */
514 +#define GPIO_WDI_AP 4 /* WDI_AP */
515 +#define GPIO_SYS_RESTART 55 /* restart PCAP power */
516 +#define GPIO_AP_STANDBY 28 /* make pcap enter standby mode */
518 +/* communicate with PCAP's PIN */
519 +#define GPIO_PCAP_SEC_INT 1 /* PCAP interrupt PIN to AP */
520 +#define GPIO_SPI_CLK 23 /* PCAP SPI port clock */
521 +#define GPIO_SPI_CE 24 /* PCAP SPI port SSPFRM */
522 +#define GPIO_SPI_MOSI 25 /* PCAP SPI port SSPTXD */
523 +#define GPIO_SPI_MISO 26 /* PCAP SPI port SSPRXD */
525 +/* blue tooth control PIN */
526 +#define GPIO_BT_WAKEUP 2 /* AP wake up bluetooth module */
527 +#define GPIO_BT_HOSTWAKE 14 /* bluetooth module wake up Ap module */
528 +#define GPIO_BT_RESET 56 /* AP reset bluetooth module */
530 +/* control LCD high - OFF low -- ON */
531 +#define GPIO_LCD_OFF 116 /* control LCD */
534 +#define GPIO_ICL_FFRXD_MD (34 | GPIO_ALT_FN_1_IN)
535 +#define GPIO_ICL_FFCTS_MD (35 | GPIO_ALT_FN_1_IN)
536 +#define GPIO_ICL_FFTXD_MD (39 | GPIO_ALT_FN_2_OUT)
537 +#define GPIO_ICL_FFRTS_MD (41 | GPIO_ALT_FN_2_OUT)
539 +#elif defined(A780_P1_AND_EARLY)
541 +/* shakehand with BP's PIN */
542 +#define GPIO_BP_RDY 0 /* BP_RDY */
543 +#define GPIO_BB_WDI 13 /* BB_WDI */
544 +#define GPIO_BB_WDI2 3 /* BB_WDI2 */
545 +#define GPIO_BB_RESET 82 /* BB_RESET */
546 +#define GPIO_MCU_INT_SW 57 /* MCU_INT_SW */
547 +#define GPIO_TC_MM_EN 89 /* TC_MM_EN */
549 +/* control PCAP direct PIN */
550 +#define GPIO_WDI_AP 4 /* WDI_AP */
551 +#define GPIO_SYS_RESTART 55 /* restart PCAP power */
552 +#define GPIO_AP_STANDBY 28 /* make pcap enter standby mode */
554 +/* communicate with PCAP's PIN */
555 +#define GPIO_PCAP_SEC_INT 1 /* PCAP interrupt PIN to AP */
556 +#define GPIO_SPI_CLK 29 /* PCAP SPI port clock */
557 +#define GPIO_SPI_CE 24 /* PCAP SPI port SSPFRM */
558 +#define GPIO_SPI_MOSI 25 /* PCAP SPI port SSPTXD */
559 +#define GPIO_SPI_MISO 26 /* PCAP SPI port SSPRXD */
561 +/* blue tooth control PIN */
562 +#define GPIO_BT_WAKEUP 2 /* AP wake up bluetooth module */
563 +#define GPIO_BT_HOSTWAKE 14 /* bluetooth module wake up Ap module */
564 +#define GPIO_BT_RESET 56 /* AP reset bluetooth module */
566 +/* control LCD high - OFF low -- ON */
567 +#define GPIO_LCD_OFF 116 /* control LCD */
570 +#define GPIO_ICL_FFRXD_MD (53 | GPIO_ALT_FN_1_IN)
571 +#define GPIO_ICL_FFCTS_MD (35 | GPIO_ALT_FN_1_IN)
572 +#define GPIO_ICL_FFTXD_MD (39 | GPIO_ALT_FN_2_OUT)
573 +#define GPIO_ICL_FFRTS_MD (41 | GPIO_ALT_FN_2_OUT)
577 +/* shakehand with BP's PIN */
578 +#define GPIO_BP_RDY 0 /* BP_RDY */
579 +#define GPIO_BB_WDI 13 /* BB_WDI */
580 +#define GPIO_BB_WDI2 3 /* BB_WDI2 */
581 +#define GPIO_BB_RESET 82 /* BB_RESET */
582 +#define GPIO_MCU_INT_SW 57 /* MCU_INT_SW */
583 +#define GPIO_TC_MM_EN 99 /* TC_MM_EN */
585 +/* control PCAP direct PIN */
586 +#define GPIO_WDI_AP 4 /* WDI_AP */
587 +#define GPIO_SYS_RESTART 55 /* restart PCAP power */
588 +//#define GPIO_AP_STANDBY 28 /* make pcap enter standby mode */
590 +/* communicate with PCAP's PIN */
591 +#define GPIO_PCAP_SEC_INT 1 /* PCAP interrupt PIN to AP */
592 +#define GPIO_SPI_CLK 29 /* PCAP SPI port clock */
593 +#define GPIO_SPI_CE 24 /* PCAP SPI port SSPFRM */
594 +#define GPIO_SPI_MOSI 25 /* PCAP SPI port SSPTXD */
595 +#define GPIO_SPI_MISO 26 /* PCAP SPI port SSPRXD */
597 +/* blue tooth control PIN */
598 +#define GPIO_BT_WAKEUP 28 /* AP wake up bluetooth module */
599 +#define GPIO_BT_HOSTWAKE 14 /* AP wake up bluetooth module */
600 +#define GPIO_BT_RESET 48 /* AP reset bluetooth module */
602 +/* control LCD high - OFF low -- ON */
603 +#define GPIO_LCD_OFF 116 /* control LCD */
606 +#define GPIO_ICL_FFRXD_MD (53 | GPIO_ALT_FN_1_IN)
607 +#define GPIO_ICL_FFCTS_MD (35 | GPIO_ALT_FN_1_IN)
608 +#define GPIO_ICL_FFTXD_MD (39 | GPIO_ALT_FN_2_OUT)
609 +#define GPIO_ICL_FFRTS_MD (41 | GPIO_ALT_FN_2_OUT)
613 + * ezx platform, wake up source edge detect bit
615 +#define PEDR_INT_SEC 1
617 +#define GPIO_FLIP_PIN 12
618 +/*E680 screen lock button*/
620 +#define GPIO_LOCK_SCREEN_PIN GPIO_FLIP_PIN
623 +#define GPIO_MMC_DETECT 11
624 +#define GPIO_MMC_CLK 32
625 +#define GPIO_MMC_DATA0 92
626 +#define GPIO_MMC_WP 107
627 +#define GPIO_MMC_DATA1 109
628 +#define GPIO_MMC_DATA2 110
629 +#define GPIO_MMC_DATA3 111
630 +#define GPIO_MMC_CMD 112
632 +/* interface function */
633 +#define GPIO_MMC_CLK_MD (GPIO_MMC_CLK | GPIO_ALT_FN_2_OUT)
634 +#define GPIO_MMC_DATA0_MD (GPIO_MMC_DATA0 | GPIO_ALT_FN_1_IN | GPIO_ALT_FN_1_OUT)
635 +#define GPIO_MMC_DATA1_MD (GPIO_MMC_DATA1 | GPIO_ALT_FN_1_IN | GPIO_ALT_FN_1_OUT)
636 +#define GPIO_MMC_DATA2_MD (GPIO_MMC_DATA2 | GPIO_ALT_FN_1_IN | GPIO_ALT_FN_1_OUT)
637 +#define GPIO_MMC_DATA3_MD (GPIO_MMC_DATA3 | GPIO_ALT_FN_1_IN | GPIO_ALT_FN_1_OUT)
639 +#define GPIO_MMC_CMD_MD (GPIO_MMC_CMD | GPIO_ALT_FN_1_IN | GPIO_ALT_FN_1_OUT)
641 +/* EMU GPIO 119 ---MUX2 120 --- MUX1 */
642 +#define GPIO_EMU_MUX1 120
643 +#define GPIO_EMU_MUX2 119
644 +#define GPIO_SNP_INT_CTL 86
645 +#define GPIO_SNP_INT_IN 87
648 +/* audio related pins */
649 +#define AP_13MHZ_OUTPUT_PIN 9
651 +#ifdef CONFIG_ARCH_EZX_E680
652 +#define GPIO_VA_SEL_BUL 79
653 +#define GPIO_FLT_SEL_BUL 80 /* out filter select pin */
654 +#define GPIO_MIDI_RESET 78 /* GPIO used by MIDI chipset */
655 +#define GPIO_MIDI_CS 33
656 +#define GPIO_MIDI_IRQ 15
657 +#define GPIO_MIDI_NPWE 49
658 +#define GPIO_MIDI_RDY 18
661 +#ifdef CONFIG_ARCH_EZX_A780
662 +#define GPIO_HW_ATTENUATE_A780 96 /* hw noise attenuation be used or bypassed, for receiver or louderspeaker mode */
667 +#define GPIO_BP_STATE 41
669 +/* define usb related pin */
670 +#define GPIO34_TXENB 34
671 +#define GPIO35_XRXD 35
672 +#define GPIO36_VMOUT 36
673 +#define GPIO39_VPOUT 39
674 +#define GPIO40_VPIN 40
675 +#define GPIO53_VMIN 53
677 +/* USB client 6 pin defination */
678 +#define GPIO34_TXENB_MD (GPIO34_TXENB | GPIO_ALT_FN_1_OUT)
679 +#define GPIO35_XRXD_MD (GPIO35_XRXD | GPIO_ALT_FN_2_IN )
680 +#define GPIO36_VMOUT_MD (GPIO36_VMOUT | GPIO_ALT_FN_1_OUT)
681 +#define GPIO39_VPOUT_MD (GPIO39_VPOUT | GPIO_ALT_FN_1_OUT)
682 +#define GPIO40_VPIN_MD (GPIO40_VPIN | GPIO_ALT_FN_3_IN )
683 +#define GPIO53_VMIN_MD (GPIO53_VMIN | GPIO_ALT_FN_2_IN )
685 +#define GPIO53_FFRXD_MD (53 | GPIO_ALT_FN_1_IN)
687 Index: linux-2.6.20.7/include/asm-arm/arch-pxa/pxa-regs.h
688 ===================================================================
689 --- linux-2.6.20.7.orig/include/asm/arch/pxa-regs.h 2007-04-21 22:31:54.000000000 -0300
690 +++ linux-2.6.20.7/include/asm-arm/arch-pxa/pxa-regs.h 2007-04-21 22:32:53.000000000 -0300
692 #define UP2OCR_HXOE (1 << 17) /* Host Port 2 Transceiver Output Enable */
693 #define UP2OCR_SEOS (1 << 24) /* Single-Ended Output Select */
695 +#define UP3OCR __REG(0x40600024) /* USB Port 3 Output Control register */
697 #define UDCCSN(x) __REG2(0x40600100, (x) << 2)
698 #define UDCCSR0 __REG(0x40600100) /* UDC Control/Status register - Endpoint 0 */
699 #define UDCCSR0_SA (1 << 7) /* Setup Active */
700 @@ -1257,6 +1259,7 @@
701 #define GPIO33_nCS_5 33 /* chip select 5 */
702 #define GPIO34_FFRXD 34 /* FFUART receive */
703 #define GPIO34_MMCCS0 34 /* MMC Chip Select 0 */
704 +#define GPIO34_USB_P2_2 34 /* USB Port2 Pin 2 */
705 #define GPIO35_FFCTS 35 /* FFUART Clear to send */
706 #define GPIO36_FFDCD 36 /* FFUART Data carrier detect */
707 #define GPIO37_FFDSR 37 /* FFUART data set ready */
708 @@ -1370,6 +1373,7 @@
709 #define GPIO18_RDY_MD (18 | GPIO_ALT_FN_1_IN)
710 #define GPIO19_DREQ1_MD (19 | GPIO_ALT_FN_1_IN)
711 #define GPIO20_DREQ0_MD (20 | GPIO_ALT_FN_1_IN)
712 +#define GPIO22_SCLK2_MD (22 | GPIO_ALT_FN_3_IN)
713 #define GPIO23_SCLK_MD (23 | GPIO_ALT_FN_2_OUT)
714 #define GPIO24_SFRM_MD (24 | GPIO_ALT_FN_2_OUT)
715 #define GPIO25_STXD_MD (25 | GPIO_ALT_FN_2_OUT)
716 @@ -1380,23 +1384,33 @@
717 #define GPIO28_BITCLK_OUT_I2S_MD (28 | GPIO_ALT_FN_1_OUT)
718 #define GPIO29_SDATA_IN_AC97_MD (29 | GPIO_ALT_FN_1_IN)
719 #define GPIO29_SDATA_IN_I2S_MD (29 | GPIO_ALT_FN_2_IN)
720 +#define GPIO29_SCLK_MD (29 | GPIO_ALT_FN_3_IN)
721 #define GPIO30_SDATA_OUT_AC97_MD (30 | GPIO_ALT_FN_2_OUT)
722 #define GPIO30_SDATA_OUT_I2S_MD (30 | GPIO_ALT_FN_1_OUT)
723 +#define GPIO30_USB_P3_2 (30 | GPIO_ALT_FN_3_OUT)
724 #define GPIO31_SYNC_I2S_MD (31 | GPIO_ALT_FN_1_OUT)
725 #define GPIO31_SYNC_AC97_MD (31 | GPIO_ALT_FN_2_OUT)
726 +#define GPIO31_USB_P3_6 (31 | GPIO_ALT_FN_3_OUT)
727 #define GPIO32_SDATA_IN1_AC97_MD (32 | GPIO_ALT_FN_1_IN)
728 #define GPIO32_SYSCLK_I2S_MD (32 | GPIO_ALT_FN_1_OUT)
729 #define GPIO32_MMCCLK_MD ( 32 | GPIO_ALT_FN_2_OUT)
730 #define GPIO33_nCS_5_MD (33 | GPIO_ALT_FN_2_OUT)
731 #define GPIO34_FFRXD_MD (34 | GPIO_ALT_FN_1_IN)
732 #define GPIO34_MMCCS0_MD (34 | GPIO_ALT_FN_2_OUT)
733 +#define GPIO34_USB_P2_2_MD (34 | GPIO_ALT_FN_1_OUT)
734 #define GPIO35_FFCTS_MD (35 | GPIO_ALT_FN_1_IN)
735 +#define GPIO35_USB_P2_1_MD (35 | GPIO_ALT_FN_2_IN)
736 #define GPIO36_FFDCD_MD (36 | GPIO_ALT_FN_1_IN)
737 +#define GPIO36_USB_P2_4_MD (36 | GPIO_ALT_FN_1_OUT)
738 #define GPIO37_FFDSR_MD (37 | GPIO_ALT_FN_1_IN)
739 +#define GPIO37_SFRM2_MD (37 | GPIO_ALT_FN_2_IN)
740 #define GPIO38_FFRI_MD (38 | GPIO_ALT_FN_1_IN)
741 +#define GPIO38_STXD2_MD (38 | GPIO_ALT_FN_2_OUT)
742 #define GPIO39_MMCCS1_MD (39 | GPIO_ALT_FN_1_OUT)
743 #define GPIO39_FFTXD_MD (39 | GPIO_ALT_FN_2_OUT)
744 +#define GPIO39_USB_P2_6_MD (39 | GPIO_ALT_FN_1_OUT)
745 #define GPIO40_FFDTR_MD (40 | GPIO_ALT_FN_2_OUT)
746 +#define GPIO40_USB_P2_5_MD (40 | GPIO_ALT_FN_3_IN)
747 #define GPIO41_FFRTS_MD (41 | GPIO_ALT_FN_2_OUT)
748 #define GPIO42_BTRXD_MD (42 | GPIO_ALT_FN_1_IN)
749 #define GPIO42_HWRXD_MD (42 | GPIO_ALT_FN_3_IN)
750 @@ -1421,13 +1435,17 @@
751 #define GPIO51_HWRTS_MD (51 | GPIO_ALT_FN_1_OUT)
752 #define GPIO51_nPIOW_MD (51 | GPIO_ALT_FN_2_OUT)
753 #define GPIO52_nPCE_1_MD (52 | GPIO_ALT_FN_2_OUT)
754 +#define GPIO52_SCLK3_MD (52 | GPIO_ALT_FN_2_OUT)
755 #define GPIO53_nPCE_2_MD (53 | GPIO_ALT_FN_2_OUT)
756 #define GPIO53_MMCCLK_MD (53 | GPIO_ALT_FN_1_OUT)
757 +#define GPIO53_FFRXD_MD (53 | GPIO_ALT_FN_1_IN)
758 +#define GPIO53_USB_P2_3_MD (53 | GPIO_ALT_FN_2_IN)
759 #define GPIO54_MMCCLK_MD (54 | GPIO_ALT_FN_1_OUT)
760 #define GPIO54_nPCE_2_MD (54 | GPIO_ALT_FN_2_OUT)
761 #define GPIO54_pSKTSEL_MD (54 | GPIO_ALT_FN_2_OUT)
762 #define GPIO55_nPREG_MD (55 | GPIO_ALT_FN_2_OUT)
763 #define GPIO56_nPWAIT_MD (56 | GPIO_ALT_FN_1_IN)
764 +#define GPIO56_USB_P3_4 (56 | GPIO_ALT_FN_1_OUT)
765 #define GPIO57_nIOIS16_MD (57 | GPIO_ALT_FN_1_IN)
766 #define GPIO58_LDD_0_MD (58 | GPIO_ALT_FN_2_OUT)
767 #define GPIO59_LDD_1_MD (59 | GPIO_ALT_FN_2_OUT)
768 @@ -1463,13 +1481,19 @@
769 #define GPIO80_nCS_4_MD (80 | GPIO_ALT_FN_2_OUT)
770 #define GPIO81_NSSP_CLK_OUT (81 | GPIO_ALT_FN_1_OUT)
771 #define GPIO81_NSSP_CLK_IN (81 | GPIO_ALT_FN_1_IN)
772 +#define GPIO81_STXD3_MD (81 | GPIO_ALT_FN_1_OUT)
773 #define GPIO82_NSSP_FRM_OUT (82 | GPIO_ALT_FN_1_OUT)
774 #define GPIO82_NSSP_FRM_IN (82 | GPIO_ALT_FN_1_IN)
775 #define GPIO83_NSSP_TX (83 | GPIO_ALT_FN_1_OUT)
776 #define GPIO83_NSSP_RX (83 | GPIO_ALT_FN_2_IN)
777 +#define GPIO83_SFRM3_MD (83 | GPIO_ALT_FN_1_IN)
778 #define GPIO84_NSSP_TX (84 | GPIO_ALT_FN_1_OUT)
779 #define GPIO84_NSSP_RX (84 | GPIO_ALT_FN_2_IN)
780 #define GPIO85_nPCE_1_MD (85 | GPIO_ALT_FN_1_OUT)
781 +#define GPIO88_SRXD2_MD (88 | GPIO_ALT_FN_2_IN)
782 +#define GPIO89_SRXD3_MD (89 | GPIO_ALT_FN_1_IN)
783 +#define GPIO90_USB_P3_5 (90 | GPIO_ALT_FN_2_IN)
784 +#define GPIO91_USB_P3_1 (91 | GPIO_ALT_FN_2_IN)
785 #define GPIO92_MMCDAT0_MD (92 | GPIO_ALT_FN_1_OUT)
786 #define GPIO102_nPCE_1_MD (102 | GPIO_ALT_FN_1_OUT)
787 #define GPIO104_pSKTSEL_MD (104 | GPIO_ALT_FN_1_OUT)
788 @@ -1481,6 +1505,7 @@
789 #define GPIO112_MMCCMD_MD (112 | GPIO_ALT_FN_1_OUT)
790 #define GPIO113_I2S_SYSCLK_MD (113 | GPIO_ALT_FN_1_OUT)
791 #define GPIO113_AC97_RESET_N_MD (113 | GPIO_ALT_FN_2_OUT)
792 +#define GPIO113_USB_P3_3 (113 | GPIO_ALT_FN_3_IN)
793 #define GPIO117_I2CSCL_MD (117 | GPIO_ALT_FN_1_OUT)
794 #define GPIO118_I2CSDA_MD (118 | GPIO_ALT_FN_1_IN)
796 @@ -1496,6 +1521,7 @@
797 #define PFER __REG(0x40F00014) /* Power Manager GPIO Falling-Edge Detect Enable Register */
798 #define PEDR __REG(0x40F00018) /* Power Manager GPIO Edge Detect Status Register */
799 #define PCFR __REG(0x40F0001C) /* Power Manager General Configuration Register */
800 +#define PGSR(x) (__REG(0x40F00020 + ((unsigned long)(x)/32*4)))
801 #define PGSR0 __REG(0x40F00020) /* Power Manager GPIO Sleep State Register for GP[31-0] */
802 #define PGSR1 __REG(0x40F00024) /* Power Manager GPIO Sleep State Register for GP[63-32] */
803 #define PGSR2 __REG(0x40F00028) /* Power Manager GPIO Sleep State Register for GP[84-64] */
804 Index: linux-2.6.20.7/arch/arm/boot/compressed/head.S
805 ===================================================================
806 --- linux-2.6.20.7.orig/arch/arm/boot/compressed/head.S 2007-04-21 22:31:54.000000000 -0300
807 +++ linux-2.6.20.7/arch/arm/boot/compressed/head.S 2007-04-21 22:32:53.000000000 -0300
812 + mov r1, #0x300 @ mach_id 0x363 is official EZX
813 + orr r1, r1, #0x63 @ bootloader JUMP doesn't set r1
816 .word 0x016f2818 @ Magic numbers to help the loader
817 .word start @ absolute load/run zImage address
818 Index: linux-2.6.20.7/include/asm-arm/arch-pxa/uncompress.h
819 ===================================================================
820 --- linux-2.6.20.7.orig/include/asm-arm/arch-pxa/uncompress.h 2007-04-21 22:31:54.000000000 -0300
821 +++ linux-2.6.20.7/include/asm-arm/arch-pxa/uncompress.h 2007-04-21 22:32:53.000000000 -0300
823 #define STUART ((volatile unsigned long *)0x40700000)
824 #define HWUART ((volatile unsigned long *)0x41600000)
830 static inline void putc(char c)
832 - while (!(UART[5] & 0x20))
833 +/* while (!(UART[5] & 0x40))
840 Index: linux-2.6.20.7/arch/arm/mach-pxa/ezx_ssp.c
841 ===================================================================
842 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
843 +++ linux-2.6.20.7/arch/arm/mach-pxa/ezx_ssp.c 2007-04-22 01:36:48.000000000 -0300
846 + * SSP control code for Motorola EZX phones
848 + * Copyright (c) 2007 Daniel Ribeiro <drwyrm@gmail.com>
850 + * This program is free software; you can redistribute it and/or modify
851 + * it under the terms of the GNU General Public License version 2 as
852 + * published by the Free Software Foundation.
856 +#include <linux/module.h>
857 +#include <linux/init.h>
858 +#include <linux/kernel.h>
859 +#include <linux/sched.h>
860 +#include <linux/slab.h>
861 +#include <linux/delay.h>
862 +#include <linux/platform_device.h>
863 +#include <asm/hardware.h>
864 +#include <asm/mach-types.h>
866 +#include <asm/arch/ssp.h>
867 +#include <asm/arch/pxa-regs.h>
871 +static DEFINE_SPINLOCK(ezx_ssp_lock);
872 +static struct ssp_dev ezx_ssp_dev;
873 +static struct ssp_state ezx_ssp_state;
874 +static struct ezxssp_machinfo *ssp_machinfo;
877 +unsigned long ezx_ssp_pcap_putget(ulong data)
879 + unsigned long flag;
882 + spin_lock_irqsave(&ezx_ssp_lock, flag);
883 + if (ssp_machinfo->cs_pcap >= 0)
884 + GPCR(ssp_machinfo->cs_pcap) = GPIO_bit(ssp_machinfo->cs_pcap);
886 + ssp_write_word(&ezx_ssp_dev,data);
887 + ssp_read_word(&ezx_ssp_dev, &ret);
889 + if (ssp_machinfo->cs_pcap >= 0)
890 + GPSR(ssp_machinfo->cs_pcap) = GPIO_bit(ssp_machinfo->cs_pcap);
891 + spin_unlock_irqrestore(&ezx_ssp_lock, flag);
895 +EXPORT_SYMBOL(ezx_ssp_pcap_putget);
901 +void __init ezx_ssp_set_machinfo(struct ezxssp_machinfo *machinfo)
903 + ssp_machinfo = machinfo;
906 +static int __init ezx_ssp_probe(struct platform_device *dev)
910 + pxa_gpio_mode(29|GPIO_ALT_FN_3_OUT);
911 + pxa_gpio_mode(GPIO24_SFRM_MD);
912 + pxa_gpio_mode(GPIO25_STXD_MD);
913 + pxa_gpio_mode(GPIO26_SRXD_MD);
915 + /* Chip Select - Disable All */
916 + if (ssp_machinfo->cs_pcap >= 0)
917 + pxa_gpio_mode(ssp_machinfo->cs_pcap | GPIO_OUT | GPIO_DFLT_HIGH);
919 + ret = ssp_init(&ezx_ssp_dev, ssp_machinfo->port, 0);
922 + printk(KERN_ERR "Unable to register SSP handler!\n");
924 + ssp_disable(&ezx_ssp_dev);
925 + ssp_config(&ezx_ssp_dev,
926 + (SSCR0_Motorola | SSCR0_DataSize(16) | SSCR0_EDSS),
927 + (SSCR1_TxTresh(1) | SSCR1_RxTresh(1)),
928 + 0, SSCR0_SerClkDiv(ssp_machinfo->clk_pcap));
929 + ssp_enable(&ezx_ssp_dev);
935 +static int ezx_ssp_remove(struct platform_device *dev)
937 + ssp_exit(&ezx_ssp_dev);
941 +static int ezx_ssp_suspend(struct platform_device *dev, pm_message_t state)
943 + ssp_flush(&ezx_ssp_dev);
944 + ssp_save_state(&ezx_ssp_dev,&ezx_ssp_state);
949 +static int ezx_ssp_resume(struct platform_device *dev)
951 + if (ssp_machinfo->cs_pcap >= 0)
952 + GPSR(ssp_machinfo->cs_pcap) = GPIO_bit(ssp_machinfo->cs_pcap);
953 + ssp_restore_state(&ezx_ssp_dev,&ezx_ssp_state);
954 + ssp_enable(&ezx_ssp_dev);
959 +static struct platform_driver ezxssp_driver = {
960 + .probe = ezx_ssp_probe,
961 + .remove = ezx_ssp_remove,
962 + .suspend = ezx_ssp_suspend,
963 + .resume = ezx_ssp_resume,
969 +int __init ezx_ssp_init(void)
971 + return platform_driver_register(&ezxssp_driver);
974 +arch_initcall(ezx_ssp_init);
975 Index: linux-2.6.20.7/arch/arm/mach-pxa/ezx.h
976 ===================================================================
977 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
978 +++ linux-2.6.20.7/arch/arm/mach-pxa/ezx.h 2007-04-22 01:38:55.000000000 -0300
980 +#include <asm/arch/ezx.h>
983 +struct ezxssp_machinfo {
989 Index: linux-2.6.20.7/arch/arm/mach-pxa/ezx_lcd.c
990 ===================================================================
991 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
992 +++ linux-2.6.20.7/arch/arm/mach-pxa/ezx_lcd.c 2007-04-21 22:32:53.000000000 -0300
995 + * linux/arch/arm/mach-ezx/a780.c
997 + * Support for the Motorola Ezx A780 Development Platform.
999 + * Author: Zhuang Xiaofan
1000 + * Created: Nov 25, 2003
1001 + * Copyright: Motorola Inc.
1003 + * This program is free software; you can redistribute it and/or modify
1004 + * it under the terms of the GNU General Public License version 2 as
1005 + * published by the Free Software Foundation.
1008 +#include <linux/fb.h>
1009 +#include <linux/delay.h>
1010 +#include <asm/arch/pxafb.h>
1011 +#include <asm/arch/pxa-regs.h>
1014 + * EZX PXA Framebuffer
1017 +static void pxafb_lcd_power(int on, struct fb_var_screeninfo *var)
1021 + GPSR3 = 0x00100000;
1023 + GPCR3 = 0x00100000;
1024 + GPDR3 |= 0x00100000;
1026 + GPSR3 = 0x00100000;
1027 + PGSR3 |= 0x00100000;
1029 + LCCR0 &= ~LCCR0_LDM; /* disable lcd disable done interrupt */
1030 + LCCR0 |= LCCR0_DIS; /* normal disable lcd */
1035 +#ifdef CONFIG_PXA_E2
1036 +static void sumatra_backlight_power(int on)
1039 + pxa_gpio_mode(GPIO16_PWM0_MD);
1040 + pxa_set_cken(CKEN0_PWM0, 1);
1042 + PWM_PWDUTY0 = 0x3ff;
1043 + PWM_PERVAL0 = 0x3ff;
1046 + PWM_PWDUTY0 = 0x0;
1047 + PWM_PERVAL0 = 0x3FF;
1048 + pxa_set_cken(CKEN0_PWM0, 0);
1052 +static struct pxafb_mode_info mode_ezx = {
1053 + .pixclock = 192308,
1058 + .left_margin = 20,
1059 + .right_margin = 10,
1061 + .upper_margin = 3,
1062 + .lower_margin = 2,
1063 + .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
1066 +static struct pxafb_mach_info ezx_fb_info __initdata = {
1067 + .modes = &mode_ezx,
1069 + .lccr0 = 0x022008B8,
1070 + .lccr3 = 0xC130FF13,
1071 + .pxafb_backlight_power = sumatra_backlight_power,
1072 + .pxafb_lcd_power = &pxafb_lcd_power,
1076 +static struct pxafb_mode_info mode_ezx = {
1077 + .pixclock = 150000,
1082 + .left_margin = 20,
1083 + .right_margin = 10,
1085 + .upper_margin = 3,
1086 + .lower_margin = 2,
1087 + .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
1090 +static struct pxafb_mach_info ezx_fb_info __initdata = {
1091 + .modes = &mode_ezx,
1093 + .lccr0 = 0x002008F8,
1094 + .lccr3 = 0x0430FF09,
1095 + .pxafb_lcd_power= &pxafb_lcd_power,
1099 +int __init __ezx_lcd_init (void)
1101 + set_pxa_fb_info(&ezx_fb_info);
1105 +arch_initcall(__ezx_lcd_init);
1106 Index: linux-2.6.20.7/arch/arm/mm/init.c
1107 ===================================================================
1108 --- linux-2.6.20.7.orig/arch/arm/mm/init.c 2007-04-21 22:32:57.000000000 -0300
1109 +++ linux-2.6.20.7/arch/arm/mm/init.c 2007-04-21 22:44:03.000000000 -0300
1110 @@ -241,6 +241,10 @@
1112 reserve_bootmem_node(pgdat, boot_pfn << PAGE_SHIFT,
1113 boot_pages << PAGE_SHIFT);
1114 +#ifdef CONFIG_ARCH_EZX
1115 + /* reserve the first page memory for exiting sleep and user off */
1116 + reserve_bootmem_node(pgdat, PHYS_OFFSET, PAGE_SIZE);
1119 #ifdef CONFIG_BLK_DEV_INITRD