4 * PCI defines and function prototypes
5 * Copyright 1994, Drew Eckhardt
6 * Copyright 1997--1999 Martin Mares <mj@ucw.cz>
8 * For more information, please consult the following manuals (look at
9 * http://www.pcisig.com/ for how to get them):
11 * PCI BIOS Specification
12 * PCI Local Bus Specification
13 * PCI to PCI Bridge Specification
14 * PCI System Design Guide
20 #include <linux/pci_regs.h> /* The pci register defines */
23 * The PCI interface treats multi-function devices as independent
24 * devices. The slot/function address of each device is encoded
25 * in a single byte as follows:
30 #define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07))
31 #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f)
32 #define PCI_FUNC(devfn) ((devfn) & 0x07)
34 /* Ioctls for /proc/bus/pci/X/Y nodes. */
35 #define PCIIOC_BASE ('P' << 24 | 'C' << 16 | 'I' << 8)
36 #define PCIIOC_CONTROLLER (PCIIOC_BASE | 0x00) /* Get controller for PCI device. */
37 #define PCIIOC_MMAP_IS_IO (PCIIOC_BASE | 0x01) /* Set mmap state to I/O space. */
38 #define PCIIOC_MMAP_IS_MEM (PCIIOC_BASE | 0x02) /* Set mmap state to MEM space. */
39 #define PCIIOC_WRITE_COMBINE (PCIIOC_BASE | 0x03) /* Enable/disable write-combining. */
43 #include <linux/mod_devicetable.h>
45 #include <linux/types.h>
46 #include <linux/init.h>
47 #include <linux/ioport.h>
48 #include <linux/list.h>
49 #include <linux/compiler.h>
50 #include <linux/errno.h>
51 #include <linux/kobject.h>
52 #include <linux/atomic.h>
53 #include <linux/device.h>
55 #include <linux/irqreturn.h>
57 /* Include the ID list */
58 #include <linux/pci_ids.h>
60 /* pci_slot represents a physical slot */
62 struct pci_bus *bus; /* The bus this slot is on */
63 struct list_head list; /* node in list of slots on this bus */
64 struct hotplug_slot *hotplug; /* Hotplug info (migrate over time) */
65 unsigned char number; /* PCI_SLOT(pci_dev->devfn) */
69 static inline const char *pci_slot_name(const struct pci_slot *slot)
71 return kobject_name(&slot->kobj);
74 /* File state for mmap()s on /proc/bus/pci/X/Y */
80 /* This defines the direction arg to the DMA mapping routines. */
81 #define PCI_DMA_BIDIRECTIONAL 0
82 #define PCI_DMA_TODEVICE 1
83 #define PCI_DMA_FROMDEVICE 2
84 #define PCI_DMA_NONE 3
87 * For PCI devices, the region numbers are assigned this way:
90 /* #0-5: standard PCI resources */
92 PCI_STD_RESOURCE_END = 5,
94 /* #6: expansion ROM resource */
97 /* device specific resources */
100 PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1,
103 /* resources assigned to buses behind the bridge */
104 #define PCI_BRIDGE_RESOURCE_NUM 4
106 PCI_BRIDGE_RESOURCES,
107 PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES +
108 PCI_BRIDGE_RESOURCE_NUM - 1,
110 /* total resources associated with a PCI device */
113 /* preserve this for compatibility */
114 DEVICE_COUNT_RESOURCE
117 typedef int __bitwise pci_power_t;
119 #define PCI_D0 ((pci_power_t __force) 0)
120 #define PCI_D1 ((pci_power_t __force) 1)
121 #define PCI_D2 ((pci_power_t __force) 2)
122 #define PCI_D3hot ((pci_power_t __force) 3)
123 #define PCI_D3cold ((pci_power_t __force) 4)
124 #define PCI_UNKNOWN ((pci_power_t __force) 5)
125 #define PCI_POWER_ERROR ((pci_power_t __force) -1)
127 /* Remember to update this when the list above changes! */
128 extern const char *pci_power_names[];
130 static inline const char *pci_power_name(pci_power_t state)
132 return pci_power_names[1 + (int) state];
135 #define PCI_PM_D2_DELAY 200
136 #define PCI_PM_D3_WAIT 10
137 #define PCI_PM_BUS_WAIT 50
139 /** The pci_channel state describes connectivity between the CPU and
140 * the pci device. If some PCI bus between here and the pci device
141 * has crashed or locked up, this info is reflected here.
143 typedef unsigned int __bitwise pci_channel_state_t;
145 enum pci_channel_state {
146 /* I/O channel is in normal state */
147 pci_channel_io_normal = (__force pci_channel_state_t) 1,
149 /* I/O to channel is blocked */
150 pci_channel_io_frozen = (__force pci_channel_state_t) 2,
152 /* PCI card is dead */
153 pci_channel_io_perm_failure = (__force pci_channel_state_t) 3,
156 typedef unsigned int __bitwise pcie_reset_state_t;
158 enum pcie_reset_state {
159 /* Reset is NOT asserted (Use to deassert reset) */
160 pcie_deassert_reset = (__force pcie_reset_state_t) 1,
162 /* Use #PERST to reset PCI-E device */
163 pcie_warm_reset = (__force pcie_reset_state_t) 2,
165 /* Use PCI-E Hot Reset to reset device */
166 pcie_hot_reset = (__force pcie_reset_state_t) 3
169 typedef unsigned short __bitwise pci_dev_flags_t;
171 /* INTX_DISABLE in PCI_COMMAND register disables MSI
174 PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) 1,
175 /* Device configuration is irrevocably lost if disabled into D3 */
176 PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) 2,
177 /* Provide indication device is assigned by a Virtual Machine Manager */
178 PCI_DEV_FLAGS_ASSIGNED = (__force pci_dev_flags_t) 4,
179 /* Device causes system crash if in D3 during S3 sleep */
180 PCI_DEV_FLAGS_NO_D3_DURING_SLEEP = (__force pci_dev_flags_t) 8,
183 enum pci_irq_reroute_variant {
184 INTEL_IRQ_REROUTE_VARIANT = 1,
185 MAX_IRQ_REROUTE_VARIANTS = 3
188 typedef unsigned short __bitwise pci_bus_flags_t;
190 PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1,
191 PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2,
194 /* Based on the PCI Hotplug Spec, but some values are made up by us */
196 PCI_SPEED_33MHz = 0x00,
197 PCI_SPEED_66MHz = 0x01,
198 PCI_SPEED_66MHz_PCIX = 0x02,
199 PCI_SPEED_100MHz_PCIX = 0x03,
200 PCI_SPEED_133MHz_PCIX = 0x04,
201 PCI_SPEED_66MHz_PCIX_ECC = 0x05,
202 PCI_SPEED_100MHz_PCIX_ECC = 0x06,
203 PCI_SPEED_133MHz_PCIX_ECC = 0x07,
204 PCI_SPEED_66MHz_PCIX_266 = 0x09,
205 PCI_SPEED_100MHz_PCIX_266 = 0x0a,
206 PCI_SPEED_133MHz_PCIX_266 = 0x0b,
212 PCI_SPEED_66MHz_PCIX_533 = 0x11,
213 PCI_SPEED_100MHz_PCIX_533 = 0x12,
214 PCI_SPEED_133MHz_PCIX_533 = 0x13,
215 PCIE_SPEED_2_5GT = 0x14,
216 PCIE_SPEED_5_0GT = 0x15,
217 PCIE_SPEED_8_0GT = 0x16,
218 PCI_SPEED_UNKNOWN = 0xff,
221 struct pci_cap_saved_data {
227 struct pci_cap_saved_state {
228 struct hlist_node next;
229 struct pci_cap_saved_data cap;
232 struct pcie_link_state;
238 * The pci_dev structure is used to describe PCI devices.
241 struct list_head bus_list; /* node in per-bus list */
242 struct pci_bus *bus; /* bus this device is on */
243 struct pci_bus *subordinate; /* bus this device bridges to */
245 void *sysdata; /* hook for sys-specific extension */
246 struct proc_dir_entry *procent; /* device entry in /proc/bus/pci */
247 struct pci_slot *slot; /* Physical slot this device is in */
249 unsigned int devfn; /* encoded device & function index */
250 unsigned short vendor;
251 unsigned short device;
252 unsigned short subsystem_vendor;
253 unsigned short subsystem_device;
254 unsigned int class; /* 3 bytes: (base,sub,prog-if) */
255 u8 revision; /* PCI revision, low byte of class word */
256 u8 hdr_type; /* PCI header type (`multi' flag masked out) */
257 u8 pcie_cap; /* PCI-E capability offset */
258 u8 pcie_type:4; /* PCI-E device/port type */
259 u8 pcie_mpss:3; /* PCI-E Max Payload Size Supported */
260 u8 rom_base_reg; /* which config register controls the ROM */
261 u8 pin; /* which interrupt pin this device uses */
263 struct pci_driver *driver; /* which driver has allocated this device */
264 u64 dma_mask; /* Mask of the bits of bus address this
265 device implements. Normally this is
266 0xffffffff. You only need to change
267 this if your device has broken DMA
268 or supports 64-bit transfers. */
270 struct device_dma_parameters dma_parms;
272 pci_power_t current_state; /* Current operating state. In ACPI-speak,
273 this is D0-D3, D0 being fully functional,
275 int pm_cap; /* PM capability offset in the
276 configuration space */
277 unsigned int pme_support:5; /* Bitmask of states from which PME#
279 unsigned int pme_interrupt:1;
280 unsigned int pme_poll:1; /* Poll device's PME status bit */
281 unsigned int d1_support:1; /* Low power state D1 is supported */
282 unsigned int d2_support:1; /* Low power state D2 is supported */
283 unsigned int no_d1d2:1; /* Only allow D0 and D3 */
284 unsigned int mmio_always_on:1; /* disallow turning off io/mem
285 decoding during bar sizing */
286 unsigned int wakeup_prepared:1;
287 unsigned int d3_delay; /* D3->D0 transition time in ms */
289 #ifdef CONFIG_PCIEASPM
290 struct pcie_link_state *link_state; /* ASPM link state. */
293 pci_channel_state_t error_state; /* current connectivity state */
294 struct device dev; /* Generic device interface */
296 int cfg_size; /* Size of configuration space */
299 * Instead of touching interrupt line and base address registers
300 * directly, use the values stored here. They might be different!
303 struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */
304 resource_size_t fw_addr[DEVICE_COUNT_RESOURCE]; /* FW-assigned addr */
306 /* These fields are used by common fixups */
307 unsigned int transparent:1; /* Transparent PCI bridge */
308 unsigned int multifunction:1;/* Part of multi-function device */
309 /* keep track of device state */
310 unsigned int is_added:1;
311 unsigned int is_busmaster:1; /* device is busmaster */
312 unsigned int no_msi:1; /* device may not use msi */
313 unsigned int block_ucfg_access:1; /* userspace config space access is blocked */
314 unsigned int broken_parity_status:1; /* Device generates false positive parity */
315 unsigned int irq_reroute_variant:2; /* device needs IRQ rerouting variant */
316 unsigned int msi_enabled:1;
317 unsigned int msix_enabled:1;
318 unsigned int ari_enabled:1; /* ARI forwarding */
319 unsigned int is_managed:1;
320 unsigned int is_pcie:1; /* Obsolete. Will be removed.
321 Use pci_is_pcie() instead */
322 unsigned int needs_freset:1; /* Dev requires fundamental reset */
323 unsigned int state_saved:1;
324 unsigned int is_physfn:1;
325 unsigned int is_virtfn:1;
326 unsigned int reset_fn:1;
327 unsigned int is_hotplug_bridge:1;
328 unsigned int __aer_firmware_first_valid:1;
329 unsigned int __aer_firmware_first:1;
330 pci_dev_flags_t dev_flags;
331 atomic_t enable_cnt; /* pci_enable_device has been called */
333 u32 saved_config_space[16]; /* config space saved at suspend time */
334 struct hlist_head saved_cap_space;
335 struct bin_attribute *rom_attr; /* attribute descriptor for sysfs ROM entry */
336 int rom_attr_enabled; /* has display of the rom attribute been enabled? */
337 struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */
338 struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */
339 #ifdef CONFIG_PCI_MSI
340 struct list_head msi_list;
343 #ifdef CONFIG_PCI_ATS
345 struct pci_sriov *sriov; /* SR-IOV capability related */
346 struct pci_dev *physfn; /* the PF this VF is associated with */
348 struct pci_ats *ats; /* Address Translation Service */
352 static inline struct pci_dev *pci_physfn(struct pci_dev *dev)
354 #ifdef CONFIG_PCI_IOV
362 extern struct pci_dev *alloc_pci_dev(void);
364 #define pci_dev_b(n) list_entry(n, struct pci_dev, bus_list)
365 #define to_pci_dev(n) container_of(n, struct pci_dev, dev)
366 #define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL)
368 static inline int pci_channel_offline(struct pci_dev *pdev)
370 return (pdev->error_state != pci_channel_io_normal);
373 static inline struct pci_cap_saved_state *pci_find_saved_cap(
374 struct pci_dev *pci_dev, char cap)
376 struct pci_cap_saved_state *tmp;
377 struct hlist_node *pos;
379 hlist_for_each_entry(tmp, pos, &pci_dev->saved_cap_space, next) {
380 if (tmp->cap.cap_nr == cap)
386 static inline void pci_add_saved_cap(struct pci_dev *pci_dev,
387 struct pci_cap_saved_state *new_cap)
389 hlist_add_head(&new_cap->next, &pci_dev->saved_cap_space);
393 * The first PCI_BRIDGE_RESOURCE_NUM PCI bus resources (those that correspond
394 * to P2P or CardBus bridge windows) go in a table. Additional ones (for
395 * buses below host bridges or subtractive decode bridges) go in the list.
396 * Use pci_bus_for_each_resource() to iterate through all the resources.
400 * PCI_SUBTRACTIVE_DECODE means the bridge forwards the window implicitly
401 * and there's no way to program the bridge with the details of the window.
402 * This does not apply to ACPI _CRS windows, even with the _DEC subtractive-
403 * decode bit set, because they are explicit and can be programmed with _SRS.
405 #define PCI_SUBTRACTIVE_DECODE 0x1
407 struct pci_bus_resource {
408 struct list_head list;
409 struct resource *res;
413 #define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */
416 struct list_head node; /* node in list of buses */
417 struct pci_bus *parent; /* parent bus this bridge is on */
418 struct list_head children; /* list of child buses */
419 struct list_head devices; /* list of devices on this bus */
420 struct pci_dev *self; /* bridge device as seen by parent */
421 struct list_head slots; /* list of slots on this bus */
422 struct resource *resource[PCI_BRIDGE_RESOURCE_NUM];
423 struct list_head resources; /* address space routed to this bus */
425 struct pci_ops *ops; /* configuration access functions */
426 void *sysdata; /* hook for sys-specific extension */
427 struct proc_dir_entry *procdir; /* directory entry in /proc/bus/pci */
429 unsigned char number; /* bus number */
430 unsigned char primary; /* number of primary bridge */
431 unsigned char secondary; /* number of secondary bridge */
432 unsigned char subordinate; /* max number of subordinate buses */
433 unsigned char max_bus_speed; /* enum pci_bus_speed */
434 unsigned char cur_bus_speed; /* enum pci_bus_speed */
438 unsigned short bridge_ctl; /* manage NO_ISA/FBB/et al behaviors */
439 pci_bus_flags_t bus_flags; /* Inherited by child busses */
440 struct device *bridge;
442 struct bin_attribute *legacy_io; /* legacy I/O for this bus */
443 struct bin_attribute *legacy_mem; /* legacy mem */
444 unsigned int is_added:1;
447 #define pci_bus_b(n) list_entry(n, struct pci_bus, node)
448 #define to_pci_bus(n) container_of(n, struct pci_bus, dev)
451 * Returns true if the pci bus is root (behind host-pci bridge),
454 static inline bool pci_is_root_bus(struct pci_bus *pbus)
456 return !(pbus->parent);
459 #ifdef CONFIG_PCI_MSI
460 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev)
462 return pci_dev->msi_enabled || pci_dev->msix_enabled;
465 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; }
469 * Error values that may be returned by PCI functions.
471 #define PCIBIOS_SUCCESSFUL 0x00
472 #define PCIBIOS_FUNC_NOT_SUPPORTED 0x81
473 #define PCIBIOS_BAD_VENDOR_ID 0x83
474 #define PCIBIOS_DEVICE_NOT_FOUND 0x86
475 #define PCIBIOS_BAD_REGISTER_NUMBER 0x87
476 #define PCIBIOS_SET_FAILED 0x88
477 #define PCIBIOS_BUFFER_TOO_SMALL 0x89
479 /* Low-level architecture-dependent routines */
482 int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val);
483 int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val);
487 * ACPI needs to be able to access PCI config space before we've done a
488 * PCI bus scan and created pci_bus structures.
490 extern int raw_pci_read(unsigned int domain, unsigned int bus,
491 unsigned int devfn, int reg, int len, u32 *val);
492 extern int raw_pci_write(unsigned int domain, unsigned int bus,
493 unsigned int devfn, int reg, int len, u32 val);
495 struct pci_bus_region {
496 resource_size_t start;
501 spinlock_t lock; /* protects list, index */
502 struct list_head list; /* for IDs added at runtime */
505 /* ---------------------------------------------------------------- */
506 /** PCI Error Recovery System (PCI-ERS). If a PCI device driver provides
507 * a set of callbacks in struct pci_error_handlers, then that device driver
508 * will be notified of PCI bus errors, and will be driven to recovery
509 * when an error occurs.
512 typedef unsigned int __bitwise pci_ers_result_t;
514 enum pci_ers_result {
515 /* no result/none/not supported in device driver */
516 PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1,
518 /* Device driver can recover without slot reset */
519 PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2,
521 /* Device driver wants slot to be reset. */
522 PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3,
524 /* Device has completely failed, is unrecoverable */
525 PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4,
527 /* Device driver is fully recovered and operational */
528 PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5,
531 /* PCI bus error event callbacks */
532 struct pci_error_handlers {
533 /* PCI bus error detected on this device */
534 pci_ers_result_t (*error_detected)(struct pci_dev *dev,
535 enum pci_channel_state error);
537 /* MMIO has been re-enabled, but not DMA */
538 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev);
540 /* PCI Express link has been reset */
541 pci_ers_result_t (*link_reset)(struct pci_dev *dev);
543 /* PCI slot has been reset */
544 pci_ers_result_t (*slot_reset)(struct pci_dev *dev);
546 /* Device driver may resume normal operations */
547 void (*resume)(struct pci_dev *dev);
550 /* ---------------------------------------------------------------- */
554 struct list_head node;
556 const struct pci_device_id *id_table; /* must be non-NULL for probe to be called */
557 int (*probe) (struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */
558 void (*remove) (struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */
559 int (*suspend) (struct pci_dev *dev, pm_message_t state); /* Device suspended */
560 int (*suspend_late) (struct pci_dev *dev, pm_message_t state);
561 int (*resume_early) (struct pci_dev *dev);
562 int (*resume) (struct pci_dev *dev); /* Device woken up */
563 void (*shutdown) (struct pci_dev *dev);
564 struct pci_error_handlers *err_handler;
565 struct device_driver driver;
566 struct pci_dynids dynids;
569 #define to_pci_driver(drv) container_of(drv, struct pci_driver, driver)
572 * DEFINE_PCI_DEVICE_TABLE - macro used to describe a pci device table
573 * @_table: device table name
575 * This macro is used to create a struct pci_device_id array (a device table)
576 * in a generic manner.
578 #define DEFINE_PCI_DEVICE_TABLE(_table) \
579 const struct pci_device_id _table[] __devinitconst
582 * PCI_DEVICE - macro used to describe a specific pci device
583 * @vend: the 16 bit PCI Vendor ID
584 * @dev: the 16 bit PCI Device ID
586 * This macro is used to create a struct pci_device_id that matches a
587 * specific device. The subvendor and subdevice fields will be set to
590 #define PCI_DEVICE(vend,dev) \
591 .vendor = (vend), .device = (dev), \
592 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
595 * PCI_DEVICE_CLASS - macro used to describe a specific pci device class
596 * @dev_class: the class, subclass, prog-if triple for this device
597 * @dev_class_mask: the class mask for this device
599 * This macro is used to create a struct pci_device_id that matches a
600 * specific PCI class. The vendor, device, subvendor, and subdevice
601 * fields will be set to PCI_ANY_ID.
603 #define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \
604 .class = (dev_class), .class_mask = (dev_class_mask), \
605 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \
606 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
609 * PCI_VDEVICE - macro used to describe a specific pci device in short form
610 * @vendor: the vendor name
611 * @device: the 16 bit PCI Device ID
613 * This macro is used to create a struct pci_device_id that matches a
614 * specific PCI device. The subvendor, and subdevice fields will be set
615 * to PCI_ANY_ID. The macro allows the next field to follow as the device
619 #define PCI_VDEVICE(vendor, device) \
620 PCI_VENDOR_ID_##vendor, (device), \
621 PCI_ANY_ID, PCI_ANY_ID, 0, 0
623 /* these external functions are only available when PCI support is enabled */
626 extern void pcie_bus_configure_settings(struct pci_bus *bus, u8 smpss);
628 enum pcie_bus_config_types {
631 PCIE_BUS_PERFORMANCE,
635 extern enum pcie_bus_config_types pcie_bus_config;
637 extern struct bus_type pci_bus_type;
639 /* Do NOT directly access these two variables, unless you are arch specific pci
640 * code, or pci core code. */
641 extern struct list_head pci_root_buses; /* list of all known PCI buses */
642 /* Some device drivers need know if pci is initiated */
643 extern int no_pci_devices(void);
645 void pcibios_fixup_bus(struct pci_bus *);
646 int __must_check pcibios_enable_device(struct pci_dev *, int mask);
647 char *pcibios_setup(char *str);
649 /* Used only when drivers/pci/setup.c is used */
650 resource_size_t pcibios_align_resource(void *, const struct resource *,
653 void pcibios_update_irq(struct pci_dev *, int irq);
655 /* Weak but can be overriden by arch */
656 void pci_fixup_cardbus(struct pci_bus *);
658 /* Generic PCI functions used internally */
660 void pcibios_scan_specific_bus(int busn);
661 extern struct pci_bus *pci_find_bus(int domain, int busnr);
662 void pci_bus_add_devices(const struct pci_bus *bus);
663 struct pci_bus *pci_scan_bus_parented(struct device *parent, int bus,
664 struct pci_ops *ops, void *sysdata);
665 static inline struct pci_bus * __devinit pci_scan_bus(int bus, struct pci_ops *ops,
668 struct pci_bus *root_bus;
669 root_bus = pci_scan_bus_parented(NULL, bus, ops, sysdata);
671 pci_bus_add_devices(root_bus);
674 struct pci_bus *pci_create_bus(struct device *parent, int bus,
675 struct pci_ops *ops, void *sysdata);
676 struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,
678 void pcie_update_link_speed(struct pci_bus *bus, u16 link_status);
679 struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr,
681 struct hotplug_slot *hotplug);
682 void pci_destroy_slot(struct pci_slot *slot);
683 void pci_renumber_slot(struct pci_slot *slot, int slot_nr);
684 int pci_scan_slot(struct pci_bus *bus, int devfn);
685 struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn);
686 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus);
687 unsigned int pci_scan_child_bus(struct pci_bus *bus);
688 int __must_check pci_bus_add_device(struct pci_dev *dev);
689 void pci_read_bridge_bases(struct pci_bus *child);
690 struct resource *pci_find_parent_resource(const struct pci_dev *dev,
691 struct resource *res);
692 u8 pci_swizzle_interrupt_pin(struct pci_dev *dev, u8 pin);
693 int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge);
694 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp);
695 extern struct pci_dev *pci_dev_get(struct pci_dev *dev);
696 extern void pci_dev_put(struct pci_dev *dev);
697 extern void pci_remove_bus(struct pci_bus *b);
698 extern void pci_remove_bus_device(struct pci_dev *dev);
699 extern void pci_stop_bus_device(struct pci_dev *dev);
700 void pci_setup_cardbus(struct pci_bus *bus);
701 extern void pci_sort_breadthfirst(void);
702 #define dev_is_pci(d) ((d)->bus == &pci_bus_type)
703 #define dev_is_pf(d) ((dev_is_pci(d) ? to_pci_dev(d)->is_physfn : false))
704 #define dev_num_vf(d) ((dev_is_pci(d) ? pci_num_vf(to_pci_dev(d)) : 0))
706 /* Generic PCI functions exported to card drivers */
708 enum pci_lost_interrupt_reason {
709 PCI_LOST_IRQ_NO_INFORMATION = 0,
710 PCI_LOST_IRQ_DISABLE_MSI,
711 PCI_LOST_IRQ_DISABLE_MSIX,
712 PCI_LOST_IRQ_DISABLE_ACPI,
714 enum pci_lost_interrupt_reason pci_lost_interrupt(struct pci_dev *dev);
715 int pci_find_capability(struct pci_dev *dev, int cap);
716 int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap);
717 int pci_find_ext_capability(struct pci_dev *dev, int cap);
718 int pci_bus_find_ext_capability(struct pci_bus *bus, unsigned int devfn,
720 int pci_find_ht_capability(struct pci_dev *dev, int ht_cap);
721 int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap);
722 struct pci_bus *pci_find_next_bus(const struct pci_bus *from);
724 struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device,
725 struct pci_dev *from);
726 struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device,
727 unsigned int ss_vendor, unsigned int ss_device,
728 struct pci_dev *from);
729 struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn);
730 struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus,
732 static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus,
735 return pci_get_domain_bus_and_slot(0, bus, devfn);
737 struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from);
738 int pci_dev_present(const struct pci_device_id *ids);
740 int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn,
742 int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn,
743 int where, u16 *val);
744 int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn,
745 int where, u32 *val);
746 int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn,
748 int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn,
750 int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn,
752 struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops);
754 static inline int pci_read_config_byte(struct pci_dev *dev, int where, u8 *val)
756 return pci_bus_read_config_byte(dev->bus, dev->devfn, where, val);
758 static inline int pci_read_config_word(struct pci_dev *dev, int where, u16 *val)
760 return pci_bus_read_config_word(dev->bus, dev->devfn, where, val);
762 static inline int pci_read_config_dword(struct pci_dev *dev, int where,
765 return pci_bus_read_config_dword(dev->bus, dev->devfn, where, val);
767 static inline int pci_write_config_byte(struct pci_dev *dev, int where, u8 val)
769 return pci_bus_write_config_byte(dev->bus, dev->devfn, where, val);
771 static inline int pci_write_config_word(struct pci_dev *dev, int where, u16 val)
773 return pci_bus_write_config_word(dev->bus, dev->devfn, where, val);
775 static inline int pci_write_config_dword(struct pci_dev *dev, int where,
778 return pci_bus_write_config_dword(dev->bus, dev->devfn, where, val);
781 int __must_check pci_enable_device(struct pci_dev *dev);
782 int __must_check pci_enable_device_io(struct pci_dev *dev);
783 int __must_check pci_enable_device_mem(struct pci_dev *dev);
784 int __must_check pci_reenable_device(struct pci_dev *);
785 int __must_check pcim_enable_device(struct pci_dev *pdev);
786 void pcim_pin_device(struct pci_dev *pdev);
788 static inline int pci_is_enabled(struct pci_dev *pdev)
790 return (atomic_read(&pdev->enable_cnt) > 0);
793 static inline int pci_is_managed(struct pci_dev *pdev)
795 return pdev->is_managed;
798 void pci_disable_device(struct pci_dev *dev);
799 void pci_set_master(struct pci_dev *dev);
800 void pci_clear_master(struct pci_dev *dev);
801 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state);
802 int pci_set_cacheline_size(struct pci_dev *dev);
803 #define HAVE_PCI_SET_MWI
804 int __must_check pci_set_mwi(struct pci_dev *dev);
805 int pci_try_set_mwi(struct pci_dev *dev);
806 void pci_clear_mwi(struct pci_dev *dev);
807 void pci_intx(struct pci_dev *dev, int enable);
808 void pci_msi_off(struct pci_dev *dev);
809 int pci_set_dma_max_seg_size(struct pci_dev *dev, unsigned int size);
810 int pci_set_dma_seg_boundary(struct pci_dev *dev, unsigned long mask);
811 int pcix_get_max_mmrbc(struct pci_dev *dev);
812 int pcix_get_mmrbc(struct pci_dev *dev);
813 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc);
814 int pcie_get_readrq(struct pci_dev *dev);
815 int pcie_set_readrq(struct pci_dev *dev, int rq);
816 int pcie_get_mps(struct pci_dev *dev);
817 int pcie_set_mps(struct pci_dev *dev, int mps);
818 int __pci_reset_function(struct pci_dev *dev);
819 int pci_reset_function(struct pci_dev *dev);
820 void pci_update_resource(struct pci_dev *dev, int resno);
821 int __must_check pci_assign_resource(struct pci_dev *dev, int i);
822 int __must_check pci_reassign_resource(struct pci_dev *dev, int i, resource_size_t add_size, resource_size_t align);
823 int pci_select_bars(struct pci_dev *dev, unsigned long flags);
825 /* ROM control related routines */
826 int pci_enable_rom(struct pci_dev *pdev);
827 void pci_disable_rom(struct pci_dev *pdev);
828 void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size);
829 void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom);
830 size_t pci_get_rom_size(struct pci_dev *pdev, void __iomem *rom, size_t size);
832 /* Power management related routines */
833 int pci_save_state(struct pci_dev *dev);
834 void pci_restore_state(struct pci_dev *dev);
835 struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev);
836 int pci_load_saved_state(struct pci_dev *dev, struct pci_saved_state *state);
837 int pci_load_and_free_saved_state(struct pci_dev *dev,
838 struct pci_saved_state **state);
839 int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state);
840 int pci_set_power_state(struct pci_dev *dev, pci_power_t state);
841 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state);
842 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state);
843 void pci_pme_active(struct pci_dev *dev, bool enable);
844 int __pci_enable_wake(struct pci_dev *dev, pci_power_t state,
845 bool runtime, bool enable);
846 int pci_wake_from_d3(struct pci_dev *dev, bool enable);
847 pci_power_t pci_target_state(struct pci_dev *dev);
848 int pci_prepare_to_sleep(struct pci_dev *dev);
849 int pci_back_from_sleep(struct pci_dev *dev);
850 bool pci_dev_run_wake(struct pci_dev *dev);
851 bool pci_check_pme_status(struct pci_dev *dev);
852 void pci_pme_wakeup_bus(struct pci_bus *bus);
854 static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state,
857 return __pci_enable_wake(dev, state, false, enable);
860 #define PCI_EXP_IDO_REQUEST (1<<0)
861 #define PCI_EXP_IDO_COMPLETION (1<<1)
862 void pci_enable_ido(struct pci_dev *dev, unsigned long type);
863 void pci_disable_ido(struct pci_dev *dev, unsigned long type);
865 enum pci_obff_signal_type {
866 PCI_EXP_OBFF_SIGNAL_L0 = 0,
867 PCI_EXP_OBFF_SIGNAL_ALWAYS = 1,
869 int pci_enable_obff(struct pci_dev *dev, enum pci_obff_signal_type);
870 void pci_disable_obff(struct pci_dev *dev);
872 bool pci_ltr_supported(struct pci_dev *dev);
873 int pci_enable_ltr(struct pci_dev *dev);
874 void pci_disable_ltr(struct pci_dev *dev);
875 int pci_set_ltr(struct pci_dev *dev, int snoop_lat_ns, int nosnoop_lat_ns);
877 /* For use by arch with custom probe code */
878 void set_pcie_port_type(struct pci_dev *pdev);
879 void set_pcie_hotplug_bridge(struct pci_dev *pdev);
881 /* Functions for PCI Hotplug drivers to use */
882 int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap);
883 #ifdef CONFIG_HOTPLUG
884 unsigned int pci_rescan_bus(struct pci_bus *bus);
887 /* Vital product data routines */
888 ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf);
889 ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf);
890 int pci_vpd_truncate(struct pci_dev *dev, size_t size);
892 /* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */
893 void pci_bus_assign_resources(const struct pci_bus *bus);
894 void pci_bus_size_bridges(struct pci_bus *bus);
895 int pci_claim_resource(struct pci_dev *, int);
896 void pci_assign_unassigned_resources(void);
897 void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge);
898 void pdev_enable_device(struct pci_dev *);
899 void pdev_sort_resources(struct pci_dev *, struct resource_list *);
900 int pci_enable_resources(struct pci_dev *, int mask);
901 void pci_fixup_irqs(u8 (*)(struct pci_dev *, u8 *),
902 int (*)(const struct pci_dev *, u8, u8));
903 #define HAVE_PCI_REQ_REGIONS 2
904 int __must_check pci_request_regions(struct pci_dev *, const char *);
905 int __must_check pci_request_regions_exclusive(struct pci_dev *, const char *);
906 void pci_release_regions(struct pci_dev *);
907 int __must_check pci_request_region(struct pci_dev *, int, const char *);
908 int __must_check pci_request_region_exclusive(struct pci_dev *, int, const char *);
909 void pci_release_region(struct pci_dev *, int);
910 int pci_request_selected_regions(struct pci_dev *, int, const char *);
911 int pci_request_selected_regions_exclusive(struct pci_dev *, int, const char *);
912 void pci_release_selected_regions(struct pci_dev *, int);
914 /* drivers/pci/bus.c */
915 void pci_bus_add_resource(struct pci_bus *bus, struct resource *res, unsigned int flags);
916 struct resource *pci_bus_resource_n(const struct pci_bus *bus, int n);
917 void pci_bus_remove_resources(struct pci_bus *bus);
919 #define pci_bus_for_each_resource(bus, res, i) \
921 (res = pci_bus_resource_n(bus, i)) || i < PCI_BRIDGE_RESOURCE_NUM; \
924 int __must_check pci_bus_alloc_resource(struct pci_bus *bus,
925 struct resource *res, resource_size_t size,
926 resource_size_t align, resource_size_t min,
927 unsigned int type_mask,
928 resource_size_t (*alignf)(void *,
929 const struct resource *,
933 void pci_enable_bridges(struct pci_bus *bus);
935 /* Proper probing supporting hot-pluggable devices */
936 int __must_check __pci_register_driver(struct pci_driver *, struct module *,
937 const char *mod_name);
940 * pci_register_driver must be a macro so that KBUILD_MODNAME can be expanded
942 #define pci_register_driver(driver) \
943 __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME)
945 void pci_unregister_driver(struct pci_driver *dev);
946 void pci_remove_behind_bridge(struct pci_dev *dev);
947 struct pci_driver *pci_dev_driver(const struct pci_dev *dev);
948 int pci_add_dynid(struct pci_driver *drv,
949 unsigned int vendor, unsigned int device,
950 unsigned int subvendor, unsigned int subdevice,
951 unsigned int class, unsigned int class_mask,
952 unsigned long driver_data);
953 const struct pci_device_id *pci_match_id(const struct pci_device_id *ids,
954 struct pci_dev *dev);
955 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max,
958 void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *),
960 int pci_cfg_space_size_ext(struct pci_dev *dev);
961 int pci_cfg_space_size(struct pci_dev *dev);
962 unsigned char pci_bus_max_busnr(struct pci_bus *bus);
963 void pci_setup_bridge(struct pci_bus *bus);
965 #define PCI_VGA_STATE_CHANGE_BRIDGE (1 << 0)
966 #define PCI_VGA_STATE_CHANGE_DECODES (1 << 1)
968 int pci_set_vga_state(struct pci_dev *pdev, bool decode,
969 unsigned int command_bits, u32 flags);
970 /* kmem_cache style wrapper around pci_alloc_consistent() */
972 #include <linux/pci-dma.h>
973 #include <linux/dmapool.h>
975 #define pci_pool dma_pool
976 #define pci_pool_create(name, pdev, size, align, allocation) \
977 dma_pool_create(name, &pdev->dev, size, align, allocation)
978 #define pci_pool_destroy(pool) dma_pool_destroy(pool)
979 #define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle)
980 #define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr)
982 enum pci_dma_burst_strategy {
983 PCI_DMA_BURST_INFINITY, /* make bursts as large as possible,
984 strategy_parameter is N/A */
985 PCI_DMA_BURST_BOUNDARY, /* disconnect at every strategy_parameter
987 PCI_DMA_BURST_MULTIPLE, /* disconnect at some multiple of
988 strategy_parameter byte boundaries */
992 u32 vector; /* kernel uses to write allocated vector */
993 u16 entry; /* driver uses to specify entry, OS writes */
997 #ifndef CONFIG_PCI_MSI
998 static inline int pci_enable_msi_block(struct pci_dev *dev, unsigned int nvec)
1003 static inline void pci_msi_shutdown(struct pci_dev *dev)
1005 static inline void pci_disable_msi(struct pci_dev *dev)
1008 static inline int pci_msix_table_size(struct pci_dev *dev)
1012 static inline int pci_enable_msix(struct pci_dev *dev,
1013 struct msix_entry *entries, int nvec)
1018 static inline void pci_msix_shutdown(struct pci_dev *dev)
1020 static inline void pci_disable_msix(struct pci_dev *dev)
1023 static inline void msi_remove_pci_irq_vectors(struct pci_dev *dev)
1026 static inline void pci_restore_msi_state(struct pci_dev *dev)
1028 static inline int pci_msi_enabled(void)
1033 extern int pci_enable_msi_block(struct pci_dev *dev, unsigned int nvec);
1034 extern void pci_msi_shutdown(struct pci_dev *dev);
1035 extern void pci_disable_msi(struct pci_dev *dev);
1036 extern int pci_msix_table_size(struct pci_dev *dev);
1037 extern int pci_enable_msix(struct pci_dev *dev,
1038 struct msix_entry *entries, int nvec);
1039 extern void pci_msix_shutdown(struct pci_dev *dev);
1040 extern void pci_disable_msix(struct pci_dev *dev);
1041 extern void msi_remove_pci_irq_vectors(struct pci_dev *dev);
1042 extern void pci_restore_msi_state(struct pci_dev *dev);
1043 extern int pci_msi_enabled(void);
1046 #ifdef CONFIG_PCIEPORTBUS
1047 extern bool pcie_ports_disabled;
1048 extern bool pcie_ports_auto;
1050 #define pcie_ports_disabled true
1051 #define pcie_ports_auto false
1054 #ifndef CONFIG_PCIEASPM
1055 static inline int pcie_aspm_enabled(void) { return 0; }
1056 static inline bool pcie_aspm_support_enabled(void) { return false; }
1058 extern int pcie_aspm_enabled(void);
1059 extern bool pcie_aspm_support_enabled(void);
1062 #ifdef CONFIG_PCIEAER
1063 void pci_no_aer(void);
1064 bool pci_aer_available(void);
1066 static inline void pci_no_aer(void) { }
1067 static inline bool pci_aer_available(void) { return false; }
1070 #ifndef CONFIG_PCIE_ECRC
1071 static inline void pcie_set_ecrc_checking(struct pci_dev *dev)
1075 static inline void pcie_ecrc_get_policy(char *str) {};
1077 extern void pcie_set_ecrc_checking(struct pci_dev *dev);
1078 extern void pcie_ecrc_get_policy(char *str);
1081 #define pci_enable_msi(pdev) pci_enable_msi_block(pdev, 1)
1083 #ifdef CONFIG_HT_IRQ
1084 /* The functions a driver should call */
1085 int ht_create_irq(struct pci_dev *dev, int idx);
1086 void ht_destroy_irq(unsigned int irq);
1087 #endif /* CONFIG_HT_IRQ */
1089 extern void pci_block_user_cfg_access(struct pci_dev *dev);
1090 extern void pci_unblock_user_cfg_access(struct pci_dev *dev);
1093 * PCI domain support. Sometimes called PCI segment (eg by ACPI),
1094 * a PCI domain is defined to be a set of PCI busses which share
1095 * configuration space.
1097 #ifdef CONFIG_PCI_DOMAINS
1098 extern int pci_domains_supported;
1100 enum { pci_domains_supported = 0 };
1101 static inline int pci_domain_nr(struct pci_bus *bus)
1106 static inline int pci_proc_domain(struct pci_bus *bus)
1110 #endif /* CONFIG_PCI_DOMAINS */
1112 /* some architectures require additional setup to direct VGA traffic */
1113 typedef int (*arch_set_vga_state_t)(struct pci_dev *pdev, bool decode,
1114 unsigned int command_bits, u32 flags);
1115 extern void pci_register_set_vga_state(arch_set_vga_state_t func);
1117 #else /* CONFIG_PCI is not enabled */
1120 * If the system does not have PCI, clearly these return errors. Define
1121 * these as simple inline functions to avoid hair in drivers.
1124 #define _PCI_NOP(o, s, t) \
1125 static inline int pci_##o##_config_##s(struct pci_dev *dev, \
1127 { return PCIBIOS_FUNC_NOT_SUPPORTED; }
1129 #define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \
1130 _PCI_NOP(o, word, u16 x) \
1131 _PCI_NOP(o, dword, u32 x)
1132 _PCI_NOP_ALL(read, *)
1133 _PCI_NOP_ALL(write,)
1135 static inline struct pci_dev *pci_get_device(unsigned int vendor,
1136 unsigned int device,
1137 struct pci_dev *from)
1142 static inline struct pci_dev *pci_get_subsys(unsigned int vendor,
1143 unsigned int device,
1144 unsigned int ss_vendor,
1145 unsigned int ss_device,
1146 struct pci_dev *from)
1151 static inline struct pci_dev *pci_get_class(unsigned int class,
1152 struct pci_dev *from)
1157 #define pci_dev_present(ids) (0)
1158 #define no_pci_devices() (1)
1159 #define pci_dev_put(dev) do { } while (0)
1161 static inline void pci_set_master(struct pci_dev *dev)
1164 static inline int pci_enable_device(struct pci_dev *dev)
1169 static inline void pci_disable_device(struct pci_dev *dev)
1172 static inline int pci_set_dma_mask(struct pci_dev *dev, u64 mask)
1177 static inline int pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask)
1182 static inline int pci_set_dma_max_seg_size(struct pci_dev *dev,
1188 static inline int pci_set_dma_seg_boundary(struct pci_dev *dev,
1194 static inline int pci_assign_resource(struct pci_dev *dev, int i)
1199 static inline int __pci_register_driver(struct pci_driver *drv,
1200 struct module *owner)
1205 static inline int pci_register_driver(struct pci_driver *drv)
1210 static inline void pci_unregister_driver(struct pci_driver *drv)
1213 static inline int pci_find_capability(struct pci_dev *dev, int cap)
1218 static inline int pci_find_next_capability(struct pci_dev *dev, u8 post,
1224 static inline int pci_find_ext_capability(struct pci_dev *dev, int cap)
1229 /* Power management related routines */
1230 static inline int pci_save_state(struct pci_dev *dev)
1235 static inline void pci_restore_state(struct pci_dev *dev)
1238 static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
1243 static inline int pci_wake_from_d3(struct pci_dev *dev, bool enable)
1248 static inline pci_power_t pci_choose_state(struct pci_dev *dev,
1254 static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1260 static inline void pci_enable_ido(struct pci_dev *dev, unsigned long type)
1264 static inline void pci_disable_ido(struct pci_dev *dev, unsigned long type)
1268 static inline int pci_enable_obff(struct pci_dev *dev, unsigned long type)
1273 static inline void pci_disable_obff(struct pci_dev *dev)
1277 static inline int pci_request_regions(struct pci_dev *dev, const char *res_name)
1282 static inline void pci_release_regions(struct pci_dev *dev)
1285 #define pci_dma_burst_advice(pdev, strat, strategy_parameter) do { } while (0)
1287 static inline void pci_block_user_cfg_access(struct pci_dev *dev)
1290 static inline void pci_unblock_user_cfg_access(struct pci_dev *dev)
1293 static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from)
1296 static inline struct pci_dev *pci_get_slot(struct pci_bus *bus,
1300 static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus,
1304 static inline int pci_domain_nr(struct pci_bus *bus)
1307 #define dev_is_pci(d) (false)
1308 #define dev_is_pf(d) (false)
1309 #define dev_num_vf(d) (0)
1310 #endif /* CONFIG_PCI */
1312 /* Include architecture-dependent settings and functions */
1314 #include <asm/pci.h>
1316 #ifndef PCIBIOS_MAX_MEM_32
1317 #define PCIBIOS_MAX_MEM_32 (-1)
1320 /* these helpers provide future and backwards compatibility
1321 * for accessing popular PCI BAR info */
1322 #define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start)
1323 #define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end)
1324 #define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags)
1325 #define pci_resource_len(dev,bar) \
1326 ((pci_resource_start((dev), (bar)) == 0 && \
1327 pci_resource_end((dev), (bar)) == \
1328 pci_resource_start((dev), (bar))) ? 0 : \
1330 (pci_resource_end((dev), (bar)) - \
1331 pci_resource_start((dev), (bar)) + 1))
1333 /* Similar to the helpers above, these manipulate per-pci_dev
1334 * driver-specific data. They are really just a wrapper around
1335 * the generic device structure functions of these calls.
1337 static inline void *pci_get_drvdata(struct pci_dev *pdev)
1339 return dev_get_drvdata(&pdev->dev);
1342 static inline void pci_set_drvdata(struct pci_dev *pdev, void *data)
1344 dev_set_drvdata(&pdev->dev, data);
1347 /* If you want to know what to call your pci_dev, ask this function.
1348 * Again, it's a wrapper around the generic device.
1350 static inline const char *pci_name(const struct pci_dev *pdev)
1352 return dev_name(&pdev->dev);
1356 /* Some archs don't want to expose struct resource to userland as-is
1357 * in sysfs and /proc
1359 #ifndef HAVE_ARCH_PCI_RESOURCE_TO_USER
1360 static inline void pci_resource_to_user(const struct pci_dev *dev, int bar,
1361 const struct resource *rsrc, resource_size_t *start,
1362 resource_size_t *end)
1364 *start = rsrc->start;
1367 #endif /* HAVE_ARCH_PCI_RESOURCE_TO_USER */
1371 * The world is not perfect and supplies us with broken PCI devices.
1372 * For at least a part of these bugs we need a work-around, so both
1373 * generic (drivers/pci/quirks.c) and per-architecture code can define
1374 * fixup hooks to be called for particular buggy devices.
1378 u16 vendor, device; /* You can use PCI_ANY_ID here of course */
1379 void (*hook)(struct pci_dev *dev);
1382 enum pci_fixup_pass {
1383 pci_fixup_early, /* Before probing BARs */
1384 pci_fixup_header, /* After reading configuration header */
1385 pci_fixup_final, /* Final phase of device fixups */
1386 pci_fixup_enable, /* pci_enable_device() time */
1387 pci_fixup_resume, /* pci_device_resume() */
1388 pci_fixup_suspend, /* pci_device_suspend */
1389 pci_fixup_resume_early, /* pci_device_resume_early() */
1392 /* Anonymous variables would be nice... */
1393 #define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, hook) \
1394 static const struct pci_fixup __pci_fixup_##name __used \
1395 __attribute__((__section__(#section))) = { vendor, device, hook };
1396 #define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \
1397 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
1398 vendor##device##hook, vendor, device, hook)
1399 #define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \
1400 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
1401 vendor##device##hook, vendor, device, hook)
1402 #define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \
1403 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
1404 vendor##device##hook, vendor, device, hook)
1405 #define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \
1406 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
1407 vendor##device##hook, vendor, device, hook)
1408 #define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \
1409 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
1410 resume##vendor##device##hook, vendor, device, hook)
1411 #define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \
1412 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
1413 resume_early##vendor##device##hook, vendor, device, hook)
1414 #define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \
1415 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
1416 suspend##vendor##device##hook, vendor, device, hook)
1418 #ifdef CONFIG_PCI_QUIRKS
1419 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev);
1421 static inline void pci_fixup_device(enum pci_fixup_pass pass,
1422 struct pci_dev *dev) {}
1425 void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen);
1426 void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr);
1427 void __iomem * const *pcim_iomap_table(struct pci_dev *pdev);
1428 int pcim_iomap_regions(struct pci_dev *pdev, u16 mask, const char *name);
1429 int pcim_iomap_regions_request_all(struct pci_dev *pdev, u16 mask,
1431 void pcim_iounmap_regions(struct pci_dev *pdev, u16 mask);
1433 extern int pci_pci_problems;
1434 #define PCIPCI_FAIL 1 /* No PCI PCI DMA */
1435 #define PCIPCI_TRITON 2
1436 #define PCIPCI_NATOMA 4
1437 #define PCIPCI_VIAETBF 8
1438 #define PCIPCI_VSFX 16
1439 #define PCIPCI_ALIMAGIK 32 /* Need low latency setting */
1440 #define PCIAGP_FAIL 64 /* No PCI to AGP DMA */
1442 extern unsigned long pci_cardbus_io_size;
1443 extern unsigned long pci_cardbus_mem_size;
1444 extern u8 __devinitdata pci_dfl_cache_line_size;
1445 extern u8 pci_cache_line_size;
1447 extern unsigned long pci_hotplug_io_size;
1448 extern unsigned long pci_hotplug_mem_size;
1450 int pcibios_add_platform_entries(struct pci_dev *dev);
1451 void pcibios_disable_device(struct pci_dev *dev);
1452 int pcibios_set_pcie_reset_state(struct pci_dev *dev,
1453 enum pcie_reset_state state);
1455 #ifdef CONFIG_PCI_MMCONFIG
1456 extern void __init pci_mmcfg_early_init(void);
1457 extern void __init pci_mmcfg_late_init(void);
1459 static inline void pci_mmcfg_early_init(void) { }
1460 static inline void pci_mmcfg_late_init(void) { }
1463 int pci_ext_cfg_avail(struct pci_dev *dev);
1465 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar);
1467 #ifdef CONFIG_PCI_IOV
1468 extern int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn);
1469 extern void pci_disable_sriov(struct pci_dev *dev);
1470 extern irqreturn_t pci_sriov_migration(struct pci_dev *dev);
1471 extern int pci_num_vf(struct pci_dev *dev);
1473 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn)
1477 static inline void pci_disable_sriov(struct pci_dev *dev)
1480 static inline irqreturn_t pci_sriov_migration(struct pci_dev *dev)
1484 static inline int pci_num_vf(struct pci_dev *dev)
1490 #if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE)
1491 extern void pci_hp_create_module_link(struct pci_slot *pci_slot);
1492 extern void pci_hp_remove_module_link(struct pci_slot *pci_slot);
1496 * pci_pcie_cap - get the saved PCIe capability offset
1499 * PCIe capability offset is calculated at PCI device initialization
1500 * time and saved in the data structure. This function returns saved
1501 * PCIe capability offset. Using this instead of pci_find_capability()
1502 * reduces unnecessary search in the PCI configuration space. If you
1503 * need to calculate PCIe capability offset from raw device for some
1504 * reasons, please use pci_find_capability() instead.
1506 static inline int pci_pcie_cap(struct pci_dev *dev)
1508 return dev->pcie_cap;
1512 * pci_is_pcie - check if the PCI device is PCI Express capable
1515 * Retrun true if the PCI device is PCI Express capable, false otherwise.
1517 static inline bool pci_is_pcie(struct pci_dev *dev)
1519 return !!pci_pcie_cap(dev);
1522 void pci_request_acs(void);
1525 #define PCI_VPD_LRDT 0x80 /* Large Resource Data Type */
1526 #define PCI_VPD_LRDT_ID(x) (x | PCI_VPD_LRDT)
1528 /* Large Resource Data Type Tag Item Names */
1529 #define PCI_VPD_LTIN_ID_STRING 0x02 /* Identifier String */
1530 #define PCI_VPD_LTIN_RO_DATA 0x10 /* Read-Only Data */
1531 #define PCI_VPD_LTIN_RW_DATA 0x11 /* Read-Write Data */
1533 #define PCI_VPD_LRDT_ID_STRING PCI_VPD_LRDT_ID(PCI_VPD_LTIN_ID_STRING)
1534 #define PCI_VPD_LRDT_RO_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RO_DATA)
1535 #define PCI_VPD_LRDT_RW_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RW_DATA)
1537 /* Small Resource Data Type Tag Item Names */
1538 #define PCI_VPD_STIN_END 0x78 /* End */
1540 #define PCI_VPD_SRDT_END PCI_VPD_STIN_END
1542 #define PCI_VPD_SRDT_TIN_MASK 0x78
1543 #define PCI_VPD_SRDT_LEN_MASK 0x07
1545 #define PCI_VPD_LRDT_TAG_SIZE 3
1546 #define PCI_VPD_SRDT_TAG_SIZE 1
1548 #define PCI_VPD_INFO_FLD_HDR_SIZE 3
1550 #define PCI_VPD_RO_KEYWORD_PARTNO "PN"
1551 #define PCI_VPD_RO_KEYWORD_MFR_ID "MN"
1552 #define PCI_VPD_RO_KEYWORD_VENDOR0 "V0"
1553 #define PCI_VPD_RO_KEYWORD_CHKSUM "RV"
1556 * pci_vpd_lrdt_size - Extracts the Large Resource Data Type length
1557 * @lrdt: Pointer to the beginning of the Large Resource Data Type tag
1559 * Returns the extracted Large Resource Data Type length.
1561 static inline u16 pci_vpd_lrdt_size(const u8 *lrdt)
1563 return (u16)lrdt[1] + ((u16)lrdt[2] << 8);
1567 * pci_vpd_srdt_size - Extracts the Small Resource Data Type length
1568 * @lrdt: Pointer to the beginning of the Small Resource Data Type tag
1570 * Returns the extracted Small Resource Data Type length.
1572 static inline u8 pci_vpd_srdt_size(const u8 *srdt)
1574 return (*srdt) & PCI_VPD_SRDT_LEN_MASK;
1578 * pci_vpd_info_field_size - Extracts the information field length
1579 * @lrdt: Pointer to the beginning of an information field header
1581 * Returns the extracted information field length.
1583 static inline u8 pci_vpd_info_field_size(const u8 *info_field)
1585 return info_field[2];
1589 * pci_vpd_find_tag - Locates the Resource Data Type tag provided
1590 * @buf: Pointer to buffered vpd data
1591 * @off: The offset into the buffer at which to begin the search
1592 * @len: The length of the vpd buffer
1593 * @rdt: The Resource Data Type to search for
1595 * Returns the index where the Resource Data Type was found or
1596 * -ENOENT otherwise.
1598 int pci_vpd_find_tag(const u8 *buf, unsigned int off, unsigned int len, u8 rdt);
1601 * pci_vpd_find_info_keyword - Locates an information field keyword in the VPD
1602 * @buf: Pointer to buffered vpd data
1603 * @off: The offset into the buffer at which to begin the search
1604 * @len: The length of the buffer area, relative to off, in which to search
1605 * @kw: The keyword to search for
1607 * Returns the index where the information field keyword was found or
1608 * -ENOENT otherwise.
1610 int pci_vpd_find_info_keyword(const u8 *buf, unsigned int off,
1611 unsigned int len, const char *kw);
1613 /* PCI <-> OF binding helpers */
1616 extern void pci_set_of_node(struct pci_dev *dev);
1617 extern void pci_release_of_node(struct pci_dev *dev);
1618 extern void pci_set_bus_of_node(struct pci_bus *bus);
1619 extern void pci_release_bus_of_node(struct pci_bus *bus);
1621 /* Arch may override this (weak) */
1622 extern struct device_node * __weak pcibios_get_phb_of_node(struct pci_bus *bus);
1624 static inline struct device_node *pci_device_to_OF_node(struct pci_dev *pdev)
1626 return pdev ? pdev->dev.of_node : NULL;
1629 static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus)
1631 return bus ? bus->dev.of_node : NULL;
1634 #else /* CONFIG_OF */
1635 static inline void pci_set_of_node(struct pci_dev *dev) { }
1636 static inline void pci_release_of_node(struct pci_dev *dev) { }
1637 static inline void pci_set_bus_of_node(struct pci_bus *bus) { }
1638 static inline void pci_release_bus_of_node(struct pci_bus *bus) { }
1639 #endif /* CONFIG_OF */
1642 * pci_find_upstream_pcie_bridge - find upstream PCIe-to-PCI bridge of a device
1643 * @pdev: the PCI device
1645 * if the device is PCIE, return NULL
1646 * if the device isn't connected to a PCIe bridge (that is its parent is a
1647 * legacy PCI bridge and the bridge is directly connected to bus 0), return its
1650 struct pci_dev *pci_find_upstream_pcie_bridge(struct pci_dev *pdev);
1652 #endif /* __KERNEL__ */
1653 #endif /* LINUX_PCI_H */