2 * Copyright (C) 2007 Mistral Solutions Pvt Ltd.
4 * X-Loader Configuation settings for the OMAP3EVM board.
6 * Derived from /include/configs/omap3430sdp.h
8 * See file CREDITS for list of people who contributed to this
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
30 /* serial printf facility takes about 3.5K */
35 * High Level Configuration Options
37 #define CONFIG_ARMCORTEXA8 1 /* This is an ARM V7 CPU core */
38 #define CONFIG_OMAP 1 /* in a TI OMAP core */
39 #define CONFIG_OMAP34XX 1 /* which is a 34XX */
40 #define CONFIG_OMAP3430 1 /* which is in a 3430 */
41 //#define CONFIG_3430SDP 1 /* working with SDP */
42 //#define CONFIG_3430_AS_3410 1 /* true for 3430 in 3410 mode */
44 #define CONFIG_OMAP3EVM 1 /* working with EVM */
46 /* Enable the below macro if MMC boot support is required */
48 #if defined(CONFIG_MMC)
53 #include <asm/arch/cpu.h> /* get chip and board defs */
55 /* uncomment it if you need timer based udelay(). it takes about 250 bytes */
59 #define V_OSCK 26000000 /* Clock output from T2 */
61 #if (V_OSCK > 19200000)
62 #define V_SCLK (V_OSCK >> 1)
67 //#define PRCM_CLK_CFG2_266MHZ 1 /* VDD2=1.15v - 133MHz DDR */
68 #define PRCM_CLK_CFG2_332MHZ 1 /* VDD2=1.15v - 166MHz DDR */
69 #define PRCM_PCLK_OPP2 1 /* ARM=381MHz - VDD1=1.20v */
72 #define CFG_3430SDRAM_DDR 1
74 /* The actual register values are defined in u-boot- mem.h */
75 /* SDRAM Bank Allocation method */
76 //#define SDRC_B_R_C 1
77 //#define SDRC_B1_R_B0_C 1
81 # define NAND_BASE_ADR NAND_BASE /* NAND flash */
82 # define ONENAND_BASE ONENAND_MAP /* OneNand flash */
84 #define OMAP34XX_GPMC_CS0_SIZE GPMC_SIZE_128M
85 #define ONENAND_ADDR ONENAND_BASE /* physical address of OneNAND at CS0*/
90 #define CFG_NS16550_SERIAL
91 #define CFG_NS16550_REG_SIZE (-4)
92 #define CFG_NS16550_CLK (48000000)
93 #define CFG_NS16550_COM1 OMAP34XX_UART1
96 * select serial console configuration
98 #define CONFIG_SERIAL1 1 /* UART1 on OMAP3EVM */
99 #define CONFIG_CONS_INDEX 1
101 #define CONFIG_BAUDRATE 115200
102 #define CFG_PBSIZE 256
104 #endif /* CFG_PRINTF */
107 * Miscellaneous configurable options
109 #define CFG_LOADADDR 0x80008000
111 #undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
113 /*-----------------------------------------------------------------------
116 * The stack sizes are set up in start.S using the settings below
118 #define CONFIG_STACKSIZE (128*1024) /* regular stack */
120 /*-----------------------------------------------------------------------
125 #define CFG_NAND_K9F1G08R0A /* Samsung 8-bit 128MB chip large page NAND chip*/
128 /* NAND is partitioned:
129 * 0x00000000 - 0x0007FFFF Booting Image
130 * 0x00080000 - 0x0023FFFF U-Boot Image
131 * 0x00240000 - 0x0027FFFF U-Boot Env Data (X-loader doesn't care)
132 * 0x00280000 - 0x0077FFFF Kernel Image
133 * 0x00780000 - 0x08000000 depends on application
135 #define NAND_UBOOT_START 0x0080000 /* Leaving first 4 blocks for x-load */
136 #define NAND_UBOOT_END 0x0240000 /* Giving a space of 2 blocks = 256KB */
137 #define NAND_BLOCK_SIZE 0x20000
139 #define GPMC_CONFIG (OMAP34XX_GPMC_BASE+0x50)
140 #define GPMC_NAND_COMMAND_0 (OMAP34XX_GPMC_BASE+0x7C)
141 #define GPMC_NAND_ADDRESS_0 (OMAP34XX_GPMC_BASE+0x80)
142 #define GPMC_NAND_DATA_0 (OMAP34XX_GPMC_BASE+0x84)
145 #define WRITE_NAND_COMMAND(d, adr) \
146 do {*(volatile u16 *)GPMC_NAND_COMMAND_0 = d;} while(0)
147 #define WRITE_NAND_ADDRESS(d, adr) \
148 do {*(volatile u16 *)GPMC_NAND_ADDRESS_0 = d;} while(0)
149 #define WRITE_NAND(d, adr) \
150 do {*(volatile u16 *)GPMC_NAND_DATA_0 = d;} while(0)
151 #define READ_NAND(adr) \
152 (*(volatile u16 *)GPMC_NAND_DATA_0)
153 #define NAND_WAIT_READY()
154 #define NAND_WP_OFF() \
155 do {*(volatile u32 *)(GPMC_CONFIG) |= 0x00000010;} while(0)
156 #define NAND_WP_ON() \
157 do {*(volatile u32 *)(GPMC_CONFIG) &= ~0x00000010;} while(0)
159 #else /* to support 8-bit NAND devices */
160 #define WRITE_NAND_COMMAND(d, adr) \
161 do {*(volatile u8 *)GPMC_NAND_COMMAND_0 = d;} while(0)
162 #define WRITE_NAND_ADDRESS(d, adr) \
163 do {*(volatile u8 *)GPMC_NAND_ADDRESS_0 = d;} while(0)
164 #define WRITE_NAND(d, adr) \
165 do {*(volatile u8 *)GPMC_NAND_DATA_0 = d;} while(0)
166 #define READ_NAND(adr) \
167 (*(volatile u8 *)GPMC_NAND_DATA_0);
168 #define NAND_WAIT_READY()
169 #define NAND_WP_OFF() \
170 do {*(volatile u32 *)(GPMC_CONFIG) |= 0x00000010;} while(0)
171 #define NAND_WP_ON() \
172 do {*(volatile u32 *)(GPMC_CONFIG) &= ~0x00000010;} while(0)
176 #define NAND_CTL_CLRALE(adr)
177 #define NAND_CTL_SETALE(adr)
178 #define NAND_CTL_CLRCLE(adr)
179 #define NAND_CTL_SETCLE(adr)
180 #define NAND_DISABLE_CE()
181 #define NAND_ENABLE_CE()
183 /*-----------------------------------------------------------------------
184 * Board oneNAND Info.
186 #define CFG_SYNC_BURST_READ 1
188 /* OneNAND is partitioned:
189 * 0x0000000 - 0x0080000 X-Loader
190 * 0x0080000 - 0x0240000 U-boot Image
191 * 0x0240000 - 0x0280000 U-Boot Env Data (X-loader doesn't care)
192 * 0x0280000 - 0x0780000 Kernel Image
193 * 0x0780000 - 0x8000000 depends on application
196 #define ONENAND_START_BLOCK 4
197 #define ONENAND_END_BLOCK 18
198 #define ONENAND_PAGE_SIZE 2048 /* 2KB */
199 #define ONENAND_BLOCK_SIZE 0x20000 /* 128KB */
201 #endif /* __CONFIG_H */