3 * Texas Instruments <www.ti.com>
4 * Richard Woodruff <r-woodruff2@ti.com>
6 * X-Loader Configuation settings for the TI OMAP SDP3430 board.
8 * See file CREDITS for list of people who contributed to this
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
30 /* serial printf facility takes about 3.5K */
35 * High Level Configuration Options
37 #define CONFIG_ARMCORTEXA8 1 /* This is an ARM V7 CPU core */
38 #define CONFIG_OMAP 1 /* in a TI OMAP core */
39 #define CONFIG_OMAP34XX 1 /* which is a 34XX */
40 #define CONFIG_OMAP3430 1 /* which is in a 3430 */
41 #define CONFIG_3430SDP 1 /* working with SDP */
42 //#define CONFIG_3430_AS_3410 1 /* true for 3430 in 3410 mode */
44 /* Enable the below macro if MMC boot support is required */
45 //#define CONFIG_MMC 1
46 #if defined(CONFIG_MMC)
51 #include <asm/arch/cpu.h> /* get chip and board defs */
53 /* uncomment it if you need timer based udelay(). it takes about 250 bytes */
57 #define V_OSCK 19200000 /* Clock output from T2 */
59 #if (V_OSCK > 19200000)
60 #define V_SCLK (V_OSCK >> 1)
65 //#define PRCM_CLK_CFG2_266MHZ 1 /* VDD2=1.15v - 133MHz DDR */
66 #define PRCM_CLK_CFG2_332MHZ 1 /* VDD2=1.15v - 166MHz DDR */
67 #define PRCM_PCLK_OPP2 1 /* ARM=381MHz - VDD1=1.20v */
70 #define CFG_3430SDRAM_DDR 1
72 /* The actual register values are defined in u-boot- mem.h */
73 /* SDRAM Bank Allocation method */
74 //#define SDRC_B_R_C 1
75 //#define SDRC_B1_R_B0_C 1
80 //#define CFG_ONENAND 1
82 # define NAND_BASE_ADR NAND_BASE /* NAND flash */
83 # define ONENAND_BASE ONENAND_MAP /* OneNand flash */
86 #define OMAP34XX_GPMC_CS0_SIZE GPMC_SIZE_128M
87 #define OMAP34XX_GPMC_CS0_MAP NAND_BASE_ADR
89 #define OMAP34XX_GPMC_CS0_SIZE GPMC_SIZE_128M
90 #define OMAP34XX_GPMC_CS0_MAP ONENAND_BASE
91 #define ONENAND_ADDR ONENAND_BASE /* physical address of OneNAND at CS0*/
97 #define CFG_NS16550_SERIAL
98 #define CFG_NS16550_REG_SIZE (-4)
99 #define CFG_NS16550_CLK (48000000)
100 #define CFG_NS16550_COM1 OMAP34XX_UART1
103 * select serial console configuration
105 #define CONFIG_SERIAL1 1 /* UART1 on 3430SDP */
106 #define CONFIG_CONS_INDEX 1
108 #define CONFIG_BAUDRATE 115200
109 #define CFG_PBSIZE 256
111 #endif /* CFG_PRINTF */
114 * Miscellaneous configurable options
116 #define CFG_LOADADDR 0x80008000
118 #undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
120 /*-----------------------------------------------------------------------
123 * The stack sizes are set up in start.S using the settings below
125 #define CONFIG_STACKSIZE (128*1024) /* regular stack */
129 /*-----------------------------------------------------------------------
134 #define CFG_NAND_K9F1G08R0A /* Samsung 8-bit 128MB chip large page NAND chip*/
137 /* NAND is partitioned:
138 * 0x00000000 - 0x0007FFFF Booting Image
139 * 0x00080000 - 0x000BFFFF U-Boot Image
140 * 0x000C0000 - 0x000FFFFF U-Boot Env Data (X-loader doesn't care)
141 * 0x00100000 - 0x002FFFFF Kernel Image
142 * 0x00300000 - 0x08000000 depends on application
144 #define NAND_UBOOT_START 0x0080000 /* Leaving first 4 blocks for x-load */
145 #define NAND_UBOOT_END 0x00C0000 /* Giving a space of 2 blocks = 256KB */
146 #define NAND_BLOCK_SIZE 0x20000
148 #define GPMC_CONFIG (OMAP34XX_GPMC_BASE+0x50)
149 #define GPMC_NAND_COMMAND_0 (OMAP34XX_GPMC_BASE+0x7C)
150 #define GPMC_NAND_ADDRESS_0 (OMAP34XX_GPMC_BASE+0x80)
151 #define GPMC_NAND_DATA_0 (OMAP34XX_GPMC_BASE+0x84)
154 #define WRITE_NAND_COMMAND(d, adr) \
155 do {*(volatile u16 *)GPMC_NAND_COMMAND_0 = d;} while(0)
156 #define WRITE_NAND_ADDRESS(d, adr) \
157 do {*(volatile u16 *)GPMC_NAND_ADDRESS_0 = d;} while(0)
158 #define WRITE_NAND(d, adr) \
159 do {*(volatile u16 *)GPMC_NAND_DATA_0 = d;} while(0)
160 #define READ_NAND(adr) \
161 (*(volatile u16 *)GPMC_NAND_DATA_0)
162 #define NAND_WAIT_READY()
163 #define NAND_WP_OFF() \
164 do {*(volatile u32 *)(GPMC_CONFIG) |= 0x00000010;} while(0)
165 #define NAND_WP_ON() \
166 do {*(volatile u32 *)(GPMC_CONFIG) &= ~0x00000010;} while(0)
168 #else /* to support 8-bit NAND devices */
169 #define WRITE_NAND_COMMAND(d, adr) \
170 do {*(volatile u8 *)GPMC_NAND_COMMAND_0 = d;} while(0)
171 #define WRITE_NAND_ADDRESS(d, adr) \
172 do {*(volatile u8 *)GPMC_NAND_ADDRESS_0 = d;} while(0)
173 #define WRITE_NAND(d, adr) \
174 do {*(volatile u8 *)GPMC_NAND_DATA_0 = d;} while(0)
175 #define READ_NAND(adr) \
176 (*(volatile u8 *)GPMC_NAND_DATA_0);
177 #define NAND_WAIT_READY()
178 #define NAND_WP_OFF() \
179 do {*(volatile u32 *)(GPMC_CONFIG) |= 0x00000010;} while(0)
180 #define NAND_WP_ON() \
181 do {*(volatile u32 *)(GPMC_CONFIG) &= ~0x00000010;} while(0)
185 #define NAND_CTL_CLRALE(adr)
186 #define NAND_CTL_SETALE(adr)
187 #define NAND_CTL_CLRCLE(adr)
188 #define NAND_CTL_SETCLE(adr)
189 #define NAND_DISABLE_CE()
190 #define NAND_ENABLE_CE()
193 /*-----------------------------------------------------------------------
194 * Board oneNAND Info.
196 #define CFG_SYNC_BURST_READ 1
198 /* OneNAND is partitioned:
199 * 0x0000000 - 0x0080000 X-Loader
200 * 0x0080000 - 0x00c0000 U-boot Image
201 * 0x00c0000 - 0x00e0000 U-Boot Env Data (X-loader doesn't care)
202 * 0x00e0000 - 0x0120000 Kernel Image
203 * 0x0120000 - 0x4000000 depends on application
206 #define ONENAND_START_BLOCK 4
207 #define ONENAND_END_BLOCK 6
208 #define ONENAND_PAGE_SIZE 2048 /* 2KB */
209 #define ONENAND_BLOCK_SIZE 0x20000 /* 128KB */
212 #endif /* __CONFIG_H */