2 * Copyright (C) 2004 - 2005 Texas Instruments.
4 * X-Loader Configuation settings for the TI OMAP H4 board.
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 /* serial printf facility takes about 3.5K */
32 /* uncomment it if you need timer based udelay(). it takes about 250 bytes */
36 * High Level Configuration Options
38 #define CONFIG_ARM1136 1 /* This is an arm1136 CPU core */
39 #define CONFIG_OMAP 1 /* in a TI OMAP core */
40 #define CONFIG_OMAP2420 1 /* which is in a 2420 */
41 #define CONFIG_OMAP2420H4 1 /* and on a H4 board */
43 #define CONFIG_OMAP242X
45 #define PRCM_CONFIG_II 1
46 //#define PRCM_CONFIG_III 1
47 #define CONFIG_PARTIAL_SRAM 1
49 //#define CFG_SDRAM_DDR 1
50 #define CFG_SDRAM_COMBO 2
51 //#define CFG_SDRAM_SDR 3
52 //#define CFG_SDRAM_STACKED 4
54 /* Chipselect and NAND information :
55 Since we share the mem.h from u-boot, we define few macros here
56 so as to pick the right gpmc values from there for the macros in mem.h
58 /* NAND fixed at CS5 */
59 #define OMAP24XX_GPMC_CS0 SMNAND
60 #define OMAP24XX_GPMC_CS0_SIZE GPMC_SIZE_64M
61 #define OMAP24XX_GPMC_CS0_MAP CFG_FLASH_BASE
65 #include <asm/arch/omap2420.h> /* get chip and board defs */
67 #define V_SCLK 12000000
68 /* input clock of PLL */
69 /* the OMAP2420 H4 has 12MHz, 13MHz, or 19.2Mhz crystal input */
70 #define CONFIG_SYS_CLK_FREQ V_SCLK
75 #define CFG_NS16550_SERIAL
76 #define CFG_NS16550_REG_SIZE (-4)
77 #define CFG_NS16550_CLK (48000000) /* can be 12M/32Khz or 48Mhz */
78 #define CFG_NS16550_COM1 OMAP2420_UART1
81 * select serial console configuration
83 #define CONFIG_SERIAL1 1 /* UART1 on H4 */
85 #define CONFIG_CONS_INDEX 1
86 #define CONFIG_BAUDRATE 115200
87 #define CFG_PBSIZE 256
89 #endif /* CFG_PRINTF */
92 * Miscellaneous configurable options
94 #define CFG_LOADADDR 0x80000000
96 #undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
98 /*-----------------------------------------------------------------------
101 * The stack sizes are set up in start.S using the settings below
103 #define CONFIG_STACKSIZE (128*1024) /* regular stack */
105 /*-----------------------------------------------------------------------
108 #define CFG_NAND_K9K1216 /* Samsung 16-bit 64MB chip */
110 #define NAND_ADDR 0x04000000 /* physical address to access nand at CS0*/
112 /* H4 NAND is partitioned:
113 * 0x0000000 - 0x0010000 Booting Image
114 * 0x0010000 - 0x0050000 U-Boot Image
115 * 0x0050000 - 0x0080000 U-Boot Env Data (X-loader doesn't care)
116 * 0x0080000 - 0x4000000 depends on application
118 #define NAND_UBOOT_START 0x0040000
119 #define NAND_UBOOT_END 0x0080000
120 #define NAND_BLOCK_SIZE 0x4000
122 #define WRITE_NAND_COMMAND(d, adr) do {*(volatile u16 *)0x6800A07C = d;} while(0)
123 #define WRITE_NAND_ADDRESS(d, adr) do {*(volatile u16 *)0x6800A080 = d;} while(0)
124 #define WRITE_NAND(d, adr) do {*(volatile u16 *)0x6800A084 = d;} while(0)
125 #define READ_NAND(adr) (*(volatile u16 *)0x6800A084)
127 #define NAND_WAIT_READY()
129 #define NAND_WP_OFF() do {*(volatile u32 *)(0x6800A050) |= 0x00000010;} while(0)
130 #define NAND_WP_ON() do {*(volatile u32 *)(0x6800A050) &= ~0x00000010;} while(0)
132 #define NAND_CTL_CLRALE(adr)
133 #define NAND_CTL_SETALE(adr)
134 #define NAND_CTL_CLRCLE(adr)
135 #define NAND_CTL_SETCLE(adr)
136 #define NAND_DISABLE_CE()
137 #define NAND_ENABLE_CE()
140 #endif /* __CONFIG_H */