include/asm/arch-omap4/omap4430.h

   1 /*
   2  * (C) Copyright 2006-2009
   3  * Texas Instruments, <www.ti.com>
   4  * Richard Woodruff <r-woodruff2@ti.com>
   5  * Syed Mohammed Khasim <x0khasim@ti.com>
   6  *
   7  * See file CREDITS for list of people who contributed to this
   8  * project.
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License
  12  * version 2 as published by the Free Software Foundation.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24
  25 #ifndef _OMAP4430_SYS_H_
  26 #define _OMAP4430_SYS_H_
  27
  28 #include <asm/arch/sizes.h>
  29
  30 /*
  31  * 4430 specific Section
  32  */
  33
  34 /* Stuff on L3 Interconnect */
  35 #define SMX_APE_BASE                    0x68000000
  36
  37 /* L3 Firewall */
  38 #define A_REQINFOPERM0          (SMX_APE_BASE + 0x05048)
  39 #define A_READPERM0             (SMX_APE_BASE + 0x05050)
  40 #define A_WRITEPERM0            (SMX_APE_BASE + 0x05058)
  41
  42 /* GPMC */
  43 #define OMAP44XX_GPMC_BASE              (0x50000000)
  44
  45 /* DMM */
  46 #define OMAP44XX_DMM_BASE               0x4E000000
  47
  48 /* SMS */
  49 #define OMAP44XX_SMS_BASE               0x6C000000
  50
  51 /* SDRC */
  52 #define OMAP44XX_SDRC_BASE              0x6D000000
  53
  54
  55 /*
  56  * L4 Peripherals - L4 Wakeup and L4 Core now
  57  */
  58 #define OMAP44XX_CORE_L4_IO_BASE        0x4A000000
  59
  60 #define OMAP44XX_WAKEUP_L4_IO_BASE      0x4A300000
  61
  62 #define OMAP44XX_L4_PER                 0x48000000
  63
  64 #define OMAP44XX_L4_IO_BASE             OMAP44XX_CORE_L4_IO_BASE
  65
  66 /* CONTROL */
  67 #define OMAP44XX_CTRL_GEN_CORE_BASE     (OMAP44XX_L4_IO_BASE+0x2000)
  68 #define OMAP44XX_CTRL_ID_CODE           (OMAP44XX_CTRL_GEN_CORE_BASE + 0x204)
  69
  70 #define OMAP44XX_CTRL_BASE              0x4a100000
  71
  72 /* TAP information  dont know for 3430*/
  73 #define OMAP44XX_TAP_BASE       (0x49000000) /*giving some junk for virtio */
  74
  75 /* UART */
  76 #define OMAP44XX_UART1                  (OMAP44XX_L4_PER+0x6a000)
  77 #define OMAP44XX_UART2                  (OMAP44XX_L4_PER+0x6c000)
  78 #define OMAP44XX_UART3                  (OMAP44XX_L4_PER+0x20000)
  79
  80 /* General Purpose Timers */
  81 #define OMAP44XX_GPT1                   0x48318000
  82 #define OMAP44XX_GPT2                   0x48032000
  83 #define OMAP44XX_GPT3                   0x48034000
  84 #define OMAP44XX_GPT4                   0x48036000
  85 #define OMAP44XX_GPT5                   0x40138000
  86 #define OMAP44XX_GPT6                   0x4013A000
  87 #define OMAP44XX_GPT7                   0x4013C000
  88 #define OMAP44XX_GPT8                   0x4013E000
  89 #define OMAP44XX_GPT9                   0x48040000
  90 #define OMAP44XX_GPT10                  0x48086000
  91 #define OMAP44XX_GPT11                  0x48088000
  92 #define OMAP44XX_GPT12                  0x48304000
  93
  94 /* WatchDog Timers (1 secure, 3 GP) */
  95 #define WD1_BASE                        (0x4A322000)
  96 #define WD2_BASE                        (0x4A314000)
  97 #define WD3_BASE                        (0x40130000)
  98
  99 /* 32KTIMER */
 100 #define SYNC_32KTIMER_BASE              (0x48320000)
 101 #define S32K_CR                         (SYNC_32KTIMER_BASE+0x10)
 102
 103 /*
 104  * SDP4430 specific Section
 105  */
 106
 107 /*
 108  *  The 443x's chip selects are programmable.  The mask ROM
 109  *  does configure CS0 to 0x08000000 before dispatch.  So, if
 110  *  you want your code to live below that address, you have to
 111  *  be prepared to jump though hoops, to reset the base address.
 112  *  Same as in SDP4430
 113  */
 114 #ifdef CONFIG_OMAP44XX
 115 /* base address for indirect vectors (internal boot mode) */
 116 #define SRAM_OFFSET0                    0x40000000
 117 #define SRAM_OFFSET1                    0x00300000
 118 #define SRAM_OFFSET2                    0x0000D000
 119 #define SRAM_OFFSET3                    0x00000800
 120 #define SRAM_VECT_CODE                  (SRAM_OFFSET0|SRAM_OFFSET1|SRAM_OFFSET2|SRAM_OFFSET3)
 121 #define LOW_LEVEL_SRAM_STACK            0x4030DFFC
 122 #endif
 123
 124 #if defined(CONFIG_4430SDP)
 125 /* FPGA on Debug board.*/
 126 # define ETH_CONTROL_REG                        (DEBUG_BASE+0x30b)
 127 # define LAN_RESET_REGISTER             (DEBUG_BASE+0x1c)
 128
 129 # define DIP_SWITCH_INPUT_REG2          (DEBUG_BASE+0x60)
 130 # define LED_REGISTER                   (DEBUG_BASE+0x40)
 131 # define FPGA_REV_REGISTER              (DEBUG_BASE+0x10)
 132 # define EEPROM_MAIN_BRD                        (DEBUG_BASE+0x10000+0x1800)
 133 # define EEPROM_CONN_BRD                        (DEBUG_BASE+0x10000+0x1900)
 134 # define EEPROM_UI_BRD                  (DEBUG_BASE+0x10000+0x1A00)
 135 # define EEPROM_MCAM_BRD                        (DEBUG_BASE+0x10000+0x1B00)
 136 # define ENHANCED_UI_EE_NAME            "750-2075"
 137 #endif
 138
 139 #endif  /* _OMAP4430_SYS_H_ */