include/asm/arch-omap4/omap4430.h

   1 /*
   2  * (C) Copyright 2006-2009
   3  * Texas Instruments, <www.ti.com>
   4  * Richard Woodruff <r-woodruff2@ti.com>
   5  * Syed Mohammed Khasim <x0khasim@ti.com>
   6  *
   7  * See file CREDITS for list of people who contributed to this
   8  * project.
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License
  12  * version 2 as published by the Free Software Foundation.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24
  25 #ifndef _OMAP4430_SYS_H_
  26 #define _OMAP4430_SYS_H_
  27
  28 #include <asm/arch/sizes.h>
  29
  30 /*
  31  * 4430 specific Section
  32  */
  33
  34 /* Stuff on L3 Interconnect */
  35 #define SMX_APE_BASE                    0x68000000
  36
  37 /* L3 Firewall */
  38 #define A_REQINFOPERM0          (SMX_APE_BASE + 0x05048)
  39 #define A_READPERM0             (SMX_APE_BASE + 0x05050)
  40 #define A_WRITEPERM0            (SMX_APE_BASE + 0x05058)
  41
  42 /* GPMC */
  43 #define OMAP44XX_GPMC_BASE              (0x50000000)
  44
  45 /* DMM */
  46 #define OMAP44XX_DMM_BASE               0x4E000000
  47
  48 /* SMS */
  49 #define OMAP44XX_SMS_BASE               0x6C000000
  50
  51 /* SDRC */
  52 #define OMAP44XX_SDRC_BASE              0x6D000000
  53
  54
  55 /*
  56  * L4 Peripherals - L4 Wakeup and L4 Core now
  57  */
  58 #define OMAP44XX_CORE_L4_IO_BASE        0x4A000000
  59
  60 #define OMAP44XX_WAKEUP_L4_IO_BASE      0x4A300000
  61
  62 #define OMAP44XX_L4_PER                 0x48000000
  63
  64 #define OMAP44XX_L4_IO_BASE             OMAP44XX_CORE_L4_IO_BASE
  65
  66 /* CONTROL */
  67 #define OMAP44XX_CTRL_GEN_CORE_BASE     (OMAP44XX_L4_IO_BASE+0x2000)
  68 #define OMAP44XX_CTRL_ID_CODE           (OMAP44XX_CTRL_GEN_CORE_BASE + 0x204)
  69
  70 #define OMAP44XX_CTRL_BASE              0x4a100000
  71 #define OMAP44XX_WKUP_CTRL_BASE         0x4A31E000
  72
  73 /* DDR */
  74 #define OMAP44XX_CONTROL_LPDDR2IO1_0    (OMAP44XX_CTRL_BASE + 0x638)
  75 #define OMAP44XX_CONTROL_LPDDR2IO1_1    (OMAP44XX_CTRL_BASE + 0x63c)
  76 #define OMAP44XX_CONTROL_LPDDR2IO1_2    (OMAP44XX_CTRL_BASE + 0x640)
  77 #define OMAP44XX_CONTROL_LPDDR2IO1_3    (OMAP44XX_CTRL_BASE + 0x644)
  78 #define OMAP44XX_CONTROL_LPDDR2IO2_0    (OMAP44XX_CTRL_BASE + 0x648)
  79 #define OMAP44XX_CONTROL_LPDDR2IO2_1    (OMAP44XX_CTRL_BASE + 0x64c)
  80 #define OMAP44XX_CONTROL_LPDDR2IO2_2    (OMAP44XX_CTRL_BASE + 0x650)
  81 #define OMAP44XX_CONTROL_LPDDR2IO2_3    (OMAP44XX_CTRL_BASE + 0x654)
  82
  83 /* eFUSE */
  84 #define OMAP44XX_CONTROL_EFUSE_1        (OMAP44XX_CTRL_BASE + 0x700)
  85 #define OMAP44XX_CONTROL_EFUSE_2        (OMAP44XX_CTRL_BASE + 0x704)
  86 #define OMAP44XX_CONTROL_EFUSE_3        (OMAP44XX_CTRL_BASE + 0x708)
  87 #define OMAP44XX_CONTROL_EFUSE_4        (OMAP44XX_CTRL_BASE + 0x70c)
  88
  89 /* PRM */
  90 #define OMAP44XX_PRM_VC_VAL_BYPASS      (OMAP44XX_WAKEUP_L4_IO_BASE + 0x7ba0)
  91 #define OMAP44XX_PRM_VC_CFG_I2C_MODE    (OMAP44XX_WAKEUP_L4_IO_BASE + 0x7ba8)
  92 #define OMAP44XX_PRM_VC_CFG_I2C_CLK     (OMAP44XX_WAKEUP_L4_IO_BASE + 0x7bac)
  93
  94 /* IRQ */
  95 #define OMAP44XX_PRM_IRQSTATUS_MPU_A9   (OMAP44XX_WAKEUP_L4_IO_BASE + 0x6010)
  96
  97
  98
  99 /* TAP information  dont know for 3430*/
 100 #define OMAP44XX_TAP_BASE       (0x49000000) /*giving some junk for virtio */
 101
 102 /* UART */
 103 #define OMAP44XX_UART1                  (OMAP44XX_L4_PER+0x6a000)
 104 #define OMAP44XX_UART2                  (OMAP44XX_L4_PER+0x6c000)
 105 #define OMAP44XX_UART3                  (OMAP44XX_L4_PER+0x20000)
 106
 107 /* General Purpose Timers */
 108 #define OMAP44XX_GPT1                   0x48318000
 109 #define OMAP44XX_GPT2                   0x48032000
 110 #define OMAP44XX_GPT3                   0x48034000
 111 #define OMAP44XX_GPT4                   0x48036000
 112 #define OMAP44XX_GPT5                   0x40138000
 113 #define OMAP44XX_GPT6                   0x4013A000
 114 #define OMAP44XX_GPT7                   0x4013C000
 115 #define OMAP44XX_GPT8                   0x4013E000
 116 #define OMAP44XX_GPT9                   0x48040000
 117 #define OMAP44XX_GPT10                  0x48086000
 118 #define OMAP44XX_GPT11                  0x48088000
 119 #define OMAP44XX_GPT12                  0x48304000
 120
 121 /* WatchDog Timers (1 secure, 3 GP) */
 122 #define WD1_BASE                        (0x4A322000)
 123 #define WD2_BASE                        (0x4A314000)
 124 #define WD3_BASE                        (0x40130000)
 125
 126 /* GPIO banks */
 127 #define OMAP44XX_GPIO_BASE1             0x4a310000
 128 #define OMAP44XX_GPIO_BASE2             0x48055000
 129
 130 #define OMAP44XX_GPIO_BASE6             0x4805D000
 131
 132 /*      common GPIO offsets */
 133
 134 #define __GPIO_REVISION                 0
 135 #define __GPIO_SYSCONFIG                0x10
 136 #define __GPIO_IRQSTATUS_RAW_0          0x24
 137 #define __GPIO_IRQSTATUS_RAW_1          0x28
 138 #define __GPIO_IRQSTATUS_0              0x2c
 139 #define __GPIO_IRQSTATUS_1              0x30
 140 #define __GPIO_IRQSTATUS_SET_0          0x34
 141 #define __GPIO_IRQSTATUS_SET_1          0x38
 142 #define __GPIO_IRQSTATUS_CLR_0          0x3c
 143 #define __GPIO_IRQSTATUS_CLR_1          0x40
 144 #define __GPIO_IRQWAKEN_0               0x44
 145 #define __GPIO_IRQWAKEN_1               0x48
 146 #define __GPIO_SYSSTATUS                0x114
 147 #define __GPIO_IRQSTATUS1               0x118
 148 #define __GPIO_CTRL                     0x130
 149 #define __GPIO_OE                       0x134
 150 #define __GPIO_DATAIN                   0x138
 151 #define __GPIO_DATAOUT                  0x13c
 152
 153 /* SCRM */
 154
 155 #define OMAP44XX_SCRM_BASE              0x4a30a000
 156
 157 #define OMAP44XX_SCRM_ALTCLKSRC         (OMAP44XX_SCRM_BASE + 0x110)
 158 #define OMAP44XX_SCRM_AUXCLK1           (OMAP44XX_SCRM_BASE + 0x314)
 159 #define OMAP44XX_SCRM_AUXCLK3           (OMAP44XX_SCRM_BASE + 0x31c)
 160
 161
 162 /* 32KTIMER */
 163 #define SYNC_32KTIMER_BASE              (0x48320000)
 164 #define S32K_CR                         (SYNC_32KTIMER_BASE+0x10)
 165
 166 /*
 167  * SDP4430 specific Section
 168  */
 169
 170 /*
 171  *  The 443x's chip selects are programmable.  The mask ROM
 172  *  does configure CS0 to 0x08000000 before dispatch.  So, if
 173  *  you want your code to live below that address, you have to
 174  *  be prepared to jump though hoops, to reset the base address.
 175  *  Same as in SDP4430
 176  */
 177 #ifdef CONFIG_OMAP44XX
 178 /* base address for indirect vectors (internal boot mode) */
 179 #define SRAM_OFFSET0                    0x40000000
 180 #define SRAM_OFFSET1                    0x00300000
 181 #define SRAM_OFFSET2                    0x0000D000
 182 #define SRAM_OFFSET3                    0x00000800
 183 #define SRAM_VECT_CODE                  (SRAM_OFFSET0|SRAM_OFFSET1|SRAM_OFFSET2|SRAM_OFFSET3)
 184 #define LOW_LEVEL_SRAM_STACK            0x4030DFFC
 185 #endif
 186
 187 #if defined(CONFIG_4430SDP)
 188 /* FPGA on Debug board.*/
 189 # define ETH_CONTROL_REG                        (DEBUG_BASE+0x30b)
 190 # define LAN_RESET_REGISTER             (DEBUG_BASE+0x1c)
 191
 192 # define DIP_SWITCH_INPUT_REG2          (DEBUG_BASE+0x60)
 193 # define LED_REGISTER                   (DEBUG_BASE+0x40)
 194 # define FPGA_REV_REGISTER              (DEBUG_BASE+0x10)
 195 # define EEPROM_MAIN_BRD                        (DEBUG_BASE+0x10000+0x1800)
 196 # define EEPROM_CONN_BRD                        (DEBUG_BASE+0x10000+0x1900)
 197 # define EEPROM_UI_BRD                  (DEBUG_BASE+0x10000+0x1A00)
 198 # define EEPROM_MCAM_BRD                        (DEBUG_BASE+0x10000+0x1B00)
 199 # define ENHANCED_UI_EE_NAME            "750-2075"
 200 #endif
 201
 202 #endif  /* _OMAP4430_SYS_H_ */