include/asm/arch-omap4/cpu.h

   1 /*
   2  * (C) Copyright 2006-2009
   3  * Texas Instruments, <www.ti.com>
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License
  10  * version 2 as published by the Free Software Foundation.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  *
  22  */
  23
  24 #ifndef _OMAP44XX_CPU_H
  25 #define  _OMAP44XX_CPU_H
  26 #include <asm/arch/omap4430.h>
  27
  28 /* Register offsets of common modules */
  29 /* Control */
  30 #define CONTROL_STATUS                  (OMAP44XX_CTRL_BASE + 0x2F0)
  31 #define OMAP44XX_MCR                    (OMAP44XX_CTRL_BASE + 0x8C)
  32 #define CONTROL_SCALABLE_OMAP_STATUS    (OMAP44XX_CTRL_BASE + 0x44C)
  33 #define CONTROL_SCALABLE_OMAP_OCP       (OMAP44XX_CTRL_BASE + 0x534)
  34
  35
  36 /* Tap Information */
  37 #define TAP_IDCODE_REG          (OMAP44XX_TAP_BASE+0x204)
  38 #define PRODUCTION_ID           (OMAP44XX_TAP_BASE+0x208)
  39
  40 /* device type */
  41 #define DEVICE_MASK             (BIT8|BIT9|BIT10)
  42 #define TST_DEVICE              0x0
  43 #define EMU_DEVICE              0x1
  44 #define HS_DEVICE               0x2
  45 #define GP_DEVICE               0x3
  46
  47 /* GPMC CS3/cs4/cs6 not avaliable */
  48 #define GPMC_BASE               (OMAP44XX_GPMC_BASE)
  49 #define GPMC_SYSCONFIG          (OMAP44XX_GPMC_BASE+0x10)
  50 #define GPMC_IRQSTATUS          (OMAP44XX_GPMC_BASE+0x18)
  51 #define GPMC_IRQENABLE          (OMAP44XX_GPMC_BASE+0x1C)
  52 #define GPMC_TIMEOUT_CONTROL    (OMAP44XX_GPMC_BASE+0x40)
  53 #define GPMC_CONFIG             (OMAP44XX_GPMC_BASE+0x50)
  54 #define GPMC_STATUS             (OMAP44XX_GPMC_BASE+0x54)
  55
  56 #define GPMC_CONFIG_CS0         (OMAP44XX_GPMC_BASE+0x60)
  57 #define GPMC_CONFIG_WIDTH       (0x30)
  58
  59 #define GPMC_CONFIG1            (0x00)
  60 #define GPMC_CONFIG2            (0x04)
  61 #define GPMC_CONFIG3            (0x08)
  62 #define GPMC_CONFIG4            (0x0C)
  63 #define GPMC_CONFIG5            (0x10)
  64 #define GPMC_CONFIG6            (0x14)
  65 #define GPMC_CONFIG7            (0x18)
  66 #define GPMC_NAND_CMD           (0x1C)
  67 #define GPMC_NAND_ADR           (0x20)
  68 #define GPMC_NAND_DAT           (0x24)
  69
  70 #define GPMC_ECC_CONFIG         (0x1F4)
  71 #define GPMC_ECC_CONTROL        (0x1F8)
  72 #define GPMC_ECC_SIZE_CONFIG    (0x1FC)
  73 #define GPMC_ECC1_RESULT        (0x200)
  74 #define GPMC_ECC2_RESULT        (0x204)
  75 #define GPMC_ECC3_RESULT        (0x208)
  76 #define GPMC_ECC4_RESULT        (0x20C)
  77 #define GPMC_ECC5_RESULT        (0x210)
  78 #define GPMC_ECC6_RESULT        (0x214)
  79 #define GPMC_ECC7_RESULT        (0x218)
  80 #define GPMC_ECC8_RESULT        (0x21C)
  81 #define GPMC_ECC9_RESULT        (0x220)
  82
  83 #define GPMC_PREFETCH_CONFIG1   (0x1e0)
  84 #define GPMC_PREFETCH_CONFIG2   (0x1e4)
  85 #define GPMC_PREFETCH_CONTROL   (0x1ec)
  86 #define GPMC_PREFETCH_STATUS    (0x1f0)
  87
  88 /* GPMC Mapping */
  89 # define FLASH_BASE             0x10000000  /* NOR flash (aligned to 256 Meg) */
  90 # define FLASH_BASE_SDPV1       0x04000000  /* NOR flash (aligned to 64 Meg) */
  91 # define FLASH_BASE_SDPV2       0x10000000  /* NOR flash (aligned to 256 Meg) */
  92 # define DEBUG_BASE             0x08000000  /* debug board */
  93 # define NAND_BASE      0x30000000  /* NAND addr (actual size small port)*/
  94 # define PISMO2_BASE    0x18000000  /* PISMO2 CS1/2 */
  95 # define ONENAND_MAP    0x20000000  /* OneNand addr (actual size small port */
  96
  97 /* DMM */
  98 #define DMM_SYSCONFIG           (OMAP44XX_DMM_BASE+0x10)
  99 #define DMM_LISA_MAP            (OMAP44XX_DMM_BASE+0x100)
 100
 101 /* SMS */
 102 #define SMS_SYSCONFIG           (OMAP44XX_SMS_BASE+0x10)
 103 #define SMS_RG_ATT0             (OMAP44XX_SMS_BASE+0x48)
 104 #define SMS_CLASS_ARB0          (OMAP44XX_SMS_BASE+0xD0)
 105 #define BURSTCOMPLETE_GROUP7    BIT31
 106
 107 #define SDRC_CS_CFG             (OMAP44XX_SDRC_BASE+0x40)
 108 #define OMAP44XX_SDRC_CS0       0x80000000
 109 #define SDRC_POWER              (OMAP44XX_SDRC_BASE+0x70)
 110 #define SDRC_MCFG_0             (OMAP44XX_SDRC_BASE+0x80)
 111 #define SDRC_MR_0               (OMAP44XX_SDRC_BASE+0x84)
 112
 113 /* timer regs offsets (32 bit regs) */
 114 #define TIDR                    0x0      /* r */
 115 #define TIOCP_CFG               0x10     /* rw */
 116 #define TISTAT                  0x14     /* r */
 117 #define TISR                    0x18     /* rw */
 118 #define TIER                    0x1C     /* rw */
 119 #define TWER                    0x20     /* rw */
 120 #define TCLR                    0x24     /* rw */
 121 #define TCRR                    0x28     /* rw */
 122 #define TLDR                    0x2C     /* rw */
 123 #define TTGR                    0x30     /* rw */
 124 #define TWPS                    0x34     /* r */
 125 #define TMAR                    0x38     /* rw */
 126 #define TCAR1                   0x3c     /* r */
 127 #define TSICR                   0x40     /* rw */
 128 #define TCAR2                   0x44     /* r */
 129 #define GPT_EN          ((0<<2)|BIT1|BIT0) /* enable sys_clk NO-prescale /1 */
 130
 131 /* Watchdog */
 132 #define WWPS                    0x34     /* r */
 133 #define WSPR                    0x48     /* rw */
 134 #define WD_UNLOCK1              0xAAAA
 135 #define WD_UNLOCK2              0x5555
 136
 137 /* FIXME */
 138 #define PRM_RSTCTRL                             0x48307250
 139   /* PRCM */
 140 #define CM_SYS_CLKSEL                           0x4a306110
 141
 142 /* PRM.CKGEN module registers */
 143 #define CM_ABE_PLL_REF_CLKSEL           0x4a30610c
 144
 145
 146 /* PRM.WKUP_CM module registers */
 147 #define CM_WKUP_CLKSTCTRL               0x4a307800
 148 #define CM_WKUP_L4WKUP_CLKCTRL          0x4a307820
 149 #define CM_WKUP_WDT1_CLKCTRL            0x4a307828
 150 #define CM_WKUP_WDT2_CLKCTRL            0x4a307830
 151 #define CM_WKUP_GPIO1_CLKCTRL           0x4a307838
 152 #define CM_WKUP_TIMER1_CLKCTRL          0x4a307840
 153 #define CM_WKUP_TIMER12_CLKCTRL         0x4a307848
 154 #define CM_WKUP_SYNCTIMER_CLKCTRL       0x4a307850
 155 #define CM_WKUP_USIM_CLKCTRL            0x4a307858
 156 #define CM_WKUP_SARRAM_CLKCTRL          0x4a307860
 157 #define CM_WKUP_KEYBOARD_CLKCTRL        0x4a307878
 158 #define CM_WKUP_RTC_CLKCTRL             0x4a307880
 159 #define CM_WKUP_BANDGAP_CLKCTRL         0x4a307888
 160
 161 /* CM1.CKGEN module registers */
 162 #define CM_CLKSEL_CORE                          0x4a004100
 163 #define CM_CLKSEL_ABE                           0x4a004108
 164 #define CM_DLL_CTRL                             0x4a004110
 165 #define CM_CLKMODE_DPLL_CORE                    0x4a004120
 166 #define CM_IDLEST_DPLL_CORE                     0x4a004124
 167 #define CM_AUTOIDLE_DPLL_CORE                   0x4a004128
 168 #define CM_CLKSEL_DPLL_CORE                     0x4a00412c
 169 #define CM_DIV_M2_DPLL_CORE                     0x4a004130
 170 #define CM_DIV_M3_DPLL_CORE                     0x4a004134
 171 #define CM_DIV_M4_DPLL_CORE                     0x4a004138
 172 #define CM_DIV_M5_DPLL_CORE                     0x4a00413c
 173 #define CM_DIV_M6_DPLL_CORE                     0x4a004140
 174 #define CM_DIV_M7_DPLL_CORE                     0x4a004144
 175 #define CM_SSC_DELTAMSTEP_DPLL_CORE             0x4a004148
 176 #define CM_SSC_MODFREQDIV_DPLL_CORE             0x4a00414c
 177 #define CM_EMU_OVERRIDE_DPLL_CORE               0x4a004150
 178 #define CM_CLKMODE_DPLL_MPU                     0x4a004160
 179 #define CM_IDLEST_DPLL_MPU                      0x4a004164
 180 #define CM_AUTOIDLE_DPLL_MPU                    0x4a004168
 181 #define CM_CLKSEL_DPLL_MPU                      0x4a00416c
 182 #define CM_DIV_M2_DPLL_MPU                      0x4a004170
 183 #define CM_SSC_DELTAMSTEP_DPLL_MPU              0x4a004188
 184 #define CM_SSC_MODFREQDIV_DPLL_MPU              0x4a00418c
 185 #define CM_BYPCLK_DPLL_MPU                      0x4a00419c
 186 #define CM_CLKMODE_DPLL_IVA                     0x4a0041a0
 187 #define CM_IDLEST_DPLL_IVA                      0x4a0041a4
 188 #define CM_AUTOIDLE_DPLL_IVA                    0x4a0041a8
 189 #define CM_CLKSEL_DPLL_IVA                      0x4a0041ac
 190 #define CM_DIV_M4_DPLL_IVA                      0x4a0041b8
 191 #define CM_DIV_M5_DPLL_IVA                      0x4a0041bc
 192 #define CM_SSC_DELTAMSTEP_DPLL_IVA              0x4a0041c8
 193 #define CM_SSC_MODFREQDIV_DPLL_IVA              0x4a0041cc
 194 #define CM_BYPCLK_DPLL_IVA                      0x4a0041dc
 195 #define CM_CLKMODE_DPLL_ABE                     0x4a0041e0
 196 #define CM_IDLEST_DPLL_ABE                      0x4a0041e4
 197 #define CM_AUTOIDLE_DPLL_ABE                    0x4a0041e8
 198 #define CM_CLKSEL_DPLL_ABE                      0x4a0041ec
 199 #define CM_DIV_M2_DPLL_ABE                      0x4a0041f0
 200 #define CM_DIV_M3_DPLL_ABE                      0x4a0041f4
 201 #define CM_SSC_DELTAMSTEP_DPLL_ABE              0x4a004208
 202 #define CM_SSC_MODFREQDIV_DPLL_ABE              0x4a00420c
 203 #define CM_CLKMODE_DPLL_DDRPHY                  0x4a004220
 204 #define CM_IDLEST_DPLL_DDRPHY                   0x4a004224
 205 #define CM_AUTOIDLE_DPLL_DDRPHY                 0x4a004228
 206 #define CM_CLKSEL_DPLL_DDRPHY                   0x4a00422c
 207 #define CM_DIV_M2_DPLL_DDRPHY                   0x4a004230
 208 #define CM_DIV_M4_DPLL_DDRPHY                   0x4a004238
 209 #define CM_DIV_M5_DPLL_DDRPHY                   0x4a00423c
 210 #define CM_DIV_M6_DPLL_DDRPHY                   0x4a004240
 211 #define CM_SSC_DELTAMSTEP_DPLL_DDRPHY           0x4a004248
 212
 213 /* CM1.ABE register offsets */
 214 #define CM1_ABE_CLKSTCTRL               0x4a004500
 215 #define CM1_ABE_L4ABE_CLKCTRL           0x4a004520
 216 #define CM1_ABE_AESS_CLKCTRL            0x4a004528
 217 #define CM1_ABE_PDM_CLKCTRL             0x4a004530
 218 #define CM1_ABE_DMIC_CLKCTRL            0x4a004538
 219 #define CM1_ABE_MCASP_CLKCTRL           0x4a004540
 220 #define CM1_ABE_MCBSP1_CLKCTRL          0x4a004548
 221 #define CM1_ABE_MCBSP2_CLKCTRL          0x4a004550
 222 #define CM1_ABE_MCBSP3_CLKCTRL          0x4a004558
 223 #define CM1_ABE_SLIMBUS_CLKCTRL         0x4a004560
 224 #define CM1_ABE_TIMER5_CLKCTRL          0x4a004568
 225 #define CM1_ABE_TIMER6_CLKCTRL          0x4a004570
 226 #define CM1_ABE_TIMER7_CLKCTRL          0x4a004578
 227 #define CM1_ABE_TIMER8_CLKCTRL          0x4a004580
 228 #define CM1_ABE_WDT3_CLKCTRL            0x4a004588
 229
 230 /* CM1.DSP register offsets */
 231 #define DSP_CLKSTCTRL                   0x4a004400
 232 #define DSP_DSP_CLKCTRL                 0x4a004420
 233
 234 /* CM2.CKGEN module registers */
 235 #define CM_CLKSEL_DUCATI_ISS_ROOT               0x4a008100
 236 #define CM_CLKSEL_USB_60MHz                     0x4a008104
 237 #define CM_SCALE_FCLK                           0x4a008108
 238 #define CM_CORE_DVFS_PERF1                      0x4a008110
 239 #define CM_CORE_DVFS_PERF2                      0x4a008114
 240 #define CM_CORE_DVFS_PERF3                      0x4a008118
 241 #define CM_CORE_DVFS_PERF4                      0x4a00811c
 242 #define CM_CORE_DVFS_CURRENT                    0x4a008124
 243 #define CM_IVA_DVFS_PERF_TESLA                  0x4a008128
 244 #define CM_IVA_DVFS_PERF_IVAHD                  0x4a00812c
 245 #define CM_IVA_DVFS_PERF_ABE                    0x4a008130
 246 #define CM_IVA_DVFS_CURRENT                     0x4a008138
 247 #define CM_CLKMODE_DPLL_PER                     0x4a008140
 248 #define CM_IDLEST_DPLL_PER                      0x4a008144
 249 #define CM_AUTOIDLE_DPLL_PER                    0x4a008148
 250 #define CM_CLKSEL_DPLL_PER                      0x4a00814c
 251 #define CM_DIV_M2_DPLL_PER                      0x4a008150
 252 #define CM_DIV_M3_DPLL_PER                      0x4a008154
 253 #define CM_DIV_M4_DPLL_PER                      0x4a008158
 254 #define CM_DIV_M5_DPLL_PER                      0x4a00815c
 255 #define CM_DIV_M6_DPLL_PER                      0x4a008160
 256 #define CM_DIV_M7_DPLL_PER                      0x4a008164
 257 #define CM_SSC_DELTAMSTEP_DPLL_PER              0x4a008168
 258 #define CM_SSC_MODFREQDIV_DPLL_PER              0x4a00816c
 259 #define CM_EMU_OVERRIDE_DPLL_PER                0x4a008170
 260 #define CM_CLKMODE_DPLL_USB                     0x4a008180
 261 #define CM_IDLEST_DPLL_USB                      0x4a008184
 262 #define CM_AUTOIDLE_DPLL_USB                    0x4a008188
 263 #define CM_CLKSEL_DPLL_USB                      0x4a00818c
 264 #define CM_DIV_M2_DPLL_USB                      0x4a008190
 265 #define CM_SSC_DELTAMSTEP_DPLL_USB              0x4a0081a8
 266 #define CM_SSC_MODFREQDIV_DPLL_USB              0x4a0081ac
 267 #define CM_CLKDCOLDO_DPLL_USB                   0x4a0081b4
 268 #define CM_CLKMODE_DPLL_UNIPRO                  0x4a0081c0
 269 #define CM_IDLEST_DPLL_UNIPRO                   0x4a0081c4
 270 #define CM_AUTOIDLE_DPLL_UNIPRO                 0x4a0081c8
 271 #define CM_CLKSEL_DPLL_UNIPRO                   0x4a0081cc
 272 #define CM_DIV_M2_DPLL_UNIPRO                   0x4a0081d0
 273 #define CM_SSC_DELTAMSTEP_DPLL_UNIPRO           0x4a0081e8
 274 #define CM_SSC_MODFREQDIV_DPLL_UNIPRO           0x4a0081ec
 275
 276 /* CM2.CORE module registers */
 277 #define CM_L3_1_CLKSTCTRL               0x4a008700
 278 #define CM_L3_1_DYNAMICDEP              0x4a008708
 279 #define CM_L3_1_L3_1_CLKCTRL            0x4a008720
 280 #define CM_L3_2_CLKSTCTRL               0x4a008800
 281 #define CM_L3_2_DYNAMICDEP              0x4a008808
 282 #define CM_L3_2_L3_2_CLKCTRL            0x4a008820
 283 #define CM_L3_2_GPMC_CLKCTRL            0x4a008828
 284 #define CM_L3_2_OCMC_RAM_CLKCTRL        0x4a008830
 285 #define CM_DUCATI_CLKSTCTRL             0x4a008900
 286 #define CM_DUCATI_STATICDEP             0x4a008904
 287 #define CM_DUCATI_DYNAMICDEP            0x4a008908
 288 #define CM_DUCATI_DUCATI_CLKCTRL        0x4a008920
 289 #define CM_SDMA_CLKSTCTRL               0x4a008a00
 290 #define CM_SDMA_STATICDEP               0x4a008a04
 291 #define CM_SDMA_DYNAMICDEP              0x4a008a08
 292 #define CM_SDMA_SDMA_CLKCTRL            0x4a008a20
 293 #define CM_MEMIF_CLKSTCTRL              0x4a008b00
 294 #define CM_MEMIF_DMM_CLKCTRL            0x4a008b20
 295 #define CM_MEMIF_EMIF_FW_CLKCTRL        0x4a008b28
 296 #define CM_MEMIF_EMIF_1_CLKCTRL         0x4a008b30
 297 #define CM_MEMIF_EMIF_2_CLKCTRL         0x4a008b38
 298 #define CM_MEMIF_DLL_CLKCTRL            0x4a008b40
 299 #define CM_MEMIF_EMIF_H1_CLKCTRL        0x4a008b50
 300 #define CM_MEMIF_EMIF_H2_CLKCTRL        0x4a008b58
 301 #define CM_MEMIF_DLL_H_CLKCTRL          0x4a008b60
 302 #define CM_D2D_CLKSTCTRL                0x4a008c00
 303 #define CM_D2D_STATICDEP                0x4a008c04
 304 #define CM_D2D_DYNAMICDEP               0x4a008c08
 305 #define CM_D2D_SAD2D_CLKCTRL            0x4a008c20
 306 #define CM_D2D_MODEM_ICR_CLKCTRL        0x4a008c28
 307 #define CM_D2D_SAD2D_FW_CLKCTRL         0x4a008c30
 308 #define CM_L4CFG_CLKSTCTRL              0x4a008d00
 309 #define CM_L4CFG_DYNAMICDEP             0x4a008d08
 310 #define CM_L4CFG_L4_CFG_CLKCTRL         0x4a008d20
 311 #define CM_L4CFG_HW_SEM_CLKCTRL         0x4a008d28
 312 #define CM_L4CFG_MAILBOX_CLKCTRL        0x4a008d30
 313 #define CM_L4CFG_SAR_ROM_CLKCTRL        0x4a008d38
 314 #define CM_L3INSTR_CLKSTCTRL            0x4a008e00
 315 #define CM_L3INSTR_L3_3_CLKCTRL         0x4a008e20
 316 #define CM_L3INSTR_L3_INSTR_CLKCTRL     0x4a008e28
 317 #define CM_L3INSTR_OCP_WP1_CLKCTRL      0x4a008e40
 318
 319 /* CM2.L4PER register offsets */
 320 #define CM_L4PER_CLKSTCTRL              0x4a009400
 321 #define CM_L4PER_DYNAMICDEP             0x4a009408
 322 #define CM_L4PER_ADC_CLKCTRL            0x4a009420
 323 #define CM_L4PER_DMTIMER10_CLKCTRL      0x4a009428
 324 #define CM_L4PER_DMTIMER11_CLKCTRL      0x4a009430
 325 #define CM_L4PER_DMTIMER2_CLKCTRL       0x4a009438
 326 #define CM_L4PER_DMTIMER3_CLKCTRL       0x4a009440
 327 #define CM_L4PER_DMTIMER4_CLKCTRL       0x4a009448
 328 #define CM_L4PER_DMTIMER9_CLKCTRL       0x4a009450
 329 #define CM_L4PER_ELM_CLKCTRL            0x4a009458
 330 #define CM_L4PER_GPIO2_CLKCTRL          0x4a009460
 331 #define CM_L4PER_GPIO3_CLKCTRL          0x4a009468
 332 #define CM_L4PER_GPIO4_CLKCTRL          0x4a009470
 333 #define CM_L4PER_GPIO5_CLKCTRL          0x4a009478
 334 #define CM_L4PER_GPIO6_CLKCTRL          0x4a009480
 335 #define CM_L4PER_HDQ1W_CLKCTRL          0x4a009488
 336 #define CM_L4PER_HECC1_CLKCTRL          0x4a009490
 337 #define CM_L4PER_HECC2_CLKCTRL          0x4a009498
 338 #define CM_L4PER_I2C1_CLKCTRL           0x4a0094a0
 339 #define CM_L4PER_I2C2_CLKCTRL           0x4a0094a8
 340 #define CM_L4PER_I2C3_CLKCTRL           0x4a0094b0
 341 #define CM_L4PER_I2C4_CLKCTRL           0x4a0094b8
 342 #define CM_L4PER_L4PER_CLKCTRL          0x4a0094c0
 343 #define CM_L4PER_MCASP2_CLKCTRL         0x4a0094d0
 344 #define CM_L4PER_MCASP3_CLKCTRL         0x4a0094d8
 345 #define CM_L4PER_MCBSP4_CLKCTRL         0x4a0094e0
 346 #define CM_L4PER_MGATE_CLKCTRL          0x4a0094e8
 347 #define CM_L4PER_MCSPI1_CLKCTRL         0x4a0094f0
 348 #define CM_L4PER_MCSPI2_CLKCTRL         0x4a0094f8
 349 #define CM_L4PER_MCSPI3_CLKCTRL         0x4a009500
 350 #define CM_L4PER_MCSPI4_CLKCTRL         0x4a009508
 351 #define CM_L4PER_MMCSD3_CLKCTRL         0x4a009520
 352 #define CM_L4PER_MMCSD4_CLKCTRL         0x4a009528
 353 #define CM_L4PER_MSPROHG_CLKCTRL        0x4a009530
 354 #define CM_L4PER_SLIMBUS2_CLKCTRL       0x4a009538
 355 #define CM_L4PER_UART1_CLKCTRL          0x4a009540
 356 #define CM_L4PER_UART2_CLKCTRL          0x4a009548
 357 #define CM_L4PER_UART3_CLKCTRL          0x4a009550
 358 #define CM_L4PER_UART4_CLKCTRL          0x4a009558
 359 #define CM_L4PER_MMCSD5_CLKCTRL         0x4a009560
 360 #define CM_L4PER_I2C5_CLKCTRL           0x4a009568
 361 #define CM_L4SEC_CLKSTCTRL              0x4a009580
 362 #define CM_L4SEC_STATICDEP              0x4a009584
 363 #define CM_L4SEC_DYNAMICDEP             0x4a009588
 364 #define CM_L4SEC_AES1_CLKCTRL           0x4a0095a0
 365 #define CM_L4SEC_AES2_CLKCTRL           0x4a0095a8
 366 #define CM_L4SEC_DES3DES_CLKCTRL        0x4a0095b0
 367 #define CM_L4SEC_PKAEIP29_CLKCTRL       0x4a0095b8
 368 #define CM_L4SEC_RNG_CLKCTRL            0x4a0095c0
 369 #define CM_L4SEC_SHA2MD51_CLKCTRL       0x4a0095c8
 370 #define CM_L4SEC_CRYPTODMA_CLKCTRL      0x4a0095d8
 371
 372 /* CM2.IVAHD */
 373 #define IVAHD_CLKSTCTRL                 0x4a008f00
 374 #define IVAHD_IVAHD_CLKCTRL             0x4a008f20
 375 #define IVAHD_SL2_CLKCTRL               0x4a008f28
 376
 377 /* CM2.L3INIT */
 378 #define CM_L3INIT_HSMMC1_CLKCTRL        0x4a009328
 379 #define CM_L3INIT_HSMMC2_CLKCTRL        0x4a009330
 380 #define CM_L3INIT_HSI_CLKCTRL           0x4a009338
 381 #define CM_L3INIT_UNIPRO1_CLKCTRL       0x4a009340
 382 #define CM_L3INIT_HSUSBHOST_CLKCTRL     0x4a009358
 383 #define CM_L3INIT_HSUSBOTG_CLKCTRL      0x4a009360
 384 #define CM_L3INIT_HSUSBTLL_CLKCTRL      0x4a009368
 385 #define CM_L3INIT_P1500_CLKCTRL         0x4a009378
 386 #define CM_L3INIT_FSUSB_CLKCTRL         0x4a0093d0
 387 #define CM_L3INIT_USBPHY_CLKCTRL        0x4a0093e0
 388
 389 /* CM2.CAM */
 390 #define CM_CAM_CLKSTCTRL                0x4a009000
 391 #define CM_CAM_ISS_CLKCTRL              0x4a009020
 392 #define CM_CAM_FDIF_CLKCTRL             0x4a009028
 393
 394 /* CM2.DSS */
 395 #define CM_DSS_CLKSTCTRL                0x4a009100
 396 #define CM_DSS_DSS_CLKCTRL              0x4a009120
 397 #define CM_DSS_DEISS_CLKCTRL            0x4a009128
 398
 399 /* CM2.SGX */
 400 #define CM_SGX_CLKSTCTRL                0x4a009200
 401 #define CM_SGX_SGX_CLKCTRL              0x4a009220
 402
 403 /* SMX-APE */
 404 #define PM_RT_APE_BASE_ADDR_ARM         (SMX_APE_BASE + 0x10000)
 405 #define PM_GPMC_BASE_ADDR_ARM           (SMX_APE_BASE + 0x12400)
 406 #define PM_OCM_RAM_BASE_ADDR_ARM        (SMX_APE_BASE + 0x12800)
 407 #define PM_OCM_ROM_BASE_ADDR_ARM        (SMX_APE_BASE + 0x12C00)
 408 #define PM_IVA2_BASE_ADDR_ARM           (SMX_APE_BASE + 0x14000)
 409
 410 #define RT_REQ_INFO_PERMISSION_1        (PM_RT_APE_BASE_ADDR_ARM + 0x68)
 411 #define RT_READ_PERMISSION_0            (PM_RT_APE_BASE_ADDR_ARM + 0x50)
 412 #define RT_WRITE_PERMISSION_0           (PM_RT_APE_BASE_ADDR_ARM + 0x58)
 413 #define RT_ADDR_MATCH_1                 (PM_RT_APE_BASE_ADDR_ARM + 0x60)
 414
 415 #define GPMC_REQ_INFO_PERMISSION_0      (PM_GPMC_BASE_ADDR_ARM + 0x48)
 416 #define GPMC_READ_PERMISSION_0          (PM_GPMC_BASE_ADDR_ARM + 0x50)
 417 #define GPMC_WRITE_PERMISSION_0         (PM_GPMC_BASE_ADDR_ARM + 0x58)
 418
 419 #define OCM_REQ_INFO_PERMISSION_0       (PM_OCM_RAM_BASE_ADDR_ARM + 0x48)
 420 #define OCM_READ_PERMISSION_0           (PM_OCM_RAM_BASE_ADDR_ARM + 0x50)
 421 #define OCM_WRITE_PERMISSION_0          (PM_OCM_RAM_BASE_ADDR_ARM + 0x58)
 422 #define OCM_ADDR_MATCH_2                (PM_OCM_RAM_BASE_ADDR_ARM + 0x80)
 423
 424 #define IVA2_REQ_INFO_PERMISSION_0      (PM_IVA2_BASE_ADDR_ARM + 0x48)
 425 #define IVA2_READ_PERMISSION_0          (PM_IVA2_BASE_ADDR_ARM + 0x50)
 426 #define IVA2_WRITE_PERMISSION_0         (PM_IVA2_BASE_ADDR_ARM + 0x58)
 427
 428 #define IVA2_REQ_INFO_PERMISSION_1      (PM_IVA2_BASE_ADDR_ARM + 0x68)
 429 #define IVA2_READ_PERMISSION_1          (PM_IVA2_BASE_ADDR_ARM + 0x70)
 430 #define IVA2_WRITE_PERMISSION_1         (PM_IVA2_BASE_ADDR_ARM + 0x78)
 431
 432 #define IVA2_REQ_INFO_PERMISSION_2      (PM_IVA2_BASE_ADDR_ARM + 0x88)
 433 #define IVA2_READ_PERMISSION_2          (PM_IVA2_BASE_ADDR_ARM + 0x90)
 434 #define IVA2_WRITE_PERMISSION_2         (PM_IVA2_BASE_ADDR_ARM + 0x98)
 435
 436 #define IVA2_REQ_INFO_PERMISSION_3      (PM_IVA2_BASE_ADDR_ARM + 0xA8)
 437 #define IVA2_READ_PERMISSION_3          (PM_IVA2_BASE_ADDR_ARM + 0xB0)
 438 #define IVA2_WRITE_PERMISSION_3         (PM_IVA2_BASE_ADDR_ARM + 0xB8)
 439
 440 /* I2C base */
 441 #define I2C_BASE1               (OMAP44XX_L4_PER + 0x70000)
 442 #define I2C_BASE2               (OMAP44XX_L4_PER + 0x72000)
 443 #define I2C_BASE3               (OMAP44XX_L4_PER + 0x60000)
 444
 445 #ifdef CONFIG_LCD
 446         extern void lcd_disable(void);
 447         extern void lcd_panel_disable(void);
 448 #endif
 449
 450 /* Silicon revisions */
 451 #define OMAP4430_SILICON_ID_INVALID     0
 452 #define OMAP4430_ES1_0  1
 453 #define OMAP4430_ES2_0  2
 454
 455 #ifndef __ASSEMBLY__
 456 /*Functions for silicon revision */
 457 unsigned int omap_revision(void);
 458 unsigned int cortex_a9_rev(void);
 459
 460 void big_delay(unsigned int count);
 461 #endif
 462
 463 #endif