3 * Texas Instruments, <www.ti.com>
4 * Syed Mohammed Khasim <khasim@ti.com>
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation's version 2 of
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 #ifndef MMC_HOST_DEF_H
26 #define MMC_HOST_DEF_H
29 * OMAP HSMMC register definitions
31 #define OMAP_HSMMC_SYSCONFIG (*(volatile unsigned int *) 0x4809C010)
32 #define OMAP_HSMMC_SYSSTATUS (*(volatile unsigned int *) 0x4809C014)
33 #define OMAP_HSMMC_CON (*(volatile unsigned int *) 0x4809C02C)
34 #define OMAP_HSMMC_BLK (*(volatile unsigned int *) 0x4809C104)
35 #define OMAP_HSMMC_ARG (*(volatile unsigned int *) 0x4809C108)
36 #define OMAP_HSMMC_CMD (*(volatile unsigned int *) 0x4809C10C)
37 #define OMAP_HSMMC_RSP10 (*(volatile unsigned int *) 0x4809C110)
38 #define OMAP_HSMMC_RSP32 (*(volatile unsigned int *) 0x4809C114)
39 #define OMAP_HSMMC_RSP54 (*(volatile unsigned int *) 0x4809C118)
40 #define OMAP_HSMMC_RSP76 (*(volatile unsigned int *) 0x4809C11C)
41 #define OMAP_HSMMC_DATA (*(volatile unsigned int *) 0x4809C120)
42 #define OMAP_HSMMC_PSTATE (*(volatile unsigned int *) 0x4809C124)
43 #define OMAP_HSMMC_HCTL (*(volatile unsigned int *) 0x4809C128)
44 #define OMAP_HSMMC_SYSCTL (*(volatile unsigned int *) 0x4809C12C)
45 #define OMAP_HSMMC_STAT (*(volatile unsigned int *) 0x4809C130)
46 #define OMAP_HSMMC_IE (*(volatile unsigned int *) 0x4809C134)
47 #define OMAP_HSMMC_CAPA (*(volatile unsigned int *) 0x4809C140)
49 /* T2 Register definitions */
50 #define CONTROL_DEV_CONF0 (*(volatile unsigned int *) 0x48002274)
51 #define CONTROL_PBIAS_LITE (*(volatile unsigned int *) 0x48002520)
54 * OMAP HS MMC Bit definitions
56 #define MMC_SOFTRESET (0x1 << 1)
57 #define RESETDONE (0x1 << 0)
58 #define NOOPENDRAIN (0x0 << 0)
59 #define OPENDRAIN (0x1 << 0)
61 #define INIT_NOINIT (0x0 << 1)
62 #define INIT_INITSTREAM (0x1 << 1)
63 #define HR_NOHOSTRESP (0x0 << 2)
64 #define STR_BLOCK (0x0 << 3)
65 #define MODE_FUNC (0x0 << 4)
66 #define DW8_1_4BITMODE (0x0 << 5)
67 #define MIT_CTO (0x0 << 6)
68 #define CDP_ACTIVEHIGH (0x0 << 7)
69 #define WPP_ACTIVEHIGH (0x0 << 8)
70 #define RESERVED_MASK (0x3 << 9)
71 #define CTPL_MMC_SD (0x0 << 11)
72 #define BLEN_512BYTESLEN (0x200 << 0)
73 #define NBLK_STPCNT (0x0 << 16)
74 #define DE_DISABLE (0x0 << 0)
75 #define BCE_DISABLE (0x0 << 1)
76 #define ACEN_DISABLE (0x0 << 2)
77 #define DDIR_OFFSET (4)
78 #define DDIR_MASK (0x1 << 4)
79 #define DDIR_WRITE (0x0 << 4)
80 #define DDIR_READ (0x1 << 4)
81 #define MSBS_SGLEBLK (0x0 << 5)
82 #define RSP_TYPE_OFFSET (16)
83 #define RSP_TYPE_MASK (0x3 << 16)
84 #define RSP_TYPE_NORSP (0x0 << 16)
85 #define RSP_TYPE_LGHT136 (0x1 << 16)
86 #define RSP_TYPE_LGHT48 (0x2 << 16)
87 #define RSP_TYPE_LGHT48B (0x3 << 16)
88 #define CCCE_NOCHECK (0x0 << 19)
89 #define CCCE_CHECK (0x1 << 19)
90 #define CICE_NOCHECK (0x0 << 20)
91 #define CICE_CHECK (0x1 << 20)
92 #define DP_OFFSET (21)
93 #define DP_MASK (0x1 << 21)
94 #define DP_NO_DATA (0x0 << 21)
95 #define DP_DATA (0x1 << 21)
96 #define CMD_TYPE_NORMAL (0x0 << 22)
97 #define INDEX_OFFSET (24)
98 #define INDEX_MASK (0x3f << 24)
99 #define INDEX(i) (i << 24)
100 #define DATI_MASK (0x1 << 1)
101 #define DATI_CMDDIS (0x1 << 1)
102 #define DTW_1_BITMODE (0x0 << 1)
103 #define DTW_4_BITMODE (0x1 << 1)
104 #define SDBP_PWROFF (0x0 << 8)
105 #define SDBP_PWRON (0x1 << 8)
106 #define SDVS_1V8 (0x5 << 9)
107 #define SDVS_3V0 (0x6 << 9)
108 #define ICE_MASK (0x1 << 0)
109 #define ICE_STOP (0x0 << 0)
110 #define ICS_MASK (0x1 << 1)
111 #define ICS_NOTREADY (0x0 << 1)
112 #define ICE_OSCILLATE (0x1 << 0)
113 #define CEN_MASK (0x1 << 2)
114 #define CEN_DISABLE (0x0 << 2)
115 #define CEN_ENABLE (0x1 << 2)
116 #define CLKD_OFFSET (6)
117 #define CLKD_MASK (0x3FF << 6)
118 #define DTO_MASK (0xF << 16)
119 #define DTO_15THDTO (0xE << 16)
120 #define SOFTRESETALL (0x1 << 24)
121 #define CC_MASK (0x1 << 0)
122 #define TC_MASK (0x1 << 1)
123 #define BWR_MASK (0x1 << 4)
124 #define BRR_MASK (0x1 << 5)
125 #define ERRI_MASK (0x1 << 15)
126 #define IE_CC (0x01 << 0)
127 #define IE_TC (0x01 << 1)
128 #define IE_BWR (0x01 << 4)
129 #define IE_BRR (0x01 << 5)
130 #define IE_CTO (0x01 << 16)
131 #define IE_CCRC (0x01 << 17)
132 #define IE_CEB (0x01 << 18)
133 #define IE_CIE (0x01 << 19)
134 #define IE_DTO (0x01 << 20)
135 #define IE_DCRC (0x01 << 21)
136 #define IE_DEB (0x01 << 22)
137 #define IE_CERR (0x01 << 28)
138 #define IE_BADA (0x01 << 29)
140 #define VS30_3V0SUP (1 << 25)
141 #define VS18_1V8SUP (1 << 26)
143 /* Driver definitions */
144 #define MMCSD_SECTOR_SIZE (512)
148 #define SECTOR_MODE 1
149 #define CLK_INITSEQ 0
154 unsigned int card_type;
155 unsigned int version;
161 #define mmc_reg_out(addr, mask, val)\
162 (addr) = (((addr)) & (~(mask))) | ((val) & (mask));
164 #endif /* MMC_HOST_DEF_H */