2 * EHCI HCD (Host Controller Driver) PCI Bus Glue.
4 * Copyright (c) 2000-2004 by David Brownell
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software Foundation,
18 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 #error "This file is PCI bus glue. CONFIG_PCI must be defined."
25 /* defined here to avoid adding to pci_ids.h for single instance use */
26 #define PCI_DEVICE_ID_INTEL_CE4100_USB 0x2e70
28 /*-------------------------------------------------------------------------*/
30 /* called after powerup, by probe or system-pm "wakeup" */
31 static int ehci_pci_reinit(struct ehci_hcd *ehci, struct pci_dev *pdev)
35 /* we expect static quirk code to handle the "extended capabilities"
36 * (currently just BIOS handoff) allowed starting with EHCI 0.96
39 /* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */
40 retval = pci_set_mwi(pdev);
42 ehci_dbg(ehci, "MWI active\n");
47 /* called during probe() after chip reset completes */
48 static int ehci_pci_setup(struct usb_hcd *hcd)
50 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
51 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
52 struct pci_dev *p_smbus;
57 switch (pdev->vendor) {
58 case PCI_VENDOR_ID_TOSHIBA_2:
59 /* celleb's companion chip */
60 if (pdev->device == 0x01b5) {
61 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
62 ehci->big_endian_mmio = 1;
65 "unsupported big endian Toshiba quirk\n");
71 ehci->caps = hcd->regs;
72 ehci->regs = hcd->regs +
73 HC_LENGTH(ehci, ehci_readl(ehci, &ehci->caps->hc_capbase));
75 dbg_hcs_params(ehci, "reset");
76 dbg_hcc_params(ehci, "reset");
78 /* ehci_init() causes memory for DMA transfers to be
79 * allocated. Thus, any vendor-specific workarounds based on
80 * limiting the type of memory used for DMA transfers must
81 * happen before ehci_init() is called. */
82 switch (pdev->vendor) {
83 case PCI_VENDOR_ID_NVIDIA:
84 /* NVidia reports that certain chips don't handle
85 * QH, ITD, or SITD addresses above 2GB. (But TD,
86 * data buffer, and periodic schedule are normal.)
88 switch (pdev->device) {
89 case 0x003c: /* MCP04 */
90 case 0x005b: /* CK804 */
91 case 0x00d8: /* CK8 */
92 case 0x00e8: /* CK8S */
93 if (pci_set_consistent_dma_mask(pdev,
94 DMA_BIT_MASK(31)) < 0)
95 ehci_warn(ehci, "can't enable NVidia "
96 "workaround for >2GB RAM\n");
102 /* cache this readonly data; minimize chip reads */
103 ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params);
105 retval = ehci_halt(ehci);
109 if ((pdev->vendor == PCI_VENDOR_ID_AMD && pdev->device == 0x7808) ||
110 (pdev->vendor == PCI_VENDOR_ID_ATI && pdev->device == 0x4396)) {
111 /* EHCI controller on AMD SB700/SB800/Hudson-2/3 platforms may
112 * read/write memory space which does not belong to it when
113 * there is NULL pointer with T-bit set to 1 in the frame list
114 * table. To avoid the issue, the frame list link pointer
115 * should always contain a valid pointer to a inactive qh.
117 ehci->use_dummy_qh = 1;
118 ehci_info(ehci, "applying AMD SB700/SB800/Hudson-2/3 EHCI "
119 "dummy qh workaround\n");
122 /* data structure init */
123 retval = ehci_init(hcd);
127 switch (pdev->vendor) {
128 case PCI_VENDOR_ID_NEC:
129 ehci->need_io_watchdog = 0;
131 case PCI_VENDOR_ID_INTEL:
132 ehci->need_io_watchdog = 0;
133 ehci->fs_i_thresh = 1;
134 if (pdev->device == 0x27cc) {
135 ehci->broken_periodic = 1;
136 ehci_info(ehci, "using broken periodic workaround\n");
138 if (pdev->device == 0x0806 || pdev->device == 0x0811
139 || pdev->device == 0x0829) {
140 ehci_info(ehci, "disable lpm for langwell/penwell\n");
143 if (pdev->device == PCI_DEVICE_ID_INTEL_CE4100_USB) {
147 if (pdev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK) {
148 /* EHCI #1 or #2 on 6 Series/C200 Series chipset */
149 if (pdev->device == 0x1c26 || pdev->device == 0x1c2d) {
150 ehci_info(ehci, "broken D3 during system sleep on ASUS\n");
151 hcd->broken_pci_sleep = 1;
152 device_set_wakeup_capable(&pdev->dev, false);
156 case PCI_VENDOR_ID_TDI:
157 if (pdev->device == PCI_DEVICE_ID_TDI_EHCI) {
162 case PCI_VENDOR_ID_AMD:
164 if (usb_amd_find_chipset_info())
165 ehci->amd_pll_fix = 1;
166 /* AMD8111 EHCI doesn't work, according to AMD errata */
167 if (pdev->device == 0x7463) {
168 ehci_info(ehci, "ignoring AMD8111 (errata)\n");
173 case PCI_VENDOR_ID_NVIDIA:
174 switch (pdev->device) {
175 /* Some NForce2 chips have problems with selective suspend;
176 * fixed in newer silicon.
179 if (pdev->revision < 0xa4)
180 ehci->no_selective_suspend = 1;
183 /* MCP89 chips on the MacBookAir3,1 give EPROTO when
184 * fetching device descriptors unless LPM is disabled.
185 * There are also intermittent problems enumerating
186 * devices with PPCD enabled.
189 ehci_info(ehci, "disable lpm/ppcd for nvidia mcp89");
192 ehci->command &= ~CMD_PPCEE;
196 case PCI_VENDOR_ID_VIA:
197 if (pdev->device == 0x3104 && (pdev->revision & 0xf0) == 0x60) {
200 /* The VT6212 defaults to a 1 usec EHCI sleep time which
201 * hogs the PCI bus *badly*. Setting bit 5 of 0x4B makes
202 * that sleep time use the conventional 10 usec.
204 pci_read_config_byte(pdev, 0x4b, &tmp);
207 pci_write_config_byte(pdev, 0x4b, tmp | 0x20);
210 case PCI_VENDOR_ID_ATI:
212 if (usb_amd_find_chipset_info())
213 ehci->amd_pll_fix = 1;
214 /* SB600 and old version of SB700 have a bug in EHCI controller,
215 * which causes usb devices lose response in some cases.
217 if ((pdev->device == 0x4386) || (pdev->device == 0x4396)) {
218 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
219 PCI_DEVICE_ID_ATI_SBX00_SMBUS,
223 rev = p_smbus->revision;
224 if ((pdev->device == 0x4386) || (rev == 0x3a)
227 ehci_info(ehci, "applying AMD SB600/SB700 USB "
228 "freeze workaround\n");
229 pci_read_config_byte(pdev, 0x53, &tmp);
230 pci_write_config_byte(pdev, 0x53, tmp | (1<<3));
232 pci_dev_put(p_smbus);
235 case PCI_VENDOR_ID_NETMOS:
236 /* MosChip frame-index-register bug */
237 ehci_info(ehci, "applying MosChip frame-index workaround\n");
238 ehci->frame_index_bug = 1;
242 /* optional debug port, normally in the first BAR */
243 temp = pci_find_capability(pdev, 0x0a);
245 pci_read_config_dword(pdev, temp, &temp);
247 if ((temp & (3 << 13)) == (1 << 13)) {
249 ehci->debug = ehci_to_hcd(ehci)->regs + temp;
250 temp = ehci_readl(ehci, &ehci->debug->control);
251 ehci_info(ehci, "debug port %d%s\n",
252 HCS_DEBUG_PORT(ehci->hcs_params),
253 (temp & DBGP_ENABLED)
256 if (!(temp & DBGP_ENABLED))
263 /* at least the Genesys GL880S needs fixup here */
264 temp = HCS_N_CC(ehci->hcs_params) * HCS_N_PCC(ehci->hcs_params);
266 if (temp && HCS_N_PORTS(ehci->hcs_params) > temp) {
267 ehci_dbg(ehci, "bogus port configuration: "
268 "cc=%d x pcc=%d < ports=%d\n",
269 HCS_N_CC(ehci->hcs_params),
270 HCS_N_PCC(ehci->hcs_params),
271 HCS_N_PORTS(ehci->hcs_params));
273 switch (pdev->vendor) {
274 case 0x17a0: /* GENESYS */
275 /* GL880S: should be PORTS=2 */
276 temp |= (ehci->hcs_params & ~0xf);
277 ehci->hcs_params = temp;
279 case PCI_VENDOR_ID_NVIDIA:
280 /* NF4: should be PCC=10 */
285 /* Serial Bus Release Number is at PCI 0x60 offset */
286 pci_read_config_byte(pdev, 0x60, &ehci->sbrn);
288 /* Keep this around for a while just in case some EHCI
289 * implementation uses legacy PCI PM support. This test
290 * can be removed on 17 Dec 2009 if the dev_warn() hasn't
291 * been triggered by then.
293 if (!device_can_wakeup(&pdev->dev)) {
296 pci_read_config_word(pdev, 0x62, &port_wake);
297 if (port_wake & 0x0001) {
298 dev_warn(&pdev->dev, "Enabling legacy PCI PM\n");
299 device_set_wakeup_capable(&pdev->dev, 1);
303 #ifdef CONFIG_USB_SUSPEND
304 /* REVISIT: the controller works fine for wakeup iff the root hub
305 * itself is "globally" suspended, but usbcore currently doesn't
306 * understand such things.
308 * System suspend currently expects to be able to suspend the entire
309 * device tree, device-at-a-time. If we failed selective suspend
310 * reports, system suspend would fail; so the root hub code must claim
311 * success. That's lying to usbcore, and it matters for runtime
312 * PM scenarios with selective suspend and remote wakeup...
314 if (ehci->no_selective_suspend && device_can_wakeup(&pdev->dev))
315 ehci_warn(ehci, "selective suspend/wakeup unavailable\n");
318 ehci_port_power(ehci, 1);
319 retval = ehci_pci_reinit(ehci, pdev);
324 /*-------------------------------------------------------------------------*/
328 /* suspend/resume, section 4.3 */
330 /* These routines rely on the PCI bus glue
331 * to handle powerdown and wakeup, and currently also on
332 * transceivers that don't need any software attention to set up
333 * the right sort of wakeup.
334 * Also they depend on separate root hub suspend/resume.
337 static int ehci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup)
339 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
343 if (time_before(jiffies, ehci->next_statechange))
346 /* Root hub was already suspended. Disable irq emission and
347 * mark HW unaccessible. The PM and USB cores make sure that
348 * the root hub is either suspended or stopped.
350 ehci_prepare_ports_for_controller_suspend(ehci, do_wakeup);
351 spin_lock_irqsave (&ehci->lock, flags);
352 ehci_writel(ehci, 0, &ehci->regs->intr_enable);
353 (void)ehci_readl(ehci, &ehci->regs->intr_enable);
355 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
356 spin_unlock_irqrestore (&ehci->lock, flags);
358 // could save FLADJ in case of Vaux power loss
359 // ... we'd only use it to handle clock skew
364 static bool usb_is_intel_switchable_ehci(struct pci_dev *pdev)
366 return pdev->class == PCI_CLASS_SERIAL_USB_EHCI &&
367 pdev->vendor == PCI_VENDOR_ID_INTEL &&
368 pdev->device == 0x1E26;
371 static void ehci_enable_xhci_companion(void)
373 struct pci_dev *companion = NULL;
375 /* The xHCI and EHCI controllers are not on the same PCI slot */
376 for_each_pci_dev(companion) {
377 if (!usb_is_intel_switchable_xhci(companion))
379 usb_enable_xhci_ports(companion);
384 static int ehci_pci_resume(struct usb_hcd *hcd, bool hibernated)
386 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
387 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
389 /* The BIOS on systems with the Intel Panther Point chipset may or may
390 * not support xHCI natively. That means that during system resume, it
391 * may switch the ports back to EHCI so that users can use their
392 * keyboard to select a kernel from GRUB after resume from hibernate.
394 * The BIOS is supposed to remember whether the OS had xHCI ports
395 * enabled before resume, and switch the ports back to xHCI when the
396 * BIOS/OS semaphore is written, but we all know we can't trust BIOS
399 * Unconditionally switch the ports back to xHCI after a system resume.
400 * We can't tell whether the EHCI or xHCI controller will be resumed
401 * first, so we have to do the port switchover in both drivers. Writing
402 * a '1' to the port switchover registers should have no effect if the
403 * port was already switched over.
405 if (usb_is_intel_switchable_ehci(pdev))
406 ehci_enable_xhci_companion();
408 // maybe restore FLADJ
410 if (time_before(jiffies, ehci->next_statechange))
413 /* Mark hardware accessible again as we are out of D3 state by now */
414 set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
416 /* If CF is still set and we aren't resuming from hibernation
417 * then we maintained PCI Vaux power.
418 * Just undo the effect of ehci_pci_suspend().
420 if (ehci_readl(ehci, &ehci->regs->configured_flag) == FLAG_CF &&
422 int mask = INTR_MASK;
424 ehci_prepare_ports_for_controller_resume(ehci);
425 if (!hcd->self.root_hub->do_remote_wakeup)
427 ehci_writel(ehci, mask, &ehci->regs->intr_enable);
428 ehci_readl(ehci, &ehci->regs->intr_enable);
432 usb_root_hub_lost_power(hcd->self.root_hub);
434 /* Else reset, to cope with power loss or flush-to-storage
435 * style "resume" having let BIOS kick in during reboot.
437 (void) ehci_halt(ehci);
438 (void) ehci_reset(ehci);
439 (void) ehci_pci_reinit(ehci, pdev);
441 /* emptying the schedule aborts any urbs */
442 spin_lock_irq(&ehci->lock);
444 end_unlink_async(ehci);
446 spin_unlock_irq(&ehci->lock);
448 ehci_writel(ehci, ehci->command, &ehci->regs->command);
449 ehci_writel(ehci, FLAG_CF, &ehci->regs->configured_flag);
450 ehci_readl(ehci, &ehci->regs->command); /* unblock posted writes */
452 /* here we "know" root ports should always stay powered */
453 ehci_port_power(ehci, 1);
455 ehci->rh_state = EHCI_RH_SUSPENDED;
460 static int ehci_update_device(struct usb_hcd *hcd, struct usb_device *udev)
462 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
465 if (!udev->parent) /* udev is root hub itself, impossible */
467 /* we only support lpm device connected to root hub yet */
468 if (ehci->has_lpm && !udev->parent->parent) {
469 rc = ehci_lpm_set_da(ehci, udev->devnum, udev->portnum);
471 rc = ehci_lpm_check(ehci, udev->portnum);
476 static const struct hc_driver ehci_pci_hc_driver = {
477 .description = hcd_name,
478 .product_desc = "EHCI Host Controller",
479 .hcd_priv_size = sizeof(struct ehci_hcd),
482 * generic hardware linkage
485 .flags = HCD_MEMORY | HCD_USB2,
488 * basic lifecycle operations
490 .reset = ehci_pci_setup,
493 .pci_suspend = ehci_pci_suspend,
494 .pci_resume = ehci_pci_resume,
497 .shutdown = ehci_shutdown,
500 * managing i/o requests and associated device resources
502 .urb_enqueue = ehci_urb_enqueue,
503 .urb_dequeue = ehci_urb_dequeue,
504 .endpoint_disable = ehci_endpoint_disable,
505 .endpoint_reset = ehci_endpoint_reset,
510 .get_frame_number = ehci_get_frame,
515 .hub_status_data = ehci_hub_status_data,
516 .hub_control = ehci_hub_control,
517 .bus_suspend = ehci_bus_suspend,
518 .bus_resume = ehci_bus_resume,
519 .relinquish_port = ehci_relinquish_port,
520 .port_handed_over = ehci_port_handed_over,
523 * call back when device connected and addressed
525 .update_device = ehci_update_device,
527 .clear_tt_buffer_complete = ehci_clear_tt_buffer_complete,
530 /*-------------------------------------------------------------------------*/
532 /* PCI driver selection metadata; PCI hotplugging uses this */
533 static const struct pci_device_id pci_ids [] = { {
534 /* handle any USB 2.0 EHCI controller */
535 PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_EHCI, ~0),
536 .driver_data = (unsigned long) &ehci_pci_hc_driver,
538 { /* end: all zeroes */ }
540 MODULE_DEVICE_TABLE(pci, pci_ids);
542 /* pci driver glue; this is a "new style" PCI driver module */
543 static struct pci_driver ehci_pci_driver = {
544 .name = (char *) hcd_name,
547 .probe = usb_hcd_pci_probe,
548 .remove = usb_hcd_pci_remove,
549 .shutdown = usb_hcd_pci_shutdown,
551 #ifdef CONFIG_PM_SLEEP
553 .pm = &usb_hcd_pci_pm_ops