2 * drivers/serial/sh-sci.c
4 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
6 * Copyright (C) 2002 - 2008 Paul Mundt
7 * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007).
9 * based off of the old drivers/char/sh-sci.c by:
11 * Copyright (C) 1999, 2000 Niibe Yutaka
12 * Copyright (C) 2000 Sugioka Toshinobu
13 * Modified to support multiple serial ports. Stuart Menefy (May 2000).
14 * Modified to support SecureEdge. David McCullough (2002)
15 * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003).
16 * Removed SH7300 support (Jul 2007).
18 * This file is subject to the terms and conditions of the GNU General Public
19 * License. See the file "COPYING" in the main directory of this archive
22 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
28 #include <linux/module.h>
29 #include <linux/errno.h>
30 #include <linux/timer.h>
31 #include <linux/interrupt.h>
32 #include <linux/tty.h>
33 #include <linux/tty_flip.h>
34 #include <linux/serial.h>
35 #include <linux/major.h>
36 #include <linux/string.h>
37 #include <linux/sysrq.h>
38 #include <linux/ioport.h>
40 #include <linux/init.h>
41 #include <linux/delay.h>
42 #include <linux/console.h>
43 #include <linux/platform_device.h>
44 #include <linux/serial_sci.h>
45 #include <linux/notifier.h>
46 #include <linux/cpufreq.h>
47 #include <linux/clk.h>
48 #include <linux/ctype.h>
49 #include <linux/err.h>
50 #include <linux/list.h>
53 #include <asm/clock.h>
54 #include <asm/sh_bios.h>
64 struct uart_port port;
69 /* Port IRQs: ERI, RXI, TXI, BRI (optional) */
70 unsigned int irqs[SCIx_NR_IRQS];
72 /* Port enable callback */
73 void (*enable)(struct uart_port *port);
75 /* Port disable callback */
76 void (*disable)(struct uart_port *port);
79 struct timer_list break_timer;
82 /* SCSCR initialization */
85 /* SCBRR calculation algo */
86 unsigned int scbrr_algo_id;
88 #ifdef CONFIG_HAVE_CLK
94 struct list_head node;
99 struct list_head ports;
101 #ifdef CONFIG_HAVE_CLK
102 struct notifier_block clk_nb;
106 /* Function prototypes */
107 static void sci_stop_tx(struct uart_port *port);
109 #define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS
111 static struct sci_port sci_ports[SCI_NPORTS];
112 static struct uart_driver sci_uart_driver;
114 static inline struct sci_port *
115 to_sci_port(struct uart_port *uart)
117 return container_of(uart, struct sci_port, port);
120 #if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE)
122 #ifdef CONFIG_CONSOLE_POLL
123 static inline void handle_error(struct uart_port *port)
125 /* Clear error flags */
126 sci_out(port, SCxSR, SCxSR_ERROR_CLEAR(port));
129 static int sci_poll_get_char(struct uart_port *port)
131 unsigned short status;
135 status = sci_in(port, SCxSR);
136 if (status & SCxSR_ERRORS(port)) {
140 } while (!(status & SCxSR_RDxF(port)));
142 c = sci_in(port, SCxRDR);
146 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
152 static void sci_poll_put_char(struct uart_port *port, unsigned char c)
154 unsigned short status;
157 status = sci_in(port, SCxSR);
158 } while (!(status & SCxSR_TDxE(port)));
160 sci_out(port, SCxTDR, c);
161 sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port));
163 #endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE */
165 #if defined(__H8300S__)
166 enum { sci_disable, sci_enable };
168 static void h8300_sci_config(struct uart_port *port, unsigned int ctrl)
170 volatile unsigned char *mstpcrl = (volatile unsigned char *)MSTPCRL;
171 int ch = (port->mapbase - SMR0) >> 3;
172 unsigned char mask = 1 << (ch+1);
174 if (ctrl == sci_disable)
180 static void h8300_sci_enable(struct uart_port *port)
182 h8300_sci_config(port, sci_enable);
185 static void h8300_sci_disable(struct uart_port *port)
187 h8300_sci_config(port, sci_disable);
191 #if defined(__H8300H__) || defined(__H8300S__)
192 static void sci_init_pins(struct uart_port *port, unsigned int cflag)
194 int ch = (port->mapbase - SMR0) >> 3;
197 H8300_GPIO_DDR(h8300_sci_pins[ch].port,
198 h8300_sci_pins[ch].rx,
200 H8300_GPIO_DDR(h8300_sci_pins[ch].port,
201 h8300_sci_pins[ch].tx,
205 H8300_SCI_DR(ch) |= h8300_sci_pins[ch].tx;
207 #elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
208 static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
210 if (port->mapbase == 0xA4400000) {
211 __raw_writew(__raw_readw(PACR) & 0xffc0, PACR);
212 __raw_writew(__raw_readw(PBCR) & 0x0fff, PBCR);
213 } else if (port->mapbase == 0xA4410000)
214 __raw_writew(__raw_readw(PBCR) & 0xf003, PBCR);
216 #elif defined(CONFIG_CPU_SUBTYPE_SH7720) || defined(CONFIG_CPU_SUBTYPE_SH7721)
217 static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
221 if (cflag & CRTSCTS) {
223 if (port->mapbase == 0xa4430000) { /* SCIF0 */
224 /* Clear PTCR bit 9-2; enable all scif pins but sck */
225 data = __raw_readw(PORT_PTCR);
226 __raw_writew((data & 0xfc03), PORT_PTCR);
227 } else if (port->mapbase == 0xa4438000) { /* SCIF1 */
228 /* Clear PVCR bit 9-2 */
229 data = __raw_readw(PORT_PVCR);
230 __raw_writew((data & 0xfc03), PORT_PVCR);
233 if (port->mapbase == 0xa4430000) { /* SCIF0 */
234 /* Clear PTCR bit 5-2; enable only tx and rx */
235 data = __raw_readw(PORT_PTCR);
236 __raw_writew((data & 0xffc3), PORT_PTCR);
237 } else if (port->mapbase == 0xa4438000) { /* SCIF1 */
238 /* Clear PVCR bit 5-2 */
239 data = __raw_readw(PORT_PVCR);
240 __raw_writew((data & 0xffc3), PORT_PVCR);
244 #elif defined(CONFIG_CPU_SH3)
245 /* For SH7705, SH7706, SH7707, SH7709, SH7709A, SH7729 */
246 static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
250 /* We need to set SCPCR to enable RTS/CTS */
251 data = __raw_readw(SCPCR);
252 /* Clear out SCP7MD1,0, SCP6MD1,0, SCP4MD1,0*/
253 __raw_writew(data & 0x0fcf, SCPCR);
255 if (!(cflag & CRTSCTS)) {
256 /* We need to set SCPCR to enable RTS/CTS */
257 data = __raw_readw(SCPCR);
258 /* Clear out SCP7MD1,0, SCP4MD1,0,
259 Set SCP6MD1,0 = {01} (output) */
260 __raw_writew((data & 0x0fcf) | 0x1000, SCPCR);
262 data = ctrl_inb(SCPDR);
263 /* Set /RTS2 (bit6) = 0 */
264 ctrl_outb(data & 0xbf, SCPDR);
267 #elif defined(CONFIG_CPU_SUBTYPE_SH7722)
268 static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
272 if (port->mapbase == 0xffe00000) {
273 data = __raw_readw(PSCR);
275 if (!(cflag & CRTSCTS))
278 __raw_writew(data, PSCR);
281 #elif defined(CONFIG_CPU_SUBTYPE_SH7763) || \
282 defined(CONFIG_CPU_SUBTYPE_SH7780) || \
283 defined(CONFIG_CPU_SUBTYPE_SH7785) || \
284 defined(CONFIG_CPU_SUBTYPE_SH7786) || \
285 defined(CONFIG_CPU_SUBTYPE_SHX3)
286 static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
288 if (!(cflag & CRTSCTS))
289 __raw_writew(0x0080, SCSPTR0); /* Set RTS = 1 */
291 #elif defined(CONFIG_CPU_SH4) && !defined(CONFIG_CPU_SH4A)
292 static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
294 if (!(cflag & CRTSCTS))
295 __raw_writew(0x0080, SCSPTR2); /* Set RTS = 1 */
298 static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
304 #if defined(CONFIG_CPU_SUBTYPE_SH7760) || \
305 defined(CONFIG_CPU_SUBTYPE_SH7780) || \
306 defined(CONFIG_CPU_SUBTYPE_SH7785) || \
307 defined(CONFIG_CPU_SUBTYPE_SH7786)
308 static inline int scif_txroom(struct uart_port *port)
310 return SCIF_TXROOM_MAX - (sci_in(port, SCTFDR) & 0xff);
313 static inline int scif_rxroom(struct uart_port *port)
315 return sci_in(port, SCRFDR) & 0xff;
317 #elif defined(CONFIG_CPU_SUBTYPE_SH7763)
318 static inline int scif_txroom(struct uart_port *port)
320 if ((port->mapbase == 0xffe00000) ||
321 (port->mapbase == 0xffe08000)) {
323 return SCIF_TXROOM_MAX - (sci_in(port, SCTFDR) & 0xff);
326 return SCIF2_TXROOM_MAX - (sci_in(port, SCFDR) >> 8);
330 static inline int scif_rxroom(struct uart_port *port)
332 if ((port->mapbase == 0xffe00000) ||
333 (port->mapbase == 0xffe08000)) {
335 return sci_in(port, SCRFDR) & 0xff;
338 return sci_in(port, SCFDR) & SCIF2_RFDC_MASK;
342 static inline int scif_txroom(struct uart_port *port)
344 return SCIF_TXROOM_MAX - (sci_in(port, SCFDR) >> 8);
347 static inline int scif_rxroom(struct uart_port *port)
349 return sci_in(port, SCFDR) & SCIF_RFDC_MASK;
353 static inline int sci_txroom(struct uart_port *port)
355 return (sci_in(port, SCxSR) & SCI_TDRE) != 0;
358 static inline int sci_rxroom(struct uart_port *port)
360 return (sci_in(port, SCxSR) & SCxSR_RDxF(port)) != 0;
363 /* ********************************************************************** *
364 * the interrupt related routines *
365 * ********************************************************************** */
367 static void sci_transmit_chars(struct uart_port *port)
369 struct circ_buf *xmit = &port->info->xmit;
370 unsigned int stopped = uart_tx_stopped(port);
371 unsigned short status;
375 status = sci_in(port, SCxSR);
376 if (!(status & SCxSR_TDxE(port))) {
377 ctrl = sci_in(port, SCSCR);
378 if (uart_circ_empty(xmit))
382 sci_out(port, SCSCR, ctrl);
386 if (port->type == PORT_SCI)
387 count = sci_txroom(port);
389 count = scif_txroom(port);
397 } else if (!uart_circ_empty(xmit) && !stopped) {
398 c = xmit->buf[xmit->tail];
399 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
404 sci_out(port, SCxTDR, c);
407 } while (--count > 0);
409 sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
411 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
412 uart_write_wakeup(port);
413 if (uart_circ_empty(xmit)) {
416 ctrl = sci_in(port, SCSCR);
418 if (port->type != PORT_SCI) {
419 sci_in(port, SCxSR); /* Dummy read */
420 sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
424 sci_out(port, SCSCR, ctrl);
428 /* On SH3, SCIF may read end-of-break as a space->mark char */
429 #define STEPFN(c) ({int __c = (c); (((__c-1)|(__c)) == -1); })
431 static inline void sci_receive_chars(struct uart_port *port)
433 struct sci_port *sci_port = to_sci_port(port);
434 struct tty_struct *tty = port->info->port.tty;
435 int i, count, copied = 0;
436 unsigned short status;
439 status = sci_in(port, SCxSR);
440 if (!(status & SCxSR_RDxF(port)))
444 if (port->type == PORT_SCI)
445 count = sci_rxroom(port);
447 count = scif_rxroom(port);
449 /* Don't copy more bytes than there is room for in the buffer */
450 count = tty_buffer_request_room(tty, count);
452 /* If for any reason we can't copy more data, we're done! */
456 if (port->type == PORT_SCI) {
457 char c = sci_in(port, SCxRDR);
458 if (uart_handle_sysrq_char(port, c) ||
459 sci_port->break_flag)
462 tty_insert_flip_char(tty, c, TTY_NORMAL);
464 for (i = 0; i < count; i++) {
465 char c = sci_in(port, SCxRDR);
466 status = sci_in(port, SCxSR);
467 #if defined(CONFIG_CPU_SH3)
468 /* Skip "chars" during break */
469 if (sci_port->break_flag) {
471 (status & SCxSR_FER(port))) {
476 /* Nonzero => end-of-break */
477 dev_dbg(port->dev, "debounce<%02x>\n", c);
478 sci_port->break_flag = 0;
485 #endif /* CONFIG_CPU_SH3 */
486 if (uart_handle_sysrq_char(port, c)) {
491 /* Store data and status */
492 if (status&SCxSR_FER(port)) {
494 dev_notice(port->dev, "frame error\n");
495 } else if (status&SCxSR_PER(port)) {
497 dev_notice(port->dev, "parity error\n");
501 tty_insert_flip_char(tty, c, flag);
505 sci_in(port, SCxSR); /* dummy read */
506 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
509 port->icount.rx += count;
513 /* Tell the rest of the system the news. New characters! */
514 tty_flip_buffer_push(tty);
516 sci_in(port, SCxSR); /* dummy read */
517 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
521 #define SCI_BREAK_JIFFIES (HZ/20)
522 /* The sci generates interrupts during the break,
523 * 1 per millisecond or so during the break period, for 9600 baud.
524 * So dont bother disabling interrupts.
525 * But dont want more than 1 break event.
526 * Use a kernel timer to periodically poll the rx line until
527 * the break is finished.
529 static void sci_schedule_break_timer(struct sci_port *port)
531 port->break_timer.expires = jiffies + SCI_BREAK_JIFFIES;
532 add_timer(&port->break_timer);
534 /* Ensure that two consecutive samples find the break over. */
535 static void sci_break_timer(unsigned long data)
537 struct sci_port *port = (struct sci_port *)data;
539 if (sci_rxd_in(&port->port) == 0) {
540 port->break_flag = 1;
541 sci_schedule_break_timer(port);
542 } else if (port->break_flag == 1) {
544 port->break_flag = 2;
545 sci_schedule_break_timer(port);
547 port->break_flag = 0;
550 static inline int sci_handle_errors(struct uart_port *port)
553 unsigned short status = sci_in(port, SCxSR);
554 struct tty_struct *tty = port->info->port.tty;
556 if (status & SCxSR_ORER(port)) {
558 if (tty_insert_flip_char(tty, 0, TTY_OVERRUN))
561 dev_notice(port->dev, "overrun error");
564 if (status & SCxSR_FER(port)) {
565 if (sci_rxd_in(port) == 0) {
566 /* Notify of BREAK */
567 struct sci_port *sci_port = to_sci_port(port);
569 if (!sci_port->break_flag) {
570 sci_port->break_flag = 1;
571 sci_schedule_break_timer(sci_port);
573 /* Do sysrq handling. */
574 if (uart_handle_break(port))
577 dev_dbg(port->dev, "BREAK detected\n");
579 if (tty_insert_flip_char(tty, 0, TTY_BREAK))
585 if (tty_insert_flip_char(tty, 0, TTY_FRAME))
588 dev_notice(port->dev, "frame error\n");
592 if (status & SCxSR_PER(port)) {
594 if (tty_insert_flip_char(tty, 0, TTY_PARITY))
597 dev_notice(port->dev, "parity error");
601 tty_flip_buffer_push(tty);
606 static inline int sci_handle_fifo_overrun(struct uart_port *port)
608 struct tty_struct *tty = port->info->port.tty;
611 if (port->type != PORT_SCIF)
614 if ((sci_in(port, SCLSR) & SCIF_ORER) != 0) {
615 sci_out(port, SCLSR, 0);
617 tty_insert_flip_char(tty, 0, TTY_OVERRUN);
618 tty_flip_buffer_push(tty);
620 dev_notice(port->dev, "overrun error\n");
627 static inline int sci_handle_breaks(struct uart_port *port)
630 unsigned short status = sci_in(port, SCxSR);
631 struct tty_struct *tty = port->info->port.tty;
632 struct sci_port *s = to_sci_port(port);
634 if (uart_handle_break(port))
637 if (!s->break_flag && status & SCxSR_BRK(port)) {
638 #if defined(CONFIG_CPU_SH3)
642 /* Notify of BREAK */
643 if (tty_insert_flip_char(tty, 0, TTY_BREAK))
646 dev_dbg(port->dev, "BREAK detected\n");
650 tty_flip_buffer_push(tty);
652 copied += sci_handle_fifo_overrun(port);
657 static irqreturn_t sci_rx_interrupt(int irq, void *port)
659 /* I think sci_receive_chars has to be called irrespective
660 * of whether the I_IXOFF is set, otherwise, how is the interrupt
663 sci_receive_chars(port);
668 static irqreturn_t sci_tx_interrupt(int irq, void *ptr)
670 struct uart_port *port = ptr;
672 spin_lock_irq(&port->lock);
673 sci_transmit_chars(port);
674 spin_unlock_irq(&port->lock);
679 static irqreturn_t sci_er_interrupt(int irq, void *ptr)
681 struct uart_port *port = ptr;
684 if (port->type == PORT_SCI) {
685 if (sci_handle_errors(port)) {
686 /* discard character in rx buffer */
688 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
691 sci_handle_fifo_overrun(port);
692 sci_rx_interrupt(irq, ptr);
695 sci_out(port, SCxSR, SCxSR_ERROR_CLEAR(port));
697 /* Kick the transmission */
698 sci_tx_interrupt(irq, ptr);
703 static irqreturn_t sci_br_interrupt(int irq, void *ptr)
705 struct uart_port *port = ptr;
708 sci_handle_breaks(port);
709 sci_out(port, SCxSR, SCxSR_BREAK_CLEAR(port));
714 static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr)
716 unsigned short ssr_status, scr_status;
717 struct uart_port *port = ptr;
718 irqreturn_t ret = IRQ_NONE;
720 ssr_status = sci_in(port, SCxSR);
721 scr_status = sci_in(port, SCSCR);
724 if ((ssr_status & 0x0020) && (scr_status & SCSCR_TIE))
725 ret = sci_tx_interrupt(irq, ptr);
727 if ((ssr_status & 0x0002) && (scr_status & SCSCR_RIE))
728 ret = sci_rx_interrupt(irq, ptr);
729 /* Error Interrupt */
730 if ((ssr_status & 0x0080) && (scr_status & SCSCR_REIE))
731 ret = sci_er_interrupt(irq, ptr);
732 /* Break Interrupt */
733 if ((ssr_status & 0x0010) && (scr_status & SCSCR_REIE))
734 ret = sci_br_interrupt(irq, ptr);
739 #ifdef CONFIG_HAVE_CLK
741 * Here we define a transistion notifier so that we can update all of our
742 * ports' baud rate when the peripheral clock changes.
744 static int sci_notifier(struct notifier_block *self,
745 unsigned long phase, void *p)
747 struct sh_sci_priv *priv = container_of(self,
748 struct sh_sci_priv, clk_nb);
749 struct sci_port *sci_port;
752 if ((phase == CPUFREQ_POSTCHANGE) ||
753 (phase == CPUFREQ_RESUMECHANGE)) {
754 spin_lock_irqsave(&priv->lock, flags);
755 list_for_each_entry(sci_port, &priv->ports, node)
756 sci_port->port.uartclk = clk_get_rate(sci_port->dclk);
758 spin_unlock_irqrestore(&priv->lock, flags);
764 static void sci_clk_enable(struct uart_port *port)
766 struct sci_port *sci_port = to_sci_port(port);
768 clk_enable(sci_port->dclk);
769 sci_port->port.uartclk = clk_get_rate(sci_port->dclk);
772 clk_enable(sci_port->iclk);
775 static void sci_clk_disable(struct uart_port *port)
777 struct sci_port *sci_port = to_sci_port(port);
780 clk_disable(sci_port->iclk);
782 clk_disable(sci_port->dclk);
786 static int sci_request_irq(struct sci_port *port)
789 irqreturn_t (*handlers[4])(int irq, void *ptr) = {
790 sci_er_interrupt, sci_rx_interrupt, sci_tx_interrupt,
793 const char *desc[] = { "SCI Receive Error", "SCI Receive Data Full",
794 "SCI Transmit Data Empty", "SCI Break" };
796 if (port->irqs[0] == port->irqs[1]) {
797 if (unlikely(!port->irqs[0]))
800 if (request_irq(port->irqs[0], sci_mpxed_interrupt,
801 IRQF_DISABLED, "sci", port)) {
802 dev_err(port->port.dev, "Can't allocate IRQ\n");
806 for (i = 0; i < ARRAY_SIZE(handlers); i++) {
807 if (unlikely(!port->irqs[i]))
810 if (request_irq(port->irqs[i], handlers[i],
811 IRQF_DISABLED, desc[i], port)) {
812 dev_err(port->port.dev, "Can't allocate IRQ\n");
821 static void sci_free_irq(struct sci_port *port)
825 if (port->irqs[0] == port->irqs[1])
826 free_irq(port->irqs[0], port);
828 for (i = 0; i < ARRAY_SIZE(port->irqs); i++) {
832 free_irq(port->irqs[i], port);
837 static unsigned int sci_tx_empty(struct uart_port *port)
843 static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl)
845 /* This routine is used for seting signals of: DTR, DCD, CTS/RTS */
846 /* We use SCIF's hardware for CTS/RTS, so don't need any for that. */
847 /* If you have signals for DTR and DCD, please implement here. */
850 static unsigned int sci_get_mctrl(struct uart_port *port)
852 /* This routine is used for geting signals of: DTR, DCD, DSR, RI,
855 return TIOCM_DTR | TIOCM_RTS | TIOCM_DSR;
858 static void sci_start_tx(struct uart_port *port)
862 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */
863 ctrl = sci_in(port, SCSCR);
865 sci_out(port, SCSCR, ctrl);
868 static void sci_stop_tx(struct uart_port *port)
872 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */
873 ctrl = sci_in(port, SCSCR);
875 sci_out(port, SCSCR, ctrl);
878 static void sci_start_rx(struct uart_port *port, unsigned int tty_start)
882 /* Set RIE (Receive Interrupt Enable) bit in SCSCR */
883 ctrl = sci_in(port, SCSCR);
884 ctrl |= SCSCR_RIE | SCSCR_REIE;
885 sci_out(port, SCSCR, ctrl);
888 static void sci_stop_rx(struct uart_port *port)
892 /* Clear RIE (Receive Interrupt Enable) bit in SCSCR */
893 ctrl = sci_in(port, SCSCR);
894 ctrl &= ~(SCSCR_RIE | SCSCR_REIE);
895 sci_out(port, SCSCR, ctrl);
898 static void sci_enable_ms(struct uart_port *port)
900 /* Nothing here yet .. */
903 static void sci_break_ctl(struct uart_port *port, int break_state)
905 /* Nothing here yet .. */
908 static int sci_startup(struct uart_port *port)
910 struct sci_port *s = to_sci_port(port);
917 sci_start_rx(port, 1);
922 static void sci_shutdown(struct uart_port *port)
924 struct sci_port *s = to_sci_port(port);
934 static unsigned int sci_scbrr_calc(unsigned int algo_id, unsigned int bps,
939 return ((freq + 16 * bps) / (16 * bps) - 1);
941 return ((freq + 16 * bps) / (32 * bps) - 1);
943 return (((freq * 2) + 16 * bps) / (16 * bps) - 1);
945 return (((freq * 2) + 16 * bps) / (32 * bps) - 1);
947 return (((freq * 1000 / 32) / bps) - 1);
950 /* Warn, but use a safe default */
952 return ((freq + 16 * bps) / (32 * bps) - 1);
955 static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
956 struct ktermios *old)
958 struct sci_port *s = to_sci_port(port);
959 unsigned int status, baud, smr_val;
962 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
964 t = sci_scbrr_calc(s->scbrr_algo_id, baud, port->uartclk);
967 status = sci_in(port, SCxSR);
968 } while (!(status & SCxSR_TEND(port)));
970 sci_out(port, SCSCR, 0x00); /* TE=0, RE=0, CKE1=0 */
972 if (port->type != PORT_SCI)
973 sci_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST);
975 smr_val = sci_in(port, SCSMR) & 3;
976 if ((termios->c_cflag & CSIZE) == CS7)
978 if (termios->c_cflag & PARENB)
980 if (termios->c_cflag & PARODD)
982 if (termios->c_cflag & CSTOPB)
985 uart_update_timeout(port, termios->c_cflag, baud);
987 sci_out(port, SCSMR, smr_val);
991 sci_out(port, SCSMR, (sci_in(port, SCSMR) & ~3) | 1);
994 sci_out(port, SCSMR, sci_in(port, SCSMR) & ~3);
996 sci_out(port, SCBRR, t);
997 udelay((1000000+(baud-1)) / baud); /* Wait one bit interval */
1000 sci_init_pins(port, termios->c_cflag);
1001 sci_out(port, SCFCR, (termios->c_cflag & CRTSCTS) ? SCFCR_MCE : 0);
1003 sci_out(port, SCSCR, s->scscr);
1005 if ((termios->c_cflag & CREAD) != 0)
1006 sci_start_rx(port, 0);
1009 static const char *sci_type(struct uart_port *port)
1011 switch (port->type) {
1025 static void sci_release_port(struct uart_port *port)
1027 /* Nothing here yet .. */
1030 static int sci_request_port(struct uart_port *port)
1032 /* Nothing here yet .. */
1036 static void sci_config_port(struct uart_port *port, int flags)
1038 struct sci_port *s = to_sci_port(port);
1040 port->type = s->type;
1045 if (port->flags & UPF_IOREMAP) {
1046 port->membase = ioremap_nocache(port->mapbase, 0x40);
1048 if (IS_ERR(port->membase))
1049 dev_err(port->dev, "can't remap port#%d\n", port->line);
1052 * For the simple (and majority of) cases where we don't
1053 * need to do any remapping, just cast the cookie
1056 port->membase = (void __iomem *)port->mapbase;
1060 static int sci_verify_port(struct uart_port *port, struct serial_struct *ser)
1062 struct sci_port *s = to_sci_port(port);
1064 if (ser->irq != s->irqs[SCIx_TXI_IRQ] || ser->irq > nr_irqs)
1066 if (ser->baud_base < 2400)
1067 /* No paper tape reader for Mitch.. */
1073 static struct uart_ops sci_uart_ops = {
1074 .tx_empty = sci_tx_empty,
1075 .set_mctrl = sci_set_mctrl,
1076 .get_mctrl = sci_get_mctrl,
1077 .start_tx = sci_start_tx,
1078 .stop_tx = sci_stop_tx,
1079 .stop_rx = sci_stop_rx,
1080 .enable_ms = sci_enable_ms,
1081 .break_ctl = sci_break_ctl,
1082 .startup = sci_startup,
1083 .shutdown = sci_shutdown,
1084 .set_termios = sci_set_termios,
1086 .release_port = sci_release_port,
1087 .request_port = sci_request_port,
1088 .config_port = sci_config_port,
1089 .verify_port = sci_verify_port,
1090 #ifdef CONFIG_CONSOLE_POLL
1091 .poll_get_char = sci_poll_get_char,
1092 .poll_put_char = sci_poll_put_char,
1096 static void __devinit sci_init_single(struct platform_device *dev,
1097 struct sci_port *sci_port,
1099 struct plat_sci_port *p)
1101 sci_port->port.ops = &sci_uart_ops;
1102 sci_port->port.iotype = UPIO_MEM;
1103 sci_port->port.line = index;
1104 sci_port->port.fifosize = 1;
1106 #if defined(__H8300H__) || defined(__H8300S__)
1108 sci_port->enable = h8300_sci_enable;
1109 sci_port->disable = h8300_sci_disable;
1111 sci_port->port.uartclk = CONFIG_CPU_CLOCK;
1112 #elif defined(CONFIG_HAVE_CLK)
1113 sci_port->iclk = p->clk ? clk_get(&dev->dev, p->clk) : NULL;
1114 sci_port->dclk = clk_get(&dev->dev, "peripheral_clk");
1115 sci_port->enable = sci_clk_enable;
1116 sci_port->disable = sci_clk_disable;
1118 #error "Need a valid uartclk"
1121 sci_port->break_timer.data = (unsigned long)sci_port;
1122 sci_port->break_timer.function = sci_break_timer;
1123 init_timer(&sci_port->break_timer);
1125 sci_port->port.mapbase = p->mapbase;
1126 sci_port->port.membase = p->membase;
1128 sci_port->scscr = p->scscr;
1129 sci_port->port.irq = p->irqs[SCIx_TXI_IRQ];
1130 sci_port->port.flags = p->flags;
1131 sci_port->port.dev = &dev->dev;
1132 sci_port->type = sci_port->port.type = p->type;
1134 memcpy(&sci_port->irqs, &p->irqs, sizeof(p->irqs));
1137 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
1138 static struct tty_driver *serial_console_device(struct console *co, int *index)
1140 struct uart_driver *p = &sci_uart_driver;
1142 return p->tty_driver;
1145 static void serial_console_putchar(struct uart_port *port, int ch)
1147 sci_poll_put_char(port, ch);
1151 * Print a string to the serial port trying not to disturb
1152 * any possible real use of the port...
1154 static void serial_console_write(struct console *co, const char *s,
1157 struct uart_port *port = co->data;
1158 struct sci_port *sci_port = to_sci_port(port);
1159 unsigned short bits;
1161 if (sci_port->enable)
1162 sci_port->enable(port);
1164 uart_console_write(port, s, count, serial_console_putchar);
1166 /* wait until fifo is empty and last bit has been transmitted */
1167 bits = SCxSR_TDxE(port) | SCxSR_TEND(port);
1168 while ((sci_in(port, SCxSR) & bits) != bits)
1171 if (sci_port->disable);
1172 sci_port->disable(port);
1175 static int __init serial_console_setup(struct console *co, char *options)
1177 struct sci_port *sci_port;
1178 struct uart_port *port;
1186 * Check whether an invalid uart number has been specified, and
1187 * if so, search for the first available port that does have
1190 if (co->index >= SCI_NPORTS)
1193 sci_port = &sci_ports[co->index];
1194 port = &sci_port->port;
1198 * Also need to check port->type, we don't actually have any
1199 * UPIO_PORT ports, but uart_report_port() handily misreports
1200 * it anyways if we don't have a port available by the time this is
1206 sci_config_port(port, 0);
1208 if (sci_port->enable)
1209 sci_port->enable(port);
1212 uart_parse_options(options, &baud, &parity, &bits, &flow);
1214 ret = uart_set_options(port, co, baud, parity, bits, flow);
1215 #if defined(__H8300H__) || defined(__H8300S__)
1216 /* disable rx interrupt */
1220 /* TODO: disable clock */
1224 static struct console serial_console = {
1226 .device = serial_console_device,
1227 .write = serial_console_write,
1228 .setup = serial_console_setup,
1229 .flags = CON_PRINTBUFFER,
1233 static int __init sci_console_init(void)
1235 register_console(&serial_console);
1238 console_initcall(sci_console_init);
1239 #endif /* CONFIG_SERIAL_SH_SCI_CONSOLE */
1241 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE)
1242 #define SCI_CONSOLE (&serial_console)
1244 #define SCI_CONSOLE 0
1247 static char banner[] __initdata =
1248 KERN_INFO "SuperH SCI(F) driver initialized\n";
1250 static struct uart_driver sci_uart_driver = {
1251 .owner = THIS_MODULE,
1252 .driver_name = "sci",
1253 .dev_name = "ttySC",
1255 .minor = SCI_MINOR_START,
1257 .cons = SCI_CONSOLE,
1261 static int sci_remove(struct platform_device *dev)
1263 struct sh_sci_priv *priv = platform_get_drvdata(dev);
1265 unsigned long flags;
1267 #ifdef CONFIG_HAVE_CLK
1268 cpufreq_unregister_notifier(&priv->clk_nb, CPUFREQ_TRANSITION_NOTIFIER);
1271 spin_lock_irqsave(&priv->lock, flags);
1272 list_for_each_entry(p, &priv->ports, node)
1273 uart_remove_one_port(&sci_uart_driver, &p->port);
1275 spin_unlock_irqrestore(&priv->lock, flags);
1281 static int __devinit sci_probe_single(struct platform_device *dev,
1283 struct plat_sci_port *p,
1284 struct sci_port *sciport)
1286 struct sh_sci_priv *priv = platform_get_drvdata(dev);
1287 unsigned long flags;
1291 if (unlikely(index >= SCI_NPORTS)) {
1292 dev_notice(&dev->dev, "Attempting to register port "
1293 "%d when only %d are available.\n",
1294 index+1, SCI_NPORTS);
1295 dev_notice(&dev->dev, "Consider bumping "
1296 "CONFIG_SERIAL_SH_SCI_NR_UARTS!\n");
1300 sci_init_single(dev, sciport, index, p);
1302 ret = uart_add_one_port(&sci_uart_driver, &sciport->port);
1306 INIT_LIST_HEAD(&sciport->node);
1308 spin_lock_irqsave(&priv->lock, flags);
1309 list_add(&sciport->node, &priv->ports);
1310 spin_unlock_irqrestore(&priv->lock, flags);
1316 * Register a set of serial devices attached to a platform device. The
1317 * list is terminated with a zero flags entry, which means we expect
1318 * all entries to have at least UPF_BOOT_AUTOCONF set. Platforms that need
1319 * remapping (such as sh64) should also set UPF_IOREMAP.
1321 static int __devinit sci_probe(struct platform_device *dev)
1323 struct plat_sci_port *p = dev->dev.platform_data;
1324 struct sh_sci_priv *priv;
1325 int i, ret = -EINVAL;
1327 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
1331 INIT_LIST_HEAD(&priv->ports);
1332 spin_lock_init(&priv->lock);
1333 platform_set_drvdata(dev, priv);
1335 #ifdef CONFIG_HAVE_CLK
1336 priv->clk_nb.notifier_call = sci_notifier;
1337 cpufreq_register_notifier(&priv->clk_nb, CPUFREQ_TRANSITION_NOTIFIER);
1340 if (dev->id != -1) {
1341 ret = sci_probe_single(dev, dev->id, p, &sci_ports[dev->id]);
1345 for (i = 0; p && p->flags != 0; p++, i++) {
1346 ret = sci_probe_single(dev, i, p, &sci_ports[i]);
1352 #ifdef CONFIG_SH_STANDARD_BIOS
1353 sh_bios_gdb_detach();
1363 static int sci_suspend(struct device *dev)
1365 struct sh_sci_priv *priv = dev_get_drvdata(dev);
1367 unsigned long flags;
1369 spin_lock_irqsave(&priv->lock, flags);
1370 list_for_each_entry(p, &priv->ports, node)
1371 uart_suspend_port(&sci_uart_driver, &p->port);
1372 spin_unlock_irqrestore(&priv->lock, flags);
1377 static int sci_resume(struct device *dev)
1379 struct sh_sci_priv *priv = dev_get_drvdata(dev);
1381 unsigned long flags;
1383 spin_lock_irqsave(&priv->lock, flags);
1384 list_for_each_entry(p, &priv->ports, node)
1385 uart_resume_port(&sci_uart_driver, &p->port);
1386 spin_unlock_irqrestore(&priv->lock, flags);
1391 static struct dev_pm_ops sci_dev_pm_ops = {
1392 .suspend = sci_suspend,
1393 .resume = sci_resume,
1396 static struct platform_driver sci_driver = {
1398 .remove = __devexit_p(sci_remove),
1401 .owner = THIS_MODULE,
1402 .pm = &sci_dev_pm_ops,
1406 static int __init sci_init(void)
1412 ret = uart_register_driver(&sci_uart_driver);
1413 if (likely(ret == 0)) {
1414 ret = platform_driver_register(&sci_driver);
1416 uart_unregister_driver(&sci_uart_driver);
1422 static void __exit sci_exit(void)
1424 platform_driver_unregister(&sci_driver);
1425 uart_unregister_driver(&sci_uart_driver);
1428 module_init(sci_init);
1429 module_exit(sci_exit);
1431 MODULE_LICENSE("GPL");
1432 MODULE_ALIAS("platform:sh-sci");