drivers/phy/rockchip/phy-rockchip-usbdp.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * Rockchip USBDP Combo PHY with Samsung IP block driver
   4  *
   5  * Copyright (C) 2021 Rockchip Electronics Co., Ltd
   6  */
   7
   8 #include <common.h>
   9 #include <clk.h>
  10 #include <dm.h>
  11 #include <dm/device_compat.h>
  12 #include <dm/devres.h>
  13 #include <dm/lists.h>
  14 #include <dm/of.h>
  15 #include <dm/of_access.h>
  16 #include <generic-phy.h>
  17 #include <linux/bitfield.h>
  18 #include <linux/usb/ch9.h>
  19 #include <linux/usb/otg.h>
  20 #include <regmap.h>
  21 #include <reset.h>
  22 #include <syscon.h>
  23 #include <asm/arch-rockchip/clock.h>
  24
  25 #include <linux/usb/phy-rockchip-usbdp.h>
  26
  27 #define BIT_WRITEABLE_SHIFT     16
  28
  29 enum {
  30         UDPHY_MODE_NONE         = 0,
  31         UDPHY_MODE_USB          = BIT(0),
  32         UDPHY_MODE_DP           = BIT(1),
  33         UDPHY_MODE_DP_USB       = BIT(1) | BIT(0),
  34 };
  35
  36 struct udphy_grf_reg {
  37         unsigned int    offset;
  38         unsigned int    bitend;
  39         unsigned int    bitstart;
  40         unsigned int    disable;
  41         unsigned int    enable;
  42 };
  43
  44 /**
  45  * struct reg_sequence - An individual write from a sequence of writes.
  46  *
  47  * @reg: Register address.
  48  * @def: Register value.
  49  * @delay_us: Delay to be applied after the register write in microseconds
  50  *
  51  * Register/value pairs for sequences of writes with an optional delay in
  52  * microseconds to be applied after each write.
  53  */
  54 struct reg_sequence {
  55         unsigned int reg;
  56         unsigned int def;
  57         unsigned int delay_us;
  58 };
  59
  60 struct udphy_grf_cfg {
  61         /* u2phy-grf */
  62         struct udphy_grf_reg    bvalid_phy_con;
  63         struct udphy_grf_reg    bvalid_grf_con;
  64
  65         /* usb-grf */
  66         struct udphy_grf_reg    usb3otg0_cfg;
  67         struct udphy_grf_reg    usb3otg1_cfg;
  68
  69         /* usbdpphy-grf */
  70         struct udphy_grf_reg    low_pwrn;
  71         struct udphy_grf_reg    rx_lfps;
  72 };
  73
  74 struct rockchip_udphy;
  75
  76 struct rockchip_udphy_cfg {
  77         unsigned int num_phys;
  78         unsigned int phy_ids[2];
  79         /* resets to be requested */
  80         const char * const *rst_list;
  81         int num_rsts;
  82
  83         struct udphy_grf_cfg grfcfg;
  84         int (*combophy_init)(struct rockchip_udphy *udphy);
  85 };
  86
  87 struct rockchip_udphy {
  88         struct udevice *dev;
  89         struct regmap *pma_regmap;
  90         struct regmap *u2phygrf;
  91         struct regmap *udphygrf;
  92         struct regmap *usbgrf;
  93         struct regmap *vogrf;
  94
  95         /* clocks and rests */
  96         struct reset_ctl *rsts;
  97
  98         /* PHY status management */
  99         bool flip;
 100         bool mode_change;
 101         u8 mode;
 102         u8 status;
 103
 104         /* utilized for USB */
 105         bool hs; /* flag for high-speed */
 106
 107         /* utilized for DP */
 108         struct gpio_desc *sbu1_dc_gpio;
 109         struct gpio_desc *sbu2_dc_gpio;
 110         u32 lane_mux_sel[4];
 111         u32 dp_lane_sel[4];
 112         u32 dp_aux_dout_sel;
 113         u32 dp_aux_din_sel;
 114         int id;
 115
 116         /* PHY const config */
 117         const struct rockchip_udphy_cfg *cfgs;
 118 };
 119
 120 static const struct reg_sequence rk3588_udphy_24m_refclk_cfg[] = {
 121         {0x0090, 0x68}, {0x0094, 0x68},
 122         {0x0128, 0x24}, {0x012c, 0x44},
 123         {0x0130, 0x3f}, {0x0134, 0x44},
 124         {0x015c, 0xa9}, {0x0160, 0x71},
 125         {0x0164, 0x71}, {0x0168, 0xa9},
 126         {0x0174, 0xa9}, {0x0178, 0x71},
 127         {0x017c, 0x71}, {0x0180, 0xa9},
 128         {0x018c, 0x41}, {0x0190, 0x00},
 129         {0x0194, 0x05}, {0x01ac, 0x2a},
 130         {0x01b0, 0x17}, {0x01b4, 0x17},
 131         {0x01b8, 0x2a}, {0x01c8, 0x04},
 132         {0x01cc, 0x08}, {0x01d0, 0x08},
 133         {0x01d4, 0x04}, {0x01d8, 0x20},
 134         {0x01dc, 0x01}, {0x01e0, 0x09},
 135         {0x01e4, 0x03}, {0x01f0, 0x29},
 136         {0x01f4, 0x02}, {0x01f8, 0x02},
 137         {0x01fc, 0x29}, {0x0208, 0x2a},
 138         {0x020c, 0x17}, {0x0210, 0x17},
 139         {0x0214, 0x2a}, {0x0224, 0x20},
 140         {0x03f0, 0x0d}, {0x03f4, 0x09},
 141         {0x03f8, 0x09}, {0x03fc, 0x0d},
 142         {0x0404, 0x0e}, {0x0408, 0x14},
 143         {0x040c, 0x14}, {0x0410, 0x3b},
 144         {0x0ce0, 0x68}, {0x0ce8, 0xd0},
 145         {0x0cf0, 0x87}, {0x0cf8, 0x70},
 146         {0x0d00, 0x70}, {0x0d08, 0xa9},
 147         {0x1ce0, 0x68}, {0x1ce8, 0xd0},
 148         {0x1cf0, 0x87}, {0x1cf8, 0x70},
 149         {0x1d00, 0x70}, {0x1d08, 0xa9},
 150         {0x0a3c, 0xd0}, {0x0a44, 0xd0},
 151         {0x0a48, 0x01}, {0x0a4c, 0x0d},
 152         {0x0a54, 0xe0}, {0x0a5c, 0xe0},
 153         {0x0a64, 0xa8}, {0x1a3c, 0xd0},
 154         {0x1a44, 0xd0}, {0x1a48, 0x01},
 155         {0x1a4c, 0x0d}, {0x1a54, 0xe0},
 156         {0x1a5c, 0xe0}, {0x1a64, 0xa8}
 157 };
 158
 159 static const struct reg_sequence rk3588_udphy_init_sequence[] = {
 160         {0x0104, 0x44}, {0x0234, 0xE8},
 161         {0x0248, 0x44}, {0x028C, 0x18},
 162         {0x081C, 0xE5}, {0x0878, 0x00},
 163         {0x0994, 0x1C}, {0x0AF0, 0x00},
 164         {0x181C, 0xE5}, {0x1878, 0x00},
 165         {0x1994, 0x1C}, {0x1AF0, 0x00},
 166         {0x0428, 0x60}, {0x0D58, 0x33},
 167         {0x1D58, 0x33}, {0x0990, 0x74},
 168         {0x0D64, 0x17}, {0x08C8, 0x13},
 169         {0x1990, 0x74}, {0x1D64, 0x17},
 170         {0x18C8, 0x13}, {0x0D90, 0x40},
 171         {0x0DA8, 0x40}, {0x0DC0, 0x40},
 172         {0x0DD8, 0x40}, {0x1D90, 0x40},
 173         {0x1DA8, 0x40}, {0x1DC0, 0x40},
 174         {0x1DD8, 0x40}, {0x03C0, 0x30},
 175         {0x03C4, 0x06}, {0x0E10, 0x00},
 176         {0x1E10, 0x00}, {0x043C, 0x0F},
 177         {0x0D2C, 0xFF}, {0x1D2C, 0xFF},
 178         {0x0D34, 0x0F}, {0x1D34, 0x0F},
 179         {0x08FC, 0x2A}, {0x0914, 0x28},
 180         {0x0A30, 0x03}, {0x0E38, 0x05},
 181         {0x0ECC, 0x27}, {0x0ED0, 0x22},
 182         {0x0ED4, 0x26}, {0x18FC, 0x2A},
 183         {0x1914, 0x28}, {0x1A30, 0x03},
 184         {0x1E38, 0x05}, {0x1ECC, 0x27},
 185         {0x1ED0, 0x22}, {0x1ED4, 0x26},
 186         {0x0048, 0x0F}, {0x0060, 0x3C},
 187         {0x0064, 0xF7}, {0x006C, 0x20},
 188         {0x0070, 0x7D}, {0x0074, 0x68},
 189         {0x0AF4, 0x1A}, {0x1AF4, 0x1A},
 190         {0x0440, 0x3F}, {0x10D4, 0x08},
 191         {0x20D4, 0x08}, {0x00D4, 0x30},
 192         {0x0024, 0x6e},
 193 };
 194
 195 static inline int grfreg_write(struct regmap *base,
 196                                const struct udphy_grf_reg *reg, bool en)
 197 {
 198         u32 val, mask, tmp;
 199
 200         tmp = en ? reg->enable : reg->disable;
 201         mask = GENMASK(reg->bitend, reg->bitstart);
 202         val = (tmp << reg->bitstart) | (mask << BIT_WRITEABLE_SHIFT);
 203
 204         return regmap_write(base, reg->offset, val);
 205 }
 206
 207 static int __regmap_multi_reg_write(struct regmap *map,
 208                                     const struct reg_sequence *regs,
 209                                     int num_regs)
 210 {
 211         int i, ret = 0;
 212
 213         for (i = 0; i < num_regs; i++) {
 214                 ret = regmap_write(map, regs[i].reg, regs[i].def);
 215
 216                 if (regs[i].delay_us)
 217                         udelay(regs[i].delay_us);
 218         }
 219
 220         return ret;
 221 }
 222
 223 static int udphy_clk_init(struct rockchip_udphy *udphy, struct udevice *dev)
 224 {
 225         return 0;
 226 }
 227
 228 static int udphy_reset_init(struct rockchip_udphy *udphy, struct udevice *dev)
 229 {
 230         const struct rockchip_udphy_cfg *cfg = udphy->cfgs;
 231         int idx;
 232         int ret;
 233
 234         udphy->rsts = devm_kcalloc(dev, cfg->num_rsts,
 235                                    sizeof(*udphy->rsts), GFP_KERNEL);
 236         if (!udphy->rsts)
 237                 return -ENOMEM;
 238
 239         for (idx = 0; idx < cfg->num_rsts; idx++) {
 240                 const char *name = cfg->rst_list[idx];
 241
 242                 ret = reset_get_by_name(dev, name, &udphy->rsts[idx]);
 243                 if (ret) {
 244                         dev_err(dev, "failed to get %s reset\n", name);
 245                         goto err;
 246                 }
 247
 248                 reset_assert(&udphy->rsts[idx]);
 249         }
 250
 251         return 0;
 252
 253 err:
 254         devm_kfree(dev, udphy->rsts);
 255         return ret;
 256 }
 257
 258 static int udphy_get_rst_idx(const char * const *list, int num, char *name)
 259 {
 260         int idx;
 261
 262         for (idx = 0; idx < num; idx++) {
 263                 if (!strcmp(list[idx], name))
 264                         return idx;
 265         }
 266
 267         return -EINVAL;
 268 }
 269
 270 static int udphy_reset_assert(struct rockchip_udphy *udphy, char *name)
 271 {
 272         const struct rockchip_udphy_cfg *cfg = udphy->cfgs;
 273         int idx;
 274
 275         idx = udphy_get_rst_idx(cfg->rst_list, cfg->num_rsts, name);
 276         if (idx < 0)
 277                 return idx;
 278
 279         return reset_assert(&udphy->rsts[idx]);
 280 }
 281
 282 static int udphy_reset_deassert(struct rockchip_udphy *udphy, char *name)
 283 {
 284         const struct rockchip_udphy_cfg *cfg = udphy->cfgs;
 285         int idx;
 286
 287         idx = udphy_get_rst_idx(cfg->rst_list, cfg->num_rsts, name);
 288         if (idx < 0)
 289                 return idx;
 290
 291         return reset_deassert(&udphy->rsts[idx]);
 292 }
 293
 294 static void udphy_u3_port_disable(struct rockchip_udphy *udphy, u8 disable)
 295 {
 296         const struct rockchip_udphy_cfg *cfg = udphy->cfgs;
 297         const struct udphy_grf_reg *preg;
 298
 299         preg = udphy->id ? &cfg->grfcfg.usb3otg1_cfg : &cfg->grfcfg.usb3otg0_cfg;
 300         grfreg_write(udphy->usbgrf, preg, disable);
 301 }
 302
 303 __maybe_unused
 304 static void udphy_usb_bvalid_enable(struct rockchip_udphy *udphy, u8 enable)
 305 {
 306         const struct rockchip_udphy_cfg *cfg = udphy->cfgs;
 307
 308         grfreg_write(udphy->u2phygrf, &cfg->grfcfg.bvalid_phy_con, enable);
 309         grfreg_write(udphy->u2phygrf, &cfg->grfcfg.bvalid_grf_con, enable);
 310 }
 311
 312 /*
 313  * In usb/dp combo phy driver, here are 2 ways to mapping lanes.
 314  *
 315  * 1 Type-C Mapping table (DP_Alt_Mode V1.0b remove ABF pin mapping)
 316  * ---------------------------------------------------------------------------
 317  * Type-C Pin   B11-B10       A2-A3       A11-A10       B2-B3
 318  * PHY Pad      ln0(tx/rx)    ln1(tx)     ln2(tx/rx)    ln3(tx)
 319  * C/E(Normal)  dpln3         dpln2       dpln0         dpln1
 320  * C/E(Flip  )  dpln0         dpln1       dpln3         dpln2
 321  * D/F(Normal)  usbrx         usbtx       dpln0         dpln1
 322  * D/F(Flip  )  dpln0         dpln1       usbrx         usbtx
 323  * A(Normal  )  dpln3         dpln1       dpln2         dpln0
 324  * A(Flip    )  dpln2         dpln0       dpln3         dpln1
 325  * B(Normal  )  usbrx         usbtx       dpln1         dpln0
 326  * B(Flip    )  dpln1         dpln0       usbrx         usbtx
 327  * ---------------------------------------------------------------------------
 328  *
 329  * 2 Mapping the lanes in dtsi
 330  * if all 4 lane assignment for dp function, define rockchip,dp-lane-mux = <x x x x>;
 331  * sample as follow:
 332  * ---------------------------------------------------------------------------
 333  *                        B11-B10       A2-A3       A11-A10       B2-B3
 334  * rockchip,dp-lane-mux   ln0(tx/rx)    ln1(tx)     ln2(tx/rx)    ln3(tx)
 335  * <0 1 2 3>              dpln0         dpln1       dpln2         dpln3
 336  * <2 3 0 1>              dpln2         dpln3       dpln0         dpln1
 337  * ---------------------------------------------------------------------------
 338  * if 2 lane for dp function, 2 lane for usb function, define rockchip,dp-lane-mux = <x x>;
 339  * sample as follow:
 340  * ---------------------------------------------------------------------------
 341  *                        B11-B10       A2-A3       A11-A10       B2-B3
 342  * rockchip,dp-lane-mux   ln0(tx/rx)    ln1(tx)     ln2(tx/rx)    ln3(tx)
 343  * <0 1>                  dpln0         dpln1       usbrx         usbtx
 344  * <2 3>                  usbrx         usbtx       dpln0         dpln1
 345  * ---------------------------------------------------------------------------
 346  */
 347
 348 __maybe_unused
 349 static int upphy_set_typec_default_mapping(struct rockchip_udphy *udphy)
 350 {
 351         if (udphy->flip) {
 352                 udphy->dp_lane_sel[0] = 0;
 353                 udphy->dp_lane_sel[1] = 1;
 354                 udphy->dp_lane_sel[2] = 3;
 355                 udphy->dp_lane_sel[3] = 2;
 356                 udphy->lane_mux_sel[0] = PHY_LANE_MUX_DP;
 357                 udphy->lane_mux_sel[1] = PHY_LANE_MUX_DP;
 358                 udphy->lane_mux_sel[2] = PHY_LANE_MUX_USB;
 359                 udphy->lane_mux_sel[3] = PHY_LANE_MUX_USB;
 360                 udphy->dp_aux_dout_sel = PHY_AUX_DP_DATA_POL_INVERT;
 361                 udphy->dp_aux_din_sel = PHY_AUX_DP_DATA_POL_INVERT;
 362         } else {
 363                 udphy->dp_lane_sel[0] = 2;
 364                 udphy->dp_lane_sel[1] = 3;
 365                 udphy->dp_lane_sel[2] = 1;
 366                 udphy->dp_lane_sel[3] = 0;
 367                 udphy->lane_mux_sel[0] = PHY_LANE_MUX_USB;
 368                 udphy->lane_mux_sel[1] = PHY_LANE_MUX_USB;
 369                 udphy->lane_mux_sel[2] = PHY_LANE_MUX_DP;
 370                 udphy->lane_mux_sel[3] = PHY_LANE_MUX_DP;
 371                 udphy->dp_aux_dout_sel = PHY_AUX_DP_DATA_POL_NORMAL;
 372                 udphy->dp_aux_din_sel = PHY_AUX_DP_DATA_POL_NORMAL;
 373         }
 374
 375         udphy->mode = UDPHY_MODE_DP_USB;
 376
 377         return 0;
 378 }
 379
 380 static int udphy_setup(struct rockchip_udphy *udphy)
 381 {
 382         const struct rockchip_udphy_cfg *cfg = udphy->cfgs;
 383         int ret = 0;
 384
 385         if (cfg->combophy_init) {
 386                 ret = cfg->combophy_init(udphy);
 387                 if (ret)
 388                         dev_err(udphy->dev, "failed to init usbdp combophy\n");
 389         }
 390
 391         return ret;
 392 }
 393
 394 static int udphy_disable(struct rockchip_udphy *udphy)
 395 {
 396         const struct rockchip_udphy_cfg *cfg = udphy->cfgs;
 397         int i;
 398
 399         for (i = 0; i < cfg->num_rsts; i++)
 400                 reset_assert(&udphy->rsts[i]);
 401
 402         return 0;
 403 }
 404
 405 static int udphy_parse_lane_mux_data(struct rockchip_udphy *udphy,
 406                                      const struct device_node *np)
 407 {
 408         struct property *prop;
 409         int ret, i, len, num_lanes;
 410
 411         prop = of_find_property(np, "rockchip,dp-lane-mux", &len);
 412         if (!prop) {
 413                 dev_dbg(udphy->dev,
 414                         "failed to find dp lane mux, following dp alt mode\n");
 415                 udphy->mode = UDPHY_MODE_USB;
 416                 return 0;
 417         }
 418
 419         num_lanes = len / sizeof(u32);
 420
 421         if (num_lanes != 2 && num_lanes != 4) {
 422                 dev_err(udphy->dev, "invalid number of lane mux\n");
 423                 return -EINVAL;
 424         }
 425
 426         ret = of_read_u32_array(np, "rockchip,dp-lane-mux", udphy->dp_lane_sel,
 427                                 num_lanes);
 428         if (ret) {
 429                 dev_err(udphy->dev, "get dp lane mux failed\n");
 430                 return -EINVAL;
 431         }
 432
 433         for (i = 0; i < num_lanes; i++) {
 434                 int j;
 435
 436                 if (udphy->dp_lane_sel[i] > 3) {
 437                         dev_err(udphy->dev,
 438                                 "lane mux between 0 and 3, exceeding the range\n");
 439                         return -EINVAL;
 440                 }
 441
 442                 udphy->lane_mux_sel[udphy->dp_lane_sel[i]] = PHY_LANE_MUX_DP;
 443
 444                 for (j = i + 1; j < num_lanes; j++) {
 445                         if (udphy->dp_lane_sel[i] == udphy->dp_lane_sel[j]) {
 446                                 dev_err(udphy->dev,
 447                                         "set repeat lane mux value\n");
 448                                 return -EINVAL;
 449                         }
 450                 }
 451         }
 452
 453         udphy->mode = UDPHY_MODE_DP;
 454         if (num_lanes == 2)
 455                 udphy->mode |= UDPHY_MODE_USB;
 456
 457         return 0;
 458 }
 459
 460 static int udphy_parse_dt(struct rockchip_udphy *udphy, struct udevice *dev)
 461 {
 462         const struct device_node *np = ofnode_to_np(dev_ofnode(dev));
 463         enum usb_device_speed maximum_speed;
 464         int ret;
 465
 466         udphy->u2phygrf = syscon_regmap_lookup_by_phandle(dev,
 467                                                           "rockchip,u2phy-grf");
 468         if (IS_ERR(udphy->u2phygrf)) {
 469                 if (PTR_ERR(udphy->u2phygrf) == -ENODEV) {
 470                         dev_warn(dev, "missing u2phy-grf dt node\n");
 471                         udphy->u2phygrf = NULL;
 472                 } else {
 473                         return PTR_ERR(udphy->u2phygrf);
 474                 }
 475         }
 476
 477         udphy->udphygrf = syscon_regmap_lookup_by_phandle(dev,
 478                                                           "rockchip,usbdpphy-grf");
 479         if (IS_ERR(udphy->udphygrf)) {
 480                 if (PTR_ERR(udphy->udphygrf) == -ENODEV) {
 481                         dev_warn(dev, "missing usbdpphy-grf dt node\n");
 482                         udphy->udphygrf = NULL;
 483                 } else {
 484                         return PTR_ERR(udphy->udphygrf);
 485                 }
 486         }
 487
 488         udphy->usbgrf = syscon_regmap_lookup_by_phandle(dev,
 489                                                         "rockchip,usb-grf");
 490         if (IS_ERR(udphy->usbgrf)) {
 491                 if (PTR_ERR(udphy->usbgrf) == -ENODEV) {
 492                         dev_warn(dev, "missing usb-grf dt node\n");
 493                         udphy->usbgrf = NULL;
 494                 } else {
 495                         return PTR_ERR(udphy->usbgrf);
 496                 }
 497         }
 498
 499         udphy->vogrf = syscon_regmap_lookup_by_phandle(dev, "rockchip,vo-grf");
 500         if (IS_ERR(udphy->vogrf)) {
 501                 if (PTR_ERR(udphy->vogrf) == -ENODEV) {
 502                         dev_warn(dev, "missing vo-grf dt node\n");
 503                         udphy->vogrf = NULL;
 504                 } else {
 505                         return PTR_ERR(udphy->vogrf);
 506                 }
 507         }
 508
 509         ret = udphy_parse_lane_mux_data(udphy, np);
 510         if (ret)
 511                 return ret;
 512
 513         if (dev_read_prop(dev, "maximum-speed", NULL)) {
 514                 maximum_speed = usb_get_maximum_speed(dev_ofnode(dev));
 515                 udphy->hs = maximum_speed <= USB_SPEED_HIGH ? true : false;
 516         }
 517
 518         ret = udphy_clk_init(udphy, dev);
 519         if (ret)
 520                 return ret;
 521
 522         ret = udphy_reset_init(udphy, dev);
 523         if (ret)
 524                 return ret;
 525
 526         return 0;
 527 }
 528
 529 static int udphy_power_on(struct rockchip_udphy *udphy, u8 mode)
 530 {
 531         int ret;
 532
 533         if (!(udphy->mode & mode)) {
 534                 dev_info(udphy->dev, "mode 0x%02x is not support\n", mode);
 535                 return 0;
 536         }
 537
 538         if (udphy->status == UDPHY_MODE_NONE) {
 539                 udphy->mode_change = false;
 540                 ret = udphy_setup(udphy);
 541                 if (ret)
 542                         return ret;
 543
 544                 if (udphy->mode & UDPHY_MODE_USB)
 545                         udphy_u3_port_disable(udphy, false);
 546         } else if (udphy->mode_change) {
 547                 udphy->mode_change = false;
 548                 udphy->status = UDPHY_MODE_NONE;
 549                 if (udphy->mode == UDPHY_MODE_DP)
 550                         udphy_u3_port_disable(udphy, true);
 551
 552                 ret = udphy_disable(udphy);
 553                 if (ret)
 554                         return ret;
 555                 ret = udphy_setup(udphy);
 556                 if (ret)
 557                         return ret;
 558         }
 559
 560         udphy->status |= mode;
 561
 562         return 0;
 563 }
 564
 565 static int udphy_power_off(struct rockchip_udphy *udphy, u8 mode)
 566 {
 567         int ret;
 568
 569         if (!(udphy->mode & mode)) {
 570                 dev_info(udphy->dev, "mode 0x%02x is not supported\n", mode);
 571                 return 0;
 572         }
 573
 574         if (!udphy->status)
 575                 return 0;
 576
 577         udphy->status &= ~mode;
 578
 579         if (udphy->status == UDPHY_MODE_NONE) {
 580                 ret = udphy_disable(udphy);
 581                 if (ret)
 582                         return ret;
 583         }
 584
 585         return 0;
 586 }
 587
 588 static int rockchip_u3phy_init(struct phy *phy)
 589 {
 590         struct udevice *parent = phy->dev->parent;
 591         struct rockchip_udphy *udphy = dev_get_priv(parent);
 592
 593         /* DP only or high-speed, disable U3 port */
 594         if (!(udphy->mode & UDPHY_MODE_USB) || udphy->hs) {
 595                 udphy_u3_port_disable(udphy, true);
 596                 return 0;
 597         }
 598
 599         return udphy_power_on(udphy, UDPHY_MODE_USB);
 600 }
 601
 602 static int rockchip_u3phy_exit(struct phy *phy)
 603 {
 604         struct udevice *parent = phy->dev->parent;
 605         struct rockchip_udphy *udphy = dev_get_priv(parent);
 606
 607         /* DP only or high-speed */
 608         if (!(udphy->mode & UDPHY_MODE_USB) || udphy->hs)
 609                 return 0;
 610
 611         return udphy_power_off(udphy, UDPHY_MODE_USB);
 612 }
 613
 614 static const struct phy_ops rockchip_u3phy_ops = {
 615         .init           = rockchip_u3phy_init,
 616         .exit           = rockchip_u3phy_exit,
 617 };
 618
 619 static int rockchip_udphy_probe(struct udevice *dev)
 620 {
 621         struct rockchip_udphy *udphy = dev_get_priv(dev);
 622         const struct rockchip_udphy_cfg *phy_cfgs;
 623         unsigned int reg;
 624         int id, ret;
 625
 626         udphy->dev = dev;
 627
 628         ret = ofnode_read_u32_index(dev_ofnode(dev), "reg", 0, &reg);
 629         if (ret) {
 630                 dev_err(dev, "failed to read reg[0] property\n");
 631                 return ret;
 632         }
 633         if (reg == 0 && dev_read_addr_cells(dev) == 2) {
 634                 ret = ofnode_read_u32_index(dev_ofnode(dev), "reg", 1, &reg);
 635                 if (ret) {
 636                         dev_err(dev, "failed to read reg[1] property\n");
 637                         return ret;
 638                 }
 639         }
 640
 641         phy_cfgs = (const struct rockchip_udphy_cfg *)dev_get_driver_data(dev);
 642         if (!phy_cfgs) {
 643                 dev_err(dev, "unable to get phy_cfgs\n");
 644                 return -EINVAL;
 645         }
 646         udphy->cfgs = phy_cfgs;
 647
 648         /* find the phy-id from the io address */
 649         udphy->id = -ENODEV;
 650         for (id = 0; id < udphy->cfgs->num_phys; id++) {
 651                 if (reg == udphy->cfgs->phy_ids[id]) {
 652                         udphy->id = id;
 653                         break;
 654                 }
 655         }
 656
 657         if (udphy->id < 0) {
 658                 dev_err(dev, "no matching device found\n");
 659                 return -ENODEV;
 660         }
 661
 662         ret = regmap_init_mem(dev_ofnode(dev), &udphy->pma_regmap);
 663         if (ret)
 664                 return ret;
 665         udphy->pma_regmap->ranges[0].start += UDPHY_PMA;
 666
 667         ret = udphy_parse_dt(udphy, dev);
 668         if (ret)
 669                 return ret;
 670
 671         return 0;
 672 }
 673
 674 static int rockchip_udphy_bind(struct udevice *parent)
 675 {
 676         struct udevice *child;
 677         ofnode subnode;
 678         const char *node_name;
 679         int ret;
 680
 681         dev_for_each_subnode(subnode, parent) {
 682                 if (!ofnode_valid(subnode)) {
 683                         printf("%s: no subnode for %s", __func__, parent->name);
 684                         return -ENXIO;
 685                 }
 686
 687                 node_name = ofnode_get_name(subnode);
 688                 debug("%s: subnode %s\n", __func__, node_name);
 689
 690                 /* if there is no match, continue */
 691                 if (strcasecmp(node_name, "usb3-port"))
 692                         continue;
 693
 694                 /* node name is usb3-port */
 695                 ret = device_bind_driver_to_node(parent,
 696                                                  "rockchip_udphy_u3_port",
 697                                                  node_name, subnode, &child);
 698                 if (ret) {
 699                         printf("%s: '%s' cannot bind its driver\n",
 700                                __func__, node_name);
 701                         return ret;
 702                 }
 703         }
 704
 705         return 0;
 706 }
 707
 708 static int rk3588_udphy_refclk_set(struct rockchip_udphy *udphy)
 709 {
 710         /* configure phy reference clock */
 711         return __regmap_multi_reg_write(udphy->pma_regmap,
 712                                         rk3588_udphy_24m_refclk_cfg,
 713                                         ARRAY_SIZE(rk3588_udphy_24m_refclk_cfg));
 714 }
 715
 716 static int rk3588_udphy_status_check(struct rockchip_udphy *udphy)
 717 {
 718         unsigned int val;
 719         int ret;
 720
 721         if (!(udphy->mode & UDPHY_MODE_USB))
 722                 return 0;
 723
 724         /* LCPLL check */
 725         ret = regmap_read_poll_timeout(udphy->pma_regmap,
 726                                        CMN_ANA_LCPLL_DONE_OFFSET,
 727                                        val, (val & CMN_ANA_LCPLL_AFC_DONE) &&
 728                                        (val & CMN_ANA_LCPLL_LOCK_DONE),
 729                                        200, 100);
 730         if (ret) {
 731                 dev_err(udphy->dev, "cmn ana lcpll lock timeout\n");
 732                 return ret;
 733         }
 734
 735         if (!udphy->flip) {
 736                 ret = regmap_read_poll_timeout(udphy->pma_regmap,
 737                                                TRSV_LN0_MON_RX_CDR_DONE_OFFSET,
 738                                                val,
 739                                                val & TRSV_LN0_MON_RX_CDR_LOCK_DONE,
 740                                                200, 100);
 741                 if (ret)
 742                         dev_err(udphy->dev, "trsv ln0 mon rx cdr lock timeout\n");
 743         } else {
 744                 ret = regmap_read_poll_timeout(udphy->pma_regmap,
 745                                                TRSV_LN2_MON_RX_CDR_DONE_OFFSET,
 746                                                val,
 747                                                val & TRSV_LN2_MON_RX_CDR_LOCK_DONE,
 748                                                200, 100);
 749                 if (ret)
 750                         dev_err(udphy->dev, "trsv ln2 mon rx cdr lock timeout\n");
 751         }
 752
 753         return 0;
 754 }
 755
 756 static int rk3588_udphy_init(struct rockchip_udphy *udphy)
 757 {
 758         const struct rockchip_udphy_cfg *cfg = udphy->cfgs;
 759         int ret;
 760
 761         /* enable rx lfps for usb */
 762         if (udphy->mode & UDPHY_MODE_USB)
 763                 grfreg_write(udphy->udphygrf, &cfg->grfcfg.rx_lfps, true);
 764
 765         /* Step 1: power on pma and deassert apb rstn */
 766         grfreg_write(udphy->udphygrf, &cfg->grfcfg.low_pwrn, true);
 767
 768         udphy_reset_deassert(udphy, "pma_apb");
 769         udphy_reset_deassert(udphy, "pcs_apb");
 770
 771         /* Step 2: set init sequence and phy refclk */
 772         ret = __regmap_multi_reg_write(udphy->pma_regmap,
 773                                        rk3588_udphy_init_sequence,
 774                                        ARRAY_SIZE(rk3588_udphy_init_sequence));
 775         if (ret) {
 776                 dev_err(udphy->dev, "init sequence set error %d\n", ret);
 777                 goto assert_apb;
 778         }
 779
 780         ret = rk3588_udphy_refclk_set(udphy);
 781         if (ret) {
 782                 dev_err(udphy->dev, "refclk set error %d\n", ret);
 783                 goto assert_apb;
 784         }
 785
 786         /* Step 3: configure lane mux */
 787         regmap_update_bits(udphy->pma_regmap, CMN_LANE_MUX_AND_EN_OFFSET,
 788                            CMN_DP_LANE_MUX_ALL | CMN_DP_LANE_EN_ALL,
 789                            FIELD_PREP(CMN_DP_LANE_MUX_N(3),
 790                                       udphy->lane_mux_sel[3]) |
 791                            FIELD_PREP(CMN_DP_LANE_MUX_N(2),
 792                                       udphy->lane_mux_sel[2]) |
 793                            FIELD_PREP(CMN_DP_LANE_MUX_N(1),
 794                                       udphy->lane_mux_sel[1]) |
 795                            FIELD_PREP(CMN_DP_LANE_MUX_N(0),
 796                                       udphy->lane_mux_sel[0]) |
 797                            FIELD_PREP(CMN_DP_LANE_EN_ALL, 0));
 798
 799         /* Step 4: deassert init rstn and wait for 200ns from datasheet */
 800         if (udphy->mode & UDPHY_MODE_USB)
 801                 udphy_reset_deassert(udphy, "init");
 802
 803         if (udphy->mode & UDPHY_MODE_DP) {
 804                 regmap_update_bits(udphy->pma_regmap, CMN_DP_RSTN_OFFSET,
 805                                    CMN_DP_INIT_RSTN,
 806                                    FIELD_PREP(CMN_DP_INIT_RSTN, 0x1));
 807         }
 808
 809         udelay(1);
 810
 811         /*  Step 5: deassert cmn/lane rstn */
 812         if (udphy->mode & UDPHY_MODE_USB) {
 813                 udphy_reset_deassert(udphy, "cmn");
 814                 udphy_reset_deassert(udphy, "lane");
 815         }
 816
 817         /*  Step 6: wait for lock done of pll */
 818         ret = rk3588_udphy_status_check(udphy);
 819         if (ret)
 820                 goto assert_phy;
 821
 822         return 0;
 823
 824 assert_phy:
 825         udphy_reset_assert(udphy, "init");
 826         udphy_reset_assert(udphy, "cmn");
 827         udphy_reset_assert(udphy, "lane");
 828
 829 assert_apb:
 830         udphy_reset_assert(udphy, "pma_apb");
 831         udphy_reset_assert(udphy, "pcs_apb");
 832
 833         return ret;
 834 }
 835
 836 static const char * const rk3588_udphy_rst_l[] = {
 837         "init", "cmn", "lane", "pcs_apb", "pma_apb"
 838 };
 839
 840 static const struct rockchip_udphy_cfg rk3588_udphy_cfgs = {
 841         .num_phys = 2,
 842         .phy_ids = {
 843                 0xfed80000,
 844                 0xfed90000,
 845         },
 846         .num_rsts = ARRAY_SIZE(rk3588_udphy_rst_l),
 847         .rst_list = rk3588_udphy_rst_l,
 848         .grfcfg = {
 849                 /* u2phy-grf */
 850                 .bvalid_phy_con         = { 0x0008, 1, 0, 0x2, 0x3 },
 851                 .bvalid_grf_con         = { 0x0010, 3, 2, 0x2, 0x3 },
 852
 853                 /* usb-grf */
 854                 .usb3otg0_cfg           = { 0x001c, 15, 0, 0x1100, 0x0188 },
 855                 .usb3otg1_cfg           = { 0x0034, 15, 0, 0x1100, 0x0188 },
 856
 857                 /* usbdpphy-grf */
 858                 .low_pwrn               = { 0x0004, 13, 13, 0, 1 },
 859                 .rx_lfps                = { 0x0004, 14, 14, 0, 1 },
 860         },
 861         .combophy_init = rk3588_udphy_init,
 862 };
 863
 864 static const struct udevice_id rockchip_udphy_dt_match[] = {
 865         {
 866                 .compatible = "rockchip,rk3588-usbdp-phy",
 867                 .data = (ulong)&rk3588_udphy_cfgs
 868         },
 869         { /* sentinel */ }
 870 };
 871
 872 U_BOOT_DRIVER(rockchip_udphy_u3_port) = {
 873         .name           = "rockchip_udphy_u3_port",
 874         .id             = UCLASS_PHY,
 875         .ops            = &rockchip_u3phy_ops,
 876 };
 877
 878 U_BOOT_DRIVER(rockchip_udphy) = {
 879         .name           = "rockchip_udphy",
 880         .id             = UCLASS_PHY,
 881         .of_match       = rockchip_udphy_dt_match,
 882         .probe          = rockchip_udphy_probe,
 883         .bind           = rockchip_udphy_bind,
 884         .priv_auto      = sizeof(struct rockchip_udphy),
 885 };