3 Broadcom B43 wireless driver
5 Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>
6 Copyright (c) 2005 Stefano Brivio <stefano.brivio@polimi.it>
7 Copyright (c) 2005-2009 Michael Buesch <m@bues.ch>
8 Copyright (c) 2005 Danny van Dyk <kugelfang@gentoo.org>
9 Copyright (c) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch>
10 Copyright (c) 2010-2011 Rafał Miłecki <zajec5@gmail.com>
13 Copyright (c) 2009 Albert Herranz <albert_herranz@yahoo.es>
15 Some parts of the code in this file are derived from the ipw2200
16 driver Copyright(c) 2003 - 2004 Intel Corporation.
18 This program is free software; you can redistribute it and/or modify
19 it under the terms of the GNU General Public License as published by
20 the Free Software Foundation; either version 2 of the License, or
21 (at your option) any later version.
23 This program is distributed in the hope that it will be useful,
24 but WITHOUT ANY WARRANTY; without even the implied warranty of
25 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
26 GNU General Public License for more details.
28 You should have received a copy of the GNU General Public License
29 along with this program; see the file COPYING. If not, write to
30 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
31 Boston, MA 02110-1301, USA.
35 #include <linux/delay.h>
36 #include <linux/init.h>
37 #include <linux/moduleparam.h>
38 #include <linux/if_arp.h>
39 #include <linux/etherdevice.h>
40 #include <linux/firmware.h>
41 #include <linux/workqueue.h>
42 #include <linux/skbuff.h>
44 #include <linux/dma-mapping.h>
45 #include <linux/slab.h>
46 #include <asm/unaligned.h>
51 #include "phy_common.h"
61 #include <linux/mmc/sdio_func.h>
63 MODULE_DESCRIPTION("Broadcom B43 wireless driver");
64 MODULE_AUTHOR("Martin Langer");
65 MODULE_AUTHOR("Stefano Brivio");
66 MODULE_AUTHOR("Michael Buesch");
67 MODULE_AUTHOR("Gábor Stefanik");
68 MODULE_AUTHOR("Rafał Miłecki");
69 MODULE_LICENSE("GPL");
71 MODULE_FIRMWARE("b43/ucode11.fw");
72 MODULE_FIRMWARE("b43/ucode13.fw");
73 MODULE_FIRMWARE("b43/ucode14.fw");
74 MODULE_FIRMWARE("b43/ucode15.fw");
75 MODULE_FIRMWARE("b43/ucode16_mimo.fw");
76 MODULE_FIRMWARE("b43/ucode5.fw");
77 MODULE_FIRMWARE("b43/ucode9.fw");
79 static int modparam_bad_frames_preempt;
80 module_param_named(bad_frames_preempt, modparam_bad_frames_preempt, int, 0444);
81 MODULE_PARM_DESC(bad_frames_preempt,
82 "enable(1) / disable(0) Bad Frames Preemption");
84 static char modparam_fwpostfix[16];
85 module_param_string(fwpostfix, modparam_fwpostfix, 16, 0444);
86 MODULE_PARM_DESC(fwpostfix, "Postfix for the .fw files to load.");
88 static int modparam_hwpctl;
89 module_param_named(hwpctl, modparam_hwpctl, int, 0444);
90 MODULE_PARM_DESC(hwpctl, "Enable hardware-side power control (default off)");
92 static int modparam_nohwcrypt;
93 module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
94 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
96 static int modparam_hwtkip;
97 module_param_named(hwtkip, modparam_hwtkip, int, 0444);
98 MODULE_PARM_DESC(hwtkip, "Enable hardware tkip.");
100 static int modparam_qos = 1;
101 module_param_named(qos, modparam_qos, int, 0444);
102 MODULE_PARM_DESC(qos, "Enable QOS support (default on)");
104 static int modparam_btcoex = 1;
105 module_param_named(btcoex, modparam_btcoex, int, 0444);
106 MODULE_PARM_DESC(btcoex, "Enable Bluetooth coexistence (default on)");
108 int b43_modparam_verbose = B43_VERBOSITY_DEFAULT;
109 module_param_named(verbose, b43_modparam_verbose, int, 0644);
110 MODULE_PARM_DESC(verbose, "Log message verbosity: 0=error, 1=warn, 2=info(default), 3=debug");
112 static int b43_modparam_pio = 0;
113 module_param_named(pio, b43_modparam_pio, int, 0644);
114 MODULE_PARM_DESC(pio, "Use PIO accesses by default: 0=DMA, 1=PIO");
116 #ifdef CONFIG_B43_BCMA
117 static const struct bcma_device_id b43_bcma_tbl[] = {
118 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_80211, 0x11, BCMA_ANY_CLASS),
119 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_80211, 0x17, BCMA_ANY_CLASS),
120 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_80211, 0x18, BCMA_ANY_CLASS),
121 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_80211, 0x1D, BCMA_ANY_CLASS),
124 MODULE_DEVICE_TABLE(bcma, b43_bcma_tbl);
127 #ifdef CONFIG_B43_SSB
128 static const struct ssb_device_id b43_ssb_tbl[] = {
129 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 5),
130 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 6),
131 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 7),
132 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 9),
133 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 10),
134 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 11),
135 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 12),
136 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 13),
137 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 15),
138 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 16),
141 MODULE_DEVICE_TABLE(ssb, b43_ssb_tbl);
144 /* Channel and ratetables are shared for all devices.
145 * They can't be const, because ieee80211 puts some precalculated
146 * data in there. This data is the same for all devices, so we don't
147 * get concurrency issues */
148 #define RATETAB_ENT(_rateid, _flags) \
150 .bitrate = B43_RATE_TO_BASE100KBPS(_rateid), \
151 .hw_value = (_rateid), \
156 * NOTE: When changing this, sync with xmit.c's
157 * b43_plcp_get_bitrate_idx_* functions!
159 static struct ieee80211_rate __b43_ratetable[] = {
160 RATETAB_ENT(B43_CCK_RATE_1MB, 0),
161 RATETAB_ENT(B43_CCK_RATE_2MB, IEEE80211_RATE_SHORT_PREAMBLE),
162 RATETAB_ENT(B43_CCK_RATE_5MB, IEEE80211_RATE_SHORT_PREAMBLE),
163 RATETAB_ENT(B43_CCK_RATE_11MB, IEEE80211_RATE_SHORT_PREAMBLE),
164 RATETAB_ENT(B43_OFDM_RATE_6MB, 0),
165 RATETAB_ENT(B43_OFDM_RATE_9MB, 0),
166 RATETAB_ENT(B43_OFDM_RATE_12MB, 0),
167 RATETAB_ENT(B43_OFDM_RATE_18MB, 0),
168 RATETAB_ENT(B43_OFDM_RATE_24MB, 0),
169 RATETAB_ENT(B43_OFDM_RATE_36MB, 0),
170 RATETAB_ENT(B43_OFDM_RATE_48MB, 0),
171 RATETAB_ENT(B43_OFDM_RATE_54MB, 0),
174 #define b43_a_ratetable (__b43_ratetable + 4)
175 #define b43_a_ratetable_size 8
176 #define b43_b_ratetable (__b43_ratetable + 0)
177 #define b43_b_ratetable_size 4
178 #define b43_g_ratetable (__b43_ratetable + 0)
179 #define b43_g_ratetable_size 12
181 #define CHAN4G(_channel, _freq, _flags) { \
182 .band = IEEE80211_BAND_2GHZ, \
183 .center_freq = (_freq), \
184 .hw_value = (_channel), \
186 .max_antenna_gain = 0, \
189 static struct ieee80211_channel b43_2ghz_chantable[] = {
207 #define CHAN5G(_channel, _flags) { \
208 .band = IEEE80211_BAND_5GHZ, \
209 .center_freq = 5000 + (5 * (_channel)), \
210 .hw_value = (_channel), \
212 .max_antenna_gain = 0, \
215 static struct ieee80211_channel b43_5ghz_nphy_chantable[] = {
216 CHAN5G(32, 0), CHAN5G(34, 0),
217 CHAN5G(36, 0), CHAN5G(38, 0),
218 CHAN5G(40, 0), CHAN5G(42, 0),
219 CHAN5G(44, 0), CHAN5G(46, 0),
220 CHAN5G(48, 0), CHAN5G(50, 0),
221 CHAN5G(52, 0), CHAN5G(54, 0),
222 CHAN5G(56, 0), CHAN5G(58, 0),
223 CHAN5G(60, 0), CHAN5G(62, 0),
224 CHAN5G(64, 0), CHAN5G(66, 0),
225 CHAN5G(68, 0), CHAN5G(70, 0),
226 CHAN5G(72, 0), CHAN5G(74, 0),
227 CHAN5G(76, 0), CHAN5G(78, 0),
228 CHAN5G(80, 0), CHAN5G(82, 0),
229 CHAN5G(84, 0), CHAN5G(86, 0),
230 CHAN5G(88, 0), CHAN5G(90, 0),
231 CHAN5G(92, 0), CHAN5G(94, 0),
232 CHAN5G(96, 0), CHAN5G(98, 0),
233 CHAN5G(100, 0), CHAN5G(102, 0),
234 CHAN5G(104, 0), CHAN5G(106, 0),
235 CHAN5G(108, 0), CHAN5G(110, 0),
236 CHAN5G(112, 0), CHAN5G(114, 0),
237 CHAN5G(116, 0), CHAN5G(118, 0),
238 CHAN5G(120, 0), CHAN5G(122, 0),
239 CHAN5G(124, 0), CHAN5G(126, 0),
240 CHAN5G(128, 0), CHAN5G(130, 0),
241 CHAN5G(132, 0), CHAN5G(134, 0),
242 CHAN5G(136, 0), CHAN5G(138, 0),
243 CHAN5G(140, 0), CHAN5G(142, 0),
244 CHAN5G(144, 0), CHAN5G(145, 0),
245 CHAN5G(146, 0), CHAN5G(147, 0),
246 CHAN5G(148, 0), CHAN5G(149, 0),
247 CHAN5G(150, 0), CHAN5G(151, 0),
248 CHAN5G(152, 0), CHAN5G(153, 0),
249 CHAN5G(154, 0), CHAN5G(155, 0),
250 CHAN5G(156, 0), CHAN5G(157, 0),
251 CHAN5G(158, 0), CHAN5G(159, 0),
252 CHAN5G(160, 0), CHAN5G(161, 0),
253 CHAN5G(162, 0), CHAN5G(163, 0),
254 CHAN5G(164, 0), CHAN5G(165, 0),
255 CHAN5G(166, 0), CHAN5G(168, 0),
256 CHAN5G(170, 0), CHAN5G(172, 0),
257 CHAN5G(174, 0), CHAN5G(176, 0),
258 CHAN5G(178, 0), CHAN5G(180, 0),
259 CHAN5G(182, 0), CHAN5G(184, 0),
260 CHAN5G(186, 0), CHAN5G(188, 0),
261 CHAN5G(190, 0), CHAN5G(192, 0),
262 CHAN5G(194, 0), CHAN5G(196, 0),
263 CHAN5G(198, 0), CHAN5G(200, 0),
264 CHAN5G(202, 0), CHAN5G(204, 0),
265 CHAN5G(206, 0), CHAN5G(208, 0),
266 CHAN5G(210, 0), CHAN5G(212, 0),
267 CHAN5G(214, 0), CHAN5G(216, 0),
268 CHAN5G(218, 0), CHAN5G(220, 0),
269 CHAN5G(222, 0), CHAN5G(224, 0),
270 CHAN5G(226, 0), CHAN5G(228, 0),
273 static struct ieee80211_channel b43_5ghz_aphy_chantable[] = {
274 CHAN5G(34, 0), CHAN5G(36, 0),
275 CHAN5G(38, 0), CHAN5G(40, 0),
276 CHAN5G(42, 0), CHAN5G(44, 0),
277 CHAN5G(46, 0), CHAN5G(48, 0),
278 CHAN5G(52, 0), CHAN5G(56, 0),
279 CHAN5G(60, 0), CHAN5G(64, 0),
280 CHAN5G(100, 0), CHAN5G(104, 0),
281 CHAN5G(108, 0), CHAN5G(112, 0),
282 CHAN5G(116, 0), CHAN5G(120, 0),
283 CHAN5G(124, 0), CHAN5G(128, 0),
284 CHAN5G(132, 0), CHAN5G(136, 0),
285 CHAN5G(140, 0), CHAN5G(149, 0),
286 CHAN5G(153, 0), CHAN5G(157, 0),
287 CHAN5G(161, 0), CHAN5G(165, 0),
288 CHAN5G(184, 0), CHAN5G(188, 0),
289 CHAN5G(192, 0), CHAN5G(196, 0),
290 CHAN5G(200, 0), CHAN5G(204, 0),
291 CHAN5G(208, 0), CHAN5G(212, 0),
296 static struct ieee80211_supported_band b43_band_5GHz_nphy = {
297 .band = IEEE80211_BAND_5GHZ,
298 .channels = b43_5ghz_nphy_chantable,
299 .n_channels = ARRAY_SIZE(b43_5ghz_nphy_chantable),
300 .bitrates = b43_a_ratetable,
301 .n_bitrates = b43_a_ratetable_size,
304 static struct ieee80211_supported_band b43_band_5GHz_aphy = {
305 .band = IEEE80211_BAND_5GHZ,
306 .channels = b43_5ghz_aphy_chantable,
307 .n_channels = ARRAY_SIZE(b43_5ghz_aphy_chantable),
308 .bitrates = b43_a_ratetable,
309 .n_bitrates = b43_a_ratetable_size,
312 static struct ieee80211_supported_band b43_band_2GHz = {
313 .band = IEEE80211_BAND_2GHZ,
314 .channels = b43_2ghz_chantable,
315 .n_channels = ARRAY_SIZE(b43_2ghz_chantable),
316 .bitrates = b43_g_ratetable,
317 .n_bitrates = b43_g_ratetable_size,
320 static void b43_wireless_core_exit(struct b43_wldev *dev);
321 static int b43_wireless_core_init(struct b43_wldev *dev);
322 static struct b43_wldev * b43_wireless_core_stop(struct b43_wldev *dev);
323 static int b43_wireless_core_start(struct b43_wldev *dev);
324 static void b43_op_bss_info_changed(struct ieee80211_hw *hw,
325 struct ieee80211_vif *vif,
326 struct ieee80211_bss_conf *conf,
329 static int b43_ratelimit(struct b43_wl *wl)
331 if (!wl || !wl->current_dev)
333 if (b43_status(wl->current_dev) < B43_STAT_STARTED)
335 /* We are up and running.
336 * Ratelimit the messages to avoid DoS over the net. */
337 return net_ratelimit();
340 void b43info(struct b43_wl *wl, const char *fmt, ...)
342 struct va_format vaf;
345 if (b43_modparam_verbose < B43_VERBOSITY_INFO)
347 if (!b43_ratelimit(wl))
355 printk(KERN_INFO "b43-%s: %pV",
356 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan", &vaf);
361 void b43err(struct b43_wl *wl, const char *fmt, ...)
363 struct va_format vaf;
366 if (b43_modparam_verbose < B43_VERBOSITY_ERROR)
368 if (!b43_ratelimit(wl))
376 printk(KERN_ERR "b43-%s ERROR: %pV",
377 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan", &vaf);
382 void b43warn(struct b43_wl *wl, const char *fmt, ...)
384 struct va_format vaf;
387 if (b43_modparam_verbose < B43_VERBOSITY_WARN)
389 if (!b43_ratelimit(wl))
397 printk(KERN_WARNING "b43-%s warning: %pV",
398 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan", &vaf);
403 void b43dbg(struct b43_wl *wl, const char *fmt, ...)
405 struct va_format vaf;
408 if (b43_modparam_verbose < B43_VERBOSITY_DEBUG)
416 printk(KERN_DEBUG "b43-%s debug: %pV",
417 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan", &vaf);
422 static void b43_ram_write(struct b43_wldev *dev, u16 offset, u32 val)
426 B43_WARN_ON(offset % 4 != 0);
428 macctl = b43_read32(dev, B43_MMIO_MACCTL);
429 if (macctl & B43_MACCTL_BE)
432 b43_write32(dev, B43_MMIO_RAM_CONTROL, offset);
434 b43_write32(dev, B43_MMIO_RAM_DATA, val);
437 static inline void b43_shm_control_word(struct b43_wldev *dev,
438 u16 routing, u16 offset)
442 /* "offset" is the WORD offset. */
446 b43_write32(dev, B43_MMIO_SHM_CONTROL, control);
449 u32 b43_shm_read32(struct b43_wldev *dev, u16 routing, u16 offset)
453 if (routing == B43_SHM_SHARED) {
454 B43_WARN_ON(offset & 0x0001);
455 if (offset & 0x0003) {
456 /* Unaligned access */
457 b43_shm_control_word(dev, routing, offset >> 2);
458 ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED);
459 b43_shm_control_word(dev, routing, (offset >> 2) + 1);
460 ret |= ((u32)b43_read16(dev, B43_MMIO_SHM_DATA)) << 16;
466 b43_shm_control_word(dev, routing, offset);
467 ret = b43_read32(dev, B43_MMIO_SHM_DATA);
472 u16 b43_shm_read16(struct b43_wldev *dev, u16 routing, u16 offset)
476 if (routing == B43_SHM_SHARED) {
477 B43_WARN_ON(offset & 0x0001);
478 if (offset & 0x0003) {
479 /* Unaligned access */
480 b43_shm_control_word(dev, routing, offset >> 2);
481 ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED);
487 b43_shm_control_word(dev, routing, offset);
488 ret = b43_read16(dev, B43_MMIO_SHM_DATA);
493 void b43_shm_write32(struct b43_wldev *dev, u16 routing, u16 offset, u32 value)
495 if (routing == B43_SHM_SHARED) {
496 B43_WARN_ON(offset & 0x0001);
497 if (offset & 0x0003) {
498 /* Unaligned access */
499 b43_shm_control_word(dev, routing, offset >> 2);
500 b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED,
502 b43_shm_control_word(dev, routing, (offset >> 2) + 1);
503 b43_write16(dev, B43_MMIO_SHM_DATA,
504 (value >> 16) & 0xFFFF);
509 b43_shm_control_word(dev, routing, offset);
510 b43_write32(dev, B43_MMIO_SHM_DATA, value);
513 void b43_shm_write16(struct b43_wldev *dev, u16 routing, u16 offset, u16 value)
515 if (routing == B43_SHM_SHARED) {
516 B43_WARN_ON(offset & 0x0001);
517 if (offset & 0x0003) {
518 /* Unaligned access */
519 b43_shm_control_word(dev, routing, offset >> 2);
520 b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED, value);
525 b43_shm_control_word(dev, routing, offset);
526 b43_write16(dev, B43_MMIO_SHM_DATA, value);
530 u64 b43_hf_read(struct b43_wldev *dev)
534 ret = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFHI);
536 ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFMI);
538 ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFLO);
543 /* Write HostFlags */
544 void b43_hf_write(struct b43_wldev *dev, u64 value)
548 lo = (value & 0x00000000FFFFULL);
549 mi = (value & 0x0000FFFF0000ULL) >> 16;
550 hi = (value & 0xFFFF00000000ULL) >> 32;
551 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFLO, lo);
552 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFMI, mi);
553 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFHI, hi);
556 /* Read the firmware capabilities bitmask (Opensource firmware only) */
557 static u16 b43_fwcapa_read(struct b43_wldev *dev)
559 B43_WARN_ON(!dev->fw.opensource);
560 return b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_FWCAPA);
563 void b43_tsf_read(struct b43_wldev *dev, u64 *tsf)
567 B43_WARN_ON(dev->dev->core_rev < 3);
569 /* The hardware guarantees us an atomic read, if we
570 * read the low register first. */
571 low = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_LOW);
572 high = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_HIGH);
579 static void b43_time_lock(struct b43_wldev *dev)
583 macctl = b43_read32(dev, B43_MMIO_MACCTL);
584 macctl |= B43_MACCTL_TBTTHOLD;
585 b43_write32(dev, B43_MMIO_MACCTL, macctl);
586 /* Commit the write */
587 b43_read32(dev, B43_MMIO_MACCTL);
590 static void b43_time_unlock(struct b43_wldev *dev)
594 macctl = b43_read32(dev, B43_MMIO_MACCTL);
595 macctl &= ~B43_MACCTL_TBTTHOLD;
596 b43_write32(dev, B43_MMIO_MACCTL, macctl);
597 /* Commit the write */
598 b43_read32(dev, B43_MMIO_MACCTL);
601 static void b43_tsf_write_locked(struct b43_wldev *dev, u64 tsf)
605 B43_WARN_ON(dev->dev->core_rev < 3);
609 /* The hardware guarantees us an atomic write, if we
610 * write the low register first. */
611 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_LOW, low);
613 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_HIGH, high);
617 void b43_tsf_write(struct b43_wldev *dev, u64 tsf)
620 b43_tsf_write_locked(dev, tsf);
621 b43_time_unlock(dev);
625 void b43_macfilter_set(struct b43_wldev *dev, u16 offset, const u8 *mac)
627 static const u8 zero_addr[ETH_ALEN] = { 0 };
634 b43_write16(dev, B43_MMIO_MACFILTER_CONTROL, offset);
638 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
641 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
644 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
647 static void b43_write_mac_bssid_templates(struct b43_wldev *dev)
651 u8 mac_bssid[ETH_ALEN * 2];
655 bssid = dev->wl->bssid;
656 mac = dev->wl->mac_addr;
658 b43_macfilter_set(dev, B43_MACFILTER_BSSID, bssid);
660 memcpy(mac_bssid, mac, ETH_ALEN);
661 memcpy(mac_bssid + ETH_ALEN, bssid, ETH_ALEN);
663 /* Write our MAC address and BSSID to template ram */
664 for (i = 0; i < ARRAY_SIZE(mac_bssid); i += sizeof(u32)) {
665 tmp = (u32) (mac_bssid[i + 0]);
666 tmp |= (u32) (mac_bssid[i + 1]) << 8;
667 tmp |= (u32) (mac_bssid[i + 2]) << 16;
668 tmp |= (u32) (mac_bssid[i + 3]) << 24;
669 b43_ram_write(dev, 0x20 + i, tmp);
673 static void b43_upload_card_macaddress(struct b43_wldev *dev)
675 b43_write_mac_bssid_templates(dev);
676 b43_macfilter_set(dev, B43_MACFILTER_SELF, dev->wl->mac_addr);
679 static void b43_set_slot_time(struct b43_wldev *dev, u16 slot_time)
681 /* slot_time is in usec. */
682 /* This test used to exit for all but a G PHY. */
683 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
685 b43_write16(dev, B43_MMIO_IFSSLOT, 510 + slot_time);
686 /* Shared memory location 0x0010 is the slot time and should be
687 * set to slot_time; however, this register is initially 0 and changing
688 * the value adversely affects the transmit rate for BCM4311
689 * devices. Until this behavior is unterstood, delete this step
691 * b43_shm_write16(dev, B43_SHM_SHARED, 0x0010, slot_time);
695 static void b43_short_slot_timing_enable(struct b43_wldev *dev)
697 b43_set_slot_time(dev, 9);
700 static void b43_short_slot_timing_disable(struct b43_wldev *dev)
702 b43_set_slot_time(dev, 20);
705 /* DummyTransmission function, as documented on
706 * http://bcm-v4.sipsolutions.net/802.11/DummyTransmission
708 void b43_dummy_transmission(struct b43_wldev *dev, bool ofdm, bool pa_on)
710 struct b43_phy *phy = &dev->phy;
711 unsigned int i, max_loop;
723 buffer[0] = 0x000201CC;
726 buffer[0] = 0x000B846E;
729 for (i = 0; i < 5; i++)
730 b43_ram_write(dev, i * 4, buffer[i]);
732 b43_write16(dev, 0x0568, 0x0000);
733 if (dev->dev->core_rev < 11)
734 b43_write16(dev, 0x07C0, 0x0000);
736 b43_write16(dev, 0x07C0, 0x0100);
737 value = (ofdm ? 0x41 : 0x40);
738 b43_write16(dev, 0x050C, value);
739 if ((phy->type == B43_PHYTYPE_N) || (phy->type == B43_PHYTYPE_LP))
740 b43_write16(dev, 0x0514, 0x1A02);
741 b43_write16(dev, 0x0508, 0x0000);
742 b43_write16(dev, 0x050A, 0x0000);
743 b43_write16(dev, 0x054C, 0x0000);
744 b43_write16(dev, 0x056A, 0x0014);
745 b43_write16(dev, 0x0568, 0x0826);
746 b43_write16(dev, 0x0500, 0x0000);
747 if (!pa_on && (phy->type == B43_PHYTYPE_N)) {
753 b43_write16(dev, 0x0502, 0x00D0);
756 b43_write16(dev, 0x0502, 0x0050);
759 b43_write16(dev, 0x0502, 0x0030);
762 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
763 b43_radio_write16(dev, 0x0051, 0x0017);
764 for (i = 0x00; i < max_loop; i++) {
765 value = b43_read16(dev, 0x050E);
770 for (i = 0x00; i < 0x0A; i++) {
771 value = b43_read16(dev, 0x050E);
776 for (i = 0x00; i < 0x19; i++) {
777 value = b43_read16(dev, 0x0690);
778 if (!(value & 0x0100))
782 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
783 b43_radio_write16(dev, 0x0051, 0x0037);
786 static void key_write(struct b43_wldev *dev,
787 u8 index, u8 algorithm, const u8 *key)
794 /* Key index/algo block */
795 kidx = b43_kidx_to_fw(dev, index);
796 value = ((kidx << 4) | algorithm);
797 b43_shm_write16(dev, B43_SHM_SHARED,
798 B43_SHM_SH_KEYIDXBLOCK + (kidx * 2), value);
800 /* Write the key to the Key Table Pointer offset */
801 offset = dev->ktp + (index * B43_SEC_KEYSIZE);
802 for (i = 0; i < B43_SEC_KEYSIZE; i += 2) {
804 value |= (u16) (key[i + 1]) << 8;
805 b43_shm_write16(dev, B43_SHM_SHARED, offset + i, value);
809 static void keymac_write(struct b43_wldev *dev, u8 index, const u8 *addr)
811 u32 addrtmp[2] = { 0, 0, };
812 u8 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
814 if (b43_new_kidx_api(dev))
815 pairwise_keys_start = B43_NR_GROUP_KEYS;
817 B43_WARN_ON(index < pairwise_keys_start);
818 /* We have four default TX keys and possibly four default RX keys.
819 * Physical mac 0 is mapped to physical key 4 or 8, depending
820 * on the firmware version.
821 * So we must adjust the index here.
823 index -= pairwise_keys_start;
824 B43_WARN_ON(index >= B43_NR_PAIRWISE_KEYS);
827 addrtmp[0] = addr[0];
828 addrtmp[0] |= ((u32) (addr[1]) << 8);
829 addrtmp[0] |= ((u32) (addr[2]) << 16);
830 addrtmp[0] |= ((u32) (addr[3]) << 24);
831 addrtmp[1] = addr[4];
832 addrtmp[1] |= ((u32) (addr[5]) << 8);
835 /* Receive match transmitter address (RCMTA) mechanism */
836 b43_shm_write32(dev, B43_SHM_RCMTA,
837 (index * 2) + 0, addrtmp[0]);
838 b43_shm_write16(dev, B43_SHM_RCMTA,
839 (index * 2) + 1, addrtmp[1]);
842 /* The ucode will use phase1 key with TEK key to decrypt rx packets.
843 * When a packet is received, the iv32 is checked.
844 * - if it doesn't the packet is returned without modification (and software
845 * decryption can be done). That's what happen when iv16 wrap.
846 * - if it does, the rc4 key is computed, and decryption is tried.
847 * Either it will success and B43_RX_MAC_DEC is returned,
848 * either it fails and B43_RX_MAC_DEC|B43_RX_MAC_DECERR is returned
849 * and the packet is not usable (it got modified by the ucode).
850 * So in order to never have B43_RX_MAC_DECERR, we should provide
851 * a iv32 and phase1key that match. Because we drop packets in case of
852 * B43_RX_MAC_DECERR, if we have a correct iv32 but a wrong phase1key, all
853 * packets will be lost without higher layer knowing (ie no resync possible
856 * NOTE : this should support 50 key like RCMTA because
857 * (B43_SHM_SH_KEYIDXBLOCK - B43_SHM_SH_TKIPTSCTTAK)/14 = 50
859 static void rx_tkip_phase1_write(struct b43_wldev *dev, u8 index, u32 iv32,
864 u8 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
866 if (!modparam_hwtkip)
869 if (b43_new_kidx_api(dev))
870 pairwise_keys_start = B43_NR_GROUP_KEYS;
872 B43_WARN_ON(index < pairwise_keys_start);
873 /* We have four default TX keys and possibly four default RX keys.
874 * Physical mac 0 is mapped to physical key 4 or 8, depending
875 * on the firmware version.
876 * So we must adjust the index here.
878 index -= pairwise_keys_start;
879 B43_WARN_ON(index >= B43_NR_PAIRWISE_KEYS);
881 if (b43_debug(dev, B43_DBG_KEYS)) {
882 b43dbg(dev->wl, "rx_tkip_phase1_write : idx 0x%x, iv32 0x%x\n",
885 /* Write the key to the RX tkip shared mem */
886 offset = B43_SHM_SH_TKIPTSCTTAK + index * (10 + 4);
887 for (i = 0; i < 10; i += 2) {
888 b43_shm_write16(dev, B43_SHM_SHARED, offset + i,
889 phase1key ? phase1key[i / 2] : 0);
891 b43_shm_write16(dev, B43_SHM_SHARED, offset + i, iv32);
892 b43_shm_write16(dev, B43_SHM_SHARED, offset + i + 2, iv32 >> 16);
895 static void b43_op_update_tkip_key(struct ieee80211_hw *hw,
896 struct ieee80211_vif *vif,
897 struct ieee80211_key_conf *keyconf,
898 struct ieee80211_sta *sta,
899 u32 iv32, u16 *phase1key)
901 struct b43_wl *wl = hw_to_b43_wl(hw);
902 struct b43_wldev *dev;
903 int index = keyconf->hw_key_idx;
905 if (B43_WARN_ON(!modparam_hwtkip))
908 /* This is only called from the RX path through mac80211, where
909 * our mutex is already locked. */
910 B43_WARN_ON(!mutex_is_locked(&wl->mutex));
911 dev = wl->current_dev;
912 B43_WARN_ON(!dev || b43_status(dev) < B43_STAT_INITIALIZED);
914 keymac_write(dev, index, NULL); /* First zero out mac to avoid race */
916 rx_tkip_phase1_write(dev, index, iv32, phase1key);
917 /* only pairwise TKIP keys are supported right now */
920 keymac_write(dev, index, sta->addr);
923 static void do_key_write(struct b43_wldev *dev,
924 u8 index, u8 algorithm,
925 const u8 *key, size_t key_len, const u8 *mac_addr)
927 u8 buf[B43_SEC_KEYSIZE] = { 0, };
928 u8 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
930 if (b43_new_kidx_api(dev))
931 pairwise_keys_start = B43_NR_GROUP_KEYS;
933 B43_WARN_ON(index >= ARRAY_SIZE(dev->key));
934 B43_WARN_ON(key_len > B43_SEC_KEYSIZE);
936 if (index >= pairwise_keys_start)
937 keymac_write(dev, index, NULL); /* First zero out mac. */
938 if (algorithm == B43_SEC_ALGO_TKIP) {
940 * We should provide an initial iv32, phase1key pair.
941 * We could start with iv32=0 and compute the corresponding
942 * phase1key, but this means calling ieee80211_get_tkip_key
943 * with a fake skb (or export other tkip function).
944 * Because we are lazy we hope iv32 won't start with
945 * 0xffffffff and let's b43_op_update_tkip_key provide a
948 rx_tkip_phase1_write(dev, index, 0xffffffff, (u16*)buf);
949 } else if (index >= pairwise_keys_start) /* clear it */
950 rx_tkip_phase1_write(dev, index, 0, NULL);
952 memcpy(buf, key, key_len);
953 key_write(dev, index, algorithm, buf);
954 if (index >= pairwise_keys_start)
955 keymac_write(dev, index, mac_addr);
957 dev->key[index].algorithm = algorithm;
960 static int b43_key_write(struct b43_wldev *dev,
961 int index, u8 algorithm,
962 const u8 *key, size_t key_len,
964 struct ieee80211_key_conf *keyconf)
967 int pairwise_keys_start;
969 /* For ALG_TKIP the key is encoded as a 256-bit (32 byte) data block:
970 * - Temporal Encryption Key (128 bits)
971 * - Temporal Authenticator Tx MIC Key (64 bits)
972 * - Temporal Authenticator Rx MIC Key (64 bits)
974 * Hardware only store TEK
976 if (algorithm == B43_SEC_ALGO_TKIP && key_len == 32)
978 if (key_len > B43_SEC_KEYSIZE)
980 for (i = 0; i < ARRAY_SIZE(dev->key); i++) {
981 /* Check that we don't already have this key. */
982 B43_WARN_ON(dev->key[i].keyconf == keyconf);
985 /* Pairwise key. Get an empty slot for the key. */
986 if (b43_new_kidx_api(dev))
987 pairwise_keys_start = B43_NR_GROUP_KEYS;
989 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
990 for (i = pairwise_keys_start;
991 i < pairwise_keys_start + B43_NR_PAIRWISE_KEYS;
993 B43_WARN_ON(i >= ARRAY_SIZE(dev->key));
994 if (!dev->key[i].keyconf) {
1001 b43warn(dev->wl, "Out of hardware key memory\n");
1005 B43_WARN_ON(index > 3);
1007 do_key_write(dev, index, algorithm, key, key_len, mac_addr);
1008 if ((index <= 3) && !b43_new_kidx_api(dev)) {
1009 /* Default RX key */
1010 B43_WARN_ON(mac_addr);
1011 do_key_write(dev, index + 4, algorithm, key, key_len, NULL);
1013 keyconf->hw_key_idx = index;
1014 dev->key[index].keyconf = keyconf;
1019 static int b43_key_clear(struct b43_wldev *dev, int index)
1021 if (B43_WARN_ON((index < 0) || (index >= ARRAY_SIZE(dev->key))))
1023 do_key_write(dev, index, B43_SEC_ALGO_NONE,
1024 NULL, B43_SEC_KEYSIZE, NULL);
1025 if ((index <= 3) && !b43_new_kidx_api(dev)) {
1026 do_key_write(dev, index + 4, B43_SEC_ALGO_NONE,
1027 NULL, B43_SEC_KEYSIZE, NULL);
1029 dev->key[index].keyconf = NULL;
1034 static void b43_clear_keys(struct b43_wldev *dev)
1038 if (b43_new_kidx_api(dev))
1039 count = B43_NR_GROUP_KEYS + B43_NR_PAIRWISE_KEYS;
1041 count = B43_NR_GROUP_KEYS * 2 + B43_NR_PAIRWISE_KEYS;
1042 for (i = 0; i < count; i++)
1043 b43_key_clear(dev, i);
1046 static void b43_dump_keymemory(struct b43_wldev *dev)
1048 unsigned int i, index, count, offset, pairwise_keys_start;
1054 struct b43_key *key;
1056 if (!b43_debug(dev, B43_DBG_KEYS))
1059 hf = b43_hf_read(dev);
1060 b43dbg(dev->wl, "Hardware key memory dump: USEDEFKEYS=%u\n",
1061 !!(hf & B43_HF_USEDEFKEYS));
1062 if (b43_new_kidx_api(dev)) {
1063 pairwise_keys_start = B43_NR_GROUP_KEYS;
1064 count = B43_NR_GROUP_KEYS + B43_NR_PAIRWISE_KEYS;
1066 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
1067 count = B43_NR_GROUP_KEYS * 2 + B43_NR_PAIRWISE_KEYS;
1069 for (index = 0; index < count; index++) {
1070 key = &(dev->key[index]);
1071 printk(KERN_DEBUG "Key slot %02u: %s",
1072 index, (key->keyconf == NULL) ? " " : "*");
1073 offset = dev->ktp + (index * B43_SEC_KEYSIZE);
1074 for (i = 0; i < B43_SEC_KEYSIZE; i += 2) {
1075 u16 tmp = b43_shm_read16(dev, B43_SHM_SHARED, offset + i);
1076 printk("%02X%02X", (tmp & 0xFF), ((tmp >> 8) & 0xFF));
1079 algo = b43_shm_read16(dev, B43_SHM_SHARED,
1080 B43_SHM_SH_KEYIDXBLOCK + (index * 2));
1081 printk(" Algo: %04X/%02X", algo, key->algorithm);
1083 if (index >= pairwise_keys_start) {
1084 if (key->algorithm == B43_SEC_ALGO_TKIP) {
1086 offset = B43_SHM_SH_TKIPTSCTTAK + (index - 4) * (10 + 4);
1087 for (i = 0; i < 14; i += 2) {
1088 u16 tmp = b43_shm_read16(dev, B43_SHM_SHARED, offset + i);
1089 printk("%02X%02X", (tmp & 0xFF), ((tmp >> 8) & 0xFF));
1092 rcmta0 = b43_shm_read32(dev, B43_SHM_RCMTA,
1093 ((index - pairwise_keys_start) * 2) + 0);
1094 rcmta1 = b43_shm_read16(dev, B43_SHM_RCMTA,
1095 ((index - pairwise_keys_start) * 2) + 1);
1096 *((__le32 *)(&mac[0])) = cpu_to_le32(rcmta0);
1097 *((__le16 *)(&mac[4])) = cpu_to_le16(rcmta1);
1098 printk(" MAC: %pM", mac);
1100 printk(" DEFAULT KEY");
1105 void b43_power_saving_ctl_bits(struct b43_wldev *dev, unsigned int ps_flags)
1113 B43_WARN_ON((ps_flags & B43_PS_ENABLED) &&
1114 (ps_flags & B43_PS_DISABLED));
1115 B43_WARN_ON((ps_flags & B43_PS_AWAKE) && (ps_flags & B43_PS_ASLEEP));
1117 if (ps_flags & B43_PS_ENABLED) {
1119 } else if (ps_flags & B43_PS_DISABLED) {
1122 //TODO: If powersave is not off and FIXME is not set and we are not in adhoc
1123 // and thus is not an AP and we are associated, set bit 25
1125 if (ps_flags & B43_PS_AWAKE) {
1127 } else if (ps_flags & B43_PS_ASLEEP) {
1130 //TODO: If the device is awake or this is an AP, or we are scanning, or FIXME,
1131 // or we are associated, or FIXME, or the latest PS-Poll packet sent was
1132 // successful, set bit26
1135 /* FIXME: For now we force awake-on and hwps-off */
1139 macctl = b43_read32(dev, B43_MMIO_MACCTL);
1141 macctl |= B43_MACCTL_HWPS;
1143 macctl &= ~B43_MACCTL_HWPS;
1145 macctl |= B43_MACCTL_AWAKE;
1147 macctl &= ~B43_MACCTL_AWAKE;
1148 b43_write32(dev, B43_MMIO_MACCTL, macctl);
1150 b43_read32(dev, B43_MMIO_MACCTL);
1151 if (awake && dev->dev->core_rev >= 5) {
1152 /* Wait for the microcode to wake up. */
1153 for (i = 0; i < 100; i++) {
1154 ucstat = b43_shm_read16(dev, B43_SHM_SHARED,
1155 B43_SHM_SH_UCODESTAT);
1156 if (ucstat != B43_SHM_SH_UCODESTAT_SLEEP)
1163 #ifdef CONFIG_B43_BCMA
1164 static void b43_bcma_phy_reset(struct b43_wldev *dev)
1168 /* Put PHY into reset */
1169 flags = bcma_aread32(dev->dev->bdev, BCMA_IOCTL);
1170 flags |= B43_BCMA_IOCTL_PHY_RESET;
1171 flags |= B43_BCMA_IOCTL_PHY_BW_20MHZ; /* Make 20 MHz def */
1172 bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, flags);
1175 /* Take PHY out of reset */
1176 flags = bcma_aread32(dev->dev->bdev, BCMA_IOCTL);
1177 flags &= ~B43_BCMA_IOCTL_PHY_RESET;
1178 flags |= BCMA_IOCTL_FGC;
1179 bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, flags);
1182 /* Do not force clock anymore */
1183 flags = bcma_aread32(dev->dev->bdev, BCMA_IOCTL);
1184 flags &= ~BCMA_IOCTL_FGC;
1185 bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, flags);
1189 static void b43_bcma_wireless_core_reset(struct b43_wldev *dev, bool gmode)
1191 b43_device_enable(dev, B43_BCMA_IOCTL_PHY_CLKEN);
1192 bcma_core_set_clockmode(dev->dev->bdev, BCMA_CLKMODE_FAST);
1193 b43_bcma_phy_reset(dev);
1194 bcma_core_pll_ctl(dev->dev->bdev, 0x300, 0x3000000, true);
1198 static void b43_ssb_wireless_core_reset(struct b43_wldev *dev, bool gmode)
1200 struct ssb_device *sdev = dev->dev->sdev;
1205 flags |= B43_TMSLOW_GMODE;
1206 flags |= B43_TMSLOW_PHYCLKEN;
1207 flags |= B43_TMSLOW_PHYRESET;
1208 if (dev->phy.type == B43_PHYTYPE_N)
1209 flags |= B43_TMSLOW_PHY_BANDWIDTH_20MHZ; /* Make 20 MHz def */
1210 b43_device_enable(dev, flags);
1211 msleep(2); /* Wait for the PLL to turn on. */
1213 /* Now take the PHY out of Reset again */
1214 tmslow = ssb_read32(sdev, SSB_TMSLOW);
1215 tmslow |= SSB_TMSLOW_FGC;
1216 tmslow &= ~B43_TMSLOW_PHYRESET;
1217 ssb_write32(sdev, SSB_TMSLOW, tmslow);
1218 ssb_read32(sdev, SSB_TMSLOW); /* flush */
1220 tmslow &= ~SSB_TMSLOW_FGC;
1221 ssb_write32(sdev, SSB_TMSLOW, tmslow);
1222 ssb_read32(sdev, SSB_TMSLOW); /* flush */
1226 void b43_wireless_core_reset(struct b43_wldev *dev, bool gmode)
1230 switch (dev->dev->bus_type) {
1231 #ifdef CONFIG_B43_BCMA
1233 b43_bcma_wireless_core_reset(dev, gmode);
1236 #ifdef CONFIG_B43_SSB
1238 b43_ssb_wireless_core_reset(dev, gmode);
1243 /* Turn Analog ON, but only if we already know the PHY-type.
1244 * This protects against very early setup where we don't know the
1245 * PHY-type, yet. wireless_core_reset will be called once again later,
1246 * when we know the PHY-type. */
1248 dev->phy.ops->switch_analog(dev, 1);
1250 macctl = b43_read32(dev, B43_MMIO_MACCTL);
1251 macctl &= ~B43_MACCTL_GMODE;
1253 macctl |= B43_MACCTL_GMODE;
1254 macctl |= B43_MACCTL_IHR_ENABLED;
1255 b43_write32(dev, B43_MMIO_MACCTL, macctl);
1258 static void handle_irq_transmit_status(struct b43_wldev *dev)
1262 struct b43_txstatus stat;
1265 v0 = b43_read32(dev, B43_MMIO_XMITSTAT_0);
1266 if (!(v0 & 0x00000001))
1268 v1 = b43_read32(dev, B43_MMIO_XMITSTAT_1);
1270 stat.cookie = (v0 >> 16);
1271 stat.seq = (v1 & 0x0000FFFF);
1272 stat.phy_stat = ((v1 & 0x00FF0000) >> 16);
1273 tmp = (v0 & 0x0000FFFF);
1274 stat.frame_count = ((tmp & 0xF000) >> 12);
1275 stat.rts_count = ((tmp & 0x0F00) >> 8);
1276 stat.supp_reason = ((tmp & 0x001C) >> 2);
1277 stat.pm_indicated = !!(tmp & 0x0080);
1278 stat.intermediate = !!(tmp & 0x0040);
1279 stat.for_ampdu = !!(tmp & 0x0020);
1280 stat.acked = !!(tmp & 0x0002);
1282 b43_handle_txstatus(dev, &stat);
1286 static void drain_txstatus_queue(struct b43_wldev *dev)
1290 if (dev->dev->core_rev < 5)
1292 /* Read all entries from the microcode TXstatus FIFO
1293 * and throw them away.
1296 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_0);
1297 if (!(dummy & 0x00000001))
1299 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_1);
1303 static u32 b43_jssi_read(struct b43_wldev *dev)
1307 val = b43_shm_read16(dev, B43_SHM_SHARED, 0x08A);
1309 val |= b43_shm_read16(dev, B43_SHM_SHARED, 0x088);
1314 static void b43_jssi_write(struct b43_wldev *dev, u32 jssi)
1316 b43_shm_write16(dev, B43_SHM_SHARED, 0x088, (jssi & 0x0000FFFF));
1317 b43_shm_write16(dev, B43_SHM_SHARED, 0x08A, (jssi & 0xFFFF0000) >> 16);
1320 static void b43_generate_noise_sample(struct b43_wldev *dev)
1322 b43_jssi_write(dev, 0x7F7F7F7F);
1323 b43_write32(dev, B43_MMIO_MACCMD,
1324 b43_read32(dev, B43_MMIO_MACCMD) | B43_MACCMD_BGNOISE);
1327 static void b43_calculate_link_quality(struct b43_wldev *dev)
1329 /* Top half of Link Quality calculation. */
1331 if (dev->phy.type != B43_PHYTYPE_G)
1333 if (dev->noisecalc.calculation_running)
1335 dev->noisecalc.calculation_running = 1;
1336 dev->noisecalc.nr_samples = 0;
1338 b43_generate_noise_sample(dev);
1341 static void handle_irq_noise(struct b43_wldev *dev)
1343 struct b43_phy_g *phy = dev->phy.g;
1349 /* Bottom half of Link Quality calculation. */
1351 if (dev->phy.type != B43_PHYTYPE_G)
1354 /* Possible race condition: It might be possible that the user
1355 * changed to a different channel in the meantime since we
1356 * started the calculation. We ignore that fact, since it's
1357 * not really that much of a problem. The background noise is
1358 * an estimation only anyway. Slightly wrong results will get damped
1359 * by the averaging of the 8 sample rounds. Additionally the
1360 * value is shortlived. So it will be replaced by the next noise
1361 * calculation round soon. */
1363 B43_WARN_ON(!dev->noisecalc.calculation_running);
1364 *((__le32 *)noise) = cpu_to_le32(b43_jssi_read(dev));
1365 if (noise[0] == 0x7F || noise[1] == 0x7F ||
1366 noise[2] == 0x7F || noise[3] == 0x7F)
1369 /* Get the noise samples. */
1370 B43_WARN_ON(dev->noisecalc.nr_samples >= 8);
1371 i = dev->noisecalc.nr_samples;
1372 noise[0] = clamp_val(noise[0], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1373 noise[1] = clamp_val(noise[1], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1374 noise[2] = clamp_val(noise[2], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1375 noise[3] = clamp_val(noise[3], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1376 dev->noisecalc.samples[i][0] = phy->nrssi_lt[noise[0]];
1377 dev->noisecalc.samples[i][1] = phy->nrssi_lt[noise[1]];
1378 dev->noisecalc.samples[i][2] = phy->nrssi_lt[noise[2]];
1379 dev->noisecalc.samples[i][3] = phy->nrssi_lt[noise[3]];
1380 dev->noisecalc.nr_samples++;
1381 if (dev->noisecalc.nr_samples == 8) {
1382 /* Calculate the Link Quality by the noise samples. */
1384 for (i = 0; i < 8; i++) {
1385 for (j = 0; j < 4; j++)
1386 average += dev->noisecalc.samples[i][j];
1392 tmp = b43_shm_read16(dev, B43_SHM_SHARED, 0x40C);
1393 tmp = (tmp / 128) & 0x1F;
1403 dev->stats.link_noise = average;
1404 dev->noisecalc.calculation_running = 0;
1408 b43_generate_noise_sample(dev);
1411 static void handle_irq_tbtt_indication(struct b43_wldev *dev)
1413 if (b43_is_mode(dev->wl, NL80211_IFTYPE_AP)) {
1416 if (1 /*FIXME: the last PSpoll frame was sent successfully */ )
1417 b43_power_saving_ctl_bits(dev, 0);
1419 if (b43_is_mode(dev->wl, NL80211_IFTYPE_ADHOC))
1423 static void handle_irq_atim_end(struct b43_wldev *dev)
1425 if (dev->dfq_valid) {
1426 b43_write32(dev, B43_MMIO_MACCMD,
1427 b43_read32(dev, B43_MMIO_MACCMD)
1428 | B43_MACCMD_DFQ_VALID);
1433 static void handle_irq_pmq(struct b43_wldev *dev)
1440 tmp = b43_read32(dev, B43_MMIO_PS_STATUS);
1441 if (!(tmp & 0x00000008))
1444 /* 16bit write is odd, but correct. */
1445 b43_write16(dev, B43_MMIO_PS_STATUS, 0x0002);
1448 static void b43_write_template_common(struct b43_wldev *dev,
1449 const u8 *data, u16 size,
1451 u16 shm_size_offset, u8 rate)
1454 struct b43_plcp_hdr4 plcp;
1457 b43_generate_plcp_hdr(&plcp, size + FCS_LEN, rate);
1458 b43_ram_write(dev, ram_offset, le32_to_cpu(plcp.data));
1459 ram_offset += sizeof(u32);
1460 /* The PLCP is 6 bytes long, but we only wrote 4 bytes, yet.
1461 * So leave the first two bytes of the next write blank.
1463 tmp = (u32) (data[0]) << 16;
1464 tmp |= (u32) (data[1]) << 24;
1465 b43_ram_write(dev, ram_offset, tmp);
1466 ram_offset += sizeof(u32);
1467 for (i = 2; i < size; i += sizeof(u32)) {
1468 tmp = (u32) (data[i + 0]);
1470 tmp |= (u32) (data[i + 1]) << 8;
1472 tmp |= (u32) (data[i + 2]) << 16;
1474 tmp |= (u32) (data[i + 3]) << 24;
1475 b43_ram_write(dev, ram_offset + i - 2, tmp);
1477 b43_shm_write16(dev, B43_SHM_SHARED, shm_size_offset,
1478 size + sizeof(struct b43_plcp_hdr6));
1481 /* Check if the use of the antenna that ieee80211 told us to
1482 * use is possible. This will fall back to DEFAULT.
1483 * "antenna_nr" is the antenna identifier we got from ieee80211. */
1484 u8 b43_ieee80211_antenna_sanitize(struct b43_wldev *dev,
1489 if (antenna_nr == 0) {
1490 /* Zero means "use default antenna". That's always OK. */
1494 /* Get the mask of available antennas. */
1496 antenna_mask = dev->dev->bus_sprom->ant_available_bg;
1498 antenna_mask = dev->dev->bus_sprom->ant_available_a;
1500 if (!(antenna_mask & (1 << (antenna_nr - 1)))) {
1501 /* This antenna is not available. Fall back to default. */
1508 /* Convert a b43 antenna number value to the PHY TX control value. */
1509 static u16 b43_antenna_to_phyctl(int antenna)
1513 return B43_TXH_PHY_ANT0;
1515 return B43_TXH_PHY_ANT1;
1517 return B43_TXH_PHY_ANT2;
1519 return B43_TXH_PHY_ANT3;
1520 case B43_ANTENNA_AUTO0:
1521 case B43_ANTENNA_AUTO1:
1522 return B43_TXH_PHY_ANT01AUTO;
1528 static void b43_write_beacon_template(struct b43_wldev *dev,
1530 u16 shm_size_offset)
1532 unsigned int i, len, variable_len;
1533 const struct ieee80211_mgmt *bcn;
1539 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(dev->wl->current_beacon);
1541 bcn = (const struct ieee80211_mgmt *)(dev->wl->current_beacon->data);
1542 len = min((size_t) dev->wl->current_beacon->len,
1543 0x200 - sizeof(struct b43_plcp_hdr6));
1544 rate = ieee80211_get_tx_rate(dev->wl->hw, info)->hw_value;
1546 b43_write_template_common(dev, (const u8 *)bcn,
1547 len, ram_offset, shm_size_offset, rate);
1549 /* Write the PHY TX control parameters. */
1550 antenna = B43_ANTENNA_DEFAULT;
1551 antenna = b43_antenna_to_phyctl(antenna);
1552 ctl = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL);
1553 /* We can't send beacons with short preamble. Would get PHY errors. */
1554 ctl &= ~B43_TXH_PHY_SHORTPRMBL;
1555 ctl &= ~B43_TXH_PHY_ANT;
1556 ctl &= ~B43_TXH_PHY_ENC;
1558 if (b43_is_cck_rate(rate))
1559 ctl |= B43_TXH_PHY_ENC_CCK;
1561 ctl |= B43_TXH_PHY_ENC_OFDM;
1562 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL, ctl);
1564 /* Find the position of the TIM and the DTIM_period value
1565 * and write them to SHM. */
1566 ie = bcn->u.beacon.variable;
1567 variable_len = len - offsetof(struct ieee80211_mgmt, u.beacon.variable);
1568 for (i = 0; i < variable_len - 2; ) {
1569 uint8_t ie_id, ie_len;
1576 /* This is the TIM Information Element */
1578 /* Check whether the ie_len is in the beacon data range. */
1579 if (variable_len < ie_len + 2 + i)
1581 /* A valid TIM is at least 4 bytes long. */
1586 tim_position = sizeof(struct b43_plcp_hdr6);
1587 tim_position += offsetof(struct ieee80211_mgmt, u.beacon.variable);
1590 dtim_period = ie[i + 3];
1592 b43_shm_write16(dev, B43_SHM_SHARED,
1593 B43_SHM_SH_TIMBPOS, tim_position);
1594 b43_shm_write16(dev, B43_SHM_SHARED,
1595 B43_SHM_SH_DTIMPER, dtim_period);
1602 * If ucode wants to modify TIM do it behind the beacon, this
1603 * will happen, for example, when doing mesh networking.
1605 b43_shm_write16(dev, B43_SHM_SHARED,
1607 len + sizeof(struct b43_plcp_hdr6));
1608 b43_shm_write16(dev, B43_SHM_SHARED,
1609 B43_SHM_SH_DTIMPER, 0);
1611 b43dbg(dev->wl, "Updated beacon template at 0x%x\n", ram_offset);
1614 static void b43_upload_beacon0(struct b43_wldev *dev)
1616 struct b43_wl *wl = dev->wl;
1618 if (wl->beacon0_uploaded)
1620 b43_write_beacon_template(dev, 0x68, 0x18);
1621 wl->beacon0_uploaded = 1;
1624 static void b43_upload_beacon1(struct b43_wldev *dev)
1626 struct b43_wl *wl = dev->wl;
1628 if (wl->beacon1_uploaded)
1630 b43_write_beacon_template(dev, 0x468, 0x1A);
1631 wl->beacon1_uploaded = 1;
1634 static void handle_irq_beacon(struct b43_wldev *dev)
1636 struct b43_wl *wl = dev->wl;
1637 u32 cmd, beacon0_valid, beacon1_valid;
1639 if (!b43_is_mode(wl, NL80211_IFTYPE_AP) &&
1640 !b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT) &&
1641 !b43_is_mode(wl, NL80211_IFTYPE_ADHOC))
1644 /* This is the bottom half of the asynchronous beacon update. */
1646 /* Ignore interrupt in the future. */
1647 dev->irq_mask &= ~B43_IRQ_BEACON;
1649 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1650 beacon0_valid = (cmd & B43_MACCMD_BEACON0_VALID);
1651 beacon1_valid = (cmd & B43_MACCMD_BEACON1_VALID);
1653 /* Schedule interrupt manually, if busy. */
1654 if (beacon0_valid && beacon1_valid) {
1655 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_BEACON);
1656 dev->irq_mask |= B43_IRQ_BEACON;
1660 if (unlikely(wl->beacon_templates_virgin)) {
1661 /* We never uploaded a beacon before.
1662 * Upload both templates now, but only mark one valid. */
1663 wl->beacon_templates_virgin = 0;
1664 b43_upload_beacon0(dev);
1665 b43_upload_beacon1(dev);
1666 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1667 cmd |= B43_MACCMD_BEACON0_VALID;
1668 b43_write32(dev, B43_MMIO_MACCMD, cmd);
1670 if (!beacon0_valid) {
1671 b43_upload_beacon0(dev);
1672 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1673 cmd |= B43_MACCMD_BEACON0_VALID;
1674 b43_write32(dev, B43_MMIO_MACCMD, cmd);
1675 } else if (!beacon1_valid) {
1676 b43_upload_beacon1(dev);
1677 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1678 cmd |= B43_MACCMD_BEACON1_VALID;
1679 b43_write32(dev, B43_MMIO_MACCMD, cmd);
1684 static void b43_do_beacon_update_trigger_work(struct b43_wldev *dev)
1686 u32 old_irq_mask = dev->irq_mask;
1688 /* update beacon right away or defer to irq */
1689 handle_irq_beacon(dev);
1690 if (old_irq_mask != dev->irq_mask) {
1691 /* The handler updated the IRQ mask. */
1692 B43_WARN_ON(!dev->irq_mask);
1693 if (b43_read32(dev, B43_MMIO_GEN_IRQ_MASK)) {
1694 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, dev->irq_mask);
1696 /* Device interrupts are currently disabled. That means
1697 * we just ran the hardirq handler and scheduled the
1698 * IRQ thread. The thread will write the IRQ mask when
1699 * it finished, so there's nothing to do here. Writing
1700 * the mask _here_ would incorrectly re-enable IRQs. */
1705 static void b43_beacon_update_trigger_work(struct work_struct *work)
1707 struct b43_wl *wl = container_of(work, struct b43_wl,
1708 beacon_update_trigger);
1709 struct b43_wldev *dev;
1711 mutex_lock(&wl->mutex);
1712 dev = wl->current_dev;
1713 if (likely(dev && (b43_status(dev) >= B43_STAT_INITIALIZED))) {
1714 if (b43_bus_host_is_sdio(dev->dev)) {
1715 /* wl->mutex is enough. */
1716 b43_do_beacon_update_trigger_work(dev);
1719 spin_lock_irq(&wl->hardirq_lock);
1720 b43_do_beacon_update_trigger_work(dev);
1722 spin_unlock_irq(&wl->hardirq_lock);
1725 mutex_unlock(&wl->mutex);
1728 /* Asynchronously update the packet templates in template RAM.
1729 * Locking: Requires wl->mutex to be locked. */
1730 static void b43_update_templates(struct b43_wl *wl)
1732 struct sk_buff *beacon;
1734 /* This is the top half of the ansynchronous beacon update.
1735 * The bottom half is the beacon IRQ.
1736 * Beacon update must be asynchronous to avoid sending an
1737 * invalid beacon. This can happen for example, if the firmware
1738 * transmits a beacon while we are updating it. */
1740 /* We could modify the existing beacon and set the aid bit in
1741 * the TIM field, but that would probably require resizing and
1742 * moving of data within the beacon template.
1743 * Simply request a new beacon and let mac80211 do the hard work. */
1744 beacon = ieee80211_beacon_get(wl->hw, wl->vif);
1745 if (unlikely(!beacon))
1748 if (wl->current_beacon)
1749 dev_kfree_skb_any(wl->current_beacon);
1750 wl->current_beacon = beacon;
1751 wl->beacon0_uploaded = 0;
1752 wl->beacon1_uploaded = 0;
1753 ieee80211_queue_work(wl->hw, &wl->beacon_update_trigger);
1756 static void b43_set_beacon_int(struct b43_wldev *dev, u16 beacon_int)
1759 if (dev->dev->core_rev >= 3) {
1760 b43_write32(dev, B43_MMIO_TSF_CFP_REP, (beacon_int << 16));
1761 b43_write32(dev, B43_MMIO_TSF_CFP_START, (beacon_int << 10));
1763 b43_write16(dev, 0x606, (beacon_int >> 6));
1764 b43_write16(dev, 0x610, beacon_int);
1766 b43_time_unlock(dev);
1767 b43dbg(dev->wl, "Set beacon interval to %u\n", beacon_int);
1770 static void b43_handle_firmware_panic(struct b43_wldev *dev)
1774 /* Read the register that contains the reason code for the panic. */
1775 reason = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_FWPANIC_REASON_REG);
1776 b43err(dev->wl, "Whoopsy, firmware panic! Reason: %u\n", reason);
1780 b43dbg(dev->wl, "The panic reason is unknown.\n");
1782 case B43_FWPANIC_DIE:
1783 /* Do not restart the controller or firmware.
1784 * The device is nonfunctional from now on.
1785 * Restarting would result in this panic to trigger again,
1786 * so we avoid that recursion. */
1788 case B43_FWPANIC_RESTART:
1789 b43_controller_restart(dev, "Microcode panic");
1794 static void handle_irq_ucode_debug(struct b43_wldev *dev)
1796 unsigned int i, cnt;
1797 u16 reason, marker_id, marker_line;
1800 /* The proprietary firmware doesn't have this IRQ. */
1801 if (!dev->fw.opensource)
1804 /* Read the register that contains the reason code for this IRQ. */
1805 reason = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_DEBUGIRQ_REASON_REG);
1808 case B43_DEBUGIRQ_PANIC:
1809 b43_handle_firmware_panic(dev);
1811 case B43_DEBUGIRQ_DUMP_SHM:
1813 break; /* Only with driver debugging enabled. */
1814 buf = kmalloc(4096, GFP_ATOMIC);
1816 b43dbg(dev->wl, "SHM-dump: Failed to allocate memory\n");
1819 for (i = 0; i < 4096; i += 2) {
1820 u16 tmp = b43_shm_read16(dev, B43_SHM_SHARED, i);
1821 buf[i / 2] = cpu_to_le16(tmp);
1823 b43info(dev->wl, "Shared memory dump:\n");
1824 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_OFFSET,
1825 16, 2, buf, 4096, 1);
1828 case B43_DEBUGIRQ_DUMP_REGS:
1830 break; /* Only with driver debugging enabled. */
1831 b43info(dev->wl, "Microcode register dump:\n");
1832 for (i = 0, cnt = 0; i < 64; i++) {
1833 u16 tmp = b43_shm_read16(dev, B43_SHM_SCRATCH, i);
1836 printk("r%02u: 0x%04X ", i, tmp);
1845 case B43_DEBUGIRQ_MARKER:
1847 break; /* Only with driver debugging enabled. */
1848 marker_id = b43_shm_read16(dev, B43_SHM_SCRATCH,
1850 marker_line = b43_shm_read16(dev, B43_SHM_SCRATCH,
1851 B43_MARKER_LINE_REG);
1852 b43info(dev->wl, "The firmware just executed the MARKER(%u) "
1853 "at line number %u\n",
1854 marker_id, marker_line);
1857 b43dbg(dev->wl, "Debug-IRQ triggered for unknown reason: %u\n",
1861 /* Acknowledge the debug-IRQ, so the firmware can continue. */
1862 b43_shm_write16(dev, B43_SHM_SCRATCH,
1863 B43_DEBUGIRQ_REASON_REG, B43_DEBUGIRQ_ACK);
1866 static void b43_do_interrupt_thread(struct b43_wldev *dev)
1869 u32 dma_reason[ARRAY_SIZE(dev->dma_reason)];
1870 u32 merged_dma_reason = 0;
1873 if (unlikely(b43_status(dev) != B43_STAT_STARTED))
1876 reason = dev->irq_reason;
1877 for (i = 0; i < ARRAY_SIZE(dma_reason); i++) {
1878 dma_reason[i] = dev->dma_reason[i];
1879 merged_dma_reason |= dma_reason[i];
1882 if (unlikely(reason & B43_IRQ_MAC_TXERR))
1883 b43err(dev->wl, "MAC transmission error\n");
1885 if (unlikely(reason & B43_IRQ_PHY_TXERR)) {
1886 b43err(dev->wl, "PHY transmission error\n");
1888 if (unlikely(atomic_dec_and_test(&dev->phy.txerr_cnt))) {
1889 atomic_set(&dev->phy.txerr_cnt,
1890 B43_PHY_TX_BADNESS_LIMIT);
1891 b43err(dev->wl, "Too many PHY TX errors, "
1892 "restarting the controller\n");
1893 b43_controller_restart(dev, "PHY TX errors");
1897 if (unlikely(merged_dma_reason & (B43_DMAIRQ_FATALMASK |
1898 B43_DMAIRQ_NONFATALMASK))) {
1899 if (merged_dma_reason & B43_DMAIRQ_FATALMASK) {
1900 b43err(dev->wl, "Fatal DMA error: "
1901 "0x%08X, 0x%08X, 0x%08X, "
1902 "0x%08X, 0x%08X, 0x%08X\n",
1903 dma_reason[0], dma_reason[1],
1904 dma_reason[2], dma_reason[3],
1905 dma_reason[4], dma_reason[5]);
1906 b43err(dev->wl, "This device does not support DMA "
1907 "on your system. It will now be switched to PIO.\n");
1908 /* Fall back to PIO transfers if we get fatal DMA errors! */
1910 b43_controller_restart(dev, "DMA error");
1913 if (merged_dma_reason & B43_DMAIRQ_NONFATALMASK) {
1914 b43err(dev->wl, "DMA error: "
1915 "0x%08X, 0x%08X, 0x%08X, "
1916 "0x%08X, 0x%08X, 0x%08X\n",
1917 dma_reason[0], dma_reason[1],
1918 dma_reason[2], dma_reason[3],
1919 dma_reason[4], dma_reason[5]);
1923 if (unlikely(reason & B43_IRQ_UCODE_DEBUG))
1924 handle_irq_ucode_debug(dev);
1925 if (reason & B43_IRQ_TBTT_INDI)
1926 handle_irq_tbtt_indication(dev);
1927 if (reason & B43_IRQ_ATIM_END)
1928 handle_irq_atim_end(dev);
1929 if (reason & B43_IRQ_BEACON)
1930 handle_irq_beacon(dev);
1931 if (reason & B43_IRQ_PMQ)
1932 handle_irq_pmq(dev);
1933 if (reason & B43_IRQ_TXFIFO_FLUSH_OK)
1935 if (reason & B43_IRQ_NOISESAMPLE_OK)
1936 handle_irq_noise(dev);
1938 /* Check the DMA reason registers for received data. */
1939 if (dma_reason[0] & B43_DMAIRQ_RX_DONE) {
1940 if (b43_using_pio_transfers(dev))
1941 b43_pio_rx(dev->pio.rx_queue);
1943 b43_dma_rx(dev->dma.rx_ring);
1945 B43_WARN_ON(dma_reason[1] & B43_DMAIRQ_RX_DONE);
1946 B43_WARN_ON(dma_reason[2] & B43_DMAIRQ_RX_DONE);
1947 B43_WARN_ON(dma_reason[3] & B43_DMAIRQ_RX_DONE);
1948 B43_WARN_ON(dma_reason[4] & B43_DMAIRQ_RX_DONE);
1949 B43_WARN_ON(dma_reason[5] & B43_DMAIRQ_RX_DONE);
1951 if (reason & B43_IRQ_TX_OK)
1952 handle_irq_transmit_status(dev);
1954 /* Re-enable interrupts on the device by restoring the current interrupt mask. */
1955 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, dev->irq_mask);
1958 if (b43_debug(dev, B43_DBG_VERBOSESTATS)) {
1960 for (i = 0; i < ARRAY_SIZE(dev->irq_bit_count); i++) {
1961 if (reason & (1 << i))
1962 dev->irq_bit_count[i]++;
1968 /* Interrupt thread handler. Handles device interrupts in thread context. */
1969 static irqreturn_t b43_interrupt_thread_handler(int irq, void *dev_id)
1971 struct b43_wldev *dev = dev_id;
1973 mutex_lock(&dev->wl->mutex);
1974 b43_do_interrupt_thread(dev);
1976 mutex_unlock(&dev->wl->mutex);
1981 static irqreturn_t b43_do_interrupt(struct b43_wldev *dev)
1985 /* This code runs under wl->hardirq_lock, but _only_ on non-SDIO busses.
1986 * On SDIO, this runs under wl->mutex. */
1988 reason = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
1989 if (reason == 0xffffffff) /* shared IRQ */
1991 reason &= dev->irq_mask;
1995 dev->dma_reason[0] = b43_read32(dev, B43_MMIO_DMA0_REASON)
1997 dev->dma_reason[1] = b43_read32(dev, B43_MMIO_DMA1_REASON)
1999 dev->dma_reason[2] = b43_read32(dev, B43_MMIO_DMA2_REASON)
2001 dev->dma_reason[3] = b43_read32(dev, B43_MMIO_DMA3_REASON)
2003 dev->dma_reason[4] = b43_read32(dev, B43_MMIO_DMA4_REASON)
2006 dev->dma_reason[5] = b43_read32(dev, B43_MMIO_DMA5_REASON)
2010 /* ACK the interrupt. */
2011 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, reason);
2012 b43_write32(dev, B43_MMIO_DMA0_REASON, dev->dma_reason[0]);
2013 b43_write32(dev, B43_MMIO_DMA1_REASON, dev->dma_reason[1]);
2014 b43_write32(dev, B43_MMIO_DMA2_REASON, dev->dma_reason[2]);
2015 b43_write32(dev, B43_MMIO_DMA3_REASON, dev->dma_reason[3]);
2016 b43_write32(dev, B43_MMIO_DMA4_REASON, dev->dma_reason[4]);
2018 b43_write32(dev, B43_MMIO_DMA5_REASON, dev->dma_reason[5]);
2021 /* Disable IRQs on the device. The IRQ thread handler will re-enable them. */
2022 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, 0);
2023 /* Save the reason bitmasks for the IRQ thread handler. */
2024 dev->irq_reason = reason;
2026 return IRQ_WAKE_THREAD;
2029 /* Interrupt handler top-half. This runs with interrupts disabled. */
2030 static irqreturn_t b43_interrupt_handler(int irq, void *dev_id)
2032 struct b43_wldev *dev = dev_id;
2035 if (unlikely(b43_status(dev) < B43_STAT_STARTED))
2038 spin_lock(&dev->wl->hardirq_lock);
2039 ret = b43_do_interrupt(dev);
2041 spin_unlock(&dev->wl->hardirq_lock);
2046 /* SDIO interrupt handler. This runs in process context. */
2047 static void b43_sdio_interrupt_handler(struct b43_wldev *dev)
2049 struct b43_wl *wl = dev->wl;
2052 mutex_lock(&wl->mutex);
2054 ret = b43_do_interrupt(dev);
2055 if (ret == IRQ_WAKE_THREAD)
2056 b43_do_interrupt_thread(dev);
2058 mutex_unlock(&wl->mutex);
2061 void b43_do_release_fw(struct b43_firmware_file *fw)
2063 release_firmware(fw->data);
2065 fw->filename = NULL;
2068 static void b43_release_firmware(struct b43_wldev *dev)
2070 b43_do_release_fw(&dev->fw.ucode);
2071 b43_do_release_fw(&dev->fw.pcm);
2072 b43_do_release_fw(&dev->fw.initvals);
2073 b43_do_release_fw(&dev->fw.initvals_band);
2076 static void b43_print_fw_helptext(struct b43_wl *wl, bool error)
2080 "http://wireless.kernel.org/en/users/Drivers/b43#devicefirmware " \
2081 "and download the correct firmware for this driver version. " \
2082 "Please carefully read all instructions on this website.\n";
2090 int b43_do_request_fw(struct b43_request_fw_context *ctx,
2092 struct b43_firmware_file *fw)
2094 const struct firmware *blob;
2095 struct b43_fw_header *hdr;
2100 /* Don't fetch anything. Free possibly cached firmware. */
2101 /* FIXME: We should probably keep it anyway, to save some headache
2102 * on suspend/resume with multiband devices. */
2103 b43_do_release_fw(fw);
2107 if ((fw->type == ctx->req_type) &&
2108 (strcmp(fw->filename, name) == 0))
2109 return 0; /* Already have this fw. */
2110 /* Free the cached firmware first. */
2111 /* FIXME: We should probably do this later after we successfully
2112 * got the new fw. This could reduce headache with multiband devices.
2113 * We could also redesign this to cache the firmware for all possible
2114 * bands all the time. */
2115 b43_do_release_fw(fw);
2118 switch (ctx->req_type) {
2119 case B43_FWTYPE_PROPRIETARY:
2120 snprintf(ctx->fwname, sizeof(ctx->fwname),
2122 modparam_fwpostfix, name);
2124 case B43_FWTYPE_OPENSOURCE:
2125 snprintf(ctx->fwname, sizeof(ctx->fwname),
2127 modparam_fwpostfix, name);
2133 err = request_firmware(&blob, ctx->fwname, ctx->dev->dev->dev);
2134 if (err == -ENOENT) {
2135 snprintf(ctx->errors[ctx->req_type],
2136 sizeof(ctx->errors[ctx->req_type]),
2137 "Firmware file \"%s\" not found\n", ctx->fwname);
2140 snprintf(ctx->errors[ctx->req_type],
2141 sizeof(ctx->errors[ctx->req_type]),
2142 "Firmware file \"%s\" request failed (err=%d)\n",
2146 if (blob->size < sizeof(struct b43_fw_header))
2148 hdr = (struct b43_fw_header *)(blob->data);
2149 switch (hdr->type) {
2150 case B43_FW_TYPE_UCODE:
2151 case B43_FW_TYPE_PCM:
2152 size = be32_to_cpu(hdr->size);
2153 if (size != blob->size - sizeof(struct b43_fw_header))
2156 case B43_FW_TYPE_IV:
2165 fw->filename = name;
2166 fw->type = ctx->req_type;
2171 snprintf(ctx->errors[ctx->req_type],
2172 sizeof(ctx->errors[ctx->req_type]),
2173 "Firmware file \"%s\" format error.\n", ctx->fwname);
2174 release_firmware(blob);
2179 static int b43_try_request_fw(struct b43_request_fw_context *ctx)
2181 struct b43_wldev *dev = ctx->dev;
2182 struct b43_firmware *fw = &ctx->dev->fw;
2183 const u8 rev = ctx->dev->dev->core_rev;
2184 const char *filename;
2188 /* Files for HT and LCN were found by trying one by one */
2191 if ((rev >= 5) && (rev <= 10)) {
2192 filename = "ucode5";
2193 } else if ((rev >= 11) && (rev <= 12)) {
2194 filename = "ucode11";
2195 } else if (rev == 13) {
2196 filename = "ucode13";
2197 } else if (rev == 14) {
2198 filename = "ucode14";
2199 } else if (rev == 15) {
2200 filename = "ucode15";
2202 switch (dev->phy.type) {
2205 filename = "ucode16_mimo";
2209 case B43_PHYTYPE_HT:
2211 filename = "ucode29_mimo";
2215 case B43_PHYTYPE_LCN:
2217 filename = "ucode24_mimo";
2225 err = b43_do_request_fw(ctx, filename, &fw->ucode);
2230 if ((rev >= 5) && (rev <= 10))
2236 fw->pcm_request_failed = 0;
2237 err = b43_do_request_fw(ctx, filename, &fw->pcm);
2238 if (err == -ENOENT) {
2239 /* We did not find a PCM file? Not fatal, but
2240 * core rev <= 10 must do without hwcrypto then. */
2241 fw->pcm_request_failed = 1;
2246 switch (dev->phy.type) {
2248 if ((rev >= 5) && (rev <= 10)) {
2249 tmshigh = ssb_read32(dev->dev->sdev, SSB_TMSHIGH);
2250 if (tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY)
2251 filename = "a0g1initvals5";
2253 filename = "a0g0initvals5";
2255 goto err_no_initvals;
2258 if ((rev >= 5) && (rev <= 10))
2259 filename = "b0g0initvals5";
2261 filename = "b0g0initvals13";
2263 goto err_no_initvals;
2267 filename = "n0initvals16";
2268 else if ((rev >= 11) && (rev <= 12))
2269 filename = "n0initvals11";
2271 goto err_no_initvals;
2273 case B43_PHYTYPE_LP:
2275 filename = "lp0initvals13";
2277 filename = "lp0initvals14";
2279 filename = "lp0initvals15";
2281 goto err_no_initvals;
2283 case B43_PHYTYPE_HT:
2285 filename = "ht0initvals29";
2287 goto err_no_initvals;
2289 case B43_PHYTYPE_LCN:
2291 filename = "lcn0initvals24";
2293 goto err_no_initvals;
2296 goto err_no_initvals;
2298 err = b43_do_request_fw(ctx, filename, &fw->initvals);
2302 /* Get bandswitch initvals */
2303 switch (dev->phy.type) {
2305 if ((rev >= 5) && (rev <= 10)) {
2306 tmshigh = ssb_read32(dev->dev->sdev, SSB_TMSHIGH);
2307 if (tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY)
2308 filename = "a0g1bsinitvals5";
2310 filename = "a0g0bsinitvals5";
2311 } else if (rev >= 11)
2314 goto err_no_initvals;
2317 if ((rev >= 5) && (rev <= 10))
2318 filename = "b0g0bsinitvals5";
2322 goto err_no_initvals;
2326 filename = "n0bsinitvals16";
2327 else if ((rev >= 11) && (rev <= 12))
2328 filename = "n0bsinitvals11";
2330 goto err_no_initvals;
2332 case B43_PHYTYPE_LP:
2334 filename = "lp0bsinitvals13";
2336 filename = "lp0bsinitvals14";
2338 filename = "lp0bsinitvals15";
2340 goto err_no_initvals;
2342 case B43_PHYTYPE_HT:
2344 filename = "ht0bsinitvals29";
2346 goto err_no_initvals;
2348 case B43_PHYTYPE_LCN:
2350 filename = "lcn0bsinitvals24";
2352 goto err_no_initvals;
2355 goto err_no_initvals;
2357 err = b43_do_request_fw(ctx, filename, &fw->initvals_band);
2364 err = ctx->fatal_failure = -EOPNOTSUPP;
2365 b43err(dev->wl, "The driver does not know which firmware (ucode) "
2366 "is required for your device (wl-core rev %u)\n", rev);
2370 err = ctx->fatal_failure = -EOPNOTSUPP;
2371 b43err(dev->wl, "The driver does not know which firmware (PCM) "
2372 "is required for your device (wl-core rev %u)\n", rev);
2376 err = ctx->fatal_failure = -EOPNOTSUPP;
2377 b43err(dev->wl, "The driver does not know which firmware (initvals) "
2378 "is required for your device (wl-core rev %u)\n", rev);
2382 /* We failed to load this firmware image. The error message
2383 * already is in ctx->errors. Return and let our caller decide
2388 b43_release_firmware(dev);
2392 static int b43_request_firmware(struct b43_wldev *dev)
2394 struct b43_request_fw_context *ctx;
2399 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
2404 ctx->req_type = B43_FWTYPE_PROPRIETARY;
2405 err = b43_try_request_fw(ctx);
2407 goto out; /* Successfully loaded it. */
2408 err = ctx->fatal_failure;
2412 ctx->req_type = B43_FWTYPE_OPENSOURCE;
2413 err = b43_try_request_fw(ctx);
2415 goto out; /* Successfully loaded it. */
2416 err = ctx->fatal_failure;
2420 /* Could not find a usable firmware. Print the errors. */
2421 for (i = 0; i < B43_NR_FWTYPES; i++) {
2422 errmsg = ctx->errors[i];
2424 b43err(dev->wl, errmsg);
2426 b43_print_fw_helptext(dev->wl, 1);
2434 static int b43_upload_microcode(struct b43_wldev *dev)
2436 struct wiphy *wiphy = dev->wl->hw->wiphy;
2437 const size_t hdr_len = sizeof(struct b43_fw_header);
2439 unsigned int i, len;
2440 u16 fwrev, fwpatch, fwdate, fwtime;
2444 /* Jump the microcode PSM to offset 0 */
2445 macctl = b43_read32(dev, B43_MMIO_MACCTL);
2446 B43_WARN_ON(macctl & B43_MACCTL_PSM_RUN);
2447 macctl |= B43_MACCTL_PSM_JMP0;
2448 b43_write32(dev, B43_MMIO_MACCTL, macctl);
2449 /* Zero out all microcode PSM registers and shared memory. */
2450 for (i = 0; i < 64; i++)
2451 b43_shm_write16(dev, B43_SHM_SCRATCH, i, 0);
2452 for (i = 0; i < 4096; i += 2)
2453 b43_shm_write16(dev, B43_SHM_SHARED, i, 0);
2455 /* Upload Microcode. */
2456 data = (__be32 *) (dev->fw.ucode.data->data + hdr_len);
2457 len = (dev->fw.ucode.data->size - hdr_len) / sizeof(__be32);
2458 b43_shm_control_word(dev, B43_SHM_UCODE | B43_SHM_AUTOINC_W, 0x0000);
2459 for (i = 0; i < len; i++) {
2460 b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
2464 if (dev->fw.pcm.data) {
2465 /* Upload PCM data. */
2466 data = (__be32 *) (dev->fw.pcm.data->data + hdr_len);
2467 len = (dev->fw.pcm.data->size - hdr_len) / sizeof(__be32);
2468 b43_shm_control_word(dev, B43_SHM_HW, 0x01EA);
2469 b43_write32(dev, B43_MMIO_SHM_DATA, 0x00004000);
2470 /* No need for autoinc bit in SHM_HW */
2471 b43_shm_control_word(dev, B43_SHM_HW, 0x01EB);
2472 for (i = 0; i < len; i++) {
2473 b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
2478 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_ALL);
2480 /* Start the microcode PSM */
2481 macctl = b43_read32(dev, B43_MMIO_MACCTL);
2482 macctl &= ~B43_MACCTL_PSM_JMP0;
2483 macctl |= B43_MACCTL_PSM_RUN;
2484 b43_write32(dev, B43_MMIO_MACCTL, macctl);
2486 /* Wait for the microcode to load and respond */
2489 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2490 if (tmp == B43_IRQ_MAC_SUSPENDED)
2494 b43err(dev->wl, "Microcode not responding\n");
2495 b43_print_fw_helptext(dev->wl, 1);
2501 b43_read32(dev, B43_MMIO_GEN_IRQ_REASON); /* dummy read */
2503 /* Get and check the revisions. */
2504 fwrev = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEREV);
2505 fwpatch = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEPATCH);
2506 fwdate = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEDATE);
2507 fwtime = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODETIME);
2509 if (fwrev <= 0x128) {
2510 b43err(dev->wl, "YOUR FIRMWARE IS TOO OLD. Firmware from "
2511 "binary drivers older than version 4.x is unsupported. "
2512 "You must upgrade your firmware files.\n");
2513 b43_print_fw_helptext(dev->wl, 1);
2517 dev->fw.rev = fwrev;
2518 dev->fw.patch = fwpatch;
2519 if (dev->fw.rev >= 598)
2520 dev->fw.hdr_format = B43_FW_HDR_598;
2521 else if (dev->fw.rev >= 410)
2522 dev->fw.hdr_format = B43_FW_HDR_410;
2524 dev->fw.hdr_format = B43_FW_HDR_351;
2525 dev->fw.opensource = (fwdate == 0xFFFF);
2527 /* Default to use-all-queues. */
2528 dev->wl->hw->queues = dev->wl->mac80211_initially_registered_queues;
2529 dev->qos_enabled = !!modparam_qos;
2530 /* Default to firmware/hardware crypto acceleration. */
2531 dev->hwcrypto_enabled = 1;
2533 if (dev->fw.opensource) {
2536 /* Patchlevel info is encoded in the "time" field. */
2537 dev->fw.patch = fwtime;
2538 b43info(dev->wl, "Loading OpenSource firmware version %u.%u\n",
2539 dev->fw.rev, dev->fw.patch);
2541 fwcapa = b43_fwcapa_read(dev);
2542 if (!(fwcapa & B43_FWCAPA_HWCRYPTO) || dev->fw.pcm_request_failed) {
2543 b43info(dev->wl, "Hardware crypto acceleration not supported by firmware\n");
2544 /* Disable hardware crypto and fall back to software crypto. */
2545 dev->hwcrypto_enabled = 0;
2547 if (!(fwcapa & B43_FWCAPA_QOS)) {
2548 b43info(dev->wl, "QoS not supported by firmware\n");
2549 /* Disable QoS. Tweak hw->queues to 1. It will be restored before
2550 * ieee80211_unregister to make sure the networking core can
2551 * properly free possible resources. */
2552 dev->wl->hw->queues = 1;
2553 dev->qos_enabled = 0;
2556 b43info(dev->wl, "Loading firmware version %u.%u "
2557 "(20%.2i-%.2i-%.2i %.2i:%.2i:%.2i)\n",
2559 (fwdate >> 12) & 0xF, (fwdate >> 8) & 0xF, fwdate & 0xFF,
2560 (fwtime >> 11) & 0x1F, (fwtime >> 5) & 0x3F, fwtime & 0x1F);
2561 if (dev->fw.pcm_request_failed) {
2562 b43warn(dev->wl, "No \"pcm5.fw\" firmware file found. "
2563 "Hardware accelerated cryptography is disabled.\n");
2564 b43_print_fw_helptext(dev->wl, 0);
2568 snprintf(wiphy->fw_version, sizeof(wiphy->fw_version), "%u.%u",
2569 dev->fw.rev, dev->fw.patch);
2570 wiphy->hw_version = dev->dev->core_id;
2572 if (dev->fw.hdr_format == B43_FW_HDR_351) {
2573 /* We're over the deadline, but we keep support for old fw
2574 * until it turns out to be in major conflict with something new. */
2575 b43warn(dev->wl, "You are using an old firmware image. "
2576 "Support for old firmware will be removed soon "
2577 "(official deadline was July 2008).\n");
2578 b43_print_fw_helptext(dev->wl, 0);
2584 macctl = b43_read32(dev, B43_MMIO_MACCTL);
2585 macctl &= ~B43_MACCTL_PSM_RUN;
2586 macctl |= B43_MACCTL_PSM_JMP0;
2587 b43_write32(dev, B43_MMIO_MACCTL, macctl);
2592 static int b43_write_initvals(struct b43_wldev *dev,
2593 const struct b43_iv *ivals,
2597 const struct b43_iv *iv;
2602 BUILD_BUG_ON(sizeof(struct b43_iv) != 6);
2604 for (i = 0; i < count; i++) {
2605 if (array_size < sizeof(iv->offset_size))
2607 array_size -= sizeof(iv->offset_size);
2608 offset = be16_to_cpu(iv->offset_size);
2609 bit32 = !!(offset & B43_IV_32BIT);
2610 offset &= B43_IV_OFFSET_MASK;
2611 if (offset >= 0x1000)
2616 if (array_size < sizeof(iv->data.d32))
2618 array_size -= sizeof(iv->data.d32);
2620 value = get_unaligned_be32(&iv->data.d32);
2621 b43_write32(dev, offset, value);
2623 iv = (const struct b43_iv *)((const uint8_t *)iv +
2629 if (array_size < sizeof(iv->data.d16))
2631 array_size -= sizeof(iv->data.d16);
2633 value = be16_to_cpu(iv->data.d16);
2634 b43_write16(dev, offset, value);
2636 iv = (const struct b43_iv *)((const uint8_t *)iv +
2647 b43err(dev->wl, "Initial Values Firmware file-format error.\n");
2648 b43_print_fw_helptext(dev->wl, 1);
2653 static int b43_upload_initvals(struct b43_wldev *dev)
2655 const size_t hdr_len = sizeof(struct b43_fw_header);
2656 const struct b43_fw_header *hdr;
2657 struct b43_firmware *fw = &dev->fw;
2658 const struct b43_iv *ivals;
2662 hdr = (const struct b43_fw_header *)(fw->initvals.data->data);
2663 ivals = (const struct b43_iv *)(fw->initvals.data->data + hdr_len);
2664 count = be32_to_cpu(hdr->size);
2665 err = b43_write_initvals(dev, ivals, count,
2666 fw->initvals.data->size - hdr_len);
2669 if (fw->initvals_band.data) {
2670 hdr = (const struct b43_fw_header *)(fw->initvals_band.data->data);
2671 ivals = (const struct b43_iv *)(fw->initvals_band.data->data + hdr_len);
2672 count = be32_to_cpu(hdr->size);
2673 err = b43_write_initvals(dev, ivals, count,
2674 fw->initvals_band.data->size - hdr_len);
2683 /* Initialize the GPIOs
2684 * http://bcm-specs.sipsolutions.net/GPIO
2686 static struct ssb_device *b43_ssb_gpio_dev(struct b43_wldev *dev)
2688 struct ssb_bus *bus = dev->dev->sdev->bus;
2690 #ifdef CONFIG_SSB_DRIVER_PCICORE
2691 return (bus->chipco.dev ? bus->chipco.dev : bus->pcicore.dev);
2693 return bus->chipco.dev;
2697 static int b43_gpio_init(struct b43_wldev *dev)
2699 struct ssb_device *gpiodev;
2702 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
2703 & ~B43_MACCTL_GPOUTSMSK);
2705 b43_write16(dev, B43_MMIO_GPIO_MASK, b43_read16(dev, B43_MMIO_GPIO_MASK)
2710 if (dev->dev->chip_id == 0x4301) {
2714 if (0 /* FIXME: conditional unknown */ ) {
2715 b43_write16(dev, B43_MMIO_GPIO_MASK,
2716 b43_read16(dev, B43_MMIO_GPIO_MASK)
2721 if (dev->dev->bus_sprom->boardflags_lo & B43_BFL_PACTRL) {
2722 b43_write16(dev, B43_MMIO_GPIO_MASK,
2723 b43_read16(dev, B43_MMIO_GPIO_MASK)
2728 if (dev->dev->core_rev >= 2)
2729 mask |= 0x0010; /* FIXME: This is redundant. */
2731 switch (dev->dev->bus_type) {
2732 #ifdef CONFIG_B43_BCMA
2734 bcma_cc_write32(&dev->dev->bdev->bus->drv_cc, BCMA_CC_GPIOCTL,
2735 (bcma_cc_read32(&dev->dev->bdev->bus->drv_cc,
2736 BCMA_CC_GPIOCTL) & mask) | set);
2739 #ifdef CONFIG_B43_SSB
2741 gpiodev = b43_ssb_gpio_dev(dev);
2743 ssb_write32(gpiodev, B43_GPIO_CONTROL,
2744 (ssb_read32(gpiodev, B43_GPIO_CONTROL)
2753 /* Turn off all GPIO stuff. Call this on module unload, for example. */
2754 static void b43_gpio_cleanup(struct b43_wldev *dev)
2756 struct ssb_device *gpiodev;
2758 switch (dev->dev->bus_type) {
2759 #ifdef CONFIG_B43_BCMA
2761 bcma_cc_write32(&dev->dev->bdev->bus->drv_cc, BCMA_CC_GPIOCTL,
2765 #ifdef CONFIG_B43_SSB
2767 gpiodev = b43_ssb_gpio_dev(dev);
2769 ssb_write32(gpiodev, B43_GPIO_CONTROL, 0);
2775 /* http://bcm-specs.sipsolutions.net/EnableMac */
2776 void b43_mac_enable(struct b43_wldev *dev)
2778 if (b43_debug(dev, B43_DBG_FIRMWARE)) {
2781 fwstate = b43_shm_read16(dev, B43_SHM_SHARED,
2782 B43_SHM_SH_UCODESTAT);
2783 if ((fwstate != B43_SHM_SH_UCODESTAT_SUSP) &&
2784 (fwstate != B43_SHM_SH_UCODESTAT_SLEEP)) {
2785 b43err(dev->wl, "b43_mac_enable(): The firmware "
2786 "should be suspended, but current state is %u\n",
2791 dev->mac_suspended--;
2792 B43_WARN_ON(dev->mac_suspended < 0);
2793 if (dev->mac_suspended == 0) {
2794 b43_write32(dev, B43_MMIO_MACCTL,
2795 b43_read32(dev, B43_MMIO_MACCTL)
2796 | B43_MACCTL_ENABLED);
2797 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON,
2798 B43_IRQ_MAC_SUSPENDED);
2800 b43_read32(dev, B43_MMIO_MACCTL);
2801 b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2802 b43_power_saving_ctl_bits(dev, 0);
2806 /* http://bcm-specs.sipsolutions.net/SuspendMAC */
2807 void b43_mac_suspend(struct b43_wldev *dev)
2813 B43_WARN_ON(dev->mac_suspended < 0);
2815 if (dev->mac_suspended == 0) {
2816 b43_power_saving_ctl_bits(dev, B43_PS_AWAKE);
2817 b43_write32(dev, B43_MMIO_MACCTL,
2818 b43_read32(dev, B43_MMIO_MACCTL)
2819 & ~B43_MACCTL_ENABLED);
2820 /* force pci to flush the write */
2821 b43_read32(dev, B43_MMIO_MACCTL);
2822 for (i = 35; i; i--) {
2823 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2824 if (tmp & B43_IRQ_MAC_SUSPENDED)
2828 /* Hm, it seems this will take some time. Use msleep(). */
2829 for (i = 40; i; i--) {
2830 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2831 if (tmp & B43_IRQ_MAC_SUSPENDED)
2835 b43err(dev->wl, "MAC suspend failed\n");
2838 dev->mac_suspended++;
2841 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/MacPhyClkSet */
2842 void b43_mac_phy_clock_set(struct b43_wldev *dev, bool on)
2846 switch (dev->dev->bus_type) {
2847 #ifdef CONFIG_B43_BCMA
2849 tmp = bcma_aread32(dev->dev->bdev, BCMA_IOCTL);
2851 tmp |= B43_BCMA_IOCTL_MACPHYCLKEN;
2853 tmp &= ~B43_BCMA_IOCTL_MACPHYCLKEN;
2854 bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, tmp);
2857 #ifdef CONFIG_B43_SSB
2859 tmp = ssb_read32(dev->dev->sdev, SSB_TMSLOW);
2861 tmp |= B43_TMSLOW_MACPHYCLKEN;
2863 tmp &= ~B43_TMSLOW_MACPHYCLKEN;
2864 ssb_write32(dev->dev->sdev, SSB_TMSLOW, tmp);
2870 static void b43_adjust_opmode(struct b43_wldev *dev)
2872 struct b43_wl *wl = dev->wl;
2876 ctl = b43_read32(dev, B43_MMIO_MACCTL);
2877 /* Reset status to STA infrastructure mode. */
2878 ctl &= ~B43_MACCTL_AP;
2879 ctl &= ~B43_MACCTL_KEEP_CTL;
2880 ctl &= ~B43_MACCTL_KEEP_BADPLCP;
2881 ctl &= ~B43_MACCTL_KEEP_BAD;
2882 ctl &= ~B43_MACCTL_PROMISC;
2883 ctl &= ~B43_MACCTL_BEACPROMISC;
2884 ctl |= B43_MACCTL_INFRA;
2886 if (b43_is_mode(wl, NL80211_IFTYPE_AP) ||
2887 b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT))
2888 ctl |= B43_MACCTL_AP;
2889 else if (b43_is_mode(wl, NL80211_IFTYPE_ADHOC))
2890 ctl &= ~B43_MACCTL_INFRA;
2892 if (wl->filter_flags & FIF_CONTROL)
2893 ctl |= B43_MACCTL_KEEP_CTL;
2894 if (wl->filter_flags & FIF_FCSFAIL)
2895 ctl |= B43_MACCTL_KEEP_BAD;
2896 if (wl->filter_flags & FIF_PLCPFAIL)
2897 ctl |= B43_MACCTL_KEEP_BADPLCP;
2898 if (wl->filter_flags & FIF_PROMISC_IN_BSS)
2899 ctl |= B43_MACCTL_PROMISC;
2900 if (wl->filter_flags & FIF_BCN_PRBRESP_PROMISC)
2901 ctl |= B43_MACCTL_BEACPROMISC;
2903 /* Workaround: On old hardware the HW-MAC-address-filter
2904 * doesn't work properly, so always run promisc in filter
2905 * it in software. */
2906 if (dev->dev->core_rev <= 4)
2907 ctl |= B43_MACCTL_PROMISC;
2909 b43_write32(dev, B43_MMIO_MACCTL, ctl);
2912 if ((ctl & B43_MACCTL_INFRA) && !(ctl & B43_MACCTL_AP)) {
2913 if (dev->dev->chip_id == 0x4306 &&
2914 dev->dev->chip_rev == 3)
2919 b43_write16(dev, 0x612, cfp_pretbtt);
2921 /* FIXME: We don't currently implement the PMQ mechanism,
2922 * so always disable it. If we want to implement PMQ,
2923 * we need to enable it here (clear DISCPMQ) in AP mode.
2925 if (0 /* ctl & B43_MACCTL_AP */) {
2926 b43_write32(dev, B43_MMIO_MACCTL,
2927 b43_read32(dev, B43_MMIO_MACCTL)
2928 & ~B43_MACCTL_DISCPMQ);
2930 b43_write32(dev, B43_MMIO_MACCTL,
2931 b43_read32(dev, B43_MMIO_MACCTL)
2932 | B43_MACCTL_DISCPMQ);
2936 static void b43_rate_memory_write(struct b43_wldev *dev, u16 rate, int is_ofdm)
2942 offset += (b43_plcp_get_ratecode_ofdm(rate) & 0x000F) * 2;
2945 offset += (b43_plcp_get_ratecode_cck(rate) & 0x000F) * 2;
2947 b43_shm_write16(dev, B43_SHM_SHARED, offset + 0x20,
2948 b43_shm_read16(dev, B43_SHM_SHARED, offset));
2951 static void b43_rate_memory_init(struct b43_wldev *dev)
2953 switch (dev->phy.type) {
2957 case B43_PHYTYPE_LP:
2958 case B43_PHYTYPE_HT:
2959 case B43_PHYTYPE_LCN:
2960 b43_rate_memory_write(dev, B43_OFDM_RATE_6MB, 1);
2961 b43_rate_memory_write(dev, B43_OFDM_RATE_12MB, 1);
2962 b43_rate_memory_write(dev, B43_OFDM_RATE_18MB, 1);
2963 b43_rate_memory_write(dev, B43_OFDM_RATE_24MB, 1);
2964 b43_rate_memory_write(dev, B43_OFDM_RATE_36MB, 1);
2965 b43_rate_memory_write(dev, B43_OFDM_RATE_48MB, 1);
2966 b43_rate_memory_write(dev, B43_OFDM_RATE_54MB, 1);
2967 if (dev->phy.type == B43_PHYTYPE_A)
2971 b43_rate_memory_write(dev, B43_CCK_RATE_1MB, 0);
2972 b43_rate_memory_write(dev, B43_CCK_RATE_2MB, 0);
2973 b43_rate_memory_write(dev, B43_CCK_RATE_5MB, 0);
2974 b43_rate_memory_write(dev, B43_CCK_RATE_11MB, 0);
2981 /* Set the default values for the PHY TX Control Words. */
2982 static void b43_set_phytxctl_defaults(struct b43_wldev *dev)
2986 ctl |= B43_TXH_PHY_ENC_CCK;
2987 ctl |= B43_TXH_PHY_ANT01AUTO;
2988 ctl |= B43_TXH_PHY_TXPWR;
2990 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL, ctl);
2991 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL, ctl);
2992 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL, ctl);
2995 /* Set the TX-Antenna for management frames sent by firmware. */
2996 static void b43_mgmtframe_txantenna(struct b43_wldev *dev, int antenna)
3001 ant = b43_antenna_to_phyctl(antenna);
3004 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL);
3005 tmp = (tmp & ~B43_TXH_PHY_ANT) | ant;
3006 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL, tmp);
3007 /* For Probe Resposes */
3008 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL);
3009 tmp = (tmp & ~B43_TXH_PHY_ANT) | ant;
3010 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL, tmp);
3013 /* This is the opposite of b43_chip_init() */
3014 static void b43_chip_exit(struct b43_wldev *dev)
3017 b43_gpio_cleanup(dev);
3018 /* firmware is released later */
3021 /* Initialize the chip
3022 * http://bcm-specs.sipsolutions.net/ChipInit
3024 static int b43_chip_init(struct b43_wldev *dev)
3026 struct b43_phy *phy = &dev->phy;
3031 /* Initialize the MAC control */
3032 macctl = B43_MACCTL_IHR_ENABLED | B43_MACCTL_SHM_ENABLED;
3034 macctl |= B43_MACCTL_GMODE;
3035 macctl |= B43_MACCTL_INFRA;
3036 b43_write32(dev, B43_MMIO_MACCTL, macctl);
3038 err = b43_request_firmware(dev);
3041 err = b43_upload_microcode(dev);
3043 goto out; /* firmware is released later */
3045 err = b43_gpio_init(dev);
3047 goto out; /* firmware is released later */
3049 err = b43_upload_initvals(dev);
3051 goto err_gpio_clean;
3053 /* Turn the Analog on and initialize the PHY. */
3054 phy->ops->switch_analog(dev, 1);
3055 err = b43_phy_init(dev);
3057 goto err_gpio_clean;
3059 /* Disable Interference Mitigation. */
3060 if (phy->ops->interf_mitigation)
3061 phy->ops->interf_mitigation(dev, B43_INTERFMODE_NONE);
3063 /* Select the antennae */
3064 if (phy->ops->set_rx_antenna)
3065 phy->ops->set_rx_antenna(dev, B43_ANTENNA_DEFAULT);
3066 b43_mgmtframe_txantenna(dev, B43_ANTENNA_DEFAULT);
3068 if (phy->type == B43_PHYTYPE_B) {
3069 value16 = b43_read16(dev, 0x005E);
3071 b43_write16(dev, 0x005E, value16);
3073 b43_write32(dev, 0x0100, 0x01000000);
3074 if (dev->dev->core_rev < 5)
3075 b43_write32(dev, 0x010C, 0x01000000);
3077 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
3078 & ~B43_MACCTL_INFRA);
3079 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
3080 | B43_MACCTL_INFRA);
3082 /* Probe Response Timeout value */
3083 /* FIXME: Default to 0, has to be set by ioctl probably... :-/ */
3084 b43_shm_write16(dev, B43_SHM_SHARED, 0x0074, 0x0000);
3086 /* Initially set the wireless operation mode. */
3087 b43_adjust_opmode(dev);
3089 if (dev->dev->core_rev < 3) {
3090 b43_write16(dev, 0x060E, 0x0000);
3091 b43_write16(dev, 0x0610, 0x8000);
3092 b43_write16(dev, 0x0604, 0x0000);
3093 b43_write16(dev, 0x0606, 0x0200);
3095 b43_write32(dev, 0x0188, 0x80000000);
3096 b43_write32(dev, 0x018C, 0x02000000);
3098 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, 0x00004000);
3099 b43_write32(dev, B43_MMIO_DMA0_IRQ_MASK, 0x0001DC00);
3100 b43_write32(dev, B43_MMIO_DMA1_IRQ_MASK, 0x0000DC00);
3101 b43_write32(dev, B43_MMIO_DMA2_IRQ_MASK, 0x0000DC00);
3102 b43_write32(dev, B43_MMIO_DMA3_IRQ_MASK, 0x0001DC00);
3103 b43_write32(dev, B43_MMIO_DMA4_IRQ_MASK, 0x0000DC00);
3104 b43_write32(dev, B43_MMIO_DMA5_IRQ_MASK, 0x0000DC00);
3106 b43_mac_phy_clock_set(dev, true);
3108 switch (dev->dev->bus_type) {
3109 #ifdef CONFIG_B43_BCMA
3111 /* FIXME: 0xE74 is quite common, but should be read from CC */
3112 b43_write16(dev, B43_MMIO_POWERUP_DELAY, 0xE74);
3115 #ifdef CONFIG_B43_SSB
3117 b43_write16(dev, B43_MMIO_POWERUP_DELAY,
3118 dev->dev->sdev->bus->chipco.fast_pwrup_delay);
3124 b43dbg(dev->wl, "Chip initialized\n");
3129 b43_gpio_cleanup(dev);
3133 static void b43_periodic_every60sec(struct b43_wldev *dev)
3135 const struct b43_phy_operations *ops = dev->phy.ops;
3137 if (ops->pwork_60sec)
3138 ops->pwork_60sec(dev);
3140 /* Force check the TX power emission now. */
3141 b43_phy_txpower_check(dev, B43_TXPWR_IGNORE_TIME);
3144 static void b43_periodic_every30sec(struct b43_wldev *dev)
3146 /* Update device statistics. */
3147 b43_calculate_link_quality(dev);
3150 static void b43_periodic_every15sec(struct b43_wldev *dev)
3152 struct b43_phy *phy = &dev->phy;
3155 if (dev->fw.opensource) {
3156 /* Check if the firmware is still alive.
3157 * It will reset the watchdog counter to 0 in its idle loop. */
3158 wdr = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_WATCHDOG_REG);
3159 if (unlikely(wdr)) {
3160 b43err(dev->wl, "Firmware watchdog: The firmware died!\n");
3161 b43_controller_restart(dev, "Firmware watchdog");
3164 b43_shm_write16(dev, B43_SHM_SCRATCH,
3165 B43_WATCHDOG_REG, 1);
3169 if (phy->ops->pwork_15sec)
3170 phy->ops->pwork_15sec(dev);
3172 atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT);
3176 if (b43_debug(dev, B43_DBG_VERBOSESTATS)) {
3179 b43dbg(dev->wl, "Stats: %7u IRQs/sec, %7u TX/sec, %7u RX/sec\n",
3180 dev->irq_count / 15,
3182 dev->rx_count / 15);
3186 for (i = 0; i < ARRAY_SIZE(dev->irq_bit_count); i++) {
3187 if (dev->irq_bit_count[i]) {
3188 b43dbg(dev->wl, "Stats: %7u IRQ-%02u/sec (0x%08X)\n",
3189 dev->irq_bit_count[i] / 15, i, (1 << i));
3190 dev->irq_bit_count[i] = 0;
3197 static void do_periodic_work(struct b43_wldev *dev)
3201 state = dev->periodic_state;
3203 b43_periodic_every60sec(dev);
3205 b43_periodic_every30sec(dev);
3206 b43_periodic_every15sec(dev);
3209 /* Periodic work locking policy:
3210 * The whole periodic work handler is protected by
3211 * wl->mutex. If another lock is needed somewhere in the
3212 * pwork callchain, it's acquired in-place, where it's needed.
3214 static void b43_periodic_work_handler(struct work_struct *work)
3216 struct b43_wldev *dev = container_of(work, struct b43_wldev,
3217 periodic_work.work);
3218 struct b43_wl *wl = dev->wl;
3219 unsigned long delay;
3221 mutex_lock(&wl->mutex);
3223 if (unlikely(b43_status(dev) != B43_STAT_STARTED))
3225 if (b43_debug(dev, B43_DBG_PWORK_STOP))
3228 do_periodic_work(dev);
3230 dev->periodic_state++;
3232 if (b43_debug(dev, B43_DBG_PWORK_FAST))
3233 delay = msecs_to_jiffies(50);
3235 delay = round_jiffies_relative(HZ * 15);
3236 ieee80211_queue_delayed_work(wl->hw, &dev->periodic_work, delay);
3238 mutex_unlock(&wl->mutex);
3241 static void b43_periodic_tasks_setup(struct b43_wldev *dev)
3243 struct delayed_work *work = &dev->periodic_work;
3245 dev->periodic_state = 0;
3246 INIT_DELAYED_WORK(work, b43_periodic_work_handler);
3247 ieee80211_queue_delayed_work(dev->wl->hw, work, 0);
3250 /* Check if communication with the device works correctly. */
3251 static int b43_validate_chipaccess(struct b43_wldev *dev)
3253 u32 v, backup0, backup4;
3255 backup0 = b43_shm_read32(dev, B43_SHM_SHARED, 0);
3256 backup4 = b43_shm_read32(dev, B43_SHM_SHARED, 4);
3258 /* Check for read/write and endianness problems. */
3259 b43_shm_write32(dev, B43_SHM_SHARED, 0, 0x55AAAA55);
3260 if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0x55AAAA55)
3262 b43_shm_write32(dev, B43_SHM_SHARED, 0, 0xAA5555AA);
3263 if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0xAA5555AA)
3266 /* Check if unaligned 32bit SHM_SHARED access works properly.
3267 * However, don't bail out on failure, because it's noncritical. */
3268 b43_shm_write16(dev, B43_SHM_SHARED, 0, 0x1122);
3269 b43_shm_write16(dev, B43_SHM_SHARED, 2, 0x3344);
3270 b43_shm_write16(dev, B43_SHM_SHARED, 4, 0x5566);
3271 b43_shm_write16(dev, B43_SHM_SHARED, 6, 0x7788);
3272 if (b43_shm_read32(dev, B43_SHM_SHARED, 2) != 0x55663344)
3273 b43warn(dev->wl, "Unaligned 32bit SHM read access is broken\n");
3274 b43_shm_write32(dev, B43_SHM_SHARED, 2, 0xAABBCCDD);
3275 if (b43_shm_read16(dev, B43_SHM_SHARED, 0) != 0x1122 ||
3276 b43_shm_read16(dev, B43_SHM_SHARED, 2) != 0xCCDD ||
3277 b43_shm_read16(dev, B43_SHM_SHARED, 4) != 0xAABB ||
3278 b43_shm_read16(dev, B43_SHM_SHARED, 6) != 0x7788)
3279 b43warn(dev->wl, "Unaligned 32bit SHM write access is broken\n");
3281 b43_shm_write32(dev, B43_SHM_SHARED, 0, backup0);
3282 b43_shm_write32(dev, B43_SHM_SHARED, 4, backup4);
3284 if ((dev->dev->core_rev >= 3) && (dev->dev->core_rev <= 10)) {
3285 /* The 32bit register shadows the two 16bit registers
3286 * with update sideeffects. Validate this. */
3287 b43_write16(dev, B43_MMIO_TSF_CFP_START, 0xAAAA);
3288 b43_write32(dev, B43_MMIO_TSF_CFP_START, 0xCCCCBBBB);
3289 if (b43_read16(dev, B43_MMIO_TSF_CFP_START_LOW) != 0xBBBB)
3291 if (b43_read16(dev, B43_MMIO_TSF_CFP_START_HIGH) != 0xCCCC)
3294 b43_write32(dev, B43_MMIO_TSF_CFP_START, 0);
3296 v = b43_read32(dev, B43_MMIO_MACCTL);
3297 v |= B43_MACCTL_GMODE;
3298 if (v != (B43_MACCTL_GMODE | B43_MACCTL_IHR_ENABLED))
3303 b43err(dev->wl, "Failed to validate the chipaccess\n");
3307 static void b43_security_init(struct b43_wldev *dev)
3309 dev->ktp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_KTP);
3310 /* KTP is a word address, but we address SHM bytewise.
3311 * So multiply by two.
3314 /* Number of RCMTA address slots */
3315 b43_write16(dev, B43_MMIO_RCMTA_COUNT, B43_NR_PAIRWISE_KEYS);
3316 /* Clear the key memory. */
3317 b43_clear_keys(dev);
3320 #ifdef CONFIG_B43_HWRNG
3321 static int b43_rng_read(struct hwrng *rng, u32 *data)
3323 struct b43_wl *wl = (struct b43_wl *)rng->priv;
3324 struct b43_wldev *dev;
3325 int count = -ENODEV;
3327 mutex_lock(&wl->mutex);
3328 dev = wl->current_dev;
3329 if (likely(dev && b43_status(dev) >= B43_STAT_INITIALIZED)) {
3330 *data = b43_read16(dev, B43_MMIO_RNG);
3331 count = sizeof(u16);
3333 mutex_unlock(&wl->mutex);
3337 #endif /* CONFIG_B43_HWRNG */
3339 static void b43_rng_exit(struct b43_wl *wl)
3341 #ifdef CONFIG_B43_HWRNG
3342 if (wl->rng_initialized)
3343 hwrng_unregister(&wl->rng);
3344 #endif /* CONFIG_B43_HWRNG */
3347 static int b43_rng_init(struct b43_wl *wl)
3351 #ifdef CONFIG_B43_HWRNG
3352 snprintf(wl->rng_name, ARRAY_SIZE(wl->rng_name),
3353 "%s_%s", KBUILD_MODNAME, wiphy_name(wl->hw->wiphy));
3354 wl->rng.name = wl->rng_name;
3355 wl->rng.data_read = b43_rng_read;
3356 wl->rng.priv = (unsigned long)wl;
3357 wl->rng_initialized = 1;
3358 err = hwrng_register(&wl->rng);
3360 wl->rng_initialized = 0;
3361 b43err(wl, "Failed to register the random "
3362 "number generator (%d)\n", err);
3364 #endif /* CONFIG_B43_HWRNG */
3369 static void b43_tx_work(struct work_struct *work)
3371 struct b43_wl *wl = container_of(work, struct b43_wl, tx_work);
3372 struct b43_wldev *dev;
3373 struct sk_buff *skb;
3376 mutex_lock(&wl->mutex);
3377 dev = wl->current_dev;
3378 if (unlikely(!dev || b43_status(dev) < B43_STAT_STARTED)) {
3379 mutex_unlock(&wl->mutex);
3383 while (skb_queue_len(&wl->tx_queue)) {
3384 skb = skb_dequeue(&wl->tx_queue);
3386 if (b43_using_pio_transfers(dev))
3387 err = b43_pio_tx(dev, skb);
3389 err = b43_dma_tx(dev, skb);
3391 dev_kfree_skb(skb); /* Drop it */
3397 mutex_unlock(&wl->mutex);
3400 static void b43_op_tx(struct ieee80211_hw *hw,
3401 struct sk_buff *skb)
3403 struct b43_wl *wl = hw_to_b43_wl(hw);
3405 if (unlikely(skb->len < 2 + 2 + 6)) {
3406 /* Too short, this can't be a valid frame. */
3407 dev_kfree_skb_any(skb);
3410 B43_WARN_ON(skb_shinfo(skb)->nr_frags);
3412 skb_queue_tail(&wl->tx_queue, skb);
3413 ieee80211_queue_work(wl->hw, &wl->tx_work);
3416 static void b43_qos_params_upload(struct b43_wldev *dev,
3417 const struct ieee80211_tx_queue_params *p,
3420 u16 params[B43_NR_QOSPARAMS];
3424 if (!dev->qos_enabled)
3427 bslots = b43_read16(dev, B43_MMIO_RNG) & p->cw_min;
3429 memset(¶ms, 0, sizeof(params));
3431 params[B43_QOSPARAM_TXOP] = p->txop * 32;
3432 params[B43_QOSPARAM_CWMIN] = p->cw_min;
3433 params[B43_QOSPARAM_CWMAX] = p->cw_max;
3434 params[B43_QOSPARAM_CWCUR] = p->cw_min;
3435 params[B43_QOSPARAM_AIFS] = p->aifs;
3436 params[B43_QOSPARAM_BSLOTS] = bslots;
3437 params[B43_QOSPARAM_REGGAP] = bslots + p->aifs;
3439 for (i = 0; i < ARRAY_SIZE(params); i++) {
3440 if (i == B43_QOSPARAM_STATUS) {
3441 tmp = b43_shm_read16(dev, B43_SHM_SHARED,
3442 shm_offset + (i * 2));
3443 /* Mark the parameters as updated. */
3445 b43_shm_write16(dev, B43_SHM_SHARED,
3446 shm_offset + (i * 2),
3449 b43_shm_write16(dev, B43_SHM_SHARED,
3450 shm_offset + (i * 2),
3456 /* Mapping of mac80211 queue numbers to b43 QoS SHM offsets. */
3457 static const u16 b43_qos_shm_offsets[] = {
3458 /* [mac80211-queue-nr] = SHM_OFFSET, */
3459 [0] = B43_QOS_VOICE,
3460 [1] = B43_QOS_VIDEO,
3461 [2] = B43_QOS_BESTEFFORT,
3462 [3] = B43_QOS_BACKGROUND,
3465 /* Update all QOS parameters in hardware. */
3466 static void b43_qos_upload_all(struct b43_wldev *dev)
3468 struct b43_wl *wl = dev->wl;
3469 struct b43_qos_params *params;
3472 if (!dev->qos_enabled)
3475 BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets) !=
3476 ARRAY_SIZE(wl->qos_params));
3478 b43_mac_suspend(dev);
3479 for (i = 0; i < ARRAY_SIZE(wl->qos_params); i++) {
3480 params = &(wl->qos_params[i]);
3481 b43_qos_params_upload(dev, &(params->p),
3482 b43_qos_shm_offsets[i]);
3484 b43_mac_enable(dev);
3487 static void b43_qos_clear(struct b43_wl *wl)
3489 struct b43_qos_params *params;
3492 /* Initialize QoS parameters to sane defaults. */
3494 BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets) !=
3495 ARRAY_SIZE(wl->qos_params));
3497 for (i = 0; i < ARRAY_SIZE(wl->qos_params); i++) {
3498 params = &(wl->qos_params[i]);
3500 switch (b43_qos_shm_offsets[i]) {
3504 params->p.cw_min = 0x0001;
3505 params->p.cw_max = 0x0001;
3510 params->p.cw_min = 0x0001;
3511 params->p.cw_max = 0x0001;
3513 case B43_QOS_BESTEFFORT:
3516 params->p.cw_min = 0x0001;
3517 params->p.cw_max = 0x03FF;
3519 case B43_QOS_BACKGROUND:
3522 params->p.cw_min = 0x0001;
3523 params->p.cw_max = 0x03FF;
3531 /* Initialize the core's QOS capabilities */
3532 static void b43_qos_init(struct b43_wldev *dev)
3534 if (!dev->qos_enabled) {
3535 /* Disable QOS support. */
3536 b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_EDCF);
3537 b43_write16(dev, B43_MMIO_IFSCTL,
3538 b43_read16(dev, B43_MMIO_IFSCTL)
3539 & ~B43_MMIO_IFSCTL_USE_EDCF);
3540 b43dbg(dev->wl, "QoS disabled\n");
3544 /* Upload the current QOS parameters. */
3545 b43_qos_upload_all(dev);
3547 /* Enable QOS support. */
3548 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_EDCF);
3549 b43_write16(dev, B43_MMIO_IFSCTL,
3550 b43_read16(dev, B43_MMIO_IFSCTL)
3551 | B43_MMIO_IFSCTL_USE_EDCF);
3552 b43dbg(dev->wl, "QoS enabled\n");
3555 static int b43_op_conf_tx(struct ieee80211_hw *hw, u16 _queue,
3556 const struct ieee80211_tx_queue_params *params)
3558 struct b43_wl *wl = hw_to_b43_wl(hw);
3559 struct b43_wldev *dev;
3560 unsigned int queue = (unsigned int)_queue;
3563 if (queue >= ARRAY_SIZE(wl->qos_params)) {
3564 /* Queue not available or don't support setting
3565 * params on this queue. Return success to not
3566 * confuse mac80211. */
3569 BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets) !=
3570 ARRAY_SIZE(wl->qos_params));
3572 mutex_lock(&wl->mutex);
3573 dev = wl->current_dev;
3574 if (unlikely(!dev || (b43_status(dev) < B43_STAT_INITIALIZED)))
3577 memcpy(&(wl->qos_params[queue].p), params, sizeof(*params));
3578 b43_mac_suspend(dev);
3579 b43_qos_params_upload(dev, &(wl->qos_params[queue].p),
3580 b43_qos_shm_offsets[queue]);
3581 b43_mac_enable(dev);
3585 mutex_unlock(&wl->mutex);
3590 static int b43_op_get_stats(struct ieee80211_hw *hw,
3591 struct ieee80211_low_level_stats *stats)
3593 struct b43_wl *wl = hw_to_b43_wl(hw);
3595 mutex_lock(&wl->mutex);
3596 memcpy(stats, &wl->ieee_stats, sizeof(*stats));
3597 mutex_unlock(&wl->mutex);
3602 static u64 b43_op_get_tsf(struct ieee80211_hw *hw)
3604 struct b43_wl *wl = hw_to_b43_wl(hw);
3605 struct b43_wldev *dev;
3608 mutex_lock(&wl->mutex);
3609 dev = wl->current_dev;
3611 if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED))
3612 b43_tsf_read(dev, &tsf);
3616 mutex_unlock(&wl->mutex);
3621 static void b43_op_set_tsf(struct ieee80211_hw *hw, u64 tsf)
3623 struct b43_wl *wl = hw_to_b43_wl(hw);
3624 struct b43_wldev *dev;
3626 mutex_lock(&wl->mutex);
3627 dev = wl->current_dev;
3629 if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED))
3630 b43_tsf_write(dev, tsf);
3632 mutex_unlock(&wl->mutex);
3635 static void b43_put_phy_into_reset(struct b43_wldev *dev)
3639 switch (dev->dev->bus_type) {
3640 #ifdef CONFIG_B43_BCMA
3643 "Putting PHY into reset not supported on BCMA\n");
3646 #ifdef CONFIG_B43_SSB
3648 tmp = ssb_read32(dev->dev->sdev, SSB_TMSLOW);
3649 tmp &= ~B43_TMSLOW_GMODE;
3650 tmp |= B43_TMSLOW_PHYRESET;
3651 tmp |= SSB_TMSLOW_FGC;
3652 ssb_write32(dev->dev->sdev, SSB_TMSLOW, tmp);
3655 tmp = ssb_read32(dev->dev->sdev, SSB_TMSLOW);
3656 tmp &= ~SSB_TMSLOW_FGC;
3657 tmp |= B43_TMSLOW_PHYRESET;
3658 ssb_write32(dev->dev->sdev, SSB_TMSLOW, tmp);
3666 static const char *band_to_string(enum ieee80211_band band)
3669 case IEEE80211_BAND_5GHZ:
3671 case IEEE80211_BAND_2GHZ:
3680 /* Expects wl->mutex locked */
3681 static int b43_switch_band(struct b43_wl *wl, struct ieee80211_channel *chan)
3683 struct b43_wldev *up_dev = NULL;
3684 struct b43_wldev *down_dev;
3685 struct b43_wldev *d;
3687 bool uninitialized_var(gmode);
3690 /* Find a device and PHY which supports the band. */
3691 list_for_each_entry(d, &wl->devlist, list) {
3692 switch (chan->band) {
3693 case IEEE80211_BAND_5GHZ:
3694 if (d->phy.supports_5ghz) {
3699 case IEEE80211_BAND_2GHZ:
3700 if (d->phy.supports_2ghz) {
3713 b43err(wl, "Could not find a device for %s-GHz band operation\n",
3714 band_to_string(chan->band));
3717 if ((up_dev == wl->current_dev) &&
3718 (!!wl->current_dev->phy.gmode == !!gmode)) {
3719 /* This device is already running. */
3722 b43dbg(wl, "Switching to %s-GHz band\n",
3723 band_to_string(chan->band));
3724 down_dev = wl->current_dev;
3726 prev_status = b43_status(down_dev);
3727 /* Shutdown the currently running core. */
3728 if (prev_status >= B43_STAT_STARTED)
3729 down_dev = b43_wireless_core_stop(down_dev);
3730 if (prev_status >= B43_STAT_INITIALIZED)
3731 b43_wireless_core_exit(down_dev);
3733 if (down_dev != up_dev) {
3734 /* We switch to a different core, so we put PHY into
3735 * RESET on the old core. */
3736 b43_put_phy_into_reset(down_dev);
3739 /* Now start the new core. */
3740 up_dev->phy.gmode = gmode;
3741 if (prev_status >= B43_STAT_INITIALIZED) {
3742 err = b43_wireless_core_init(up_dev);
3744 b43err(wl, "Fatal: Could not initialize device for "
3745 "selected %s-GHz band\n",
3746 band_to_string(chan->band));
3750 if (prev_status >= B43_STAT_STARTED) {
3751 err = b43_wireless_core_start(up_dev);
3753 b43err(wl, "Fatal: Coult not start device for "
3754 "selected %s-GHz band\n",
3755 band_to_string(chan->band));
3756 b43_wireless_core_exit(up_dev);
3760 B43_WARN_ON(b43_status(up_dev) != prev_status);
3762 wl->current_dev = up_dev;
3766 /* Whoops, failed to init the new core. No core is operating now. */
3767 wl->current_dev = NULL;
3771 /* Write the short and long frame retry limit values. */
3772 static void b43_set_retry_limits(struct b43_wldev *dev,
3773 unsigned int short_retry,
3774 unsigned int long_retry)
3776 /* The retry limit is a 4-bit counter. Enforce this to avoid overflowing
3777 * the chip-internal counter. */
3778 short_retry = min(short_retry, (unsigned int)0xF);
3779 long_retry = min(long_retry, (unsigned int)0xF);
3781 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_SRLIMIT,
3783 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_LRLIMIT,
3787 static int b43_op_config(struct ieee80211_hw *hw, u32 changed)
3789 struct b43_wl *wl = hw_to_b43_wl(hw);
3790 struct b43_wldev *dev;
3791 struct b43_phy *phy;
3792 struct ieee80211_conf *conf = &hw->conf;
3795 bool reload_bss = false;
3797 mutex_lock(&wl->mutex);
3799 dev = wl->current_dev;
3801 /* Switch the band (if necessary). This might change the active core. */
3802 err = b43_switch_band(wl, conf->channel);
3804 goto out_unlock_mutex;
3806 /* Need to reload all settings if the core changed */
3807 if (dev != wl->current_dev) {
3808 dev = wl->current_dev;
3815 if (conf_is_ht(conf))
3817 (conf_is_ht40_minus(conf) || conf_is_ht40_plus(conf));
3819 phy->is_40mhz = false;
3821 b43_mac_suspend(dev);
3823 if (changed & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
3824 b43_set_retry_limits(dev, conf->short_frame_max_tx_count,
3825 conf->long_frame_max_tx_count);
3826 changed &= ~IEEE80211_CONF_CHANGE_RETRY_LIMITS;
3828 goto out_mac_enable;
3830 /* Switch to the requested channel.
3831 * The firmware takes care of races with the TX handler. */
3832 if (conf->channel->hw_value != phy->channel)
3833 b43_switch_channel(dev, conf->channel->hw_value);
3835 dev->wl->radiotap_enabled = !!(conf->flags & IEEE80211_CONF_MONITOR);
3837 /* Adjust the desired TX power level. */
3838 if (conf->power_level != 0) {
3839 if (conf->power_level != phy->desired_txpower) {
3840 phy->desired_txpower = conf->power_level;
3841 b43_phy_txpower_check(dev, B43_TXPWR_IGNORE_TIME |
3842 B43_TXPWR_IGNORE_TSSI);
3846 /* Antennas for RX and management frame TX. */
3847 antenna = B43_ANTENNA_DEFAULT;
3848 b43_mgmtframe_txantenna(dev, antenna);
3849 antenna = B43_ANTENNA_DEFAULT;
3850 if (phy->ops->set_rx_antenna)
3851 phy->ops->set_rx_antenna(dev, antenna);
3853 if (wl->radio_enabled != phy->radio_on) {
3854 if (wl->radio_enabled) {
3855 b43_software_rfkill(dev, false);
3856 b43info(dev->wl, "Radio turned on by software\n");
3857 if (!dev->radio_hw_enable) {
3858 b43info(dev->wl, "The hardware RF-kill button "
3859 "still turns the radio physically off. "
3860 "Press the button to turn it on.\n");
3863 b43_software_rfkill(dev, true);
3864 b43info(dev->wl, "Radio turned off by software\n");
3869 b43_mac_enable(dev);
3871 mutex_unlock(&wl->mutex);
3873 if (wl->vif && reload_bss)
3874 b43_op_bss_info_changed(hw, wl->vif, &wl->vif->bss_conf, ~0);
3879 static void b43_update_basic_rates(struct b43_wldev *dev, u32 brates)
3881 struct ieee80211_supported_band *sband =
3882 dev->wl->hw->wiphy->bands[b43_current_band(dev->wl)];
3883 struct ieee80211_rate *rate;
3885 u16 basic, direct, offset, basic_offset, rateptr;
3887 for (i = 0; i < sband->n_bitrates; i++) {
3888 rate = &sband->bitrates[i];
3890 if (b43_is_cck_rate(rate->hw_value)) {
3891 direct = B43_SHM_SH_CCKDIRECT;
3892 basic = B43_SHM_SH_CCKBASIC;
3893 offset = b43_plcp_get_ratecode_cck(rate->hw_value);
3896 direct = B43_SHM_SH_OFDMDIRECT;
3897 basic = B43_SHM_SH_OFDMBASIC;
3898 offset = b43_plcp_get_ratecode_ofdm(rate->hw_value);
3902 rate = ieee80211_get_response_rate(sband, brates, rate->bitrate);
3904 if (b43_is_cck_rate(rate->hw_value)) {
3905 basic_offset = b43_plcp_get_ratecode_cck(rate->hw_value);
3906 basic_offset &= 0xF;
3908 basic_offset = b43_plcp_get_ratecode_ofdm(rate->hw_value);
3909 basic_offset &= 0xF;
3913 * Get the pointer that we need to point to
3914 * from the direct map
3916 rateptr = b43_shm_read16(dev, B43_SHM_SHARED,
3917 direct + 2 * basic_offset);
3918 /* and write it to the basic map */
3919 b43_shm_write16(dev, B43_SHM_SHARED, basic + 2 * offset,
3924 static void b43_op_bss_info_changed(struct ieee80211_hw *hw,
3925 struct ieee80211_vif *vif,
3926 struct ieee80211_bss_conf *conf,
3929 struct b43_wl *wl = hw_to_b43_wl(hw);
3930 struct b43_wldev *dev;
3932 mutex_lock(&wl->mutex);
3934 dev = wl->current_dev;
3935 if (!dev || b43_status(dev) < B43_STAT_STARTED)
3936 goto out_unlock_mutex;
3938 B43_WARN_ON(wl->vif != vif);
3940 if (changed & BSS_CHANGED_BSSID) {
3942 memcpy(wl->bssid, conf->bssid, ETH_ALEN);
3944 memset(wl->bssid, 0, ETH_ALEN);
3947 if (b43_status(dev) >= B43_STAT_INITIALIZED) {
3948 if (changed & BSS_CHANGED_BEACON &&
3949 (b43_is_mode(wl, NL80211_IFTYPE_AP) ||
3950 b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT) ||
3951 b43_is_mode(wl, NL80211_IFTYPE_ADHOC)))
3952 b43_update_templates(wl);
3954 if (changed & BSS_CHANGED_BSSID)
3955 b43_write_mac_bssid_templates(dev);
3958 b43_mac_suspend(dev);
3960 /* Update templates for AP/mesh mode. */
3961 if (changed & BSS_CHANGED_BEACON_INT &&
3962 (b43_is_mode(wl, NL80211_IFTYPE_AP) ||
3963 b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT) ||
3964 b43_is_mode(wl, NL80211_IFTYPE_ADHOC)) &&
3966 b43_set_beacon_int(dev, conf->beacon_int);
3968 if (changed & BSS_CHANGED_BASIC_RATES)
3969 b43_update_basic_rates(dev, conf->basic_rates);
3971 if (changed & BSS_CHANGED_ERP_SLOT) {
3972 if (conf->use_short_slot)
3973 b43_short_slot_timing_enable(dev);
3975 b43_short_slot_timing_disable(dev);
3978 b43_mac_enable(dev);
3980 mutex_unlock(&wl->mutex);
3983 static int b43_op_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
3984 struct ieee80211_vif *vif, struct ieee80211_sta *sta,
3985 struct ieee80211_key_conf *key)
3987 struct b43_wl *wl = hw_to_b43_wl(hw);
3988 struct b43_wldev *dev;
3992 static const u8 bcast_addr[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
3994 if (modparam_nohwcrypt)
3995 return -ENOSPC; /* User disabled HW-crypto */
3997 mutex_lock(&wl->mutex);
3999 dev = wl->current_dev;
4001 if (!dev || b43_status(dev) < B43_STAT_INITIALIZED)
4004 if (dev->fw.pcm_request_failed || !dev->hwcrypto_enabled) {
4005 /* We don't have firmware for the crypto engine.
4006 * Must use software-crypto. */
4012 switch (key->cipher) {
4013 case WLAN_CIPHER_SUITE_WEP40:
4014 algorithm = B43_SEC_ALGO_WEP40;
4016 case WLAN_CIPHER_SUITE_WEP104:
4017 algorithm = B43_SEC_ALGO_WEP104;
4019 case WLAN_CIPHER_SUITE_TKIP:
4020 algorithm = B43_SEC_ALGO_TKIP;
4022 case WLAN_CIPHER_SUITE_CCMP:
4023 algorithm = B43_SEC_ALGO_AES;
4029 index = (u8) (key->keyidx);
4035 if (algorithm == B43_SEC_ALGO_TKIP &&
4036 (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE) ||
4037 !modparam_hwtkip)) {
4038 /* We support only pairwise key */
4043 if (key->flags & IEEE80211_KEY_FLAG_PAIRWISE) {
4044 if (WARN_ON(!sta)) {
4048 /* Pairwise key with an assigned MAC address. */
4049 err = b43_key_write(dev, -1, algorithm,
4050 key->key, key->keylen,
4054 err = b43_key_write(dev, index, algorithm,
4055 key->key, key->keylen, NULL, key);
4060 if (algorithm == B43_SEC_ALGO_WEP40 ||
4061 algorithm == B43_SEC_ALGO_WEP104) {
4062 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_USEDEFKEYS);
4065 b43_hf_read(dev) & ~B43_HF_USEDEFKEYS);
4067 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
4068 if (algorithm == B43_SEC_ALGO_TKIP)
4069 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
4072 err = b43_key_clear(dev, key->hw_key_idx);
4083 b43dbg(wl, "%s hardware based encryption for keyidx: %d, "
4085 cmd == SET_KEY ? "Using" : "Disabling", key->keyidx,
4086 sta ? sta->addr : bcast_addr);
4087 b43_dump_keymemory(dev);
4089 mutex_unlock(&wl->mutex);
4094 static void b43_op_configure_filter(struct ieee80211_hw *hw,
4095 unsigned int changed, unsigned int *fflags,
4098 struct b43_wl *wl = hw_to_b43_wl(hw);
4099 struct b43_wldev *dev;
4101 mutex_lock(&wl->mutex);
4102 dev = wl->current_dev;
4108 *fflags &= FIF_PROMISC_IN_BSS |
4114 FIF_BCN_PRBRESP_PROMISC;
4116 changed &= FIF_PROMISC_IN_BSS |
4122 FIF_BCN_PRBRESP_PROMISC;
4124 wl->filter_flags = *fflags;
4126 if (changed && b43_status(dev) >= B43_STAT_INITIALIZED)
4127 b43_adjust_opmode(dev);
4130 mutex_unlock(&wl->mutex);
4133 /* Locking: wl->mutex
4134 * Returns the current dev. This might be different from the passed in dev,
4135 * because the core might be gone away while we unlocked the mutex. */
4136 static struct b43_wldev * b43_wireless_core_stop(struct b43_wldev *dev)
4139 struct b43_wldev *orig_dev;
4146 if (!dev || b43_status(dev) < B43_STAT_STARTED)
4149 /* Cancel work. Unlock to avoid deadlocks. */
4150 mutex_unlock(&wl->mutex);
4151 cancel_delayed_work_sync(&dev->periodic_work);
4152 cancel_work_sync(&wl->tx_work);
4153 mutex_lock(&wl->mutex);
4154 dev = wl->current_dev;
4155 if (!dev || b43_status(dev) < B43_STAT_STARTED) {
4156 /* Whoops, aliens ate up the device while we were unlocked. */
4160 /* Disable interrupts on the device. */
4161 b43_set_status(dev, B43_STAT_INITIALIZED);
4162 if (b43_bus_host_is_sdio(dev->dev)) {
4163 /* wl->mutex is locked. That is enough. */
4164 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, 0);
4165 b43_read32(dev, B43_MMIO_GEN_IRQ_MASK); /* Flush */
4167 spin_lock_irq(&wl->hardirq_lock);
4168 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, 0);
4169 b43_read32(dev, B43_MMIO_GEN_IRQ_MASK); /* Flush */
4170 spin_unlock_irq(&wl->hardirq_lock);
4172 /* Synchronize and free the interrupt handlers. Unlock to avoid deadlocks. */
4174 mutex_unlock(&wl->mutex);
4175 if (b43_bus_host_is_sdio(dev->dev)) {
4176 b43_sdio_free_irq(dev);
4178 synchronize_irq(dev->dev->irq);
4179 free_irq(dev->dev->irq, dev);
4181 mutex_lock(&wl->mutex);
4182 dev = wl->current_dev;
4185 if (dev != orig_dev) {
4186 if (b43_status(dev) >= B43_STAT_STARTED)
4190 mask = b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
4191 B43_WARN_ON(mask != 0xFFFFFFFF && mask);
4193 /* Drain the TX queue */
4194 while (skb_queue_len(&wl->tx_queue))
4195 dev_kfree_skb(skb_dequeue(&wl->tx_queue));
4197 b43_mac_suspend(dev);
4199 b43dbg(wl, "Wireless interface stopped\n");
4204 /* Locking: wl->mutex */
4205 static int b43_wireless_core_start(struct b43_wldev *dev)
4209 B43_WARN_ON(b43_status(dev) != B43_STAT_INITIALIZED);
4211 drain_txstatus_queue(dev);
4212 if (b43_bus_host_is_sdio(dev->dev)) {
4213 err = b43_sdio_request_irq(dev, b43_sdio_interrupt_handler);
4215 b43err(dev->wl, "Cannot request SDIO IRQ\n");
4219 err = request_threaded_irq(dev->dev->irq, b43_interrupt_handler,
4220 b43_interrupt_thread_handler,
4221 IRQF_SHARED, KBUILD_MODNAME, dev);
4223 b43err(dev->wl, "Cannot request IRQ-%d\n",
4229 /* We are ready to run. */
4230 ieee80211_wake_queues(dev->wl->hw);
4231 b43_set_status(dev, B43_STAT_STARTED);
4233 /* Start data flow (TX/RX). */
4234 b43_mac_enable(dev);
4235 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, dev->irq_mask);
4237 /* Start maintenance work */
4238 b43_periodic_tasks_setup(dev);
4242 b43dbg(dev->wl, "Wireless interface started\n");
4247 /* Get PHY and RADIO versioning numbers */
4248 static int b43_phy_versioning(struct b43_wldev *dev)
4250 struct b43_phy *phy = &dev->phy;
4258 int unsupported = 0;
4260 /* Get PHY versioning */
4261 tmp = b43_read16(dev, B43_MMIO_PHY_VER);
4262 analog_type = (tmp & B43_PHYVER_ANALOG) >> B43_PHYVER_ANALOG_SHIFT;
4263 phy_type = (tmp & B43_PHYVER_TYPE) >> B43_PHYVER_TYPE_SHIFT;
4264 phy_rev = (tmp & B43_PHYVER_VERSION);
4271 if (phy_rev != 2 && phy_rev != 4 && phy_rev != 6
4279 #ifdef CONFIG_B43_PHY_N
4285 #ifdef CONFIG_B43_PHY_LP
4286 case B43_PHYTYPE_LP:
4291 #ifdef CONFIG_B43_PHY_HT
4292 case B43_PHYTYPE_HT:
4297 #ifdef CONFIG_B43_PHY_LCN
4298 case B43_PHYTYPE_LCN:
4307 b43err(dev->wl, "FOUND UNSUPPORTED PHY "
4308 "(Analog %u, Type %u, Revision %u)\n",
4309 analog_type, phy_type, phy_rev);
4312 b43dbg(dev->wl, "Found PHY: Analog %u, Type %u, Revision %u\n",
4313 analog_type, phy_type, phy_rev);
4315 /* Get RADIO versioning */
4316 if (dev->dev->core_rev >= 24) {
4319 for (tmp = 0; tmp < 3; tmp++) {
4320 b43_write16(dev, B43_MMIO_RADIO24_CONTROL, tmp);
4321 radio24[tmp] = b43_read16(dev, B43_MMIO_RADIO24_DATA);
4324 /* Broadcom uses "id" for our "ver" and has separated "ver" */
4325 /* radio_ver = (radio24[0] & 0xF0) >> 4; */
4327 radio_manuf = 0x17F;
4328 radio_ver = (radio24[2] << 8) | radio24[1];
4329 radio_rev = (radio24[0] & 0xF);
4331 if (dev->dev->chip_id == 0x4317) {
4332 if (dev->dev->chip_rev == 0)
4334 else if (dev->dev->chip_rev == 1)
4339 b43_write16(dev, B43_MMIO_RADIO_CONTROL,
4341 tmp = b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
4342 b43_write16(dev, B43_MMIO_RADIO_CONTROL,
4344 tmp |= (u32)b43_read16(dev, B43_MMIO_RADIO_DATA_HIGH)
4347 radio_manuf = (tmp & 0x00000FFF);
4348 radio_ver = (tmp & 0x0FFFF000) >> 12;
4349 radio_rev = (tmp & 0xF0000000) >> 28;
4352 if (radio_manuf != 0x17F /* Broadcom */)
4356 if (radio_ver != 0x2060)
4360 if (radio_manuf != 0x17F)
4364 if ((radio_ver & 0xFFF0) != 0x2050)
4368 if (radio_ver != 0x2050)
4372 if (radio_ver != 0x2055 && radio_ver != 0x2056)
4375 case B43_PHYTYPE_LP:
4376 if (radio_ver != 0x2062 && radio_ver != 0x2063)
4379 case B43_PHYTYPE_HT:
4380 if (radio_ver != 0x2059)
4383 case B43_PHYTYPE_LCN:
4384 if (radio_ver != 0x2064)
4391 b43err(dev->wl, "FOUND UNSUPPORTED RADIO "
4392 "(Manuf 0x%X, Version 0x%X, Revision %u)\n",
4393 radio_manuf, radio_ver, radio_rev);
4396 b43dbg(dev->wl, "Found Radio: Manuf 0x%X, Version 0x%X, Revision %u\n",
4397 radio_manuf, radio_ver, radio_rev);
4399 phy->radio_manuf = radio_manuf;
4400 phy->radio_ver = radio_ver;
4401 phy->radio_rev = radio_rev;
4403 phy->analog = analog_type;
4404 phy->type = phy_type;
4410 static void setup_struct_phy_for_init(struct b43_wldev *dev,
4411 struct b43_phy *phy)
4413 phy->hardware_power_control = !!modparam_hwpctl;
4414 phy->next_txpwr_check_time = jiffies;
4415 /* PHY TX errors counter. */
4416 atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT);
4419 phy->phy_locked = 0;
4420 phy->radio_locked = 0;
4424 static void setup_struct_wldev_for_init(struct b43_wldev *dev)
4428 /* Assume the radio is enabled. If it's not enabled, the state will
4429 * immediately get fixed on the first periodic work run. */
4430 dev->radio_hw_enable = 1;
4433 memset(&dev->stats, 0, sizeof(dev->stats));
4435 setup_struct_phy_for_init(dev, &dev->phy);
4437 /* IRQ related flags */
4438 dev->irq_reason = 0;
4439 memset(dev->dma_reason, 0, sizeof(dev->dma_reason));
4440 dev->irq_mask = B43_IRQ_MASKTEMPLATE;
4441 if (b43_modparam_verbose < B43_VERBOSITY_DEBUG)
4442 dev->irq_mask &= ~B43_IRQ_PHY_TXERR;
4444 dev->mac_suspended = 1;
4446 /* Noise calculation context */
4447 memset(&dev->noisecalc, 0, sizeof(dev->noisecalc));
4450 static void b43_bluetooth_coext_enable(struct b43_wldev *dev)
4452 struct ssb_sprom *sprom = dev->dev->bus_sprom;
4455 if (!modparam_btcoex)
4457 if (!(sprom->boardflags_lo & B43_BFL_BTCOEXIST))
4459 if (dev->phy.type != B43_PHYTYPE_B && !dev->phy.gmode)
4462 hf = b43_hf_read(dev);
4463 if (sprom->boardflags_lo & B43_BFL_BTCMOD)
4464 hf |= B43_HF_BTCOEXALT;
4466 hf |= B43_HF_BTCOEX;
4467 b43_hf_write(dev, hf);
4470 static void b43_bluetooth_coext_disable(struct b43_wldev *dev)
4472 if (!modparam_btcoex)
4477 static void b43_imcfglo_timeouts_workaround(struct b43_wldev *dev)
4479 struct ssb_bus *bus;
4482 if (dev->dev->bus_type != B43_BUS_SSB)
4485 bus = dev->dev->sdev->bus;
4487 if ((bus->chip_id == 0x4311 && bus->chip_rev == 2) ||
4488 (bus->chip_id == 0x4312)) {
4489 tmp = ssb_read32(dev->dev->sdev, SSB_IMCFGLO);
4490 tmp &= ~SSB_IMCFGLO_REQTO;
4491 tmp &= ~SSB_IMCFGLO_SERTO;
4493 ssb_write32(dev->dev->sdev, SSB_IMCFGLO, tmp);
4494 ssb_commit_settings(bus);
4498 static void b43_set_synth_pu_delay(struct b43_wldev *dev, bool idle)
4502 /* The time value is in microseconds. */
4503 if (dev->phy.type == B43_PHYTYPE_A)
4507 if (b43_is_mode(dev->wl, NL80211_IFTYPE_ADHOC) || idle)
4509 if ((dev->phy.radio_ver == 0x2050) && (dev->phy.radio_rev == 8))
4510 pu_delay = max(pu_delay, (u16)2400);
4512 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_SPUWKUP, pu_delay);
4515 /* Set the TSF CFP pre-TargetBeaconTransmissionTime. */
4516 static void b43_set_pretbtt(struct b43_wldev *dev)
4520 /* The time value is in microseconds. */
4521 if (b43_is_mode(dev->wl, NL80211_IFTYPE_ADHOC)) {
4524 if (dev->phy.type == B43_PHYTYPE_A)
4529 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRETBTT, pretbtt);
4530 b43_write16(dev, B43_MMIO_TSF_CFP_PRETBTT, pretbtt);
4533 /* Shutdown a wireless core */
4534 /* Locking: wl->mutex */
4535 static void b43_wireless_core_exit(struct b43_wldev *dev)
4539 B43_WARN_ON(dev && b43_status(dev) > B43_STAT_INITIALIZED);
4540 if (!dev || b43_status(dev) != B43_STAT_INITIALIZED)
4543 /* Unregister HW RNG driver */
4544 b43_rng_exit(dev->wl);
4546 b43_set_status(dev, B43_STAT_UNINIT);
4548 /* Stop the microcode PSM. */
4549 macctl = b43_read32(dev, B43_MMIO_MACCTL);
4550 macctl &= ~B43_MACCTL_PSM_RUN;
4551 macctl |= B43_MACCTL_PSM_JMP0;
4552 b43_write32(dev, B43_MMIO_MACCTL, macctl);
4557 dev->phy.ops->switch_analog(dev, 0);
4558 if (dev->wl->current_beacon) {
4559 dev_kfree_skb_any(dev->wl->current_beacon);
4560 dev->wl->current_beacon = NULL;
4563 b43_device_disable(dev, 0);
4564 b43_bus_may_powerdown(dev);
4567 /* Initialize a wireless core */
4568 static int b43_wireless_core_init(struct b43_wldev *dev)
4570 struct ssb_sprom *sprom = dev->dev->bus_sprom;
4571 struct b43_phy *phy = &dev->phy;
4575 B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT);
4577 err = b43_bus_powerup(dev, 0);
4580 if (!b43_device_is_enabled(dev))
4581 b43_wireless_core_reset(dev, phy->gmode);
4583 /* Reset all data structures. */
4584 setup_struct_wldev_for_init(dev);
4585 phy->ops->prepare_structs(dev);
4587 /* Enable IRQ routing to this device. */
4588 switch (dev->dev->bus_type) {
4589 #ifdef CONFIG_B43_BCMA
4591 bcma_core_pci_irq_ctl(&dev->dev->bdev->bus->drv_pci,
4592 dev->dev->bdev, true);
4595 #ifdef CONFIG_B43_SSB
4597 ssb_pcicore_dev_irqvecs_enable(&dev->dev->sdev->bus->pcicore,
4603 b43_imcfglo_timeouts_workaround(dev);
4604 b43_bluetooth_coext_disable(dev);
4605 if (phy->ops->prepare_hardware) {
4606 err = phy->ops->prepare_hardware(dev);
4610 err = b43_chip_init(dev);
4613 b43_shm_write16(dev, B43_SHM_SHARED,
4614 B43_SHM_SH_WLCOREREV, dev->dev->core_rev);
4615 hf = b43_hf_read(dev);
4616 if (phy->type == B43_PHYTYPE_G) {
4620 if (sprom->boardflags_lo & B43_BFL_PACTRL)
4621 hf |= B43_HF_OFDMPABOOST;
4623 if (phy->radio_ver == 0x2050) {
4624 if (phy->radio_rev == 6)
4625 hf |= B43_HF_4318TSSI;
4626 if (phy->radio_rev < 6)
4627 hf |= B43_HF_VCORECALC;
4629 if (sprom->boardflags_lo & B43_BFL_XTAL_NOSLOW)
4630 hf |= B43_HF_DSCRQ; /* Disable slowclock requests from ucode. */
4631 #ifdef CONFIG_SSB_DRIVER_PCICORE
4632 if (dev->dev->bus_type == B43_BUS_SSB &&
4633 dev->dev->sdev->bus->bustype == SSB_BUSTYPE_PCI &&
4634 dev->dev->sdev->bus->pcicore.dev->id.revision <= 10)
4635 hf |= B43_HF_PCISCW; /* PCI slow clock workaround. */
4637 hf &= ~B43_HF_SKCFPUP;
4638 b43_hf_write(dev, hf);
4640 b43_set_retry_limits(dev, B43_DEFAULT_SHORT_RETRY_LIMIT,
4641 B43_DEFAULT_LONG_RETRY_LIMIT);
4642 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_SFFBLIM, 3);
4643 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_LFFBLIM, 2);
4645 /* Disable sending probe responses from firmware.
4646 * Setting the MaxTime to one usec will always trigger
4647 * a timeout, so we never send any probe resp.
4648 * A timeout of zero is infinite. */
4649 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRMAXTIME, 1);
4651 b43_rate_memory_init(dev);
4652 b43_set_phytxctl_defaults(dev);
4654 /* Minimum Contention Window */
4655 if (phy->type == B43_PHYTYPE_B)
4656 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0x1F);
4658 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0xF);
4659 /* Maximum Contention Window */
4660 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MAXCONT, 0x3FF);
4662 if (b43_bus_host_is_pcmcia(dev->dev) ||
4663 b43_bus_host_is_sdio(dev->dev)) {
4664 dev->__using_pio_transfers = 1;
4665 err = b43_pio_init(dev);
4666 } else if (dev->use_pio) {
4667 b43warn(dev->wl, "Forced PIO by use_pio module parameter. "
4668 "This should not be needed and will result in lower "
4670 dev->__using_pio_transfers = 1;
4671 err = b43_pio_init(dev);
4673 dev->__using_pio_transfers = 0;
4674 err = b43_dma_init(dev);
4679 b43_set_synth_pu_delay(dev, 1);
4680 b43_bluetooth_coext_enable(dev);
4682 b43_bus_powerup(dev, !(sprom->boardflags_lo & B43_BFL_XTAL_NOSLOW));
4683 b43_upload_card_macaddress(dev);
4684 b43_security_init(dev);
4686 ieee80211_wake_queues(dev->wl->hw);
4688 b43_set_status(dev, B43_STAT_INITIALIZED);
4690 /* Register HW RNG driver */
4691 b43_rng_init(dev->wl);
4699 b43_bus_may_powerdown(dev);
4700 B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT);
4704 static int b43_op_add_interface(struct ieee80211_hw *hw,
4705 struct ieee80211_vif *vif)
4707 struct b43_wl *wl = hw_to_b43_wl(hw);
4708 struct b43_wldev *dev;
4709 int err = -EOPNOTSUPP;
4711 /* TODO: allow WDS/AP devices to coexist */
4713 if (vif->type != NL80211_IFTYPE_AP &&
4714 vif->type != NL80211_IFTYPE_MESH_POINT &&
4715 vif->type != NL80211_IFTYPE_STATION &&
4716 vif->type != NL80211_IFTYPE_WDS &&
4717 vif->type != NL80211_IFTYPE_ADHOC)
4720 mutex_lock(&wl->mutex);
4722 goto out_mutex_unlock;
4724 b43dbg(wl, "Adding Interface type %d\n", vif->type);
4726 dev = wl->current_dev;
4729 wl->if_type = vif->type;
4730 memcpy(wl->mac_addr, vif->addr, ETH_ALEN);
4732 b43_adjust_opmode(dev);
4733 b43_set_pretbtt(dev);
4734 b43_set_synth_pu_delay(dev, 0);
4735 b43_upload_card_macaddress(dev);
4739 mutex_unlock(&wl->mutex);
4742 b43_op_bss_info_changed(hw, vif, &vif->bss_conf, ~0);
4747 static void b43_op_remove_interface(struct ieee80211_hw *hw,
4748 struct ieee80211_vif *vif)
4750 struct b43_wl *wl = hw_to_b43_wl(hw);
4751 struct b43_wldev *dev = wl->current_dev;
4753 b43dbg(wl, "Removing Interface type %d\n", vif->type);
4755 mutex_lock(&wl->mutex);
4757 B43_WARN_ON(!wl->operating);
4758 B43_WARN_ON(wl->vif != vif);
4763 b43_adjust_opmode(dev);
4764 memset(wl->mac_addr, 0, ETH_ALEN);
4765 b43_upload_card_macaddress(dev);
4767 mutex_unlock(&wl->mutex);
4770 static int b43_op_start(struct ieee80211_hw *hw)
4772 struct b43_wl *wl = hw_to_b43_wl(hw);
4773 struct b43_wldev *dev = wl->current_dev;
4777 /* Kill all old instance specific information to make sure
4778 * the card won't use it in the short timeframe between start
4779 * and mac80211 reconfiguring it. */
4780 memset(wl->bssid, 0, ETH_ALEN);
4781 memset(wl->mac_addr, 0, ETH_ALEN);
4782 wl->filter_flags = 0;
4783 wl->radiotap_enabled = 0;
4785 wl->beacon0_uploaded = 0;
4786 wl->beacon1_uploaded = 0;
4787 wl->beacon_templates_virgin = 1;
4788 wl->radio_enabled = 1;
4790 mutex_lock(&wl->mutex);
4792 if (b43_status(dev) < B43_STAT_INITIALIZED) {
4793 err = b43_wireless_core_init(dev);
4795 goto out_mutex_unlock;
4799 if (b43_status(dev) < B43_STAT_STARTED) {
4800 err = b43_wireless_core_start(dev);
4803 b43_wireless_core_exit(dev);
4804 goto out_mutex_unlock;
4808 /* XXX: only do if device doesn't support rfkill irq */
4809 wiphy_rfkill_start_polling(hw->wiphy);
4812 mutex_unlock(&wl->mutex);
4814 /* reload configuration */
4815 b43_op_config(hw, ~0);
4820 static void b43_op_stop(struct ieee80211_hw *hw)
4822 struct b43_wl *wl = hw_to_b43_wl(hw);
4823 struct b43_wldev *dev = wl->current_dev;
4825 cancel_work_sync(&(wl->beacon_update_trigger));
4827 mutex_lock(&wl->mutex);
4828 if (b43_status(dev) >= B43_STAT_STARTED) {
4829 dev = b43_wireless_core_stop(dev);
4833 b43_wireless_core_exit(dev);
4834 wl->radio_enabled = 0;
4837 mutex_unlock(&wl->mutex);
4839 cancel_work_sync(&(wl->txpower_adjust_work));
4842 static int b43_op_beacon_set_tim(struct ieee80211_hw *hw,
4843 struct ieee80211_sta *sta, bool set)
4845 struct b43_wl *wl = hw_to_b43_wl(hw);
4847 /* FIXME: add locking */
4848 b43_update_templates(wl);
4853 static void b43_op_sta_notify(struct ieee80211_hw *hw,
4854 struct ieee80211_vif *vif,
4855 enum sta_notify_cmd notify_cmd,
4856 struct ieee80211_sta *sta)
4858 struct b43_wl *wl = hw_to_b43_wl(hw);
4860 B43_WARN_ON(!vif || wl->vif != vif);
4863 static void b43_op_sw_scan_start_notifier(struct ieee80211_hw *hw)
4865 struct b43_wl *wl = hw_to_b43_wl(hw);
4866 struct b43_wldev *dev;
4868 mutex_lock(&wl->mutex);
4869 dev = wl->current_dev;
4870 if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED)) {
4871 /* Disable CFP update during scan on other channels. */
4872 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_SKCFPUP);
4874 mutex_unlock(&wl->mutex);
4877 static void b43_op_sw_scan_complete_notifier(struct ieee80211_hw *hw)
4879 struct b43_wl *wl = hw_to_b43_wl(hw);
4880 struct b43_wldev *dev;
4882 mutex_lock(&wl->mutex);
4883 dev = wl->current_dev;
4884 if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED)) {
4885 /* Re-enable CFP update. */
4886 b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_SKCFPUP);
4888 mutex_unlock(&wl->mutex);
4891 static int b43_op_get_survey(struct ieee80211_hw *hw, int idx,
4892 struct survey_info *survey)
4894 struct b43_wl *wl = hw_to_b43_wl(hw);
4895 struct b43_wldev *dev = wl->current_dev;
4896 struct ieee80211_conf *conf = &hw->conf;
4901 survey->channel = conf->channel;
4902 survey->filled = SURVEY_INFO_NOISE_DBM;
4903 survey->noise = dev->stats.link_noise;
4908 static const struct ieee80211_ops b43_hw_ops = {
4910 .conf_tx = b43_op_conf_tx,
4911 .add_interface = b43_op_add_interface,
4912 .remove_interface = b43_op_remove_interface,
4913 .config = b43_op_config,
4914 .bss_info_changed = b43_op_bss_info_changed,
4915 .configure_filter = b43_op_configure_filter,
4916 .set_key = b43_op_set_key,
4917 .update_tkip_key = b43_op_update_tkip_key,
4918 .get_stats = b43_op_get_stats,
4919 .get_tsf = b43_op_get_tsf,
4920 .set_tsf = b43_op_set_tsf,
4921 .start = b43_op_start,
4922 .stop = b43_op_stop,
4923 .set_tim = b43_op_beacon_set_tim,
4924 .sta_notify = b43_op_sta_notify,
4925 .sw_scan_start = b43_op_sw_scan_start_notifier,
4926 .sw_scan_complete = b43_op_sw_scan_complete_notifier,
4927 .get_survey = b43_op_get_survey,
4928 .rfkill_poll = b43_rfkill_poll,
4931 /* Hard-reset the chip. Do not call this directly.
4932 * Use b43_controller_restart()
4934 static void b43_chip_reset(struct work_struct *work)
4936 struct b43_wldev *dev =
4937 container_of(work, struct b43_wldev, restart_work);
4938 struct b43_wl *wl = dev->wl;
4942 mutex_lock(&wl->mutex);
4944 prev_status = b43_status(dev);
4945 /* Bring the device down... */
4946 if (prev_status >= B43_STAT_STARTED) {
4947 dev = b43_wireless_core_stop(dev);
4953 if (prev_status >= B43_STAT_INITIALIZED)
4954 b43_wireless_core_exit(dev);
4956 /* ...and up again. */
4957 if (prev_status >= B43_STAT_INITIALIZED) {
4958 err = b43_wireless_core_init(dev);
4962 if (prev_status >= B43_STAT_STARTED) {
4963 err = b43_wireless_core_start(dev);
4965 b43_wireless_core_exit(dev);
4971 wl->current_dev = NULL; /* Failed to init the dev. */
4972 mutex_unlock(&wl->mutex);
4975 b43err(wl, "Controller restart FAILED\n");
4979 /* reload configuration */
4980 b43_op_config(wl->hw, ~0);
4982 b43_op_bss_info_changed(wl->hw, wl->vif, &wl->vif->bss_conf, ~0);
4984 b43info(wl, "Controller restarted\n");
4987 static int b43_setup_bands(struct b43_wldev *dev,
4988 bool have_2ghz_phy, bool have_5ghz_phy)
4990 struct ieee80211_hw *hw = dev->wl->hw;
4993 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &b43_band_2GHz;
4994 if (dev->phy.type == B43_PHYTYPE_N) {
4996 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = &b43_band_5GHz_nphy;
4999 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = &b43_band_5GHz_aphy;
5002 dev->phy.supports_2ghz = have_2ghz_phy;
5003 dev->phy.supports_5ghz = have_5ghz_phy;
5008 static void b43_wireless_core_detach(struct b43_wldev *dev)
5010 /* We release firmware that late to not be required to re-request
5011 * is all the time when we reinit the core. */
5012 b43_release_firmware(dev);
5016 static int b43_wireless_core_attach(struct b43_wldev *dev)
5018 struct b43_wl *wl = dev->wl;
5019 struct pci_dev *pdev = NULL;
5022 bool have_2ghz_phy = 0, have_5ghz_phy = 0;
5024 /* Do NOT do any device initialization here.
5025 * Do it in wireless_core_init() instead.
5026 * This function is for gathering basic information about the HW, only.
5027 * Also some structs may be set up here. But most likely you want to have
5028 * that in core_init(), too.
5031 #ifdef CONFIG_B43_SSB
5032 if (dev->dev->bus_type == B43_BUS_SSB &&
5033 dev->dev->sdev->bus->bustype == SSB_BUSTYPE_PCI)
5034 pdev = dev->dev->sdev->bus->host_pci;
5037 err = b43_bus_powerup(dev, 0);
5039 b43err(wl, "Bus powerup failed\n");
5043 /* Get the PHY type. */
5044 switch (dev->dev->bus_type) {
5045 #ifdef CONFIG_B43_BCMA
5047 tmp = bcma_aread32(dev->dev->bdev, BCMA_IOST);
5048 have_2ghz_phy = !!(tmp & B43_BCMA_IOST_2G_PHY);
5049 have_5ghz_phy = !!(tmp & B43_BCMA_IOST_5G_PHY);
5052 #ifdef CONFIG_B43_SSB
5054 if (dev->dev->core_rev >= 5) {
5055 tmp = ssb_read32(dev->dev->sdev, SSB_TMSHIGH);
5056 have_2ghz_phy = !!(tmp & B43_TMSHIGH_HAVE_2GHZ_PHY);
5057 have_5ghz_phy = !!(tmp & B43_TMSHIGH_HAVE_5GHZ_PHY);
5064 dev->phy.gmode = have_2ghz_phy;
5065 dev->phy.radio_on = 1;
5066 b43_wireless_core_reset(dev, dev->phy.gmode);
5068 err = b43_phy_versioning(dev);
5071 /* Check if this device supports multiband. */
5073 (pdev->device != 0x4312 &&
5074 pdev->device != 0x4319 && pdev->device != 0x4324)) {
5075 /* No multiband support. */
5078 switch (dev->phy.type) {
5082 case B43_PHYTYPE_LP: //FIXME not always!
5083 #if 0 //FIXME enabling 5GHz causes a NULL pointer dereference
5088 case B43_PHYTYPE_HT:
5089 case B43_PHYTYPE_LCN:
5096 if (dev->phy.type == B43_PHYTYPE_A) {
5098 b43err(wl, "IEEE 802.11a devices are unsupported\n");
5102 if (1 /* disable A-PHY */) {
5103 /* FIXME: For now we disable the A-PHY on multi-PHY devices. */
5104 if (dev->phy.type != B43_PHYTYPE_N &&
5105 dev->phy.type != B43_PHYTYPE_LP) {
5111 err = b43_phy_allocate(dev);
5115 dev->phy.gmode = have_2ghz_phy;
5116 b43_wireless_core_reset(dev, dev->phy.gmode);
5118 err = b43_validate_chipaccess(dev);
5121 err = b43_setup_bands(dev, have_2ghz_phy, have_5ghz_phy);
5125 /* Now set some default "current_dev" */
5126 if (!wl->current_dev)
5127 wl->current_dev = dev;
5128 INIT_WORK(&dev->restart_work, b43_chip_reset);
5130 dev->phy.ops->switch_analog(dev, 0);
5131 b43_device_disable(dev, 0);
5132 b43_bus_may_powerdown(dev);
5140 b43_bus_may_powerdown(dev);
5144 static void b43_one_core_detach(struct b43_bus_dev *dev)
5146 struct b43_wldev *wldev;
5149 /* Do not cancel ieee80211-workqueue based work here.
5150 * See comment in b43_remove(). */
5152 wldev = b43_bus_get_wldev(dev);
5154 b43_debugfs_remove_device(wldev);
5155 b43_wireless_core_detach(wldev);
5156 list_del(&wldev->list);
5158 b43_bus_set_wldev(dev, NULL);
5162 static int b43_one_core_attach(struct b43_bus_dev *dev, struct b43_wl *wl)
5164 struct b43_wldev *wldev;
5167 wldev = kzalloc(sizeof(*wldev), GFP_KERNEL);
5171 wldev->use_pio = b43_modparam_pio;
5174 b43_set_status(wldev, B43_STAT_UNINIT);
5175 wldev->bad_frames_preempt = modparam_bad_frames_preempt;
5176 INIT_LIST_HEAD(&wldev->list);
5178 err = b43_wireless_core_attach(wldev);
5180 goto err_kfree_wldev;
5182 list_add(&wldev->list, &wl->devlist);
5184 b43_bus_set_wldev(dev, wldev);
5185 b43_debugfs_add_device(wldev);
5195 #define IS_PDEV(pdev, _vendor, _device, _subvendor, _subdevice) ( \
5196 (pdev->vendor == PCI_VENDOR_ID_##_vendor) && \
5197 (pdev->device == _device) && \
5198 (pdev->subsystem_vendor == PCI_VENDOR_ID_##_subvendor) && \
5199 (pdev->subsystem_device == _subdevice) )
5201 static void b43_sprom_fixup(struct ssb_bus *bus)
5203 struct pci_dev *pdev;
5205 /* boardflags workarounds */
5206 if (bus->boardinfo.vendor == SSB_BOARDVENDOR_DELL &&
5207 bus->chip_id == 0x4301 && bus->boardinfo.rev == 0x74)
5208 bus->sprom.boardflags_lo |= B43_BFL_BTCOEXIST;
5209 if (bus->boardinfo.vendor == PCI_VENDOR_ID_APPLE &&
5210 bus->boardinfo.type == 0x4E && bus->boardinfo.rev > 0x40)
5211 bus->sprom.boardflags_lo |= B43_BFL_PACTRL;
5212 if (bus->bustype == SSB_BUSTYPE_PCI) {
5213 pdev = bus->host_pci;
5214 if (IS_PDEV(pdev, BROADCOM, 0x4318, ASUSTEK, 0x100F) ||
5215 IS_PDEV(pdev, BROADCOM, 0x4320, DELL, 0x0003) ||
5216 IS_PDEV(pdev, BROADCOM, 0x4320, HP, 0x12f8) ||
5217 IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0015) ||
5218 IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0014) ||
5219 IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0013) ||
5220 IS_PDEV(pdev, BROADCOM, 0x4320, MOTOROLA, 0x7010))
5221 bus->sprom.boardflags_lo &= ~B43_BFL_BTCOEXIST;
5225 static void b43_wireless_exit(struct b43_bus_dev *dev, struct b43_wl *wl)
5227 struct ieee80211_hw *hw = wl->hw;
5229 ssb_set_devtypedata(dev->sdev, NULL);
5230 ieee80211_free_hw(hw);
5233 static struct b43_wl *b43_wireless_init(struct b43_bus_dev *dev)
5235 struct ssb_sprom *sprom = dev->bus_sprom;
5236 struct ieee80211_hw *hw;
5240 hw = ieee80211_alloc_hw(sizeof(*wl), &b43_hw_ops);
5242 b43err(NULL, "Could not allocate ieee80211 device\n");
5243 return ERR_PTR(-ENOMEM);
5245 wl = hw_to_b43_wl(hw);
5248 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
5249 IEEE80211_HW_SIGNAL_DBM;
5251 hw->wiphy->interface_modes =
5252 BIT(NL80211_IFTYPE_AP) |
5253 BIT(NL80211_IFTYPE_MESH_POINT) |
5254 BIT(NL80211_IFTYPE_STATION) |
5255 BIT(NL80211_IFTYPE_WDS) |
5256 BIT(NL80211_IFTYPE_ADHOC);
5258 hw->queues = modparam_qos ? 4 : 1;
5259 wl->mac80211_initially_registered_queues = hw->queues;
5261 SET_IEEE80211_DEV(hw, dev->dev);
5262 if (is_valid_ether_addr(sprom->et1mac))
5263 SET_IEEE80211_PERM_ADDR(hw, sprom->et1mac);
5265 SET_IEEE80211_PERM_ADDR(hw, sprom->il0mac);
5267 /* Initialize struct b43_wl */
5269 mutex_init(&wl->mutex);
5270 spin_lock_init(&wl->hardirq_lock);
5271 INIT_LIST_HEAD(&wl->devlist);
5272 INIT_WORK(&wl->beacon_update_trigger, b43_beacon_update_trigger_work);
5273 INIT_WORK(&wl->txpower_adjust_work, b43_phy_txpower_adjust_work);
5274 INIT_WORK(&wl->tx_work, b43_tx_work);
5275 skb_queue_head_init(&wl->tx_queue);
5277 snprintf(chip_name, ARRAY_SIZE(chip_name),
5278 (dev->chip_id > 0x9999) ? "%d" : "%04X", dev->chip_id);
5279 b43info(wl, "Broadcom %s WLAN found (core revision %u)\n", chip_name,
5284 #ifdef CONFIG_B43_BCMA
5285 static int b43_bcma_probe(struct bcma_device *core)
5287 struct b43_bus_dev *dev;
5291 dev = b43_bus_dev_bcma_init(core);
5295 wl = b43_wireless_init(dev);
5301 err = b43_one_core_attach(dev, wl);
5303 goto bcma_err_wireless_exit;
5305 err = ieee80211_register_hw(wl->hw);
5307 goto bcma_err_one_core_detach;
5308 b43_leds_register(wl->current_dev);
5313 bcma_err_one_core_detach:
5314 b43_one_core_detach(dev);
5315 bcma_err_wireless_exit:
5316 ieee80211_free_hw(wl->hw);
5320 static void b43_bcma_remove(struct bcma_device *core)
5322 struct b43_wldev *wldev = bcma_get_drvdata(core);
5323 struct b43_wl *wl = wldev->wl;
5325 /* We must cancel any work here before unregistering from ieee80211,
5326 * as the ieee80211 unreg will destroy the workqueue. */
5327 cancel_work_sync(&wldev->restart_work);
5329 /* Restore the queues count before unregistering, because firmware detect
5330 * might have modified it. Restoring is important, so the networking
5331 * stack can properly free resources. */
5332 wl->hw->queues = wl->mac80211_initially_registered_queues;
5333 b43_leds_stop(wldev);
5334 ieee80211_unregister_hw(wl->hw);
5336 b43_one_core_detach(wldev->dev);
5338 b43_leds_unregister(wl);
5340 ieee80211_free_hw(wl->hw);
5343 static struct bcma_driver b43_bcma_driver = {
5344 .name = KBUILD_MODNAME,
5345 .id_table = b43_bcma_tbl,
5346 .probe = b43_bcma_probe,
5347 .remove = b43_bcma_remove,
5351 #ifdef CONFIG_B43_SSB
5353 int b43_ssb_probe(struct ssb_device *sdev, const struct ssb_device_id *id)
5355 struct b43_bus_dev *dev;
5360 dev = b43_bus_dev_ssb_init(sdev);
5364 wl = ssb_get_devtypedata(sdev);
5366 /* Probing the first core. Must setup common struct b43_wl */
5368 b43_sprom_fixup(sdev->bus);
5369 wl = b43_wireless_init(dev);
5374 ssb_set_devtypedata(sdev, wl);
5375 B43_WARN_ON(ssb_get_devtypedata(sdev) != wl);
5377 err = b43_one_core_attach(dev, wl);
5379 goto err_wireless_exit;
5382 err = ieee80211_register_hw(wl->hw);
5384 goto err_one_core_detach;
5385 b43_leds_register(wl->current_dev);
5391 err_one_core_detach:
5392 b43_one_core_detach(dev);
5395 b43_wireless_exit(dev, wl);
5399 static void b43_ssb_remove(struct ssb_device *sdev)
5401 struct b43_wl *wl = ssb_get_devtypedata(sdev);
5402 struct b43_wldev *wldev = ssb_get_drvdata(sdev);
5403 struct b43_bus_dev *dev = wldev->dev;
5405 /* We must cancel any work here before unregistering from ieee80211,
5406 * as the ieee80211 unreg will destroy the workqueue. */
5407 cancel_work_sync(&wldev->restart_work);
5410 if (wl->current_dev == wldev) {
5411 /* Restore the queues count before unregistering, because firmware detect
5412 * might have modified it. Restoring is important, so the networking
5413 * stack can properly free resources. */
5414 wl->hw->queues = wl->mac80211_initially_registered_queues;
5415 b43_leds_stop(wldev);
5416 ieee80211_unregister_hw(wl->hw);
5419 b43_one_core_detach(dev);
5421 if (list_empty(&wl->devlist)) {
5422 b43_leds_unregister(wl);
5423 /* Last core on the chip unregistered.
5424 * We can destroy common struct b43_wl.
5426 b43_wireless_exit(dev, wl);
5430 static struct ssb_driver b43_ssb_driver = {
5431 .name = KBUILD_MODNAME,
5432 .id_table = b43_ssb_tbl,
5433 .probe = b43_ssb_probe,
5434 .remove = b43_ssb_remove,
5436 #endif /* CONFIG_B43_SSB */
5438 /* Perform a hardware reset. This can be called from any context. */
5439 void b43_controller_restart(struct b43_wldev *dev, const char *reason)
5441 /* Must avoid requeueing, if we are in shutdown. */
5442 if (b43_status(dev) < B43_STAT_INITIALIZED)
5444 b43info(dev->wl, "Controller RESET (%s) ...\n", reason);
5445 ieee80211_queue_work(dev->wl->hw, &dev->restart_work);
5448 static void b43_print_driverinfo(void)
5450 const char *feat_pci = "", *feat_pcmcia = "", *feat_nphy = "",
5451 *feat_leds = "", *feat_sdio = "";
5453 #ifdef CONFIG_B43_PCI_AUTOSELECT
5456 #ifdef CONFIG_B43_PCMCIA
5459 #ifdef CONFIG_B43_PHY_N
5462 #ifdef CONFIG_B43_LEDS
5465 #ifdef CONFIG_B43_SDIO
5468 printk(KERN_INFO "Broadcom 43xx driver loaded "
5469 "[ Features: %s%s%s%s%s ]\n",
5470 feat_pci, feat_pcmcia, feat_nphy,
5471 feat_leds, feat_sdio);
5474 static int __init b43_init(void)
5479 err = b43_pcmcia_init();
5482 err = b43_sdio_init();
5484 goto err_pcmcia_exit;
5485 #ifdef CONFIG_B43_BCMA
5486 err = bcma_driver_register(&b43_bcma_driver);
5490 #ifdef CONFIG_B43_SSB
5491 err = ssb_driver_register(&b43_ssb_driver);
5493 goto err_bcma_driver_exit;
5495 b43_print_driverinfo();
5499 #ifdef CONFIG_B43_SSB
5500 err_bcma_driver_exit:
5502 #ifdef CONFIG_B43_BCMA
5503 bcma_driver_unregister(&b43_bcma_driver);
5514 static void __exit b43_exit(void)
5516 #ifdef CONFIG_B43_SSB
5517 ssb_driver_unregister(&b43_ssb_driver);
5519 #ifdef CONFIG_B43_BCMA
5520 bcma_driver_unregister(&b43_bcma_driver);
5527 module_init(b43_init)
5528 module_exit(b43_exit)