2 * Copyright (c) 2010-2011 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 #include <asm/unaligned.h>
19 #include "ar9003_phy.h"
20 #include "ar9003_eeprom.h"
22 #define COMP_HDR_LEN 4
23 #define COMP_CKSUM_LEN 2
25 #define LE16(x) __constant_cpu_to_le16(x)
26 #define LE32(x) __constant_cpu_to_le32(x)
28 /* Local defines to distinguish between extension and control CTL's */
29 #define EXT_ADDITIVE (0x8000)
30 #define CTL_11A_EXT (CTL_11A | EXT_ADDITIVE)
31 #define CTL_11G_EXT (CTL_11G | EXT_ADDITIVE)
32 #define CTL_11B_EXT (CTL_11B | EXT_ADDITIVE)
33 #define REDUCE_SCALED_POWER_BY_TWO_CHAIN 6 /* 10*log10(2)*2 */
34 #define REDUCE_SCALED_POWER_BY_THREE_CHAIN 9 /* 10*log10(3)*2 */
35 #define PWRINCR_3_TO_1_CHAIN 9 /* 10*log(3)*2 */
36 #define PWRINCR_3_TO_2_CHAIN 3 /* floor(10*log(3/2)*2) */
37 #define PWRINCR_2_TO_1_CHAIN 6 /* 10*log(2)*2 */
39 #define SUB_NUM_CTL_MODES_AT_5G_40 2 /* excluding HT40, EXT-OFDM */
40 #define SUB_NUM_CTL_MODES_AT_2G_40 3 /* excluding HT40, EXT-OFDM, EXT-CCK */
42 #define CTL(_tpower, _flag) ((_tpower) | ((_flag) << 6))
44 #define EEPROM_DATA_LEN_9485 1088
46 static int ar9003_hw_power_interpolate(int32_t x,
47 int32_t *px, int32_t *py, u_int16_t np);
50 static const struct ar9300_eeprom ar9300_default = {
53 .macAddr = {0, 2, 3, 4, 5, 6},
54 .custData = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
55 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
57 .regDmn = { LE16(0), LE16(0x1f) },
58 .txrxMask = 0x77, /* 4 bits tx and 4 bits rx */
60 .opFlags = AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A,
64 .blueToothOptions = 0,
66 .deviceType = 5, /* takes lower byte in eeprom location */
67 .pwrTableOffset = AR9300_PWR_TABLE_OFFSET,
68 .params_for_tuning_caps = {0, 0},
69 .featureEnable = 0x0c,
71 * bit0 - enable tx temp comp - disabled
72 * bit1 - enable tx volt comp - disabled
73 * bit2 - enable fastClock - enabled
74 * bit3 - enable doubling - enabled
75 * bit4 - enable internal regulator - disabled
76 * bit5 - enable pa predistortion - disabled
78 .miscConfiguration = 0, /* bit0 - turn down drivestrength */
79 .eepromWriteEnableGpio = 3,
82 .rxBandSelectGpio = 0xff,
87 /* ar9300_modal_eep_header 2g */
88 /* 4 idle,t1,t2,b(4 bits per setting) */
89 .antCtrlCommon = LE32(0x110),
90 /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
91 .antCtrlCommon2 = LE32(0x22222),
94 * antCtrlChain[AR9300_MAX_CHAINS]; 6 idle, t, r,
95 * rx1, rx12, b (2 bits each)
97 .antCtrlChain = { LE16(0x150), LE16(0x150), LE16(0x150) },
100 * xatten1DB[AR9300_MAX_CHAINS]; 3 xatten1_db
101 * for ar9280 (0xa20c/b20c 5:0)
103 .xatten1DB = {0, 0, 0},
106 * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
107 * for ar9280 (0xa20c/b20c 16:12
109 .xatten1Margin = {0, 0, 0},
114 * spurChans[OSPREY_EEPROM_MODAL_SPURS]; spur
115 * channels in usual fbin coding format
117 .spurChans = {0, 0, 0, 0, 0},
120 * noiseFloorThreshCh[AR9300_MAX_CHAINS]; 3 Check
121 * if the register is per chain
123 .noiseFloorThreshCh = {-1, 0, 0},
124 .ob = {1, 1, 1},/* 3 chain */
125 .db_stage2 = {1, 1, 1}, /* 3 chain */
126 .db_stage3 = {0, 0, 0},
127 .db_stage4 = {0, 0, 0},
129 .txFrameToDataStart = 0x0e,
130 .txFrameToPaOn = 0x0e,
131 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
133 .switchSettling = 0x2c,
134 .adcDesiredSize = -30,
137 .txFrameToXpaOn = 0xe,
139 .papdRateMaskHt20 = LE32(0x0cf0e0e0),
140 .papdRateMaskHt40 = LE32(0x6cf0e0e0),
142 0, 0, 0, 0, 0, 0, 0, 0,
146 .ant_div_control = 0,
147 .future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
154 /* ar9300_cal_data_per_freq_op_loop 2g */
156 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
157 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
158 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
160 .calTarget_freqbin_Cck = {
164 .calTarget_freqbin_2G = {
169 .calTarget_freqbin_2GHT20 = {
174 .calTarget_freqbin_2GHT40 = {
179 .calTargetPowerCck = {
180 /* 1L-5L,5S,11L,11S */
181 { {36, 36, 36, 36} },
182 { {36, 36, 36, 36} },
184 .calTargetPower2G = {
186 { {32, 32, 28, 24} },
187 { {32, 32, 28, 24} },
188 { {32, 32, 28, 24} },
190 .calTargetPower2GHT20 = {
191 { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
192 { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
193 { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
195 .calTargetPower2GHT40 = {
196 { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
197 { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
198 { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
201 0x11, 0x12, 0x15, 0x17, 0x41, 0x42,
202 0x45, 0x47, 0x31, 0x32, 0x35, 0x37,
232 /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
233 /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
234 /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
235 /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(2484, 1),
239 /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
240 /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
241 /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
246 /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
247 /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
253 /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
254 /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
255 /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
256 /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
260 /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
261 /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
262 /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
266 /* Data[9].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
267 /* Data[9].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
268 /* Data[9].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
273 /* Data[10].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
274 /* Data[10].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
275 /* Data[10].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
280 /* Data[11].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
281 /* Data[11].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
282 /* Data[11].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
283 /* Data[11].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
287 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
288 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
289 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 1) } },
291 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0) } },
292 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
293 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
295 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0) } },
296 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
297 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
299 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
300 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
301 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
304 /* 4 idle,t1,t2,b (4 bits per setting) */
305 .antCtrlCommon = LE32(0x110),
306 /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */
307 .antCtrlCommon2 = LE32(0x22222),
308 /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
310 LE16(0x000), LE16(0x000), LE16(0x000),
312 /* xatten1DB 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */
313 .xatten1DB = {0, 0, 0},
316 * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
317 * for merlin (0xa20c/b20c 16:12
319 .xatten1Margin = {0, 0, 0},
322 /* spurChans spur channels in usual fbin coding format */
323 .spurChans = {0, 0, 0, 0, 0},
324 /* noiseFloorThreshCh Check if the register is per chain */
325 .noiseFloorThreshCh = {-1, 0, 0},
326 .ob = {3, 3, 3}, /* 3 chain */
327 .db_stage2 = {3, 3, 3}, /* 3 chain */
328 .db_stage3 = {3, 3, 3}, /* doesn't exist for 2G */
329 .db_stage4 = {3, 3, 3}, /* don't exist for 2G */
331 .txFrameToDataStart = 0x0e,
332 .txFrameToPaOn = 0x0e,
333 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
335 .switchSettling = 0x2d,
336 .adcDesiredSize = -30,
339 .txFrameToXpaOn = 0xe,
341 .papdRateMaskHt20 = LE32(0x0c80c080),
342 .papdRateMaskHt40 = LE32(0x0080c080),
344 0, 0, 0, 0, 0, 0, 0, 0,
350 .xatten1DBLow = {0, 0, 0},
351 .xatten1MarginLow = {0, 0, 0},
352 .xatten1DBHigh = {0, 0, 0},
353 .xatten1MarginHigh = {0, 0, 0}
398 .calTarget_freqbin_5G = {
408 .calTarget_freqbin_5GHT20 = {
418 .calTarget_freqbin_5GHT40 = {
428 .calTargetPower5G = {
430 { {20, 20, 20, 10} },
431 { {20, 20, 20, 10} },
432 { {20, 20, 20, 10} },
433 { {20, 20, 20, 10} },
434 { {20, 20, 20, 10} },
435 { {20, 20, 20, 10} },
436 { {20, 20, 20, 10} },
437 { {20, 20, 20, 10} },
439 .calTargetPower5GHT20 = {
441 * 0_8_16,1-3_9-11_17-19,
442 * 4,5,6,7,12,13,14,15,20,21,22,23
444 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
445 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
446 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
447 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
448 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
449 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
450 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
451 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
453 .calTargetPower5GHT40 = {
455 * 0_8_16,1-3_9-11_17-19,
456 * 4,5,6,7,12,13,14,15,20,21,22,23
458 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
459 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
460 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
461 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
462 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
463 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
464 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
465 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
468 0x10, 0x16, 0x18, 0x40, 0x46,
469 0x48, 0x30, 0x36, 0x38
473 /* Data[0].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
474 /* Data[0].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
475 /* Data[0].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
476 /* Data[0].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
477 /* Data[0].ctlEdges[4].bChannel */ FREQ2FBIN(5600, 0),
478 /* Data[0].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
479 /* Data[0].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
480 /* Data[0].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
483 /* Data[1].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
484 /* Data[1].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
485 /* Data[1].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
486 /* Data[1].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
487 /* Data[1].ctlEdges[4].bChannel */ FREQ2FBIN(5520, 0),
488 /* Data[1].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
489 /* Data[1].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
490 /* Data[1].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
494 /* Data[2].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
495 /* Data[2].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
496 /* Data[2].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
497 /* Data[2].ctlEdges[3].bChannel */ FREQ2FBIN(5310, 0),
498 /* Data[2].ctlEdges[4].bChannel */ FREQ2FBIN(5510, 0),
499 /* Data[2].ctlEdges[5].bChannel */ FREQ2FBIN(5550, 0),
500 /* Data[2].ctlEdges[6].bChannel */ FREQ2FBIN(5670, 0),
501 /* Data[2].ctlEdges[7].bChannel */ FREQ2FBIN(5755, 0)
505 /* Data[3].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
506 /* Data[3].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
507 /* Data[3].ctlEdges[2].bChannel */ FREQ2FBIN(5260, 0),
508 /* Data[3].ctlEdges[3].bChannel */ FREQ2FBIN(5320, 0),
509 /* Data[3].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
510 /* Data[3].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
511 /* Data[3].ctlEdges[6].bChannel */ 0xFF,
512 /* Data[3].ctlEdges[7].bChannel */ 0xFF,
516 /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
517 /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
518 /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(5500, 0),
519 /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(5700, 0),
520 /* Data[4].ctlEdges[4].bChannel */ 0xFF,
521 /* Data[4].ctlEdges[5].bChannel */ 0xFF,
522 /* Data[4].ctlEdges[6].bChannel */ 0xFF,
523 /* Data[4].ctlEdges[7].bChannel */ 0xFF,
527 /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
528 /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(5270, 0),
529 /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(5310, 0),
530 /* Data[5].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
531 /* Data[5].ctlEdges[4].bChannel */ FREQ2FBIN(5590, 0),
532 /* Data[5].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
533 /* Data[5].ctlEdges[6].bChannel */ 0xFF,
534 /* Data[5].ctlEdges[7].bChannel */ 0xFF
538 /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
539 /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
540 /* Data[6].ctlEdges[2].bChannel */ FREQ2FBIN(5220, 0),
541 /* Data[6].ctlEdges[3].bChannel */ FREQ2FBIN(5260, 0),
542 /* Data[6].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
543 /* Data[6].ctlEdges[5].bChannel */ FREQ2FBIN(5600, 0),
544 /* Data[6].ctlEdges[6].bChannel */ FREQ2FBIN(5700, 0),
545 /* Data[6].ctlEdges[7].bChannel */ FREQ2FBIN(5745, 0)
549 /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
550 /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
551 /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(5320, 0),
552 /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
553 /* Data[7].ctlEdges[4].bChannel */ FREQ2FBIN(5560, 0),
554 /* Data[7].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
555 /* Data[7].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
556 /* Data[7].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
560 /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
561 /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
562 /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
563 /* Data[8].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
564 /* Data[8].ctlEdges[4].bChannel */ FREQ2FBIN(5550, 0),
565 /* Data[8].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
566 /* Data[8].ctlEdges[6].bChannel */ FREQ2FBIN(5755, 0),
567 /* Data[8].ctlEdges[7].bChannel */ FREQ2FBIN(5795, 0)
573 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
574 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
579 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
580 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
585 CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 1),
586 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
591 CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0),
592 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
597 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
598 CTL(60, 0), CTL(60, 0), CTL(60, 0), CTL(60, 0),
603 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
604 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
609 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
610 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
615 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
616 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
621 CTL(60, 1), CTL(60, 0), CTL(60, 1), CTL(60, 1),
622 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
628 static const struct ar9300_eeprom ar9300_x113 = {
630 .templateVersion = 6,
631 .macAddr = {0x00, 0x03, 0x7f, 0x0, 0x0, 0x0},
632 .custData = {"x113-023-f0000"},
634 .regDmn = { LE16(0), LE16(0x1f) },
635 .txrxMask = 0x77, /* 4 bits tx and 4 bits rx */
637 .opFlags = AR5416_OPFLAGS_11A,
641 .blueToothOptions = 0,
643 .deviceType = 5, /* takes lower byte in eeprom location */
644 .pwrTableOffset = AR9300_PWR_TABLE_OFFSET,
645 .params_for_tuning_caps = {0, 0},
646 .featureEnable = 0x0d,
648 * bit0 - enable tx temp comp - disabled
649 * bit1 - enable tx volt comp - disabled
650 * bit2 - enable fastClock - enabled
651 * bit3 - enable doubling - enabled
652 * bit4 - enable internal regulator - disabled
653 * bit5 - enable pa predistortion - disabled
655 .miscConfiguration = 0, /* bit0 - turn down drivestrength */
656 .eepromWriteEnableGpio = 6,
657 .wlanDisableGpio = 0,
659 .rxBandSelectGpio = 0xff,
664 /* ar9300_modal_eep_header 2g */
665 /* 4 idle,t1,t2,b(4 bits per setting) */
666 .antCtrlCommon = LE32(0x110),
667 /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
668 .antCtrlCommon2 = LE32(0x44444),
671 * antCtrlChain[AR9300_MAX_CHAINS]; 6 idle, t, r,
672 * rx1, rx12, b (2 bits each)
674 .antCtrlChain = { LE16(0x150), LE16(0x150), LE16(0x150) },
677 * xatten1DB[AR9300_MAX_CHAINS]; 3 xatten1_db
678 * for ar9280 (0xa20c/b20c 5:0)
680 .xatten1DB = {0, 0, 0},
683 * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
684 * for ar9280 (0xa20c/b20c 16:12
686 .xatten1Margin = {0, 0, 0},
691 * spurChans[OSPREY_EEPROM_MODAL_SPURS]; spur
692 * channels in usual fbin coding format
694 .spurChans = {FREQ2FBIN(2464, 1), 0, 0, 0, 0},
697 * noiseFloorThreshCh[AR9300_MAX_CHAINS]; 3 Check
698 * if the register is per chain
700 .noiseFloorThreshCh = {-1, 0, 0},
701 .ob = {1, 1, 1},/* 3 chain */
702 .db_stage2 = {1, 1, 1}, /* 3 chain */
703 .db_stage3 = {0, 0, 0},
704 .db_stage4 = {0, 0, 0},
706 .txFrameToDataStart = 0x0e,
707 .txFrameToPaOn = 0x0e,
708 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
710 .switchSettling = 0x2c,
711 .adcDesiredSize = -30,
714 .txFrameToXpaOn = 0xe,
716 .papdRateMaskHt20 = LE32(0x0c80c080),
717 .papdRateMaskHt40 = LE32(0x0080c080),
719 0, 0, 0, 0, 0, 0, 0, 0,
723 .ant_div_control = 0,
724 .future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
731 /* ar9300_cal_data_per_freq_op_loop 2g */
733 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
734 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
735 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
737 .calTarget_freqbin_Cck = {
741 .calTarget_freqbin_2G = {
746 .calTarget_freqbin_2GHT20 = {
751 .calTarget_freqbin_2GHT40 = {
756 .calTargetPowerCck = {
757 /* 1L-5L,5S,11L,11S */
758 { {34, 34, 34, 34} },
759 { {34, 34, 34, 34} },
761 .calTargetPower2G = {
763 { {34, 34, 32, 32} },
764 { {34, 34, 32, 32} },
765 { {34, 34, 32, 32} },
767 .calTargetPower2GHT20 = {
768 { {32, 32, 32, 32, 32, 28, 32, 32, 30, 28, 0, 0, 0, 0} },
769 { {32, 32, 32, 32, 32, 28, 32, 32, 30, 28, 0, 0, 0, 0} },
770 { {32, 32, 32, 32, 32, 28, 32, 32, 30, 28, 0, 0, 0, 0} },
772 .calTargetPower2GHT40 = {
773 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
774 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
775 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
778 0x11, 0x12, 0x15, 0x17, 0x41, 0x42,
779 0x45, 0x47, 0x31, 0x32, 0x35, 0x37,
809 /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
810 /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
811 /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
812 /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(2484, 1),
816 /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
817 /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
818 /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
823 /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
824 /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
830 /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
831 /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
832 /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
833 /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
837 /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
838 /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
839 /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
843 /* Data[9].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
844 /* Data[9].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
845 /* Data[9].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
850 /* Data[10].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
851 /* Data[10].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
852 /* Data[10].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
857 /* Data[11].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
858 /* Data[11].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
859 /* Data[11].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
860 /* Data[11].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
864 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
865 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
866 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 1) } },
868 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0) } },
869 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
870 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
872 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0) } },
873 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
874 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
876 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
877 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
878 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
881 /* 4 idle,t1,t2,b (4 bits per setting) */
882 .antCtrlCommon = LE32(0x220),
883 /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */
884 .antCtrlCommon2 = LE32(0x11111),
885 /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
887 LE16(0x150), LE16(0x150), LE16(0x150),
889 /* xatten1DB 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */
890 .xatten1DB = {0, 0, 0},
893 * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
894 * for merlin (0xa20c/b20c 16:12
896 .xatten1Margin = {0, 0, 0},
899 /* spurChans spur channels in usual fbin coding format */
900 .spurChans = {FREQ2FBIN(5500, 0), 0, 0, 0, 0},
901 /* noiseFloorThreshCh Check if the register is per chain */
902 .noiseFloorThreshCh = {-1, 0, 0},
903 .ob = {3, 3, 3}, /* 3 chain */
904 .db_stage2 = {3, 3, 3}, /* 3 chain */
905 .db_stage3 = {3, 3, 3}, /* doesn't exist for 2G */
906 .db_stage4 = {3, 3, 3}, /* don't exist for 2G */
908 .txFrameToDataStart = 0x0e,
909 .txFrameToPaOn = 0x0e,
910 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
912 .switchSettling = 0x2d,
913 .adcDesiredSize = -30,
916 .txFrameToXpaOn = 0xe,
918 .papdRateMaskHt20 = LE32(0x0cf0e0e0),
919 .papdRateMaskHt40 = LE32(0x6cf0e0e0),
921 0, 0, 0, 0, 0, 0, 0, 0,
926 .tempSlopeHigh = 105,
927 .xatten1DBLow = {0, 0, 0},
928 .xatten1MarginLow = {0, 0, 0},
929 .xatten1DBHigh = {0, 0, 0},
930 .xatten1MarginHigh = {0, 0, 0}
975 .calTarget_freqbin_5G = {
985 .calTarget_freqbin_5GHT20 = {
995 .calTarget_freqbin_5GHT40 = {
1005 .calTargetPower5G = {
1007 { {42, 40, 40, 34} },
1008 { {42, 40, 40, 34} },
1009 { {42, 40, 40, 34} },
1010 { {42, 40, 40, 34} },
1011 { {42, 40, 40, 34} },
1012 { {42, 40, 40, 34} },
1013 { {42, 40, 40, 34} },
1014 { {42, 40, 40, 34} },
1016 .calTargetPower5GHT20 = {
1018 * 0_8_16,1-3_9-11_17-19,
1019 * 4,5,6,7,12,13,14,15,20,21,22,23
1021 { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
1022 { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
1023 { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
1024 { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
1025 { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
1026 { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
1027 { {38, 38, 38, 38, 32, 28, 38, 38, 32, 28, 38, 38, 32, 26} },
1028 { {36, 36, 36, 36, 32, 28, 36, 36, 32, 28, 36, 36, 32, 26} },
1030 .calTargetPower5GHT40 = {
1032 * 0_8_16,1-3_9-11_17-19,
1033 * 4,5,6,7,12,13,14,15,20,21,22,23
1035 { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
1036 { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
1037 { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
1038 { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
1039 { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
1040 { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
1041 { {36, 36, 36, 36, 30, 26, 36, 36, 30, 26, 36, 36, 30, 24} },
1042 { {34, 34, 34, 34, 30, 26, 34, 34, 30, 26, 34, 34, 30, 24} },
1045 0x10, 0x16, 0x18, 0x40, 0x46,
1046 0x48, 0x30, 0x36, 0x38
1050 /* Data[0].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1051 /* Data[0].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1052 /* Data[0].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
1053 /* Data[0].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
1054 /* Data[0].ctlEdges[4].bChannel */ FREQ2FBIN(5600, 0),
1055 /* Data[0].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1056 /* Data[0].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
1057 /* Data[0].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
1060 /* Data[1].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1061 /* Data[1].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1062 /* Data[1].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
1063 /* Data[1].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
1064 /* Data[1].ctlEdges[4].bChannel */ FREQ2FBIN(5520, 0),
1065 /* Data[1].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1066 /* Data[1].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
1067 /* Data[1].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
1071 /* Data[2].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
1072 /* Data[2].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
1073 /* Data[2].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
1074 /* Data[2].ctlEdges[3].bChannel */ FREQ2FBIN(5310, 0),
1075 /* Data[2].ctlEdges[4].bChannel */ FREQ2FBIN(5510, 0),
1076 /* Data[2].ctlEdges[5].bChannel */ FREQ2FBIN(5550, 0),
1077 /* Data[2].ctlEdges[6].bChannel */ FREQ2FBIN(5670, 0),
1078 /* Data[2].ctlEdges[7].bChannel */ FREQ2FBIN(5755, 0)
1082 /* Data[3].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1083 /* Data[3].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
1084 /* Data[3].ctlEdges[2].bChannel */ FREQ2FBIN(5260, 0),
1085 /* Data[3].ctlEdges[3].bChannel */ FREQ2FBIN(5320, 0),
1086 /* Data[3].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
1087 /* Data[3].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1088 /* Data[3].ctlEdges[6].bChannel */ 0xFF,
1089 /* Data[3].ctlEdges[7].bChannel */ 0xFF,
1093 /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1094 /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1095 /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(5500, 0),
1096 /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(5700, 0),
1097 /* Data[4].ctlEdges[4].bChannel */ 0xFF,
1098 /* Data[4].ctlEdges[5].bChannel */ 0xFF,
1099 /* Data[4].ctlEdges[6].bChannel */ 0xFF,
1100 /* Data[4].ctlEdges[7].bChannel */ 0xFF,
1104 /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
1105 /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(5270, 0),
1106 /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(5310, 0),
1107 /* Data[5].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
1108 /* Data[5].ctlEdges[4].bChannel */ FREQ2FBIN(5590, 0),
1109 /* Data[5].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
1110 /* Data[5].ctlEdges[6].bChannel */ 0xFF,
1111 /* Data[5].ctlEdges[7].bChannel */ 0xFF
1115 /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1116 /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
1117 /* Data[6].ctlEdges[2].bChannel */ FREQ2FBIN(5220, 0),
1118 /* Data[6].ctlEdges[3].bChannel */ FREQ2FBIN(5260, 0),
1119 /* Data[6].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
1120 /* Data[6].ctlEdges[5].bChannel */ FREQ2FBIN(5600, 0),
1121 /* Data[6].ctlEdges[6].bChannel */ FREQ2FBIN(5700, 0),
1122 /* Data[6].ctlEdges[7].bChannel */ FREQ2FBIN(5745, 0)
1126 /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1127 /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1128 /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(5320, 0),
1129 /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
1130 /* Data[7].ctlEdges[4].bChannel */ FREQ2FBIN(5560, 0),
1131 /* Data[7].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1132 /* Data[7].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
1133 /* Data[7].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
1137 /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
1138 /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
1139 /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
1140 /* Data[8].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
1141 /* Data[8].ctlEdges[4].bChannel */ FREQ2FBIN(5550, 0),
1142 /* Data[8].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
1143 /* Data[8].ctlEdges[6].bChannel */ FREQ2FBIN(5755, 0),
1144 /* Data[8].ctlEdges[7].bChannel */ FREQ2FBIN(5795, 0)
1147 .ctlPowerData_5G = {
1150 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1151 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1156 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1157 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1162 CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 1),
1163 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1168 CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1169 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
1174 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1175 CTL(60, 0), CTL(60, 0), CTL(60, 0), CTL(60, 0),
1180 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1181 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
1186 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1187 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1192 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
1193 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1198 CTL(60, 1), CTL(60, 0), CTL(60, 1), CTL(60, 1),
1199 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
1206 static const struct ar9300_eeprom ar9300_h112 = {
1208 .templateVersion = 3,
1209 .macAddr = {0x00, 0x03, 0x7f, 0x0, 0x0, 0x0},
1210 .custData = {"h112-241-f0000"},
1212 .regDmn = { LE16(0), LE16(0x1f) },
1213 .txrxMask = 0x77, /* 4 bits tx and 4 bits rx */
1215 .opFlags = AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A,
1219 .blueToothOptions = 0,
1221 .deviceType = 5, /* takes lower byte in eeprom location */
1222 .pwrTableOffset = AR9300_PWR_TABLE_OFFSET,
1223 .params_for_tuning_caps = {0, 0},
1224 .featureEnable = 0x0d,
1226 * bit0 - enable tx temp comp - disabled
1227 * bit1 - enable tx volt comp - disabled
1228 * bit2 - enable fastClock - enabled
1229 * bit3 - enable doubling - enabled
1230 * bit4 - enable internal regulator - disabled
1231 * bit5 - enable pa predistortion - disabled
1233 .miscConfiguration = 0, /* bit0 - turn down drivestrength */
1234 .eepromWriteEnableGpio = 6,
1235 .wlanDisableGpio = 0,
1237 .rxBandSelectGpio = 0xff,
1242 /* ar9300_modal_eep_header 2g */
1243 /* 4 idle,t1,t2,b(4 bits per setting) */
1244 .antCtrlCommon = LE32(0x110),
1245 /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
1246 .antCtrlCommon2 = LE32(0x44444),
1249 * antCtrlChain[AR9300_MAX_CHAINS]; 6 idle, t, r,
1250 * rx1, rx12, b (2 bits each)
1252 .antCtrlChain = { LE16(0x150), LE16(0x150), LE16(0x150) },
1255 * xatten1DB[AR9300_MAX_CHAINS]; 3 xatten1_db
1256 * for ar9280 (0xa20c/b20c 5:0)
1258 .xatten1DB = {0, 0, 0},
1261 * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
1262 * for ar9280 (0xa20c/b20c 16:12
1264 .xatten1Margin = {0, 0, 0},
1269 * spurChans[OSPREY_EEPROM_MODAL_SPURS]; spur
1270 * channels in usual fbin coding format
1272 .spurChans = {FREQ2FBIN(2464, 1), 0, 0, 0, 0},
1275 * noiseFloorThreshCh[AR9300_MAX_CHAINS]; 3 Check
1276 * if the register is per chain
1278 .noiseFloorThreshCh = {-1, 0, 0},
1279 .ob = {1, 1, 1},/* 3 chain */
1280 .db_stage2 = {1, 1, 1}, /* 3 chain */
1281 .db_stage3 = {0, 0, 0},
1282 .db_stage4 = {0, 0, 0},
1284 .txFrameToDataStart = 0x0e,
1285 .txFrameToPaOn = 0x0e,
1286 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
1288 .switchSettling = 0x2c,
1289 .adcDesiredSize = -30,
1292 .txFrameToXpaOn = 0xe,
1294 .papdRateMaskHt20 = LE32(0x80c080),
1295 .papdRateMaskHt40 = LE32(0x80c080),
1297 0, 0, 0, 0, 0, 0, 0, 0,
1301 .ant_div_control = 0,
1302 .future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
1309 /* ar9300_cal_data_per_freq_op_loop 2g */
1311 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
1312 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
1313 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
1315 .calTarget_freqbin_Cck = {
1319 .calTarget_freqbin_2G = {
1324 .calTarget_freqbin_2GHT20 = {
1329 .calTarget_freqbin_2GHT40 = {
1334 .calTargetPowerCck = {
1335 /* 1L-5L,5S,11L,11S */
1336 { {34, 34, 34, 34} },
1337 { {34, 34, 34, 34} },
1339 .calTargetPower2G = {
1341 { {34, 34, 32, 32} },
1342 { {34, 34, 32, 32} },
1343 { {34, 34, 32, 32} },
1345 .calTargetPower2GHT20 = {
1346 { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 28, 28, 28, 24} },
1347 { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 28, 28, 28, 24} },
1348 { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 28, 28, 28, 24} },
1350 .calTargetPower2GHT40 = {
1351 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 26, 26, 26, 22} },
1352 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 26, 26, 26, 22} },
1353 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 26, 26, 26, 22} },
1356 0x11, 0x12, 0x15, 0x17, 0x41, 0x42,
1357 0x45, 0x47, 0x31, 0x32, 0x35, 0x37,
1387 /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
1388 /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
1389 /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
1390 /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(2484, 1),
1394 /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
1395 /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
1396 /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
1401 /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
1402 /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
1408 /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
1409 /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
1410 /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
1411 /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
1415 /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
1416 /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
1417 /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
1421 /* Data[9].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
1422 /* Data[9].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
1423 /* Data[9].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
1428 /* Data[10].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
1429 /* Data[10].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
1430 /* Data[10].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
1435 /* Data[11].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
1436 /* Data[11].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
1437 /* Data[11].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
1438 /* Data[11].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
1441 .ctlPowerData_2G = {
1442 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
1443 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
1444 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 1) } },
1446 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0) } },
1447 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
1448 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
1450 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0) } },
1451 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
1452 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
1454 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
1455 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
1456 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
1459 /* 4 idle,t1,t2,b (4 bits per setting) */
1460 .antCtrlCommon = LE32(0x220),
1461 /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */
1462 .antCtrlCommon2 = LE32(0x44444),
1463 /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
1465 LE16(0x150), LE16(0x150), LE16(0x150),
1467 /* xatten1DB 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */
1468 .xatten1DB = {0, 0, 0},
1471 * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
1472 * for merlin (0xa20c/b20c 16:12
1474 .xatten1Margin = {0, 0, 0},
1477 /* spurChans spur channels in usual fbin coding format */
1478 .spurChans = {0, 0, 0, 0, 0},
1479 /* noiseFloorThreshCh Check if the register is per chain */
1480 .noiseFloorThreshCh = {-1, 0, 0},
1481 .ob = {3, 3, 3}, /* 3 chain */
1482 .db_stage2 = {3, 3, 3}, /* 3 chain */
1483 .db_stage3 = {3, 3, 3}, /* doesn't exist for 2G */
1484 .db_stage4 = {3, 3, 3}, /* don't exist for 2G */
1486 .txFrameToDataStart = 0x0e,
1487 .txFrameToPaOn = 0x0e,
1488 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
1490 .switchSettling = 0x2d,
1491 .adcDesiredSize = -30,
1494 .txFrameToXpaOn = 0xe,
1496 .papdRateMaskHt20 = LE32(0x0cf0e0e0),
1497 .papdRateMaskHt40 = LE32(0x6cf0e0e0),
1499 0, 0, 0, 0, 0, 0, 0, 0,
1504 .tempSlopeHigh = 50,
1505 .xatten1DBLow = {0, 0, 0},
1506 .xatten1MarginLow = {0, 0, 0},
1507 .xatten1DBHigh = {0, 0, 0},
1508 .xatten1MarginHigh = {0, 0, 0}
1553 .calTarget_freqbin_5G = {
1563 .calTarget_freqbin_5GHT20 = {
1573 .calTarget_freqbin_5GHT40 = {
1583 .calTargetPower5G = {
1585 { {30, 30, 28, 24} },
1586 { {30, 30, 28, 24} },
1587 { {30, 30, 28, 24} },
1588 { {30, 30, 28, 24} },
1589 { {30, 30, 28, 24} },
1590 { {30, 30, 28, 24} },
1591 { {30, 30, 28, 24} },
1592 { {30, 30, 28, 24} },
1594 .calTargetPower5GHT20 = {
1596 * 0_8_16,1-3_9-11_17-19,
1597 * 4,5,6,7,12,13,14,15,20,21,22,23
1599 { {30, 30, 30, 28, 24, 20, 30, 28, 24, 20, 20, 20, 20, 16} },
1600 { {30, 30, 30, 28, 24, 20, 30, 28, 24, 20, 20, 20, 20, 16} },
1601 { {30, 30, 30, 26, 22, 18, 30, 26, 22, 18, 18, 18, 18, 16} },
1602 { {30, 30, 30, 26, 22, 18, 30, 26, 22, 18, 18, 18, 18, 16} },
1603 { {30, 30, 30, 24, 20, 16, 30, 24, 20, 16, 16, 16, 16, 14} },
1604 { {30, 30, 30, 24, 20, 16, 30, 24, 20, 16, 16, 16, 16, 14} },
1605 { {30, 30, 30, 22, 18, 14, 30, 22, 18, 14, 14, 14, 14, 12} },
1606 { {30, 30, 30, 22, 18, 14, 30, 22, 18, 14, 14, 14, 14, 12} },
1608 .calTargetPower5GHT40 = {
1610 * 0_8_16,1-3_9-11_17-19,
1611 * 4,5,6,7,12,13,14,15,20,21,22,23
1613 { {28, 28, 28, 26, 22, 18, 28, 26, 22, 18, 18, 18, 18, 14} },
1614 { {28, 28, 28, 26, 22, 18, 28, 26, 22, 18, 18, 18, 18, 14} },
1615 { {28, 28, 28, 24, 20, 16, 28, 24, 20, 16, 16, 16, 16, 12} },
1616 { {28, 28, 28, 24, 20, 16, 28, 24, 20, 16, 16, 16, 16, 12} },
1617 { {28, 28, 28, 22, 18, 14, 28, 22, 18, 14, 14, 14, 14, 10} },
1618 { {28, 28, 28, 22, 18, 14, 28, 22, 18, 14, 14, 14, 14, 10} },
1619 { {28, 28, 28, 20, 16, 12, 28, 20, 16, 12, 12, 12, 12, 8} },
1620 { {28, 28, 28, 20, 16, 12, 28, 20, 16, 12, 12, 12, 12, 8} },
1623 0x10, 0x16, 0x18, 0x40, 0x46,
1624 0x48, 0x30, 0x36, 0x38
1628 /* Data[0].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1629 /* Data[0].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1630 /* Data[0].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
1631 /* Data[0].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
1632 /* Data[0].ctlEdges[4].bChannel */ FREQ2FBIN(5600, 0),
1633 /* Data[0].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1634 /* Data[0].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
1635 /* Data[0].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
1638 /* Data[1].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1639 /* Data[1].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1640 /* Data[1].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
1641 /* Data[1].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
1642 /* Data[1].ctlEdges[4].bChannel */ FREQ2FBIN(5520, 0),
1643 /* Data[1].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1644 /* Data[1].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
1645 /* Data[1].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
1649 /* Data[2].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
1650 /* Data[2].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
1651 /* Data[2].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
1652 /* Data[2].ctlEdges[3].bChannel */ FREQ2FBIN(5310, 0),
1653 /* Data[2].ctlEdges[4].bChannel */ FREQ2FBIN(5510, 0),
1654 /* Data[2].ctlEdges[5].bChannel */ FREQ2FBIN(5550, 0),
1655 /* Data[2].ctlEdges[6].bChannel */ FREQ2FBIN(5670, 0),
1656 /* Data[2].ctlEdges[7].bChannel */ FREQ2FBIN(5755, 0)
1660 /* Data[3].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1661 /* Data[3].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
1662 /* Data[3].ctlEdges[2].bChannel */ FREQ2FBIN(5260, 0),
1663 /* Data[3].ctlEdges[3].bChannel */ FREQ2FBIN(5320, 0),
1664 /* Data[3].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
1665 /* Data[3].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1666 /* Data[3].ctlEdges[6].bChannel */ 0xFF,
1667 /* Data[3].ctlEdges[7].bChannel */ 0xFF,
1671 /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1672 /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1673 /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(5500, 0),
1674 /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(5700, 0),
1675 /* Data[4].ctlEdges[4].bChannel */ 0xFF,
1676 /* Data[4].ctlEdges[5].bChannel */ 0xFF,
1677 /* Data[4].ctlEdges[6].bChannel */ 0xFF,
1678 /* Data[4].ctlEdges[7].bChannel */ 0xFF,
1682 /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
1683 /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(5270, 0),
1684 /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(5310, 0),
1685 /* Data[5].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
1686 /* Data[5].ctlEdges[4].bChannel */ FREQ2FBIN(5590, 0),
1687 /* Data[5].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
1688 /* Data[5].ctlEdges[6].bChannel */ 0xFF,
1689 /* Data[5].ctlEdges[7].bChannel */ 0xFF
1693 /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1694 /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
1695 /* Data[6].ctlEdges[2].bChannel */ FREQ2FBIN(5220, 0),
1696 /* Data[6].ctlEdges[3].bChannel */ FREQ2FBIN(5260, 0),
1697 /* Data[6].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
1698 /* Data[6].ctlEdges[5].bChannel */ FREQ2FBIN(5600, 0),
1699 /* Data[6].ctlEdges[6].bChannel */ FREQ2FBIN(5700, 0),
1700 /* Data[6].ctlEdges[7].bChannel */ FREQ2FBIN(5745, 0)
1704 /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1705 /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1706 /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(5320, 0),
1707 /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
1708 /* Data[7].ctlEdges[4].bChannel */ FREQ2FBIN(5560, 0),
1709 /* Data[7].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1710 /* Data[7].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
1711 /* Data[7].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
1715 /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
1716 /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
1717 /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
1718 /* Data[8].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
1719 /* Data[8].ctlEdges[4].bChannel */ FREQ2FBIN(5550, 0),
1720 /* Data[8].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
1721 /* Data[8].ctlEdges[6].bChannel */ FREQ2FBIN(5755, 0),
1722 /* Data[8].ctlEdges[7].bChannel */ FREQ2FBIN(5795, 0)
1725 .ctlPowerData_5G = {
1728 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1729 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1734 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1735 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1740 CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 1),
1741 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1746 CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1747 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
1752 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1753 CTL(60, 0), CTL(60, 0), CTL(60, 0), CTL(60, 0),
1758 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1759 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
1764 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1765 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1770 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
1771 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1776 CTL(60, 1), CTL(60, 0), CTL(60, 1), CTL(60, 1),
1777 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
1784 static const struct ar9300_eeprom ar9300_x112 = {
1786 .templateVersion = 5,
1787 .macAddr = {0x00, 0x03, 0x7f, 0x0, 0x0, 0x0},
1788 .custData = {"x112-041-f0000"},
1790 .regDmn = { LE16(0), LE16(0x1f) },
1791 .txrxMask = 0x77, /* 4 bits tx and 4 bits rx */
1793 .opFlags = AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A,
1797 .blueToothOptions = 0,
1799 .deviceType = 5, /* takes lower byte in eeprom location */
1800 .pwrTableOffset = AR9300_PWR_TABLE_OFFSET,
1801 .params_for_tuning_caps = {0, 0},
1802 .featureEnable = 0x0d,
1804 * bit0 - enable tx temp comp - disabled
1805 * bit1 - enable tx volt comp - disabled
1806 * bit2 - enable fastclock - enabled
1807 * bit3 - enable doubling - enabled
1808 * bit4 - enable internal regulator - disabled
1809 * bit5 - enable pa predistortion - disabled
1811 .miscConfiguration = 0, /* bit0 - turn down drivestrength */
1812 .eepromWriteEnableGpio = 6,
1813 .wlanDisableGpio = 0,
1815 .rxBandSelectGpio = 0xff,
1820 /* ar9300_modal_eep_header 2g */
1821 /* 4 idle,t1,t2,b(4 bits per setting) */
1822 .antCtrlCommon = LE32(0x110),
1823 /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
1824 .antCtrlCommon2 = LE32(0x22222),
1827 * antCtrlChain[ar9300_max_chains]; 6 idle, t, r,
1828 * rx1, rx12, b (2 bits each)
1830 .antCtrlChain = { LE16(0x10), LE16(0x10), LE16(0x10) },
1833 * xatten1DB[AR9300_max_chains]; 3 xatten1_db
1834 * for ar9280 (0xa20c/b20c 5:0)
1836 .xatten1DB = {0x1b, 0x1b, 0x1b},
1839 * xatten1Margin[ar9300_max_chains]; 3 xatten1_margin
1840 * for ar9280 (0xa20c/b20c 16:12
1842 .xatten1Margin = {0x15, 0x15, 0x15},
1847 * spurChans[OSPrey_eeprom_modal_sPURS]; spur
1848 * channels in usual fbin coding format
1850 .spurChans = {FREQ2FBIN(2464, 1), 0, 0, 0, 0},
1853 * noiseFloorThreshch[ar9300_max_cHAINS]; 3 Check
1854 * if the register is per chain
1856 .noiseFloorThreshCh = {-1, 0, 0},
1857 .ob = {1, 1, 1},/* 3 chain */
1858 .db_stage2 = {1, 1, 1}, /* 3 chain */
1859 .db_stage3 = {0, 0, 0},
1860 .db_stage4 = {0, 0, 0},
1862 .txFrameToDataStart = 0x0e,
1863 .txFrameToPaOn = 0x0e,
1864 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
1866 .switchSettling = 0x2c,
1867 .adcDesiredSize = -30,
1870 .txFrameToXpaOn = 0xe,
1872 .papdRateMaskHt20 = LE32(0x0c80c080),
1873 .papdRateMaskHt40 = LE32(0x0080c080),
1875 0, 0, 0, 0, 0, 0, 0, 0,
1879 .ant_div_control = 0,
1880 .future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
1887 /* ar9300_cal_data_per_freq_op_loop 2g */
1889 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
1890 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
1891 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
1893 .calTarget_freqbin_Cck = {
1897 .calTarget_freqbin_2G = {
1902 .calTarget_freqbin_2GHT20 = {
1907 .calTarget_freqbin_2GHT40 = {
1912 .calTargetPowerCck = {
1913 /* 1L-5L,5S,11L,11s */
1914 { {38, 38, 38, 38} },
1915 { {38, 38, 38, 38} },
1917 .calTargetPower2G = {
1919 { {38, 38, 36, 34} },
1920 { {38, 38, 36, 34} },
1921 { {38, 38, 34, 32} },
1923 .calTargetPower2GHT20 = {
1924 { {36, 36, 36, 36, 36, 34, 34, 32, 30, 28, 28, 28, 28, 26} },
1925 { {36, 36, 36, 36, 36, 34, 36, 34, 32, 30, 30, 30, 28, 26} },
1926 { {36, 36, 36, 36, 36, 34, 34, 32, 30, 28, 28, 28, 28, 26} },
1928 .calTargetPower2GHT40 = {
1929 { {36, 36, 36, 36, 34, 32, 32, 30, 28, 26, 26, 26, 26, 24} },
1930 { {36, 36, 36, 36, 34, 32, 34, 32, 30, 28, 28, 28, 28, 24} },
1931 { {36, 36, 36, 36, 34, 32, 32, 30, 28, 26, 26, 26, 26, 24} },
1934 0x11, 0x12, 0x15, 0x17, 0x41, 0x42,
1935 0x45, 0x47, 0x31, 0x32, 0x35, 0x37,
1965 /* Data[4].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
1966 /* Data[4].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
1967 /* Data[4].ctledges[2].bchannel */ FREQ2FBIN(2472, 1),
1968 /* Data[4].ctledges[3].bchannel */ FREQ2FBIN(2484, 1),
1972 /* Data[5].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
1973 /* Data[5].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
1974 /* Data[5].ctledges[2].bchannel */ FREQ2FBIN(2472, 1),
1979 /* Data[6].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
1980 /* Data[6].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
1986 /* Data[7].ctledges[0].bchannel */ FREQ2FBIN(2422, 1),
1987 /* Data[7].ctledges[1].bchannel */ FREQ2FBIN(2427, 1),
1988 /* Data[7].ctledges[2].bchannel */ FREQ2FBIN(2447, 1),
1989 /* Data[7].ctledges[3].bchannel */ FREQ2FBIN(2462, 1),
1993 /* Data[8].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
1994 /* Data[8].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
1995 /* Data[8].ctledges[2].bchannel */ FREQ2FBIN(2472, 1),
1999 /* Data[9].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
2000 /* Data[9].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
2001 /* Data[9].ctledges[2].bchannel */ FREQ2FBIN(2472, 1),
2006 /* Data[10].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
2007 /* Data[10].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
2008 /* Data[10].ctledges[2].bchannel */ FREQ2FBIN(2472, 1),
2013 /* Data[11].ctledges[0].bchannel */ FREQ2FBIN(2422, 1),
2014 /* Data[11].ctledges[1].bchannel */ FREQ2FBIN(2427, 1),
2015 /* Data[11].ctledges[2].bchannel */ FREQ2FBIN(2447, 1),
2016 /* Data[11].ctledges[3].bchannel */ FREQ2FBIN(2462, 1),
2019 .ctlPowerData_2G = {
2020 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2021 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2022 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 1) } },
2024 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0) } },
2025 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2026 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2028 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0) } },
2029 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2030 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2032 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2033 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
2034 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
2037 /* 4 idle,t1,t2,b (4 bits per setting) */
2038 .antCtrlCommon = LE32(0x110),
2039 /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */
2040 .antCtrlCommon2 = LE32(0x22222),
2041 /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
2043 LE16(0x0), LE16(0x0), LE16(0x0),
2045 /* xatten1DB 3 xatten1_db for ar9280 (0xa20c/b20c 5:0) */
2046 .xatten1DB = {0x13, 0x19, 0x17},
2049 * xatten1Margin[ar9300_max_chains]; 3 xatten1_margin
2050 * for merlin (0xa20c/b20c 16:12
2052 .xatten1Margin = {0x19, 0x19, 0x19},
2055 /* spurChans spur channels in usual fbin coding format */
2056 .spurChans = {0, 0, 0, 0, 0},
2057 /* noiseFloorThreshch check if the register is per chain */
2058 .noiseFloorThreshCh = {-1, 0, 0},
2059 .ob = {3, 3, 3}, /* 3 chain */
2060 .db_stage2 = {3, 3, 3}, /* 3 chain */
2061 .db_stage3 = {3, 3, 3}, /* doesn't exist for 2G */
2062 .db_stage4 = {3, 3, 3}, /* don't exist for 2G */
2064 .txFrameToDataStart = 0x0e,
2065 .txFrameToPaOn = 0x0e,
2066 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
2068 .switchSettling = 0x2d,
2069 .adcDesiredSize = -30,
2072 .txFrameToXpaOn = 0xe,
2074 .papdRateMaskHt20 = LE32(0x0cf0e0e0),
2075 .papdRateMaskHt40 = LE32(0x6cf0e0e0),
2077 0, 0, 0, 0, 0, 0, 0, 0,
2082 .tempSlopeHigh = 105,
2083 .xatten1DBLow = {0x10, 0x14, 0x10},
2084 .xatten1MarginLow = {0x19, 0x19 , 0x19},
2085 .xatten1DBHigh = {0x1d, 0x20, 0x24},
2086 .xatten1MarginHigh = {0x10, 0x10, 0x10}
2131 .calTarget_freqbin_5G = {
2141 .calTarget_freqbin_5GHT20 = {
2151 .calTarget_freqbin_5GHT40 = {
2161 .calTargetPower5G = {
2163 { {32, 32, 28, 26} },
2164 { {32, 32, 28, 26} },
2165 { {32, 32, 28, 26} },
2166 { {32, 32, 26, 24} },
2167 { {32, 32, 26, 24} },
2168 { {32, 32, 24, 22} },
2169 { {30, 30, 24, 22} },
2170 { {30, 30, 24, 22} },
2172 .calTargetPower5GHT20 = {
2174 * 0_8_16,1-3_9-11_17-19,
2175 * 4,5,6,7,12,13,14,15,20,21,22,23
2177 { {32, 32, 32, 32, 28, 26, 32, 28, 26, 24, 24, 24, 22, 22} },
2178 { {32, 32, 32, 32, 28, 26, 32, 28, 26, 24, 24, 24, 22, 22} },
2179 { {32, 32, 32, 32, 28, 26, 32, 28, 26, 24, 24, 24, 22, 22} },
2180 { {32, 32, 32, 32, 28, 26, 32, 26, 24, 22, 22, 22, 20, 20} },
2181 { {32, 32, 32, 32, 28, 26, 32, 26, 24, 22, 20, 18, 16, 16} },
2182 { {32, 32, 32, 32, 28, 26, 32, 24, 20, 16, 18, 16, 14, 14} },
2183 { {30, 30, 30, 30, 28, 26, 30, 24, 20, 16, 18, 16, 14, 14} },
2184 { {30, 30, 30, 30, 28, 26, 30, 24, 20, 16, 18, 16, 14, 14} },
2186 .calTargetPower5GHT40 = {
2188 * 0_8_16,1-3_9-11_17-19,
2189 * 4,5,6,7,12,13,14,15,20,21,22,23
2191 { {32, 32, 32, 30, 28, 26, 30, 28, 26, 24, 24, 24, 22, 22} },
2192 { {32, 32, 32, 30, 28, 26, 30, 28, 26, 24, 24, 24, 22, 22} },
2193 { {32, 32, 32, 30, 28, 26, 30, 28, 26, 24, 24, 24, 22, 22} },
2194 { {32, 32, 32, 30, 28, 26, 30, 26, 24, 22, 22, 22, 20, 20} },
2195 { {32, 32, 32, 30, 28, 26, 30, 26, 24, 22, 20, 18, 16, 16} },
2196 { {32, 32, 32, 30, 28, 26, 30, 22, 20, 16, 18, 16, 14, 14} },
2197 { {30, 30, 30, 30, 28, 26, 30, 22, 20, 16, 18, 16, 14, 14} },
2198 { {30, 30, 30, 30, 28, 26, 30, 22, 20, 16, 18, 16, 14, 14} },
2201 0x10, 0x16, 0x18, 0x40, 0x46,
2202 0x48, 0x30, 0x36, 0x38
2206 /* Data[0].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
2207 /* Data[0].ctledges[1].bchannel */ FREQ2FBIN(5260, 0),
2208 /* Data[0].ctledges[2].bchannel */ FREQ2FBIN(5280, 0),
2209 /* Data[0].ctledges[3].bchannel */ FREQ2FBIN(5500, 0),
2210 /* Data[0].ctledges[4].bchannel */ FREQ2FBIN(5600, 0),
2211 /* Data[0].ctledges[5].bchannel */ FREQ2FBIN(5700, 0),
2212 /* Data[0].ctledges[6].bchannel */ FREQ2FBIN(5745, 0),
2213 /* Data[0].ctledges[7].bchannel */ FREQ2FBIN(5825, 0)
2216 /* Data[1].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
2217 /* Data[1].ctledges[1].bchannel */ FREQ2FBIN(5260, 0),
2218 /* Data[1].ctledges[2].bchannel */ FREQ2FBIN(5280, 0),
2219 /* Data[1].ctledges[3].bchannel */ FREQ2FBIN(5500, 0),
2220 /* Data[1].ctledges[4].bchannel */ FREQ2FBIN(5520, 0),
2221 /* Data[1].ctledges[5].bchannel */ FREQ2FBIN(5700, 0),
2222 /* Data[1].ctledges[6].bchannel */ FREQ2FBIN(5745, 0),
2223 /* Data[1].ctledges[7].bchannel */ FREQ2FBIN(5825, 0)
2227 /* Data[2].ctledges[0].bchannel */ FREQ2FBIN(5190, 0),
2228 /* Data[2].ctledges[1].bchannel */ FREQ2FBIN(5230, 0),
2229 /* Data[2].ctledges[2].bchannel */ FREQ2FBIN(5270, 0),
2230 /* Data[2].ctledges[3].bchannel */ FREQ2FBIN(5310, 0),
2231 /* Data[2].ctledges[4].bchannel */ FREQ2FBIN(5510, 0),
2232 /* Data[2].ctledges[5].bchannel */ FREQ2FBIN(5550, 0),
2233 /* Data[2].ctledges[6].bchannel */ FREQ2FBIN(5670, 0),
2234 /* Data[2].ctledges[7].bchannel */ FREQ2FBIN(5755, 0)
2238 /* Data[3].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
2239 /* Data[3].ctledges[1].bchannel */ FREQ2FBIN(5200, 0),
2240 /* Data[3].ctledges[2].bchannel */ FREQ2FBIN(5260, 0),
2241 /* Data[3].ctledges[3].bchannel */ FREQ2FBIN(5320, 0),
2242 /* Data[3].ctledges[4].bchannel */ FREQ2FBIN(5500, 0),
2243 /* Data[3].ctledges[5].bchannel */ FREQ2FBIN(5700, 0),
2244 /* Data[3].ctledges[6].bchannel */ 0xFF,
2245 /* Data[3].ctledges[7].bchannel */ 0xFF,
2249 /* Data[4].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
2250 /* Data[4].ctledges[1].bchannel */ FREQ2FBIN(5260, 0),
2251 /* Data[4].ctledges[2].bchannel */ FREQ2FBIN(5500, 0),
2252 /* Data[4].ctledges[3].bchannel */ FREQ2FBIN(5700, 0),
2253 /* Data[4].ctledges[4].bchannel */ 0xFF,
2254 /* Data[4].ctledges[5].bchannel */ 0xFF,
2255 /* Data[4].ctledges[6].bchannel */ 0xFF,
2256 /* Data[4].ctledges[7].bchannel */ 0xFF,
2260 /* Data[5].ctledges[0].bchannel */ FREQ2FBIN(5190, 0),
2261 /* Data[5].ctledges[1].bchannel */ FREQ2FBIN(5270, 0),
2262 /* Data[5].ctledges[2].bchannel */ FREQ2FBIN(5310, 0),
2263 /* Data[5].ctledges[3].bchannel */ FREQ2FBIN(5510, 0),
2264 /* Data[5].ctledges[4].bchannel */ FREQ2FBIN(5590, 0),
2265 /* Data[5].ctledges[5].bchannel */ FREQ2FBIN(5670, 0),
2266 /* Data[5].ctledges[6].bchannel */ 0xFF,
2267 /* Data[5].ctledges[7].bchannel */ 0xFF
2271 /* Data[6].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
2272 /* Data[6].ctledges[1].bchannel */ FREQ2FBIN(5200, 0),
2273 /* Data[6].ctledges[2].bchannel */ FREQ2FBIN(5220, 0),
2274 /* Data[6].ctledges[3].bchannel */ FREQ2FBIN(5260, 0),
2275 /* Data[6].ctledges[4].bchannel */ FREQ2FBIN(5500, 0),
2276 /* Data[6].ctledges[5].bchannel */ FREQ2FBIN(5600, 0),
2277 /* Data[6].ctledges[6].bchannel */ FREQ2FBIN(5700, 0),
2278 /* Data[6].ctledges[7].bchannel */ FREQ2FBIN(5745, 0)
2282 /* Data[7].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
2283 /* Data[7].ctledges[1].bchannel */ FREQ2FBIN(5260, 0),
2284 /* Data[7].ctledges[2].bchannel */ FREQ2FBIN(5320, 0),
2285 /* Data[7].ctledges[3].bchannel */ FREQ2FBIN(5500, 0),
2286 /* Data[7].ctledges[4].bchannel */ FREQ2FBIN(5560, 0),
2287 /* Data[7].ctledges[5].bchannel */ FREQ2FBIN(5700, 0),
2288 /* Data[7].ctledges[6].bchannel */ FREQ2FBIN(5745, 0),
2289 /* Data[7].ctledges[7].bchannel */ FREQ2FBIN(5825, 0)
2293 /* Data[8].ctledges[0].bchannel */ FREQ2FBIN(5190, 0),
2294 /* Data[8].ctledges[1].bchannel */ FREQ2FBIN(5230, 0),
2295 /* Data[8].ctledges[2].bchannel */ FREQ2FBIN(5270, 0),
2296 /* Data[8].ctledges[3].bchannel */ FREQ2FBIN(5510, 0),
2297 /* Data[8].ctledges[4].bchannel */ FREQ2FBIN(5550, 0),
2298 /* Data[8].ctledges[5].bchannel */ FREQ2FBIN(5670, 0),
2299 /* Data[8].ctledges[6].bchannel */ FREQ2FBIN(5755, 0),
2300 /* Data[8].ctledges[7].bchannel */ FREQ2FBIN(5795, 0)
2303 .ctlPowerData_5G = {
2306 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2307 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2312 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2313 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2318 CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 1),
2319 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2324 CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2325 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
2330 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2331 CTL(60, 0), CTL(60, 0), CTL(60, 0), CTL(60, 0),
2336 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2337 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
2342 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2343 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2348 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
2349 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2354 CTL(60, 1), CTL(60, 0), CTL(60, 1), CTL(60, 1),
2355 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
2361 static const struct ar9300_eeprom ar9300_h116 = {
2363 .templateVersion = 4,
2364 .macAddr = {0x00, 0x03, 0x7f, 0x0, 0x0, 0x0},
2365 .custData = {"h116-041-f0000"},
2367 .regDmn = { LE16(0), LE16(0x1f) },
2368 .txrxMask = 0x33, /* 4 bits tx and 4 bits rx */
2370 .opFlags = AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A,
2374 .blueToothOptions = 0,
2376 .deviceType = 5, /* takes lower byte in eeprom location */
2377 .pwrTableOffset = AR9300_PWR_TABLE_OFFSET,
2378 .params_for_tuning_caps = {0, 0},
2379 .featureEnable = 0x0d,
2381 * bit0 - enable tx temp comp - disabled
2382 * bit1 - enable tx volt comp - disabled
2383 * bit2 - enable fastClock - enabled
2384 * bit3 - enable doubling - enabled
2385 * bit4 - enable internal regulator - disabled
2386 * bit5 - enable pa predistortion - disabled
2388 .miscConfiguration = 0, /* bit0 - turn down drivestrength */
2389 .eepromWriteEnableGpio = 6,
2390 .wlanDisableGpio = 0,
2392 .rxBandSelectGpio = 0xff,
2397 /* ar9300_modal_eep_header 2g */
2398 /* 4 idle,t1,t2,b(4 bits per setting) */
2399 .antCtrlCommon = LE32(0x110),
2400 /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
2401 .antCtrlCommon2 = LE32(0x44444),
2404 * antCtrlChain[AR9300_MAX_CHAINS]; 6 idle, t, r,
2405 * rx1, rx12, b (2 bits each)
2407 .antCtrlChain = { LE16(0x10), LE16(0x10), LE16(0x10) },
2410 * xatten1DB[AR9300_MAX_CHAINS]; 3 xatten1_db
2411 * for ar9280 (0xa20c/b20c 5:0)
2413 .xatten1DB = {0x1f, 0x1f, 0x1f},
2416 * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
2417 * for ar9280 (0xa20c/b20c 16:12
2419 .xatten1Margin = {0x12, 0x12, 0x12},
2424 * spurChans[OSPREY_EEPROM_MODAL_SPURS]; spur
2425 * channels in usual fbin coding format
2427 .spurChans = {FREQ2FBIN(2464, 1), 0, 0, 0, 0},
2430 * noiseFloorThreshCh[AR9300_MAX_CHAINS]; 3 Check
2431 * if the register is per chain
2433 .noiseFloorThreshCh = {-1, 0, 0},
2434 .ob = {1, 1, 1},/* 3 chain */
2435 .db_stage2 = {1, 1, 1}, /* 3 chain */
2436 .db_stage3 = {0, 0, 0},
2437 .db_stage4 = {0, 0, 0},
2439 .txFrameToDataStart = 0x0e,
2440 .txFrameToPaOn = 0x0e,
2441 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
2443 .switchSettling = 0x2c,
2444 .adcDesiredSize = -30,
2447 .txFrameToXpaOn = 0xe,
2449 .papdRateMaskHt20 = LE32(0x0c80C080),
2450 .papdRateMaskHt40 = LE32(0x0080C080),
2452 0, 0, 0, 0, 0, 0, 0, 0,
2456 .ant_div_control = 0,
2457 .future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
2464 /* ar9300_cal_data_per_freq_op_loop 2g */
2466 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
2467 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
2468 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
2470 .calTarget_freqbin_Cck = {
2474 .calTarget_freqbin_2G = {
2479 .calTarget_freqbin_2GHT20 = {
2484 .calTarget_freqbin_2GHT40 = {
2489 .calTargetPowerCck = {
2490 /* 1L-5L,5S,11L,11S */
2491 { {34, 34, 34, 34} },
2492 { {34, 34, 34, 34} },
2494 .calTargetPower2G = {
2496 { {34, 34, 32, 32} },
2497 { {34, 34, 32, 32} },
2498 { {34, 34, 32, 32} },
2500 .calTargetPower2GHT20 = {
2501 { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 0, 0, 0, 0} },
2502 { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 0, 0, 0, 0} },
2503 { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 0, 0, 0, 0} },
2505 .calTargetPower2GHT40 = {
2506 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
2507 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
2508 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
2511 0x11, 0x12, 0x15, 0x17, 0x41, 0x42,
2512 0x45, 0x47, 0x31, 0x32, 0x35, 0x37,
2542 /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
2543 /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
2544 /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
2545 /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(2484, 1),
2549 /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
2550 /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
2551 /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
2556 /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
2557 /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
2563 /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
2564 /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
2565 /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
2566 /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
2570 /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
2571 /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
2572 /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
2576 /* Data[9].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
2577 /* Data[9].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
2578 /* Data[9].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
2583 /* Data[10].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
2584 /* Data[10].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
2585 /* Data[10].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
2590 /* Data[11].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
2591 /* Data[11].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
2592 /* Data[11].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
2593 /* Data[11].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
2596 .ctlPowerData_2G = {
2597 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2598 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2599 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 1) } },
2601 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0) } },
2602 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2603 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2605 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0) } },
2606 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2607 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2609 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2610 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
2611 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
2614 /* 4 idle,t1,t2,b (4 bits per setting) */
2615 .antCtrlCommon = LE32(0x220),
2616 /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */
2617 .antCtrlCommon2 = LE32(0x44444),
2618 /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
2620 LE16(0x150), LE16(0x150), LE16(0x150),
2622 /* xatten1DB 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */
2623 .xatten1DB = {0x19, 0x19, 0x19},
2626 * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
2627 * for merlin (0xa20c/b20c 16:12
2629 .xatten1Margin = {0x14, 0x14, 0x14},
2632 /* spurChans spur channels in usual fbin coding format */
2633 .spurChans = {0, 0, 0, 0, 0},
2634 /* noiseFloorThreshCh Check if the register is per chain */
2635 .noiseFloorThreshCh = {-1, 0, 0},
2636 .ob = {3, 3, 3}, /* 3 chain */
2637 .db_stage2 = {3, 3, 3}, /* 3 chain */
2638 .db_stage3 = {3, 3, 3}, /* doesn't exist for 2G */
2639 .db_stage4 = {3, 3, 3}, /* don't exist for 2G */
2641 .txFrameToDataStart = 0x0e,
2642 .txFrameToPaOn = 0x0e,
2643 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
2645 .switchSettling = 0x2d,
2646 .adcDesiredSize = -30,
2649 .txFrameToXpaOn = 0xe,
2651 .papdRateMaskHt20 = LE32(0x0cf0e0e0),
2652 .papdRateMaskHt40 = LE32(0x6cf0e0e0),
2654 0, 0, 0, 0, 0, 0, 0, 0,
2659 .tempSlopeHigh = 50,
2660 .xatten1DBLow = {0, 0, 0},
2661 .xatten1MarginLow = {0, 0, 0},
2662 .xatten1DBHigh = {0, 0, 0},
2663 .xatten1MarginHigh = {0, 0, 0}
2708 .calTarget_freqbin_5G = {
2718 .calTarget_freqbin_5GHT20 = {
2728 .calTarget_freqbin_5GHT40 = {
2738 .calTargetPower5G = {
2740 { {30, 30, 28, 24} },
2741 { {30, 30, 28, 24} },
2742 { {30, 30, 28, 24} },
2743 { {30, 30, 28, 24} },
2744 { {30, 30, 28, 24} },
2745 { {30, 30, 28, 24} },
2746 { {30, 30, 28, 24} },
2747 { {30, 30, 28, 24} },
2749 .calTargetPower5GHT20 = {
2751 * 0_8_16,1-3_9-11_17-19,
2752 * 4,5,6,7,12,13,14,15,20,21,22,23
2754 { {30, 30, 30, 28, 24, 20, 30, 28, 24, 20, 0, 0, 0, 0} },
2755 { {30, 30, 30, 28, 24, 20, 30, 28, 24, 20, 0, 0, 0, 0} },
2756 { {30, 30, 30, 26, 22, 18, 30, 26, 22, 18, 0, 0, 0, 0} },
2757 { {30, 30, 30, 26, 22, 18, 30, 26, 22, 18, 0, 0, 0, 0} },
2758 { {30, 30, 30, 24, 20, 16, 30, 24, 20, 16, 0, 0, 0, 0} },
2759 { {30, 30, 30, 24, 20, 16, 30, 24, 20, 16, 0, 0, 0, 0} },
2760 { {30, 30, 30, 22, 18, 14, 30, 22, 18, 14, 0, 0, 0, 0} },
2761 { {30, 30, 30, 22, 18, 14, 30, 22, 18, 14, 0, 0, 0, 0} },
2763 .calTargetPower5GHT40 = {
2765 * 0_8_16,1-3_9-11_17-19,
2766 * 4,5,6,7,12,13,14,15,20,21,22,23
2768 { {28, 28, 28, 26, 22, 18, 28, 26, 22, 18, 0, 0, 0, 0} },
2769 { {28, 28, 28, 26, 22, 18, 28, 26, 22, 18, 0, 0, 0, 0} },
2770 { {28, 28, 28, 24, 20, 16, 28, 24, 20, 16, 0, 0, 0, 0} },
2771 { {28, 28, 28, 24, 20, 16, 28, 24, 20, 16, 0, 0, 0, 0} },
2772 { {28, 28, 28, 22, 18, 14, 28, 22, 18, 14, 0, 0, 0, 0} },
2773 { {28, 28, 28, 22, 18, 14, 28, 22, 18, 14, 0, 0, 0, 0} },
2774 { {28, 28, 28, 20, 16, 12, 28, 20, 16, 12, 0, 0, 0, 0} },
2775 { {28, 28, 28, 20, 16, 12, 28, 20, 16, 12, 0, 0, 0, 0} },
2778 0x10, 0x16, 0x18, 0x40, 0x46,
2779 0x48, 0x30, 0x36, 0x38
2783 /* Data[0].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
2784 /* Data[0].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
2785 /* Data[0].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
2786 /* Data[0].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
2787 /* Data[0].ctlEdges[4].bChannel */ FREQ2FBIN(5600, 0),
2788 /* Data[0].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
2789 /* Data[0].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
2790 /* Data[0].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
2793 /* Data[1].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
2794 /* Data[1].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
2795 /* Data[1].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
2796 /* Data[1].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
2797 /* Data[1].ctlEdges[4].bChannel */ FREQ2FBIN(5520, 0),
2798 /* Data[1].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
2799 /* Data[1].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
2800 /* Data[1].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
2804 /* Data[2].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
2805 /* Data[2].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
2806 /* Data[2].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
2807 /* Data[2].ctlEdges[3].bChannel */ FREQ2FBIN(5310, 0),
2808 /* Data[2].ctlEdges[4].bChannel */ FREQ2FBIN(5510, 0),
2809 /* Data[2].ctlEdges[5].bChannel */ FREQ2FBIN(5550, 0),
2810 /* Data[2].ctlEdges[6].bChannel */ FREQ2FBIN(5670, 0),
2811 /* Data[2].ctlEdges[7].bChannel */ FREQ2FBIN(5755, 0)
2815 /* Data[3].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
2816 /* Data[3].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
2817 /* Data[3].ctlEdges[2].bChannel */ FREQ2FBIN(5260, 0),
2818 /* Data[3].ctlEdges[3].bChannel */ FREQ2FBIN(5320, 0),
2819 /* Data[3].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
2820 /* Data[3].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
2821 /* Data[3].ctlEdges[6].bChannel */ 0xFF,
2822 /* Data[3].ctlEdges[7].bChannel */ 0xFF,
2826 /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
2827 /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
2828 /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(5500, 0),
2829 /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(5700, 0),
2830 /* Data[4].ctlEdges[4].bChannel */ 0xFF,
2831 /* Data[4].ctlEdges[5].bChannel */ 0xFF,
2832 /* Data[4].ctlEdges[6].bChannel */ 0xFF,
2833 /* Data[4].ctlEdges[7].bChannel */ 0xFF,
2837 /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
2838 /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(5270, 0),
2839 /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(5310, 0),
2840 /* Data[5].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
2841 /* Data[5].ctlEdges[4].bChannel */ FREQ2FBIN(5590, 0),
2842 /* Data[5].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
2843 /* Data[5].ctlEdges[6].bChannel */ 0xFF,
2844 /* Data[5].ctlEdges[7].bChannel */ 0xFF
2848 /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
2849 /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
2850 /* Data[6].ctlEdges[2].bChannel */ FREQ2FBIN(5220, 0),
2851 /* Data[6].ctlEdges[3].bChannel */ FREQ2FBIN(5260, 0),
2852 /* Data[6].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
2853 /* Data[6].ctlEdges[5].bChannel */ FREQ2FBIN(5600, 0),
2854 /* Data[6].ctlEdges[6].bChannel */ FREQ2FBIN(5700, 0),
2855 /* Data[6].ctlEdges[7].bChannel */ FREQ2FBIN(5745, 0)
2859 /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
2860 /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
2861 /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(5320, 0),
2862 /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
2863 /* Data[7].ctlEdges[4].bChannel */ FREQ2FBIN(5560, 0),
2864 /* Data[7].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
2865 /* Data[7].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
2866 /* Data[7].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
2870 /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
2871 /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
2872 /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
2873 /* Data[8].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
2874 /* Data[8].ctlEdges[4].bChannel */ FREQ2FBIN(5550, 0),
2875 /* Data[8].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
2876 /* Data[8].ctlEdges[6].bChannel */ FREQ2FBIN(5755, 0),
2877 /* Data[8].ctlEdges[7].bChannel */ FREQ2FBIN(5795, 0)
2880 .ctlPowerData_5G = {
2883 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2884 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2889 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2890 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2895 CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 1),
2896 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2901 CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2902 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
2907 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2908 CTL(60, 0), CTL(60, 0), CTL(60, 0), CTL(60, 0),
2913 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2914 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
2919 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2920 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2925 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
2926 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2931 CTL(60, 1), CTL(60, 0), CTL(60, 1), CTL(60, 1),
2932 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
2939 static const struct ar9300_eeprom *ar9300_eep_templates[] = {
2947 static const struct ar9300_eeprom *ar9003_eeprom_struct_find_by_id(int id)
2949 #define N_LOOP (sizeof(ar9300_eep_templates) / sizeof(ar9300_eep_templates[0]))
2952 for (it = 0; it < N_LOOP; it++)
2953 if (ar9300_eep_templates[it]->templateVersion == id)
2954 return ar9300_eep_templates[it];
2960 static u16 ath9k_hw_fbin2freq(u8 fbin, bool is2GHz)
2962 if (fbin == AR5416_BCHAN_UNUSED)
2965 return (u16) ((is2GHz) ? (2300 + fbin) : (4800 + 5 * fbin));
2968 static int ath9k_hw_ar9300_check_eeprom(struct ath_hw *ah)
2973 static int interpolate(int x, int xa, int xb, int ya, int yb)
2975 int bf, factor, plus;
2977 bf = 2 * (yb - ya) * (x - xa) / (xb - xa);
2980 return ya + factor + plus;
2983 static u32 ath9k_hw_ar9300_get_eeprom(struct ath_hw *ah,
2984 enum eeprom_param param)
2986 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
2987 struct ar9300_base_eep_hdr *pBase = &eep->baseEepHeader;
2991 return get_unaligned_be16(eep->macAddr);
2993 return get_unaligned_be16(eep->macAddr + 2);
2995 return get_unaligned_be16(eep->macAddr + 4);
2997 return le16_to_cpu(pBase->regDmn[0]);
2999 return le16_to_cpu(pBase->regDmn[1]);
3001 return pBase->deviceCap;
3003 return pBase->opCapFlags.opFlags;
3005 return pBase->rfSilent;
3007 return (pBase->txrxMask >> 4) & 0xf;
3009 return pBase->txrxMask & 0xf;
3010 case EEP_DRIVE_STRENGTH:
3011 #define AR9300_EEP_BASE_DRIV_STRENGTH 0x1
3012 return pBase->miscConfiguration & AR9300_EEP_BASE_DRIV_STRENGTH;
3013 case EEP_INTERNAL_REGULATOR:
3014 /* Bit 4 is internal regulator flag */
3015 return (pBase->featureEnable & 0x10) >> 4;
3017 return le32_to_cpu(pBase->swreg);
3019 return !!(pBase->featureEnable & BIT(5));
3020 case EEP_CHAIN_MASK_REDUCE:
3021 return (pBase->miscConfiguration >> 0x3) & 0x1;
3022 case EEP_ANT_DIV_CTL1:
3023 return eep->base_ext1.ant_div_control;
3029 static bool ar9300_eeprom_read_byte(struct ath_common *common, int address,
3034 if (unlikely(!ath9k_hw_nvram_read(common, address / 2, &val)))
3037 *buffer = (val >> (8 * (address % 2))) & 0xff;
3041 static bool ar9300_eeprom_read_word(struct ath_common *common, int address,
3046 if (unlikely(!ath9k_hw_nvram_read(common, address / 2, &val)))
3049 buffer[0] = val >> 8;
3050 buffer[1] = val & 0xff;
3055 static bool ar9300_read_eeprom(struct ath_hw *ah, int address, u8 *buffer,
3058 struct ath_common *common = ath9k_hw_common(ah);
3061 if ((address < 0) || ((address + count) / 2 > AR9300_EEPROM_SIZE - 1)) {
3062 ath_dbg(common, ATH_DBG_EEPROM,
3063 "eeprom address not in range\n");
3068 * Since we're reading the bytes in reverse order from a little-endian
3069 * word stream, an even address means we only use the lower half of
3070 * the 16-bit word at that address
3072 if (address % 2 == 0) {
3073 if (!ar9300_eeprom_read_byte(common, address--, buffer++))
3079 for (i = 0; i < count / 2; i++) {
3080 if (!ar9300_eeprom_read_word(common, address, buffer))
3088 if (!ar9300_eeprom_read_byte(common, address, buffer))
3094 ath_dbg(common, ATH_DBG_EEPROM,
3095 "unable to read eeprom region at offset %d\n", address);
3099 static bool ar9300_otp_read_word(struct ath_hw *ah, int addr, u32 *data)
3101 REG_READ(ah, AR9300_OTP_BASE + (4 * addr));
3103 if (!ath9k_hw_wait(ah, AR9300_OTP_STATUS, AR9300_OTP_STATUS_TYPE,
3104 AR9300_OTP_STATUS_VALID, 1000))
3107 *data = REG_READ(ah, AR9300_OTP_READ_DATA);
3111 static bool ar9300_read_otp(struct ath_hw *ah, int address, u8 *buffer,
3117 for (i = 0; i < count; i++) {
3118 int offset = 8 * ((address - i) % 4);
3119 if (!ar9300_otp_read_word(ah, (address - i) / 4, &data))
3122 buffer[i] = (data >> offset) & 0xff;
3129 static void ar9300_comp_hdr_unpack(u8 *best, int *code, int *reference,
3130 int *length, int *major, int *minor)
3132 unsigned long value[4];
3138 *code = ((value[0] >> 5) & 0x0007);
3139 *reference = (value[0] & 0x001f) | ((value[1] >> 2) & 0x0020);
3140 *length = ((value[1] << 4) & 0x07f0) | ((value[2] >> 4) & 0x000f);
3141 *major = (value[2] & 0x000f);
3142 *minor = (value[3] & 0x00ff);
3145 static u16 ar9300_comp_cksum(u8 *data, int dsize)
3147 int it, checksum = 0;
3149 for (it = 0; it < dsize; it++) {
3150 checksum += data[it];
3157 static bool ar9300_uncompress_block(struct ath_hw *ah,
3167 struct ath_common *common = ath9k_hw_common(ah);
3171 for (it = 0; it < size; it += (length+2)) {
3175 length = block[it+1];
3178 if (length > 0 && spot >= 0 && spot+length <= mdataSize) {
3179 ath_dbg(common, ATH_DBG_EEPROM,
3180 "Restore at %d: spot=%d offset=%d length=%d\n",
3181 it, spot, offset, length);
3182 memcpy(&mptr[spot], &block[it+2], length);
3184 } else if (length > 0) {
3185 ath_dbg(common, ATH_DBG_EEPROM,
3186 "Bad restore at %d: spot=%d offset=%d length=%d\n",
3187 it, spot, offset, length);
3194 static int ar9300_compress_decision(struct ath_hw *ah,
3199 u8 *word, int length, int mdata_size)
3201 struct ath_common *common = ath9k_hw_common(ah);
3202 const struct ar9300_eeprom *eep = NULL;
3206 if (length != mdata_size) {
3207 ath_dbg(common, ATH_DBG_EEPROM,
3208 "EEPROM structure size mismatch memory=%d eeprom=%d\n",
3209 mdata_size, length);
3212 memcpy(mptr, (u8 *) (word + COMP_HDR_LEN), length);
3213 ath_dbg(common, ATH_DBG_EEPROM,
3214 "restored eeprom %d: uncompressed, length %d\n",
3217 case _CompressBlock:
3218 if (reference == 0) {
3220 eep = ar9003_eeprom_struct_find_by_id(reference);
3222 ath_dbg(common, ATH_DBG_EEPROM,
3223 "can't find reference eeprom struct %d\n",
3227 memcpy(mptr, eep, mdata_size);
3229 ath_dbg(common, ATH_DBG_EEPROM,
3230 "restore eeprom %d: block, reference %d, length %d\n",
3231 it, reference, length);
3232 ar9300_uncompress_block(ah, mptr, mdata_size,
3233 (u8 *) (word + COMP_HDR_LEN), length);
3236 ath_dbg(common, ATH_DBG_EEPROM,
3237 "unknown compression code %d\n", code);
3243 typedef bool (*eeprom_read_op)(struct ath_hw *ah, int address, u8 *buffer,
3246 static bool ar9300_check_header(void *data)
3249 return !(*word == 0 || *word == ~0);
3252 static bool ar9300_check_eeprom_header(struct ath_hw *ah, eeprom_read_op read,
3257 if (!read(ah, base_addr, header, 4))
3260 return ar9300_check_header(header);
3263 static int ar9300_eeprom_restore_flash(struct ath_hw *ah, u8 *mptr,
3266 struct ath_common *common = ath9k_hw_common(ah);
3267 u16 *data = (u16 *) mptr;
3270 for (i = 0; i < mdata_size / 2; i++, data++)
3271 ath9k_hw_nvram_read(common, i, data);
3276 * Read the configuration data from the eeprom.
3277 * The data can be put in any specified memory buffer.
3279 * Returns -1 on error.
3280 * Returns address of next memory location on success.
3282 static int ar9300_eeprom_restore_internal(struct ath_hw *ah,
3283 u8 *mptr, int mdata_size)
3290 int reference, length, major, minor;
3293 u16 checksum, mchecksum;
3294 struct ath_common *common = ath9k_hw_common(ah);
3295 eeprom_read_op read;
3297 if (ath9k_hw_use_flash(ah))
3298 return ar9300_eeprom_restore_flash(ah, mptr, mdata_size);
3300 word = kzalloc(2048, GFP_KERNEL);
3304 memcpy(mptr, &ar9300_default, mdata_size);
3306 read = ar9300_read_eeprom;
3307 if (AR_SREV_9485(ah))
3308 cptr = AR9300_BASE_ADDR_4K;
3309 else if (AR_SREV_9330(ah))
3310 cptr = AR9300_BASE_ADDR_512;
3312 cptr = AR9300_BASE_ADDR;
3313 ath_dbg(common, ATH_DBG_EEPROM,
3314 "Trying EEPROM access at Address 0x%04x\n", cptr);
3315 if (ar9300_check_eeprom_header(ah, read, cptr))
3318 cptr = AR9300_BASE_ADDR_512;
3319 ath_dbg(common, ATH_DBG_EEPROM,
3320 "Trying EEPROM access at Address 0x%04x\n", cptr);
3321 if (ar9300_check_eeprom_header(ah, read, cptr))
3324 read = ar9300_read_otp;
3325 cptr = AR9300_BASE_ADDR;
3326 ath_dbg(common, ATH_DBG_EEPROM,
3327 "Trying OTP access at Address 0x%04x\n", cptr);
3328 if (ar9300_check_eeprom_header(ah, read, cptr))
3331 cptr = AR9300_BASE_ADDR_512;
3332 ath_dbg(common, ATH_DBG_EEPROM,
3333 "Trying OTP access at Address 0x%04x\n", cptr);
3334 if (ar9300_check_eeprom_header(ah, read, cptr))
3340 ath_dbg(common, ATH_DBG_EEPROM, "Found valid EEPROM data\n");
3342 for (it = 0; it < MSTATE; it++) {
3343 if (!read(ah, cptr, word, COMP_HDR_LEN))
3346 if (!ar9300_check_header(word))
3349 ar9300_comp_hdr_unpack(word, &code, &reference,
3350 &length, &major, &minor);
3351 ath_dbg(common, ATH_DBG_EEPROM,
3352 "Found block at %x: code=%d ref=%d length=%d major=%d minor=%d\n",
3353 cptr, code, reference, length, major, minor);
3354 if ((!AR_SREV_9485(ah) && length >= 1024) ||
3355 (AR_SREV_9485(ah) && length > EEPROM_DATA_LEN_9485)) {
3356 ath_dbg(common, ATH_DBG_EEPROM,
3357 "Skipping bad header\n");
3358 cptr -= COMP_HDR_LEN;
3363 read(ah, cptr, word, COMP_HDR_LEN + osize + COMP_CKSUM_LEN);
3364 checksum = ar9300_comp_cksum(&word[COMP_HDR_LEN], length);
3365 mchecksum = get_unaligned_le16(&word[COMP_HDR_LEN + osize]);
3366 ath_dbg(common, ATH_DBG_EEPROM,
3367 "checksum %x %x\n", checksum, mchecksum);
3368 if (checksum == mchecksum) {
3369 ar9300_compress_decision(ah, it, code, reference, mptr,
3370 word, length, mdata_size);
3372 ath_dbg(common, ATH_DBG_EEPROM,
3373 "skipping block with bad checksum\n");
3375 cptr -= (COMP_HDR_LEN + osize + COMP_CKSUM_LEN);
3387 * Restore the configuration structure by reading the eeprom.
3388 * This function destroys any existing in-memory structure
3391 static bool ath9k_hw_ar9300_fill_eeprom(struct ath_hw *ah)
3393 u8 *mptr = (u8 *) &ah->eeprom.ar9300_eep;
3395 if (ar9300_eeprom_restore_internal(ah, mptr,
3396 sizeof(struct ar9300_eeprom)) < 0)
3402 #if defined(CONFIG_ATH9K_DEBUGFS) || defined(CONFIG_ATH9K_HTC_DEBUGFS)
3403 static u32 ar9003_dump_modal_eeprom(char *buf, u32 len, u32 size,
3404 struct ar9300_modal_eep_header *modal_hdr)
3406 PR_EEP("Chain0 Ant. Control", le16_to_cpu(modal_hdr->antCtrlChain[0]));
3407 PR_EEP("Chain1 Ant. Control", le16_to_cpu(modal_hdr->antCtrlChain[1]));
3408 PR_EEP("Chain2 Ant. Control", le16_to_cpu(modal_hdr->antCtrlChain[2]));
3409 PR_EEP("Ant. Common Control", le32_to_cpu(modal_hdr->antCtrlCommon));
3410 PR_EEP("Ant. Common Control2", le32_to_cpu(modal_hdr->antCtrlCommon2));
3411 PR_EEP("Ant. Gain", modal_hdr->antennaGain);
3412 PR_EEP("Switch Settle", modal_hdr->switchSettling);
3413 PR_EEP("Chain0 xatten1DB", modal_hdr->xatten1DB[0]);
3414 PR_EEP("Chain1 xatten1DB", modal_hdr->xatten1DB[1]);
3415 PR_EEP("Chain2 xatten1DB", modal_hdr->xatten1DB[2]);
3416 PR_EEP("Chain0 xatten1Margin", modal_hdr->xatten1Margin[0]);
3417 PR_EEP("Chain1 xatten1Margin", modal_hdr->xatten1Margin[1]);
3418 PR_EEP("Chain2 xatten1Margin", modal_hdr->xatten1Margin[2]);
3419 PR_EEP("Temp Slope", modal_hdr->tempSlope);
3420 PR_EEP("Volt Slope", modal_hdr->voltSlope);
3421 PR_EEP("spur Channels0", modal_hdr->spurChans[0]);
3422 PR_EEP("spur Channels1", modal_hdr->spurChans[1]);
3423 PR_EEP("spur Channels2", modal_hdr->spurChans[2]);
3424 PR_EEP("spur Channels3", modal_hdr->spurChans[3]);
3425 PR_EEP("spur Channels4", modal_hdr->spurChans[4]);
3426 PR_EEP("Chain0 NF Threshold", modal_hdr->noiseFloorThreshCh[0]);
3427 PR_EEP("Chain1 NF Threshold", modal_hdr->noiseFloorThreshCh[1]);
3428 PR_EEP("Chain2 NF Threshold", modal_hdr->noiseFloorThreshCh[2]);
3429 PR_EEP("xPA Bias Level", modal_hdr->xpaBiasLvl);
3430 PR_EEP("txFrameToDataStart", modal_hdr->txFrameToDataStart);
3431 PR_EEP("txFrameToPaOn", modal_hdr->txFrameToPaOn);
3432 PR_EEP("txFrameToXpaOn", modal_hdr->txFrameToXpaOn);
3433 PR_EEP("txClip", modal_hdr->txClip);
3434 PR_EEP("ADC Desired size", modal_hdr->adcDesiredSize);
3435 PR_EEP("Chain0 ob", modal_hdr->ob[0]);
3436 PR_EEP("Chain1 ob", modal_hdr->ob[1]);
3437 PR_EEP("Chain2 ob", modal_hdr->ob[2]);
3439 PR_EEP("Chain0 db_stage2", modal_hdr->db_stage2[0]);
3440 PR_EEP("Chain1 db_stage2", modal_hdr->db_stage2[1]);
3441 PR_EEP("Chain2 db_stage2", modal_hdr->db_stage2[2]);
3442 PR_EEP("Chain0 db_stage3", modal_hdr->db_stage3[0]);
3443 PR_EEP("Chain1 db_stage3", modal_hdr->db_stage3[1]);
3444 PR_EEP("Chain2 db_stage3", modal_hdr->db_stage3[2]);
3445 PR_EEP("Chain0 db_stage4", modal_hdr->db_stage4[0]);
3446 PR_EEP("Chain1 db_stage4", modal_hdr->db_stage4[1]);
3447 PR_EEP("Chain2 db_stage4", modal_hdr->db_stage4[2]);
3452 static u32 ath9k_hw_ar9003_dump_eeprom(struct ath_hw *ah, bool dump_base_hdr,
3453 u8 *buf, u32 len, u32 size)
3455 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3456 struct ar9300_base_eep_hdr *pBase;
3458 if (!dump_base_hdr) {
3459 len += snprintf(buf + len, size - len,
3460 "%20s :\n", "2GHz modal Header");
3461 len += ar9003_dump_modal_eeprom(buf, len, size,
3462 &eep->modalHeader2G);
3463 len += snprintf(buf + len, size - len,
3464 "%20s :\n", "5GHz modal Header");
3465 len += ar9003_dump_modal_eeprom(buf, len, size,
3466 &eep->modalHeader5G);
3470 pBase = &eep->baseEepHeader;
3472 PR_EEP("EEPROM Version", ah->eeprom.ar9300_eep.eepromVersion);
3473 PR_EEP("RegDomain1", le16_to_cpu(pBase->regDmn[0]));
3474 PR_EEP("RegDomain2", le16_to_cpu(pBase->regDmn[1]));
3475 PR_EEP("TX Mask", (pBase->txrxMask >> 4));
3476 PR_EEP("RX Mask", (pBase->txrxMask & 0x0f));
3477 PR_EEP("Allow 5GHz", !!(pBase->opCapFlags.opFlags &
3478 AR5416_OPFLAGS_11A));
3479 PR_EEP("Allow 2GHz", !!(pBase->opCapFlags.opFlags &
3480 AR5416_OPFLAGS_11G));
3481 PR_EEP("Disable 2GHz HT20", !!(pBase->opCapFlags.opFlags &
3482 AR5416_OPFLAGS_N_2G_HT20));
3483 PR_EEP("Disable 2GHz HT40", !!(pBase->opCapFlags.opFlags &
3484 AR5416_OPFLAGS_N_2G_HT40));
3485 PR_EEP("Disable 5Ghz HT20", !!(pBase->opCapFlags.opFlags &
3486 AR5416_OPFLAGS_N_5G_HT20));
3487 PR_EEP("Disable 5Ghz HT40", !!(pBase->opCapFlags.opFlags &
3488 AR5416_OPFLAGS_N_5G_HT40));
3489 PR_EEP("Big Endian", !!(pBase->opCapFlags.eepMisc & 0x01));
3490 PR_EEP("RF Silent", pBase->rfSilent);
3491 PR_EEP("BT option", pBase->blueToothOptions);
3492 PR_EEP("Device Cap", pBase->deviceCap);
3493 PR_EEP("Device Type", pBase->deviceType);
3494 PR_EEP("Power Table Offset", pBase->pwrTableOffset);
3495 PR_EEP("Tuning Caps1", pBase->params_for_tuning_caps[0]);
3496 PR_EEP("Tuning Caps2", pBase->params_for_tuning_caps[1]);
3497 PR_EEP("Enable Tx Temp Comp", !!(pBase->featureEnable & BIT(0)));
3498 PR_EEP("Enable Tx Volt Comp", !!(pBase->featureEnable & BIT(1)));
3499 PR_EEP("Enable fast clock", !!(pBase->featureEnable & BIT(2)));
3500 PR_EEP("Enable doubling", !!(pBase->featureEnable & BIT(3)));
3501 PR_EEP("Internal regulator", !!(pBase->featureEnable & BIT(4)));
3502 PR_EEP("Enable Paprd", !!(pBase->featureEnable & BIT(5)));
3503 PR_EEP("Driver Strength", !!(pBase->miscConfiguration & BIT(0)));
3504 PR_EEP("Chain mask Reduce", (pBase->miscConfiguration >> 0x3) & 0x1);
3505 PR_EEP("Write enable Gpio", pBase->eepromWriteEnableGpio);
3506 PR_EEP("WLAN Disable Gpio", pBase->wlanDisableGpio);
3507 PR_EEP("WLAN LED Gpio", pBase->wlanLedGpio);
3508 PR_EEP("Rx Band Select Gpio", pBase->rxBandSelectGpio);
3509 PR_EEP("Tx Gain", pBase->txrxgain >> 4);
3510 PR_EEP("Rx Gain", pBase->txrxgain & 0xf);
3511 PR_EEP("SW Reg", le32_to_cpu(pBase->swreg));
3513 len += snprintf(buf + len, size - len, "%20s : %pM\n", "MacAddress",
3514 ah->eeprom.ar9300_eep.macAddr);
3522 static u32 ath9k_hw_ar9003_dump_eeprom(struct ath_hw *ah, bool dump_base_hdr,
3523 u8 *buf, u32 len, u32 size)
3529 /* XXX: review hardware docs */
3530 static int ath9k_hw_ar9300_get_eeprom_ver(struct ath_hw *ah)
3532 return ah->eeprom.ar9300_eep.eepromVersion;
3535 /* XXX: could be read from the eepromVersion, not sure yet */
3536 static int ath9k_hw_ar9300_get_eeprom_rev(struct ath_hw *ah)
3541 static s32 ar9003_hw_xpa_bias_level_get(struct ath_hw *ah, bool is2ghz)
3543 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3546 return eep->modalHeader2G.xpaBiasLvl;
3548 return eep->modalHeader5G.xpaBiasLvl;
3551 static void ar9003_hw_xpa_bias_level_apply(struct ath_hw *ah, bool is2ghz)
3553 int bias = ar9003_hw_xpa_bias_level_get(ah, is2ghz);
3555 if (AR_SREV_9485(ah) || AR_SREV_9330(ah) || AR_SREV_9340(ah))
3556 REG_RMW_FIELD(ah, AR_CH0_TOP2, AR_CH0_TOP2_XPABIASLVL, bias);
3557 else if (AR_SREV_9480(ah))
3558 REG_RMW_FIELD(ah, AR_CH0_TOP, AR_CH0_TOP_XPABIASLVL, bias);
3560 REG_RMW_FIELD(ah, AR_CH0_TOP, AR_CH0_TOP_XPABIASLVL, bias);
3561 REG_RMW_FIELD(ah, AR_CH0_THERM,
3562 AR_CH0_THERM_XPABIASLVL_MSB,
3564 REG_RMW_FIELD(ah, AR_CH0_THERM,
3565 AR_CH0_THERM_XPASHORT2GND, 1);
3569 static u16 ar9003_switch_com_spdt_get(struct ath_hw *ah, bool is_2ghz)
3571 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3575 val = eep->modalHeader2G.switchcomspdt;
3577 val = eep->modalHeader5G.switchcomspdt;
3578 return le32_to_cpu(val);
3582 static u32 ar9003_hw_ant_ctrl_common_get(struct ath_hw *ah, bool is2ghz)
3584 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3588 val = eep->modalHeader2G.antCtrlCommon;
3590 val = eep->modalHeader5G.antCtrlCommon;
3591 return le32_to_cpu(val);
3594 static u32 ar9003_hw_ant_ctrl_common_2_get(struct ath_hw *ah, bool is2ghz)
3596 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3600 val = eep->modalHeader2G.antCtrlCommon2;
3602 val = eep->modalHeader5G.antCtrlCommon2;
3603 return le32_to_cpu(val);
3606 static u16 ar9003_hw_ant_ctrl_chain_get(struct ath_hw *ah,
3610 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3613 if (chain >= 0 && chain < AR9300_MAX_CHAINS) {
3615 val = eep->modalHeader2G.antCtrlChain[chain];
3617 val = eep->modalHeader5G.antCtrlChain[chain];
3620 return le16_to_cpu(val);
3623 static void ar9003_hw_ant_ctrl_apply(struct ath_hw *ah, bool is2ghz)
3628 static const u32 switch_chain_reg[AR9300_MAX_CHAINS] = {
3629 AR_PHY_SWITCH_CHAIN_0,
3630 AR_PHY_SWITCH_CHAIN_1,
3631 AR_PHY_SWITCH_CHAIN_2,
3634 u32 value = ar9003_hw_ant_ctrl_common_get(ah, is2ghz);
3636 if (AR_SREV_9480(ah)) {
3637 if (AR_SREV_9480_10(ah)) {
3638 value &= ~AR_SWITCH_TABLE_COM_SPDT;
3639 value |= 0x00100000;
3641 REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM,
3642 AR_SWITCH_TABLE_COM_AR9480_ALL, value);
3644 REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM,
3645 AR_SWITCH_TABLE_COM_ALL, value);
3649 * AR9480 defines new switch table for BT/WLAN,
3650 * here's new field name in XXX.ref for both 2G and 5G.
3651 * Register: [GLB_CONTROL] GLB_CONTROL (@0x20044)
3652 * 15:12 R/W SWITCH_TABLE_COM_SPDT_WLAN_RX
3653 * SWITCH_TABLE_COM_SPDT_WLAN_RX
3655 * 11:8 R/W SWITCH_TABLE_COM_SPDT_WLAN_TX
3656 * SWITCH_TABLE_COM_SPDT_WLAN_TX
3658 * 7:4 R/W SWITCH_TABLE_COM_SPDT_WLAN_IDLE
3659 * SWITCH_TABLE_COM_SPDT_WLAN_IDLE
3661 if (AR_SREV_9480_20_OR_LATER(ah)) {
3662 value = ar9003_switch_com_spdt_get(ah, is2ghz);
3663 REG_RMW_FIELD(ah, AR_PHY_GLB_CONTROL,
3664 AR_SWITCH_TABLE_COM_SPDT_ALL, value);
3667 value = ar9003_hw_ant_ctrl_common_2_get(ah, is2ghz);
3668 REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM_2, AR_SWITCH_TABLE_COM2_ALL, value);
3670 for (chain = 0; chain < AR9300_MAX_CHAINS; chain++) {
3671 if ((ah->rxchainmask & BIT(chain)) ||
3672 (ah->txchainmask & BIT(chain))) {
3673 value = ar9003_hw_ant_ctrl_chain_get(ah, chain,
3675 REG_RMW_FIELD(ah, switch_chain_reg[chain],
3676 AR_SWITCH_TABLE_ALL, value);
3680 if (AR_SREV_9330(ah) || AR_SREV_9485(ah)) {
3681 value = ath9k_hw_ar9300_get_eeprom(ah, EEP_ANT_DIV_CTL1);
3683 * main_lnaconf, alt_lnaconf, main_tb, alt_tb
3684 * are the fields present
3686 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
3687 regval &= (~AR_ANT_DIV_CTRL_ALL);
3688 regval |= (value & 0x3f) << AR_ANT_DIV_CTRL_ALL_S;
3690 regval &= (~AR_PHY_9485_ANT_DIV_LNADIV);
3691 regval |= ((value >> 6) & 0x1) <<
3692 AR_PHY_9485_ANT_DIV_LNADIV_S;
3693 REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
3695 /*enable fast_div */
3696 regval = REG_READ(ah, AR_PHY_CCK_DETECT);
3697 regval &= (~AR_FAST_DIV_ENABLE);
3698 regval |= ((value >> 7) & 0x1) <<
3699 AR_FAST_DIV_ENABLE_S;
3700 REG_WRITE(ah, AR_PHY_CCK_DETECT, regval);
3702 ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
3703 /* check whether antenna diversity is enabled */
3704 if ((ant_div_ctl1 >> 0x6) == 0x3) {
3705 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
3707 * clear bits 25-30 main_lnaconf, alt_lnaconf,
3710 regval &= (~(AR_PHY_9485_ANT_DIV_MAIN_LNACONF |
3711 AR_PHY_9485_ANT_DIV_ALT_LNACONF |
3712 AR_PHY_9485_ANT_DIV_ALT_GAINTB |
3713 AR_PHY_9485_ANT_DIV_MAIN_GAINTB));
3714 /* by default use LNA1 for the main antenna */
3715 regval |= (AR_PHY_9485_ANT_DIV_LNA1 <<
3716 AR_PHY_9485_ANT_DIV_MAIN_LNACONF_S);
3717 regval |= (AR_PHY_9485_ANT_DIV_LNA2 <<
3718 AR_PHY_9485_ANT_DIV_ALT_LNACONF_S);
3719 REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
3727 static void ar9003_hw_drive_strength_apply(struct ath_hw *ah)
3732 drive_strength = ath9k_hw_ar9300_get_eeprom(ah, EEP_DRIVE_STRENGTH);
3734 if (!drive_strength)
3737 reg = REG_READ(ah, AR_PHY_65NM_CH0_BIAS1);
3745 REG_WRITE(ah, AR_PHY_65NM_CH0_BIAS1, reg);
3747 reg = REG_READ(ah, AR_PHY_65NM_CH0_BIAS2);
3758 REG_WRITE(ah, AR_PHY_65NM_CH0_BIAS2, reg);
3760 reg = REG_READ(ah, AR_PHY_65NM_CH0_BIAS4);
3765 REG_WRITE(ah, AR_PHY_65NM_CH0_BIAS4, reg);
3768 static u16 ar9003_hw_atten_chain_get(struct ath_hw *ah, int chain,
3769 struct ath9k_channel *chan)
3773 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3775 if (chain >= 0 && chain < 3) {
3776 if (IS_CHAN_2GHZ(chan))
3777 return eep->modalHeader2G.xatten1DB[chain];
3778 else if (eep->base_ext2.xatten1DBLow[chain] != 0) {
3779 t[0] = eep->base_ext2.xatten1DBLow[chain];
3781 t[1] = eep->modalHeader5G.xatten1DB[chain];
3783 t[2] = eep->base_ext2.xatten1DBHigh[chain];
3785 value = ar9003_hw_power_interpolate((s32) chan->channel,
3789 return eep->modalHeader5G.xatten1DB[chain];
3796 static u16 ar9003_hw_atten_chain_get_margin(struct ath_hw *ah, int chain,
3797 struct ath9k_channel *chan)
3801 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3803 if (chain >= 0 && chain < 3) {
3804 if (IS_CHAN_2GHZ(chan))
3805 return eep->modalHeader2G.xatten1Margin[chain];
3806 else if (eep->base_ext2.xatten1MarginLow[chain] != 0) {
3807 t[0] = eep->base_ext2.xatten1MarginLow[chain];
3809 t[1] = eep->modalHeader5G.xatten1Margin[chain];
3811 t[2] = eep->base_ext2.xatten1MarginHigh[chain];
3813 value = ar9003_hw_power_interpolate((s32) chan->channel,
3817 return eep->modalHeader5G.xatten1Margin[chain];
3823 static void ar9003_hw_atten_apply(struct ath_hw *ah, struct ath9k_channel *chan)
3827 unsigned long ext_atten_reg[3] = {AR_PHY_EXT_ATTEN_CTL_0,
3828 AR_PHY_EXT_ATTEN_CTL_1,
3829 AR_PHY_EXT_ATTEN_CTL_2,
3832 /* Test value. if 0 then attenuation is unused. Don't load anything. */
3833 for (i = 0; i < 3; i++) {
3834 if (ah->txchainmask & BIT(i)) {
3835 value = ar9003_hw_atten_chain_get(ah, i, chan);
3836 REG_RMW_FIELD(ah, ext_atten_reg[i],
3837 AR_PHY_EXT_ATTEN_CTL_XATTEN1_DB, value);
3839 value = ar9003_hw_atten_chain_get_margin(ah, i, chan);
3840 REG_RMW_FIELD(ah, ext_atten_reg[i],
3841 AR_PHY_EXT_ATTEN_CTL_XATTEN1_MARGIN,
3847 static bool is_pmu_set(struct ath_hw *ah, u32 pmu_reg, int pmu_set)
3851 while (pmu_set != REG_READ(ah, pmu_reg)) {
3854 REG_WRITE(ah, pmu_reg, pmu_set);
3861 static void ar9003_hw_internal_regulator_apply(struct ath_hw *ah)
3863 int internal_regulator =
3864 ath9k_hw_ar9300_get_eeprom(ah, EEP_INTERNAL_REGULATOR);
3867 if (internal_regulator) {
3868 if (AR_SREV_9330(ah) || AR_SREV_9485(ah)) {
3871 reg_pmu_set = REG_READ(ah, AR_PHY_PMU2) & ~AR_PHY_PMU2_PGM;
3872 REG_WRITE(ah, AR_PHY_PMU2, reg_pmu_set);
3873 if (!is_pmu_set(ah, AR_PHY_PMU2, reg_pmu_set))
3876 if (AR_SREV_9330(ah)) {
3877 if (ah->is_clk_25mhz) {
3878 reg_pmu_set = (3 << 1) | (8 << 4) |
3879 (3 << 8) | (1 << 14) |
3880 (6 << 17) | (1 << 20) |
3883 reg_pmu_set = (4 << 1) | (7 << 4) |
3884 (3 << 8) | (1 << 14) |
3885 (6 << 17) | (1 << 20) |
3889 reg_pmu_set = (5 << 1) | (7 << 4) |
3890 (2 << 8) | (2 << 14) |
3891 (6 << 17) | (1 << 20) |
3892 (3 << 24) | (1 << 28);
3895 REG_WRITE(ah, AR_PHY_PMU1, reg_pmu_set);
3896 if (!is_pmu_set(ah, AR_PHY_PMU1, reg_pmu_set))
3899 reg_pmu_set = (REG_READ(ah, AR_PHY_PMU2) & ~0xFFC00000)
3901 REG_WRITE(ah, AR_PHY_PMU2, reg_pmu_set);
3902 if (!is_pmu_set(ah, AR_PHY_PMU2, reg_pmu_set))
3905 reg_pmu_set = (REG_READ(ah, AR_PHY_PMU2) & ~0x00200000)
3907 REG_WRITE(ah, AR_PHY_PMU2, reg_pmu_set);
3908 if (!is_pmu_set(ah, AR_PHY_PMU2, reg_pmu_set))
3910 } else if (AR_SREV_9480(ah)) {
3911 reg_val = ath9k_hw_ar9300_get_eeprom(ah, EEP_SWREG);
3912 REG_WRITE(ah, AR_PHY_PMU1, reg_val);
3914 /* Internal regulator is ON. Write swreg register. */
3915 reg_val = ath9k_hw_ar9300_get_eeprom(ah, EEP_SWREG);
3916 REG_WRITE(ah, AR_RTC_REG_CONTROL1,
3917 REG_READ(ah, AR_RTC_REG_CONTROL1) &
3918 (~AR_RTC_REG_CONTROL1_SWREG_PROGRAM));
3919 REG_WRITE(ah, AR_RTC_REG_CONTROL0, reg_val);
3920 /* Set REG_CONTROL1.SWREG_PROGRAM */
3921 REG_WRITE(ah, AR_RTC_REG_CONTROL1,
3923 AR_RTC_REG_CONTROL1) |
3924 AR_RTC_REG_CONTROL1_SWREG_PROGRAM);
3927 if (AR_SREV_9330(ah) || AR_SREV_9485(ah)) {
3928 REG_RMW_FIELD(ah, AR_PHY_PMU2, AR_PHY_PMU2_PGM, 0);
3929 while (REG_READ_FIELD(ah, AR_PHY_PMU2,
3933 REG_RMW_FIELD(ah, AR_PHY_PMU1, AR_PHY_PMU1_PWD, 0x1);
3934 while (!REG_READ_FIELD(ah, AR_PHY_PMU1,
3937 REG_RMW_FIELD(ah, AR_PHY_PMU2, AR_PHY_PMU2_PGM, 0x1);
3938 while (!REG_READ_FIELD(ah, AR_PHY_PMU2,
3941 } else if (AR_SREV_9480(ah))
3942 REG_RMW_FIELD(ah, AR_PHY_PMU1, AR_PHY_PMU1_PWD, 0x1);
3944 reg_val = REG_READ(ah, AR_RTC_SLEEP_CLK) |
3945 AR_RTC_FORCE_SWREG_PRD;
3946 REG_WRITE(ah, AR_RTC_SLEEP_CLK, reg_val);
3952 static void ar9003_hw_apply_tuning_caps(struct ath_hw *ah)
3954 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3955 u8 tuning_caps_param = eep->baseEepHeader.params_for_tuning_caps[0];
3957 if (eep->baseEepHeader.featureEnable & 0x40) {
3958 tuning_caps_param &= 0x7f;
3959 REG_RMW_FIELD(ah, AR_CH0_XTAL, AR_CH0_XTAL_CAPINDAC,
3961 REG_RMW_FIELD(ah, AR_CH0_XTAL, AR_CH0_XTAL_CAPOUTDAC,
3966 static void ath9k_hw_ar9300_set_board_values(struct ath_hw *ah,
3967 struct ath9k_channel *chan)
3969 ar9003_hw_xpa_bias_level_apply(ah, IS_CHAN_2GHZ(chan));
3970 ar9003_hw_ant_ctrl_apply(ah, IS_CHAN_2GHZ(chan));
3971 ar9003_hw_drive_strength_apply(ah);
3972 ar9003_hw_atten_apply(ah, chan);
3973 if (!AR_SREV_9330(ah) && !AR_SREV_9340(ah))
3974 ar9003_hw_internal_regulator_apply(ah);
3975 if (AR_SREV_9485(ah) || AR_SREV_9330(ah) || AR_SREV_9340(ah))
3976 ar9003_hw_apply_tuning_caps(ah);
3979 static void ath9k_hw_ar9300_set_addac(struct ath_hw *ah,
3980 struct ath9k_channel *chan)
3985 * Returns the interpolated y value corresponding to the specified x value
3986 * from the np ordered pairs of data (px,py).
3987 * The pairs do not have to be in any order.
3988 * If the specified x value is less than any of the px,
3989 * the returned y value is equal to the py for the lowest px.
3990 * If the specified x value is greater than any of the px,
3991 * the returned y value is equal to the py for the highest px.
3993 static int ar9003_hw_power_interpolate(int32_t x,
3994 int32_t *px, int32_t *py, u_int16_t np)
3997 int lx = 0, ly = 0, lhave = 0;
3998 int hx = 0, hy = 0, hhave = 0;
4005 /* identify best lower and higher x calibration measurement */
4006 for (ip = 0; ip < np; ip++) {
4009 /* this measurement is higher than our desired x */
4011 if (!hhave || dx > (x - hx)) {
4012 /* new best higher x measurement */
4018 /* this measurement is lower than our desired x */
4020 if (!lhave || dx < (x - lx)) {
4021 /* new best lower x measurement */
4029 /* the low x is good */
4031 /* so is the high x */
4033 /* they're the same, so just pick one */
4036 else /* interpolate */
4037 y = interpolate(x, lx, hx, ly, hy);
4038 } else /* only low is good, use it */
4040 } else if (hhave) /* only high is good, use it */
4042 else /* nothing is good,this should never happen unless np=0, ???? */
4047 static u8 ar9003_hw_eeprom_get_tgt_pwr(struct ath_hw *ah,
4048 u16 rateIndex, u16 freq, bool is2GHz)
4051 s32 targetPowerArray[AR9300_NUM_5G_20_TARGET_POWERS];
4052 s32 freqArray[AR9300_NUM_5G_20_TARGET_POWERS];
4053 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
4054 struct cal_tgt_pow_legacy *pEepromTargetPwr;
4058 numPiers = AR9300_NUM_2G_20_TARGET_POWERS;
4059 pEepromTargetPwr = eep->calTargetPower2G;
4060 pFreqBin = eep->calTarget_freqbin_2G;
4062 numPiers = AR9300_NUM_5G_20_TARGET_POWERS;
4063 pEepromTargetPwr = eep->calTargetPower5G;
4064 pFreqBin = eep->calTarget_freqbin_5G;
4068 * create array of channels and targetpower from
4069 * targetpower piers stored on eeprom
4071 for (i = 0; i < numPiers; i++) {
4072 freqArray[i] = FBIN2FREQ(pFreqBin[i], is2GHz);
4073 targetPowerArray[i] = pEepromTargetPwr[i].tPow2x[rateIndex];
4076 /* interpolate to get target power for given frequency */
4077 return (u8) ar9003_hw_power_interpolate((s32) freq,
4079 targetPowerArray, numPiers);
4082 static u8 ar9003_hw_eeprom_get_ht20_tgt_pwr(struct ath_hw *ah,
4084 u16 freq, bool is2GHz)
4087 s32 targetPowerArray[AR9300_NUM_5G_20_TARGET_POWERS];
4088 s32 freqArray[AR9300_NUM_5G_20_TARGET_POWERS];
4089 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
4090 struct cal_tgt_pow_ht *pEepromTargetPwr;
4094 numPiers = AR9300_NUM_2G_20_TARGET_POWERS;
4095 pEepromTargetPwr = eep->calTargetPower2GHT20;
4096 pFreqBin = eep->calTarget_freqbin_2GHT20;
4098 numPiers = AR9300_NUM_5G_20_TARGET_POWERS;
4099 pEepromTargetPwr = eep->calTargetPower5GHT20;
4100 pFreqBin = eep->calTarget_freqbin_5GHT20;
4104 * create array of channels and targetpower
4105 * from targetpower piers stored on eeprom
4107 for (i = 0; i < numPiers; i++) {
4108 freqArray[i] = FBIN2FREQ(pFreqBin[i], is2GHz);
4109 targetPowerArray[i] = pEepromTargetPwr[i].tPow2x[rateIndex];
4112 /* interpolate to get target power for given frequency */
4113 return (u8) ar9003_hw_power_interpolate((s32) freq,
4115 targetPowerArray, numPiers);
4118 static u8 ar9003_hw_eeprom_get_ht40_tgt_pwr(struct ath_hw *ah,
4120 u16 freq, bool is2GHz)
4123 s32 targetPowerArray[AR9300_NUM_5G_40_TARGET_POWERS];
4124 s32 freqArray[AR9300_NUM_5G_40_TARGET_POWERS];
4125 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
4126 struct cal_tgt_pow_ht *pEepromTargetPwr;
4130 numPiers = AR9300_NUM_2G_40_TARGET_POWERS;
4131 pEepromTargetPwr = eep->calTargetPower2GHT40;
4132 pFreqBin = eep->calTarget_freqbin_2GHT40;
4134 numPiers = AR9300_NUM_5G_40_TARGET_POWERS;
4135 pEepromTargetPwr = eep->calTargetPower5GHT40;
4136 pFreqBin = eep->calTarget_freqbin_5GHT40;
4140 * create array of channels and targetpower from
4141 * targetpower piers stored on eeprom
4143 for (i = 0; i < numPiers; i++) {
4144 freqArray[i] = FBIN2FREQ(pFreqBin[i], is2GHz);
4145 targetPowerArray[i] = pEepromTargetPwr[i].tPow2x[rateIndex];
4148 /* interpolate to get target power for given frequency */
4149 return (u8) ar9003_hw_power_interpolate((s32) freq,
4151 targetPowerArray, numPiers);
4154 static u8 ar9003_hw_eeprom_get_cck_tgt_pwr(struct ath_hw *ah,
4155 u16 rateIndex, u16 freq)
4157 u16 numPiers = AR9300_NUM_2G_CCK_TARGET_POWERS, i;
4158 s32 targetPowerArray[AR9300_NUM_2G_CCK_TARGET_POWERS];
4159 s32 freqArray[AR9300_NUM_2G_CCK_TARGET_POWERS];
4160 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
4161 struct cal_tgt_pow_legacy *pEepromTargetPwr = eep->calTargetPowerCck;
4162 u8 *pFreqBin = eep->calTarget_freqbin_Cck;
4165 * create array of channels and targetpower from
4166 * targetpower piers stored on eeprom
4168 for (i = 0; i < numPiers; i++) {
4169 freqArray[i] = FBIN2FREQ(pFreqBin[i], 1);
4170 targetPowerArray[i] = pEepromTargetPwr[i].tPow2x[rateIndex];
4173 /* interpolate to get target power for given frequency */
4174 return (u8) ar9003_hw_power_interpolate((s32) freq,
4176 targetPowerArray, numPiers);
4179 /* Set tx power registers to array of values passed in */
4180 static int ar9003_hw_tx_power_regwrite(struct ath_hw *ah, u8 * pPwrArray)
4182 #define POW_SM(_r, _s) (((_r) & 0x3f) << (_s))
4183 /* make sure forced gain is not set */
4184 REG_WRITE(ah, AR_PHY_TX_FORCED_GAIN, 0);
4186 /* Write the OFDM power per rate set */
4188 /* 6 (LSB), 9, 12, 18 (MSB) */
4189 REG_WRITE(ah, AR_PHY_POWER_TX_RATE(0),
4190 POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 24) |
4191 POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 16) |
4192 POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 8) |
4193 POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 0));
4195 /* 24 (LSB), 36, 48, 54 (MSB) */
4196 REG_WRITE(ah, AR_PHY_POWER_TX_RATE(1),
4197 POW_SM(pPwrArray[ALL_TARGET_LEGACY_54], 24) |
4198 POW_SM(pPwrArray[ALL_TARGET_LEGACY_48], 16) |
4199 POW_SM(pPwrArray[ALL_TARGET_LEGACY_36], 8) |
4200 POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 0));
4202 /* Write the CCK power per rate set */
4204 /* 1L (LSB), reserved, 2L, 2S (MSB) */
4205 REG_WRITE(ah, AR_PHY_POWER_TX_RATE(2),
4206 POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 24) |
4207 POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 16) |
4208 /* POW_SM(txPowerTimes2, 8) | this is reserved for AR9003 */
4209 POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 0));
4211 /* 5.5L (LSB), 5.5S, 11L, 11S (MSB) */
4212 REG_WRITE(ah, AR_PHY_POWER_TX_RATE(3),
4213 POW_SM(pPwrArray[ALL_TARGET_LEGACY_11S], 24) |
4214 POW_SM(pPwrArray[ALL_TARGET_LEGACY_11L], 16) |
4215 POW_SM(pPwrArray[ALL_TARGET_LEGACY_5S], 8) |
4216 POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 0)
4219 /* Write the power for duplicated frames - HT40 */
4221 /* dup40_cck (LSB), dup40_ofdm, ext20_cck, ext20_ofdm (MSB) */
4222 REG_WRITE(ah, AR_PHY_POWER_TX_RATE(8),
4223 POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 24) |
4224 POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 16) |
4225 POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 8) |
4226 POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 0)
4229 /* Write the HT20 power per rate set */
4231 /* 0/8/16 (LSB), 1-3/9-11/17-19, 4, 5 (MSB) */
4232 REG_WRITE(ah, AR_PHY_POWER_TX_RATE(4),
4233 POW_SM(pPwrArray[ALL_TARGET_HT20_5], 24) |
4234 POW_SM(pPwrArray[ALL_TARGET_HT20_4], 16) |
4235 POW_SM(pPwrArray[ALL_TARGET_HT20_1_3_9_11_17_19], 8) |
4236 POW_SM(pPwrArray[ALL_TARGET_HT20_0_8_16], 0)
4239 /* 6 (LSB), 7, 12, 13 (MSB) */
4240 REG_WRITE(ah, AR_PHY_POWER_TX_RATE(5),
4241 POW_SM(pPwrArray[ALL_TARGET_HT20_13], 24) |
4242 POW_SM(pPwrArray[ALL_TARGET_HT20_12], 16) |
4243 POW_SM(pPwrArray[ALL_TARGET_HT20_7], 8) |
4244 POW_SM(pPwrArray[ALL_TARGET_HT20_6], 0)
4247 /* 14 (LSB), 15, 20, 21 */
4248 REG_WRITE(ah, AR_PHY_POWER_TX_RATE(9),
4249 POW_SM(pPwrArray[ALL_TARGET_HT20_21], 24) |
4250 POW_SM(pPwrArray[ALL_TARGET_HT20_20], 16) |
4251 POW_SM(pPwrArray[ALL_TARGET_HT20_15], 8) |
4252 POW_SM(pPwrArray[ALL_TARGET_HT20_14], 0)
4255 /* Mixed HT20 and HT40 rates */
4257 /* HT20 22 (LSB), HT20 23, HT40 22, HT40 23 (MSB) */
4258 REG_WRITE(ah, AR_PHY_POWER_TX_RATE(10),
4259 POW_SM(pPwrArray[ALL_TARGET_HT40_23], 24) |
4260 POW_SM(pPwrArray[ALL_TARGET_HT40_22], 16) |
4261 POW_SM(pPwrArray[ALL_TARGET_HT20_23], 8) |
4262 POW_SM(pPwrArray[ALL_TARGET_HT20_22], 0)
4266 * Write the HT40 power per rate set
4267 * correct PAR difference between HT40 and HT20/LEGACY
4268 * 0/8/16 (LSB), 1-3/9-11/17-19, 4, 5 (MSB)
4270 REG_WRITE(ah, AR_PHY_POWER_TX_RATE(6),
4271 POW_SM(pPwrArray[ALL_TARGET_HT40_5], 24) |
4272 POW_SM(pPwrArray[ALL_TARGET_HT40_4], 16) |
4273 POW_SM(pPwrArray[ALL_TARGET_HT40_1_3_9_11_17_19], 8) |
4274 POW_SM(pPwrArray[ALL_TARGET_HT40_0_8_16], 0)
4277 /* 6 (LSB), 7, 12, 13 (MSB) */
4278 REG_WRITE(ah, AR_PHY_POWER_TX_RATE(7),
4279 POW_SM(pPwrArray[ALL_TARGET_HT40_13], 24) |
4280 POW_SM(pPwrArray[ALL_TARGET_HT40_12], 16) |
4281 POW_SM(pPwrArray[ALL_TARGET_HT40_7], 8) |
4282 POW_SM(pPwrArray[ALL_TARGET_HT40_6], 0)
4285 /* 14 (LSB), 15, 20, 21 */
4286 REG_WRITE(ah, AR_PHY_POWER_TX_RATE(11),
4287 POW_SM(pPwrArray[ALL_TARGET_HT40_21], 24) |
4288 POW_SM(pPwrArray[ALL_TARGET_HT40_20], 16) |
4289 POW_SM(pPwrArray[ALL_TARGET_HT40_15], 8) |
4290 POW_SM(pPwrArray[ALL_TARGET_HT40_14], 0)
4297 static void ar9003_hw_set_target_power_eeprom(struct ath_hw *ah, u16 freq,
4298 u8 *targetPowerValT2)
4300 /* XXX: hard code for now, need to get from eeprom struct */
4301 u8 ht40PowerIncForPdadc = 0;
4302 bool is2GHz = false;
4304 struct ath_common *common = ath9k_hw_common(ah);
4309 targetPowerValT2[ALL_TARGET_LEGACY_6_24] =
4310 ar9003_hw_eeprom_get_tgt_pwr(ah, LEGACY_TARGET_RATE_6_24, freq,
4312 targetPowerValT2[ALL_TARGET_LEGACY_36] =
4313 ar9003_hw_eeprom_get_tgt_pwr(ah, LEGACY_TARGET_RATE_36, freq,
4315 targetPowerValT2[ALL_TARGET_LEGACY_48] =
4316 ar9003_hw_eeprom_get_tgt_pwr(ah, LEGACY_TARGET_RATE_48, freq,
4318 targetPowerValT2[ALL_TARGET_LEGACY_54] =
4319 ar9003_hw_eeprom_get_tgt_pwr(ah, LEGACY_TARGET_RATE_54, freq,
4321 targetPowerValT2[ALL_TARGET_LEGACY_1L_5L] =
4322 ar9003_hw_eeprom_get_cck_tgt_pwr(ah, LEGACY_TARGET_RATE_1L_5L,
4324 targetPowerValT2[ALL_TARGET_LEGACY_5S] =
4325 ar9003_hw_eeprom_get_cck_tgt_pwr(ah, LEGACY_TARGET_RATE_5S, freq);
4326 targetPowerValT2[ALL_TARGET_LEGACY_11L] =
4327 ar9003_hw_eeprom_get_cck_tgt_pwr(ah, LEGACY_TARGET_RATE_11L, freq);
4328 targetPowerValT2[ALL_TARGET_LEGACY_11S] =
4329 ar9003_hw_eeprom_get_cck_tgt_pwr(ah, LEGACY_TARGET_RATE_11S, freq);
4330 targetPowerValT2[ALL_TARGET_HT20_0_8_16] =
4331 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_0_8_16, freq,
4333 targetPowerValT2[ALL_TARGET_HT20_1_3_9_11_17_19] =
4334 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_1_3_9_11_17_19,
4336 targetPowerValT2[ALL_TARGET_HT20_4] =
4337 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_4, freq,
4339 targetPowerValT2[ALL_TARGET_HT20_5] =
4340 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_5, freq,
4342 targetPowerValT2[ALL_TARGET_HT20_6] =
4343 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_6, freq,
4345 targetPowerValT2[ALL_TARGET_HT20_7] =
4346 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_7, freq,
4348 targetPowerValT2[ALL_TARGET_HT20_12] =
4349 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_12, freq,
4351 targetPowerValT2[ALL_TARGET_HT20_13] =
4352 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_13, freq,
4354 targetPowerValT2[ALL_TARGET_HT20_14] =
4355 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_14, freq,
4357 targetPowerValT2[ALL_TARGET_HT20_15] =
4358 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_15, freq,
4360 targetPowerValT2[ALL_TARGET_HT20_20] =
4361 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_20, freq,
4363 targetPowerValT2[ALL_TARGET_HT20_21] =
4364 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_21, freq,
4366 targetPowerValT2[ALL_TARGET_HT20_22] =
4367 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_22, freq,
4369 targetPowerValT2[ALL_TARGET_HT20_23] =
4370 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_23, freq,
4372 targetPowerValT2[ALL_TARGET_HT40_0_8_16] =
4373 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_0_8_16, freq,
4374 is2GHz) + ht40PowerIncForPdadc;
4375 targetPowerValT2[ALL_TARGET_HT40_1_3_9_11_17_19] =
4376 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_1_3_9_11_17_19,
4378 is2GHz) + ht40PowerIncForPdadc;
4379 targetPowerValT2[ALL_TARGET_HT40_4] =
4380 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_4, freq,
4381 is2GHz) + ht40PowerIncForPdadc;
4382 targetPowerValT2[ALL_TARGET_HT40_5] =
4383 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_5, freq,
4384 is2GHz) + ht40PowerIncForPdadc;
4385 targetPowerValT2[ALL_TARGET_HT40_6] =
4386 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_6, freq,
4387 is2GHz) + ht40PowerIncForPdadc;
4388 targetPowerValT2[ALL_TARGET_HT40_7] =
4389 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_7, freq,
4390 is2GHz) + ht40PowerIncForPdadc;
4391 targetPowerValT2[ALL_TARGET_HT40_12] =
4392 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_12, freq,
4393 is2GHz) + ht40PowerIncForPdadc;
4394 targetPowerValT2[ALL_TARGET_HT40_13] =
4395 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_13, freq,
4396 is2GHz) + ht40PowerIncForPdadc;
4397 targetPowerValT2[ALL_TARGET_HT40_14] =
4398 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_14, freq,
4399 is2GHz) + ht40PowerIncForPdadc;
4400 targetPowerValT2[ALL_TARGET_HT40_15] =
4401 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_15, freq,
4402 is2GHz) + ht40PowerIncForPdadc;
4403 targetPowerValT2[ALL_TARGET_HT40_20] =
4404 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_20, freq,
4405 is2GHz) + ht40PowerIncForPdadc;
4406 targetPowerValT2[ALL_TARGET_HT40_21] =
4407 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_21, freq,
4408 is2GHz) + ht40PowerIncForPdadc;
4409 targetPowerValT2[ALL_TARGET_HT40_22] =
4410 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_22, freq,
4411 is2GHz) + ht40PowerIncForPdadc;
4412 targetPowerValT2[ALL_TARGET_HT40_23] =
4413 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_23, freq,
4414 is2GHz) + ht40PowerIncForPdadc;
4416 for (i = 0; i < ar9300RateSize; i++) {
4417 ath_dbg(common, ATH_DBG_EEPROM,
4418 "TPC[%02d] 0x%08x\n", i, targetPowerValT2[i]);
4422 static int ar9003_hw_cal_pier_get(struct ath_hw *ah,
4428 int *ptemperature, int *pvoltage)
4431 struct ar9300_cal_data_per_freq_op_loop *pCalPierStruct;
4433 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
4434 struct ath_common *common = ath9k_hw_common(ah);
4436 if (ichain >= AR9300_MAX_CHAINS) {
4437 ath_dbg(common, ATH_DBG_EEPROM,
4438 "Invalid chain index, must be less than %d\n",
4443 if (mode) { /* 5GHz */
4444 if (ipier >= AR9300_NUM_5G_CAL_PIERS) {
4445 ath_dbg(common, ATH_DBG_EEPROM,
4446 "Invalid 5GHz cal pier index, must be less than %d\n",
4447 AR9300_NUM_5G_CAL_PIERS);
4450 pCalPier = &(eep->calFreqPier5G[ipier]);
4451 pCalPierStruct = &(eep->calPierData5G[ichain][ipier]);
4454 if (ipier >= AR9300_NUM_2G_CAL_PIERS) {
4455 ath_dbg(common, ATH_DBG_EEPROM,
4456 "Invalid 2GHz cal pier index, must be less than %d\n",
4457 AR9300_NUM_2G_CAL_PIERS);
4461 pCalPier = &(eep->calFreqPier2G[ipier]);
4462 pCalPierStruct = &(eep->calPierData2G[ichain][ipier]);
4466 *pfrequency = FBIN2FREQ(*pCalPier, is2GHz);
4467 *pcorrection = pCalPierStruct->refPower;
4468 *ptemperature = pCalPierStruct->tempMeas;
4469 *pvoltage = pCalPierStruct->voltMeas;
4474 static int ar9003_hw_power_control_override(struct ath_hw *ah,
4477 int *voltage, int *temperature)
4480 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
4483 REG_RMW(ah, AR_PHY_TPC_11_B0,
4484 (correction[0] << AR_PHY_TPC_OLPC_GAIN_DELTA_S),
4485 AR_PHY_TPC_OLPC_GAIN_DELTA);
4486 if (ah->caps.tx_chainmask & BIT(1))
4487 REG_RMW(ah, AR_PHY_TPC_11_B1,
4488 (correction[1] << AR_PHY_TPC_OLPC_GAIN_DELTA_S),
4489 AR_PHY_TPC_OLPC_GAIN_DELTA);
4490 if (ah->caps.tx_chainmask & BIT(2))
4491 REG_RMW(ah, AR_PHY_TPC_11_B2,
4492 (correction[2] << AR_PHY_TPC_OLPC_GAIN_DELTA_S),
4493 AR_PHY_TPC_OLPC_GAIN_DELTA);
4495 /* enable open loop power control on chip */
4496 REG_RMW(ah, AR_PHY_TPC_6_B0,
4497 (3 << AR_PHY_TPC_6_ERROR_EST_MODE_S),
4498 AR_PHY_TPC_6_ERROR_EST_MODE);
4499 if (ah->caps.tx_chainmask & BIT(1))
4500 REG_RMW(ah, AR_PHY_TPC_6_B1,
4501 (3 << AR_PHY_TPC_6_ERROR_EST_MODE_S),
4502 AR_PHY_TPC_6_ERROR_EST_MODE);
4503 if (ah->caps.tx_chainmask & BIT(2))
4504 REG_RMW(ah, AR_PHY_TPC_6_B2,
4505 (3 << AR_PHY_TPC_6_ERROR_EST_MODE_S),
4506 AR_PHY_TPC_6_ERROR_EST_MODE);
4509 * enable temperature compensation
4510 * Need to use register names
4512 if (frequency < 4000)
4513 tempSlope = eep->modalHeader2G.tempSlope;
4514 else if (eep->base_ext2.tempSlopeLow != 0) {
4515 t[0] = eep->base_ext2.tempSlopeLow;
4517 t[1] = eep->modalHeader5G.tempSlope;
4519 t[2] = eep->base_ext2.tempSlopeHigh;
4521 tempSlope = ar9003_hw_power_interpolate((s32) frequency,
4524 tempSlope = eep->modalHeader5G.tempSlope;
4526 REG_RMW_FIELD(ah, AR_PHY_TPC_19, AR_PHY_TPC_19_ALPHA_THERM, tempSlope);
4528 if (AR_SREV_9480_20(ah))
4529 REG_RMW_FIELD(ah, AR_PHY_TPC_19_B1,
4530 AR_PHY_TPC_19_B1_ALPHA_THERM, tempSlope);
4533 REG_RMW_FIELD(ah, AR_PHY_TPC_18, AR_PHY_TPC_18_THERM_CAL_VALUE,
4539 /* Apply the recorded correction values. */
4540 static int ar9003_hw_calibration_apply(struct ath_hw *ah, int frequency)
4542 int ichain, ipier, npier;
4544 int lfrequency[AR9300_MAX_CHAINS],
4545 lcorrection[AR9300_MAX_CHAINS],
4546 ltemperature[AR9300_MAX_CHAINS], lvoltage[AR9300_MAX_CHAINS];
4547 int hfrequency[AR9300_MAX_CHAINS],
4548 hcorrection[AR9300_MAX_CHAINS],
4549 htemperature[AR9300_MAX_CHAINS], hvoltage[AR9300_MAX_CHAINS];
4551 int correction[AR9300_MAX_CHAINS],
4552 voltage[AR9300_MAX_CHAINS], temperature[AR9300_MAX_CHAINS];
4553 int pfrequency, pcorrection, ptemperature, pvoltage;
4554 struct ath_common *common = ath9k_hw_common(ah);
4556 mode = (frequency >= 4000);
4558 npier = AR9300_NUM_5G_CAL_PIERS;
4560 npier = AR9300_NUM_2G_CAL_PIERS;
4562 for (ichain = 0; ichain < AR9300_MAX_CHAINS; ichain++) {
4563 lfrequency[ichain] = 0;
4564 hfrequency[ichain] = 100000;
4566 /* identify best lower and higher frequency calibration measurement */
4567 for (ichain = 0; ichain < AR9300_MAX_CHAINS; ichain++) {
4568 for (ipier = 0; ipier < npier; ipier++) {
4569 if (!ar9003_hw_cal_pier_get(ah, mode, ipier, ichain,
4570 &pfrequency, &pcorrection,
4571 &ptemperature, &pvoltage)) {
4572 fdiff = frequency - pfrequency;
4575 * this measurement is higher than
4576 * our desired frequency
4579 if (hfrequency[ichain] <= 0 ||
4580 hfrequency[ichain] >= 100000 ||
4582 (frequency - hfrequency[ichain])) {
4585 * frequency measurement
4587 hfrequency[ichain] = pfrequency;
4588 hcorrection[ichain] =
4590 htemperature[ichain] =
4592 hvoltage[ichain] = pvoltage;
4596 if (lfrequency[ichain] <= 0
4598 (frequency - lfrequency[ichain])) {
4601 * frequency measurement
4603 lfrequency[ichain] = pfrequency;
4604 lcorrection[ichain] =
4606 ltemperature[ichain] =
4608 lvoltage[ichain] = pvoltage;
4616 for (ichain = 0; ichain < AR9300_MAX_CHAINS; ichain++) {
4617 ath_dbg(common, ATH_DBG_EEPROM,
4618 "ch=%d f=%d low=%d %d h=%d %d\n",
4619 ichain, frequency, lfrequency[ichain],
4620 lcorrection[ichain], hfrequency[ichain],
4621 hcorrection[ichain]);
4622 /* they're the same, so just pick one */
4623 if (hfrequency[ichain] == lfrequency[ichain]) {
4624 correction[ichain] = lcorrection[ichain];
4625 voltage[ichain] = lvoltage[ichain];
4626 temperature[ichain] = ltemperature[ichain];
4628 /* the low frequency is good */
4629 else if (frequency - lfrequency[ichain] < 1000) {
4630 /* so is the high frequency, interpolate */
4631 if (hfrequency[ichain] - frequency < 1000) {
4633 correction[ichain] = interpolate(frequency,
4636 lcorrection[ichain],
4637 hcorrection[ichain]);
4639 temperature[ichain] = interpolate(frequency,
4642 ltemperature[ichain],
4643 htemperature[ichain]);
4645 voltage[ichain] = interpolate(frequency,
4651 /* only low is good, use it */
4653 correction[ichain] = lcorrection[ichain];
4654 temperature[ichain] = ltemperature[ichain];
4655 voltage[ichain] = lvoltage[ichain];
4658 /* only high is good, use it */
4659 else if (hfrequency[ichain] - frequency < 1000) {
4660 correction[ichain] = hcorrection[ichain];
4661 temperature[ichain] = htemperature[ichain];
4662 voltage[ichain] = hvoltage[ichain];
4663 } else { /* nothing is good, presume 0???? */
4664 correction[ichain] = 0;
4665 temperature[ichain] = 0;
4666 voltage[ichain] = 0;
4670 ar9003_hw_power_control_override(ah, frequency, correction, voltage,
4673 ath_dbg(common, ATH_DBG_EEPROM,
4674 "for frequency=%d, calibration correction = %d %d %d\n",
4675 frequency, correction[0], correction[1], correction[2]);
4680 static u16 ar9003_hw_get_direct_edge_power(struct ar9300_eeprom *eep,
4685 struct cal_ctl_data_2g *ctl_2g = eep->ctlPowerData_2G;
4686 struct cal_ctl_data_5g *ctl_5g = eep->ctlPowerData_5G;
4689 return CTL_EDGE_TPOWER(ctl_2g[idx].ctlEdges[edge]);
4691 return CTL_EDGE_TPOWER(ctl_5g[idx].ctlEdges[edge]);
4694 static u16 ar9003_hw_get_indirect_edge_power(struct ar9300_eeprom *eep,
4700 struct cal_ctl_data_2g *ctl_2g = eep->ctlPowerData_2G;
4701 struct cal_ctl_data_5g *ctl_5g = eep->ctlPowerData_5G;
4703 u8 *ctl_freqbin = is2GHz ?
4704 &eep->ctl_freqbin_2G[idx][0] :
4705 &eep->ctl_freqbin_5G[idx][0];
4708 if (ath9k_hw_fbin2freq(ctl_freqbin[edge - 1], 1) < freq &&
4709 CTL_EDGE_FLAGS(ctl_2g[idx].ctlEdges[edge - 1]))
4710 return CTL_EDGE_TPOWER(ctl_2g[idx].ctlEdges[edge - 1]);
4712 if (ath9k_hw_fbin2freq(ctl_freqbin[edge - 1], 0) < freq &&
4713 CTL_EDGE_FLAGS(ctl_5g[idx].ctlEdges[edge - 1]))
4714 return CTL_EDGE_TPOWER(ctl_5g[idx].ctlEdges[edge - 1]);
4717 return MAX_RATE_POWER;
4721 * Find the maximum conformance test limit for the given channel and CTL info
4723 static u16 ar9003_hw_get_max_edge_power(struct ar9300_eeprom *eep,
4724 u16 freq, int idx, bool is2GHz)
4726 u16 twiceMaxEdgePower = MAX_RATE_POWER;
4727 u8 *ctl_freqbin = is2GHz ?
4728 &eep->ctl_freqbin_2G[idx][0] :
4729 &eep->ctl_freqbin_5G[idx][0];
4730 u16 num_edges = is2GHz ?
4731 AR9300_NUM_BAND_EDGES_2G : AR9300_NUM_BAND_EDGES_5G;
4734 /* Get the edge power */
4736 (edge < num_edges) && (ctl_freqbin[edge] != AR5416_BCHAN_UNUSED);
4739 * If there's an exact channel match or an inband flag set
4740 * on the lower channel use the given rdEdgePower
4742 if (freq == ath9k_hw_fbin2freq(ctl_freqbin[edge], is2GHz)) {
4744 ar9003_hw_get_direct_edge_power(eep, idx,
4747 } else if ((edge > 0) &&
4748 (freq < ath9k_hw_fbin2freq(ctl_freqbin[edge],
4751 ar9003_hw_get_indirect_edge_power(eep, idx,
4755 * Leave loop - no more affecting edges possible in
4756 * this monotonic increasing list
4761 return twiceMaxEdgePower;
4764 static void ar9003_hw_set_power_per_rate_table(struct ath_hw *ah,
4765 struct ath9k_channel *chan,
4766 u8 *pPwrArray, u16 cfgCtl,
4767 u8 twiceAntennaReduction,
4768 u8 twiceMaxRegulatoryPower,
4771 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
4772 struct ath_common *common = ath9k_hw_common(ah);
4773 struct ar9300_eeprom *pEepData = &ah->eeprom.ar9300_eep;
4774 u16 twiceMaxEdgePower = MAX_RATE_POWER;
4775 static const u16 tpScaleReductionTable[5] = {
4776 0, 3, 6, 9, MAX_RATE_POWER
4779 int16_t twiceLargestAntenna;
4780 u16 scaledPower = 0, minCtlPower, maxRegAllowedPower;
4781 static const u16 ctlModesFor11a[] = {
4782 CTL_11A, CTL_5GHT20, CTL_11A_EXT, CTL_5GHT40
4784 static const u16 ctlModesFor11g[] = {
4785 CTL_11B, CTL_11G, CTL_2GHT20, CTL_11B_EXT,
4786 CTL_11G_EXT, CTL_2GHT40
4789 const u16 *pCtlMode;
4791 struct chan_centers centers;
4794 u16 twiceMinEdgePower;
4795 bool is2ghz = IS_CHAN_2GHZ(chan);
4797 ath9k_hw_get_channel_centers(ah, chan, ¢ers);
4799 /* Compute TxPower reduction due to Antenna Gain */
4801 twiceLargestAntenna = pEepData->modalHeader2G.antennaGain;
4803 twiceLargestAntenna = pEepData->modalHeader5G.antennaGain;
4805 twiceLargestAntenna = (int16_t)min((twiceAntennaReduction) -
4806 twiceLargestAntenna, 0);
4809 * scaledPower is the minimum of the user input power level
4810 * and the regulatory allowed power level
4812 maxRegAllowedPower = twiceMaxRegulatoryPower + twiceLargestAntenna;
4814 if (regulatory->tp_scale != ATH9K_TP_SCALE_MAX) {
4815 maxRegAllowedPower -=
4816 (tpScaleReductionTable[(regulatory->tp_scale)] * 2);
4819 scaledPower = min(powerLimit, maxRegAllowedPower);
4822 * Reduce scaled Power by number of chains active to get
4823 * to per chain tx power level
4825 switch (ar5416_get_ntxchains(ah->txchainmask)) {
4829 if (scaledPower > REDUCE_SCALED_POWER_BY_TWO_CHAIN)
4830 scaledPower -= REDUCE_SCALED_POWER_BY_TWO_CHAIN;
4835 if (scaledPower > REDUCE_SCALED_POWER_BY_THREE_CHAIN)
4836 scaledPower -= REDUCE_SCALED_POWER_BY_THREE_CHAIN;
4842 scaledPower = max((u16)0, scaledPower);
4845 * Get target powers from EEPROM - our baseline for TX Power
4848 /* Setup for CTL modes */
4849 /* CTL_11B, CTL_11G, CTL_2GHT20 */
4851 ARRAY_SIZE(ctlModesFor11g) -
4852 SUB_NUM_CTL_MODES_AT_2G_40;
4853 pCtlMode = ctlModesFor11g;
4854 if (IS_CHAN_HT40(chan))
4856 numCtlModes = ARRAY_SIZE(ctlModesFor11g);
4858 /* Setup for CTL modes */
4859 /* CTL_11A, CTL_5GHT20 */
4860 numCtlModes = ARRAY_SIZE(ctlModesFor11a) -
4861 SUB_NUM_CTL_MODES_AT_5G_40;
4862 pCtlMode = ctlModesFor11a;
4863 if (IS_CHAN_HT40(chan))
4865 numCtlModes = ARRAY_SIZE(ctlModesFor11a);
4869 * For MIMO, need to apply regulatory caps individually across
4870 * dynamically running modes: CCK, OFDM, HT20, HT40
4872 * The outer loop walks through each possible applicable runtime mode.
4873 * The inner loop walks through each ctlIndex entry in EEPROM.
4874 * The ctl value is encoded as [7:4] == test group, [3:0] == test mode.
4876 for (ctlMode = 0; ctlMode < numCtlModes; ctlMode++) {
4877 bool isHt40CtlMode = (pCtlMode[ctlMode] == CTL_5GHT40) ||
4878 (pCtlMode[ctlMode] == CTL_2GHT40);
4880 freq = centers.synth_center;
4881 else if (pCtlMode[ctlMode] & EXT_ADDITIVE)
4882 freq = centers.ext_center;
4884 freq = centers.ctl_center;
4886 ath_dbg(common, ATH_DBG_REGULATORY,
4887 "LOOP-Mode ctlMode %d < %d, isHt40CtlMode %d, EXT_ADDITIVE %d\n",
4888 ctlMode, numCtlModes, isHt40CtlMode,
4889 (pCtlMode[ctlMode] & EXT_ADDITIVE));
4891 /* walk through each CTL index stored in EEPROM */
4893 ctlIndex = pEepData->ctlIndex_2G;
4894 ctlNum = AR9300_NUM_CTLS_2G;
4896 ctlIndex = pEepData->ctlIndex_5G;
4897 ctlNum = AR9300_NUM_CTLS_5G;
4900 for (i = 0; (i < ctlNum) && ctlIndex[i]; i++) {
4901 ath_dbg(common, ATH_DBG_REGULATORY,
4902 "LOOP-Ctlidx %d: cfgCtl 0x%2.2x pCtlMode 0x%2.2x ctlIndex 0x%2.2x chan %d\n",
4903 i, cfgCtl, pCtlMode[ctlMode], ctlIndex[i],
4907 * compare test group from regulatory
4908 * channel list with test mode from pCtlMode
4911 if ((((cfgCtl & ~CTL_MODE_M) |
4912 (pCtlMode[ctlMode] & CTL_MODE_M)) ==
4914 (((cfgCtl & ~CTL_MODE_M) |
4915 (pCtlMode[ctlMode] & CTL_MODE_M)) ==
4916 ((ctlIndex[i] & CTL_MODE_M) |
4919 ar9003_hw_get_max_edge_power(pEepData,
4923 if ((cfgCtl & ~CTL_MODE_M) == SD_NO_CTL)
4925 * Find the minimum of all CTL
4926 * edge powers that apply to
4930 min(twiceMaxEdgePower,
4941 minCtlPower = (u8)min(twiceMaxEdgePower, scaledPower);
4943 ath_dbg(common, ATH_DBG_REGULATORY,
4944 "SEL-Min ctlMode %d pCtlMode %d 2xMaxEdge %d sP %d minCtlPwr %d\n",
4945 ctlMode, pCtlMode[ctlMode], twiceMaxEdgePower,
4946 scaledPower, minCtlPower);
4948 /* Apply ctl mode to correct target power set */
4949 switch (pCtlMode[ctlMode]) {
4951 for (i = ALL_TARGET_LEGACY_1L_5L;
4952 i <= ALL_TARGET_LEGACY_11S; i++)
4954 (u8)min((u16)pPwrArray[i],
4959 for (i = ALL_TARGET_LEGACY_6_24;
4960 i <= ALL_TARGET_LEGACY_54; i++)
4962 (u8)min((u16)pPwrArray[i],
4967 for (i = ALL_TARGET_HT20_0_8_16;
4968 i <= ALL_TARGET_HT20_21; i++)
4970 (u8)min((u16)pPwrArray[i],
4972 pPwrArray[ALL_TARGET_HT20_22] =
4973 (u8)min((u16)pPwrArray[ALL_TARGET_HT20_22],
4975 pPwrArray[ALL_TARGET_HT20_23] =
4976 (u8)min((u16)pPwrArray[ALL_TARGET_HT20_23],
4981 for (i = ALL_TARGET_HT40_0_8_16;
4982 i <= ALL_TARGET_HT40_23; i++)
4984 (u8)min((u16)pPwrArray[i],
4990 } /* end ctl mode checking */
4993 static inline u8 mcsidx_to_tgtpwridx(unsigned int mcs_idx, u8 base_pwridx)
4995 u8 mod_idx = mcs_idx % 8;
4998 return mod_idx ? (base_pwridx + 1) : base_pwridx;
5000 return base_pwridx + 4 * (mcs_idx / 8) + mod_idx - 2;
5003 static void ath9k_hw_ar9300_set_txpower(struct ath_hw *ah,
5004 struct ath9k_channel *chan, u16 cfgCtl,
5005 u8 twiceAntennaReduction,
5006 u8 twiceMaxRegulatoryPower,
5007 u8 powerLimit, bool test)
5009 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
5010 struct ath_common *common = ath9k_hw_common(ah);
5011 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
5012 struct ar9300_modal_eep_header *modal_hdr;
5013 u8 targetPowerValT2[ar9300RateSize];
5014 u8 target_power_val_t2_eep[ar9300RateSize];
5015 unsigned int i = 0, paprd_scale_factor = 0;
5016 u8 pwr_idx, min_pwridx = 0;
5018 ar9003_hw_set_target_power_eeprom(ah, chan->channel, targetPowerValT2);
5020 if (ah->eep_ops->get_eeprom(ah, EEP_PAPRD)) {
5021 if (IS_CHAN_2GHZ(chan))
5022 modal_hdr = &eep->modalHeader2G;
5024 modal_hdr = &eep->modalHeader5G;
5026 ah->paprd_ratemask =
5027 le32_to_cpu(modal_hdr->papdRateMaskHt20) &
5028 AR9300_PAPRD_RATE_MASK;
5030 ah->paprd_ratemask_ht40 =
5031 le32_to_cpu(modal_hdr->papdRateMaskHt40) &
5032 AR9300_PAPRD_RATE_MASK;
5034 paprd_scale_factor = ar9003_get_paprd_scale_factor(ah, chan);
5035 min_pwridx = IS_CHAN_HT40(chan) ? ALL_TARGET_HT40_0_8_16 :
5036 ALL_TARGET_HT20_0_8_16;
5038 if (!ah->paprd_table_write_done) {
5039 memcpy(target_power_val_t2_eep, targetPowerValT2,
5040 sizeof(targetPowerValT2));
5041 for (i = 0; i < 24; i++) {
5042 pwr_idx = mcsidx_to_tgtpwridx(i, min_pwridx);
5043 if (ah->paprd_ratemask & (1 << i)) {
5044 if (targetPowerValT2[pwr_idx] &&
5045 targetPowerValT2[pwr_idx] ==
5046 target_power_val_t2_eep[pwr_idx])
5047 targetPowerValT2[pwr_idx] -=
5052 memcpy(target_power_val_t2_eep, targetPowerValT2,
5053 sizeof(targetPowerValT2));
5056 ar9003_hw_set_power_per_rate_table(ah, chan,
5057 targetPowerValT2, cfgCtl,
5058 twiceAntennaReduction,
5059 twiceMaxRegulatoryPower,
5062 if (ah->eep_ops->get_eeprom(ah, EEP_PAPRD)) {
5063 for (i = 0; i < ar9300RateSize; i++) {
5064 if ((ah->paprd_ratemask & (1 << i)) &&
5065 (abs(targetPowerValT2[i] -
5066 target_power_val_t2_eep[i]) >
5067 paprd_scale_factor)) {
5068 ah->paprd_ratemask &= ~(1 << i);
5069 ath_dbg(common, ATH_DBG_EEPROM,
5070 "paprd disabled for mcs %d\n", i);
5075 regulatory->max_power_level = 0;
5076 for (i = 0; i < ar9300RateSize; i++) {
5077 if (targetPowerValT2[i] > regulatory->max_power_level)
5078 regulatory->max_power_level = targetPowerValT2[i];
5084 for (i = 0; i < ar9300RateSize; i++) {
5085 ath_dbg(common, ATH_DBG_EEPROM,
5086 "TPC[%02d] 0x%08x\n", i, targetPowerValT2[i]);
5089 ah->txpower_limit = regulatory->max_power_level;
5091 /* Write target power array to registers */
5092 ar9003_hw_tx_power_regwrite(ah, targetPowerValT2);
5093 ar9003_hw_calibration_apply(ah, chan->channel);
5095 if (IS_CHAN_2GHZ(chan)) {
5096 if (IS_CHAN_HT40(chan))
5097 i = ALL_TARGET_HT40_0_8_16;
5099 i = ALL_TARGET_HT20_0_8_16;
5101 if (IS_CHAN_HT40(chan))
5102 i = ALL_TARGET_HT40_7;
5104 i = ALL_TARGET_HT20_7;
5106 ah->paprd_target_power = targetPowerValT2[i];
5109 static u16 ath9k_hw_ar9300_get_spur_channel(struct ath_hw *ah,
5115 s32 ar9003_hw_get_tx_gain_idx(struct ath_hw *ah)
5117 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
5119 return (eep->baseEepHeader.txrxgain >> 4) & 0xf; /* bits 7:4 */
5122 s32 ar9003_hw_get_rx_gain_idx(struct ath_hw *ah)
5124 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
5126 return (eep->baseEepHeader.txrxgain) & 0xf; /* bits 3:0 */
5129 u8 *ar9003_get_spur_chan_ptr(struct ath_hw *ah, bool is_2ghz)
5131 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
5134 return eep->modalHeader2G.spurChans;
5136 return eep->modalHeader5G.spurChans;
5139 unsigned int ar9003_get_paprd_scale_factor(struct ath_hw *ah,
5140 struct ath9k_channel *chan)
5142 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
5144 if (IS_CHAN_2GHZ(chan))
5145 return MS(le32_to_cpu(eep->modalHeader2G.papdRateMaskHt20),
5146 AR9300_PAPRD_SCALE_1);
5148 if (chan->channel >= 5700)
5149 return MS(le32_to_cpu(eep->modalHeader5G.papdRateMaskHt20),
5150 AR9300_PAPRD_SCALE_1);
5151 else if (chan->channel >= 5400)
5152 return MS(le32_to_cpu(eep->modalHeader5G.papdRateMaskHt40),
5153 AR9300_PAPRD_SCALE_2);
5155 return MS(le32_to_cpu(eep->modalHeader5G.papdRateMaskHt40),
5156 AR9300_PAPRD_SCALE_1);
5160 const struct eeprom_ops eep_ar9300_ops = {
5161 .check_eeprom = ath9k_hw_ar9300_check_eeprom,
5162 .get_eeprom = ath9k_hw_ar9300_get_eeprom,
5163 .fill_eeprom = ath9k_hw_ar9300_fill_eeprom,
5164 .dump_eeprom = ath9k_hw_ar9003_dump_eeprom,
5165 .get_eeprom_ver = ath9k_hw_ar9300_get_eeprom_ver,
5166 .get_eeprom_rev = ath9k_hw_ar9300_get_eeprom_rev,
5167 .set_board_values = ath9k_hw_ar9300_set_board_values,
5168 .set_addac = ath9k_hw_ar9300_set_addac,
5169 .set_txpower = ath9k_hw_ar9300_set_txpower,
5170 .get_spur_channel = ath9k_hw_ar9300_get_spur_channel