2 * Copyright (c) 2008-2011 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 #include <linux/kernel.h>
21 struct ani_ofdm_level_entry {
22 int spur_immunity_level;
24 int ofdm_weak_signal_on;
27 /* values here are relative to the INI */
34 * WS: OFDM / CCK Weak Signal detection
35 * MRC-CCK: Maximal Ratio Combining for CCK
38 static const struct ani_ofdm_level_entry ofdm_level_table[] = {
40 { 0, 0, 1 }, /* lvl 0 */
41 { 1, 1, 1 }, /* lvl 1 */
42 { 2, 2, 1 }, /* lvl 2 */
43 { 3, 2, 1 }, /* lvl 3 (default) */
44 { 4, 3, 1 }, /* lvl 4 */
45 { 5, 4, 1 }, /* lvl 5 */
46 { 6, 5, 1 }, /* lvl 6 */
47 { 7, 6, 1 }, /* lvl 7 */
48 { 7, 7, 1 }, /* lvl 8 */
49 { 7, 8, 0 } /* lvl 9 */
51 #define ATH9K_ANI_OFDM_NUM_LEVEL \
52 ARRAY_SIZE(ofdm_level_table)
53 #define ATH9K_ANI_OFDM_MAX_LEVEL \
54 (ATH9K_ANI_OFDM_NUM_LEVEL-1)
55 #define ATH9K_ANI_OFDM_DEF_LEVEL \
56 3 /* default level - matches the INI settings */
59 * MRC (Maximal Ratio Combining) has always been used with multi-antenna ofdm.
60 * With OFDM for single stream you just add up all antenna inputs, you're
61 * only interested in what you get after FFT. Signal aligment is also not
62 * required for OFDM because any phase difference adds up in the frequency
65 * MRC requires extra work for use with CCK. You need to align the antenna
66 * signals from the different antenna before you can add the signals together.
67 * You need aligment of signals as CCK is in time domain, so addition can cancel
68 * your signal completely if phase is 180 degrees (think of adding sine waves).
69 * You also need to remove noise before the addition and this is where ANI
70 * MRC CCK comes into play. One of the antenna inputs may be stronger but
71 * lower SNR, so just adding after alignment can be dangerous.
73 * Regardless of alignment in time, the antenna signals add constructively after
74 * FFT and improve your reception. For more information:
76 * http://en.wikipedia.org/wiki/Maximal-ratio_combining
79 struct ani_cck_level_entry {
84 static const struct ani_cck_level_entry cck_level_table[] = {
88 { 2, 1 }, /* lvl 2 (default) */
93 { 7, 0 }, /* lvl 7 (only for high rssi) */
94 { 8, 0 } /* lvl 8 (only for high rssi) */
97 #define ATH9K_ANI_CCK_NUM_LEVEL \
98 ARRAY_SIZE(cck_level_table)
99 #define ATH9K_ANI_CCK_MAX_LEVEL \
100 (ATH9K_ANI_CCK_NUM_LEVEL-1)
101 #define ATH9K_ANI_CCK_MAX_LEVEL_LOW_RSSI \
102 (ATH9K_ANI_CCK_NUM_LEVEL-3)
103 #define ATH9K_ANI_CCK_DEF_LEVEL \
104 2 /* default level - matches the INI settings */
106 static bool use_new_ani(struct ath_hw *ah)
108 return AR_SREV_9300_20_OR_LATER(ah) || modparam_force_new_ani;
111 static void ath9k_hw_update_mibstats(struct ath_hw *ah,
112 struct ath9k_mib_stats *stats)
114 stats->ackrcv_bad += REG_READ(ah, AR_ACK_FAIL);
115 stats->rts_bad += REG_READ(ah, AR_RTS_FAIL);
116 stats->fcs_bad += REG_READ(ah, AR_FCS_FAIL);
117 stats->rts_good += REG_READ(ah, AR_RTS_OK);
118 stats->beacons += REG_READ(ah, AR_BEACON_CNT);
121 static void ath9k_ani_restart(struct ath_hw *ah)
123 struct ar5416AniState *aniState;
124 struct ath_common *common = ath9k_hw_common(ah);
125 u32 ofdm_base = 0, cck_base = 0;
130 aniState = &ah->curchan->ani;
131 aniState->listenTime = 0;
133 if (!use_new_ani(ah)) {
134 ofdm_base = AR_PHY_COUNTMAX - ah->config.ofdm_trig_high;
135 cck_base = AR_PHY_COUNTMAX - ah->config.cck_trig_high;
138 ath_dbg(common, ATH_DBG_ANI,
139 "Writing ofdmbase=%u cckbase=%u\n", ofdm_base, cck_base);
141 ENABLE_REGWRITE_BUFFER(ah);
143 REG_WRITE(ah, AR_PHY_ERR_1, ofdm_base);
144 REG_WRITE(ah, AR_PHY_ERR_2, cck_base);
145 REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING);
146 REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING);
148 REGWRITE_BUFFER_FLUSH(ah);
150 ath9k_hw_update_mibstats(ah, &ah->ah_mibStats);
152 aniState->ofdmPhyErrCount = 0;
153 aniState->cckPhyErrCount = 0;
156 static void ath9k_hw_ani_ofdm_err_trigger_old(struct ath_hw *ah)
158 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
159 struct ar5416AniState *aniState;
162 aniState = &ah->curchan->ani;
164 if (aniState->noiseImmunityLevel < HAL_NOISE_IMMUNE_MAX) {
165 if (ath9k_hw_ani_control(ah, ATH9K_ANI_NOISE_IMMUNITY_LEVEL,
166 aniState->noiseImmunityLevel + 1)) {
171 if (aniState->spurImmunityLevel < HAL_SPUR_IMMUNE_MAX) {
172 if (ath9k_hw_ani_control(ah, ATH9K_ANI_SPUR_IMMUNITY_LEVEL,
173 aniState->spurImmunityLevel + 1)) {
178 if (ah->opmode == NL80211_IFTYPE_AP) {
179 if (aniState->firstepLevel < HAL_FIRST_STEP_MAX) {
180 ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL,
181 aniState->firstepLevel + 1);
185 rssi = BEACON_RSSI(ah);
186 if (rssi > aniState->rssiThrHigh) {
187 if (!aniState->ofdmWeakSigDetectOff) {
188 if (ath9k_hw_ani_control(ah,
189 ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION,
191 ath9k_hw_ani_control(ah,
192 ATH9K_ANI_SPUR_IMMUNITY_LEVEL, 0);
196 if (aniState->firstepLevel < HAL_FIRST_STEP_MAX) {
197 ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL,
198 aniState->firstepLevel + 1);
201 } else if (rssi > aniState->rssiThrLow) {
202 if (aniState->ofdmWeakSigDetectOff)
203 ath9k_hw_ani_control(ah,
204 ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION,
206 if (aniState->firstepLevel < HAL_FIRST_STEP_MAX)
207 ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL,
208 aniState->firstepLevel + 1);
211 if ((conf->channel->band == IEEE80211_BAND_2GHZ) &&
213 if (!aniState->ofdmWeakSigDetectOff)
214 ath9k_hw_ani_control(ah,
215 ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION,
217 if (aniState->firstepLevel > 0)
218 ath9k_hw_ani_control(ah,
219 ATH9K_ANI_FIRSTEP_LEVEL, 0);
225 static void ath9k_hw_ani_cck_err_trigger_old(struct ath_hw *ah)
227 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
228 struct ar5416AniState *aniState;
231 aniState = &ah->curchan->ani;
232 if (aniState->noiseImmunityLevel < HAL_NOISE_IMMUNE_MAX) {
233 if (ath9k_hw_ani_control(ah, ATH9K_ANI_NOISE_IMMUNITY_LEVEL,
234 aniState->noiseImmunityLevel + 1)) {
238 if (ah->opmode == NL80211_IFTYPE_AP) {
239 if (aniState->firstepLevel < HAL_FIRST_STEP_MAX) {
240 ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL,
241 aniState->firstepLevel + 1);
245 rssi = BEACON_RSSI(ah);
246 if (rssi > aniState->rssiThrLow) {
247 if (aniState->firstepLevel < HAL_FIRST_STEP_MAX)
248 ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL,
249 aniState->firstepLevel + 1);
251 if ((conf->channel->band == IEEE80211_BAND_2GHZ) &&
253 if (aniState->firstepLevel > 0)
254 ath9k_hw_ani_control(ah,
255 ATH9K_ANI_FIRSTEP_LEVEL, 0);
260 /* Adjust the OFDM Noise Immunity Level */
261 static void ath9k_hw_set_ofdm_nil(struct ath_hw *ah, u8 immunityLevel)
263 struct ar5416AniState *aniState = &ah->curchan->ani;
264 struct ath_common *common = ath9k_hw_common(ah);
265 const struct ani_ofdm_level_entry *entry_ofdm;
266 const struct ani_cck_level_entry *entry_cck;
268 aniState->noiseFloor = BEACON_RSSI(ah);
270 ath_dbg(common, ATH_DBG_ANI,
271 "**** ofdmlevel %d=>%d, rssi=%d[lo=%d hi=%d]\n",
272 aniState->ofdmNoiseImmunityLevel,
273 immunityLevel, aniState->noiseFloor,
274 aniState->rssiThrLow, aniState->rssiThrHigh);
276 if (aniState->update_ani)
277 aniState->ofdmNoiseImmunityLevel = immunityLevel;
279 entry_ofdm = &ofdm_level_table[aniState->ofdmNoiseImmunityLevel];
280 entry_cck = &cck_level_table[aniState->cckNoiseImmunityLevel];
282 if (aniState->spurImmunityLevel != entry_ofdm->spur_immunity_level)
283 ath9k_hw_ani_control(ah,
284 ATH9K_ANI_SPUR_IMMUNITY_LEVEL,
285 entry_ofdm->spur_immunity_level);
287 if (aniState->firstepLevel != entry_ofdm->fir_step_level &&
288 entry_ofdm->fir_step_level >= entry_cck->fir_step_level)
289 ath9k_hw_ani_control(ah,
290 ATH9K_ANI_FIRSTEP_LEVEL,
291 entry_ofdm->fir_step_level);
293 if ((ah->opmode != NL80211_IFTYPE_STATION &&
294 ah->opmode != NL80211_IFTYPE_ADHOC) ||
295 aniState->noiseFloor <= aniState->rssiThrHigh) {
296 if (aniState->ofdmWeakSigDetectOff)
297 /* force on ofdm weak sig detect */
298 ath9k_hw_ani_control(ah,
299 ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION,
301 else if (aniState->ofdmWeakSigDetectOff ==
302 entry_ofdm->ofdm_weak_signal_on)
303 ath9k_hw_ani_control(ah,
304 ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION,
305 entry_ofdm->ofdm_weak_signal_on);
309 static void ath9k_hw_ani_ofdm_err_trigger(struct ath_hw *ah)
311 struct ar5416AniState *aniState;
316 if (!use_new_ani(ah)) {
317 ath9k_hw_ani_ofdm_err_trigger_old(ah);
321 aniState = &ah->curchan->ani;
323 if (aniState->ofdmNoiseImmunityLevel < ATH9K_ANI_OFDM_MAX_LEVEL)
324 ath9k_hw_set_ofdm_nil(ah, aniState->ofdmNoiseImmunityLevel + 1);
328 * Set the ANI settings to match an CCK level.
330 static void ath9k_hw_set_cck_nil(struct ath_hw *ah, u_int8_t immunityLevel)
332 struct ar5416AniState *aniState = &ah->curchan->ani;
333 struct ath_common *common = ath9k_hw_common(ah);
334 const struct ani_ofdm_level_entry *entry_ofdm;
335 const struct ani_cck_level_entry *entry_cck;
337 aniState->noiseFloor = BEACON_RSSI(ah);
338 ath_dbg(common, ATH_DBG_ANI,
339 "**** ccklevel %d=>%d, rssi=%d[lo=%d hi=%d]\n",
340 aniState->cckNoiseImmunityLevel, immunityLevel,
341 aniState->noiseFloor, aniState->rssiThrLow,
342 aniState->rssiThrHigh);
344 if ((ah->opmode == NL80211_IFTYPE_STATION ||
345 ah->opmode == NL80211_IFTYPE_ADHOC) &&
346 aniState->noiseFloor <= aniState->rssiThrLow &&
347 immunityLevel > ATH9K_ANI_CCK_MAX_LEVEL_LOW_RSSI)
348 immunityLevel = ATH9K_ANI_CCK_MAX_LEVEL_LOW_RSSI;
350 if (aniState->update_ani)
351 aniState->cckNoiseImmunityLevel = immunityLevel;
353 entry_ofdm = &ofdm_level_table[aniState->ofdmNoiseImmunityLevel];
354 entry_cck = &cck_level_table[aniState->cckNoiseImmunityLevel];
356 if (aniState->firstepLevel != entry_cck->fir_step_level &&
357 entry_cck->fir_step_level >= entry_ofdm->fir_step_level)
358 ath9k_hw_ani_control(ah,
359 ATH9K_ANI_FIRSTEP_LEVEL,
360 entry_cck->fir_step_level);
362 /* Skip MRC CCK for pre AR9003 families */
363 if (!AR_SREV_9300_20_OR_LATER(ah) || AR_SREV_9485(ah))
366 if (aniState->mrcCCKOff == entry_cck->mrc_cck_on)
367 ath9k_hw_ani_control(ah,
369 entry_cck->mrc_cck_on);
372 static void ath9k_hw_ani_cck_err_trigger(struct ath_hw *ah)
374 struct ar5416AniState *aniState;
379 if (!use_new_ani(ah)) {
380 ath9k_hw_ani_cck_err_trigger_old(ah);
384 aniState = &ah->curchan->ani;
386 if (aniState->cckNoiseImmunityLevel < ATH9K_ANI_CCK_MAX_LEVEL)
387 ath9k_hw_set_cck_nil(ah, aniState->cckNoiseImmunityLevel + 1);
390 static void ath9k_hw_ani_lower_immunity_old(struct ath_hw *ah)
392 struct ar5416AniState *aniState;
395 aniState = &ah->curchan->ani;
397 if (ah->opmode == NL80211_IFTYPE_AP) {
398 if (aniState->firstepLevel > 0) {
399 if (ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL,
400 aniState->firstepLevel - 1))
404 rssi = BEACON_RSSI(ah);
405 if (rssi > aniState->rssiThrHigh) {
407 } else if (rssi > aniState->rssiThrLow) {
408 if (aniState->ofdmWeakSigDetectOff) {
409 if (ath9k_hw_ani_control(ah,
410 ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION,
414 if (aniState->firstepLevel > 0) {
415 if (ath9k_hw_ani_control(ah,
416 ATH9K_ANI_FIRSTEP_LEVEL,
417 aniState->firstepLevel - 1) == true)
421 if (aniState->firstepLevel > 0) {
422 if (ath9k_hw_ani_control(ah,
423 ATH9K_ANI_FIRSTEP_LEVEL,
424 aniState->firstepLevel - 1) == true)
430 if (aniState->spurImmunityLevel > 0) {
431 if (ath9k_hw_ani_control(ah, ATH9K_ANI_SPUR_IMMUNITY_LEVEL,
432 aniState->spurImmunityLevel - 1))
436 if (aniState->noiseImmunityLevel > 0) {
437 ath9k_hw_ani_control(ah, ATH9K_ANI_NOISE_IMMUNITY_LEVEL,
438 aniState->noiseImmunityLevel - 1);
444 * only lower either OFDM or CCK errors per turn
445 * we lower the other one next time
447 static void ath9k_hw_ani_lower_immunity(struct ath_hw *ah)
449 struct ar5416AniState *aniState;
451 aniState = &ah->curchan->ani;
453 if (!use_new_ani(ah)) {
454 ath9k_hw_ani_lower_immunity_old(ah);
458 /* lower OFDM noise immunity */
459 if (aniState->ofdmNoiseImmunityLevel > 0 &&
460 (aniState->ofdmsTurn || aniState->cckNoiseImmunityLevel == 0)) {
461 ath9k_hw_set_ofdm_nil(ah, aniState->ofdmNoiseImmunityLevel - 1);
465 /* lower CCK noise immunity */
466 if (aniState->cckNoiseImmunityLevel > 0)
467 ath9k_hw_set_cck_nil(ah, aniState->cckNoiseImmunityLevel - 1);
470 static void ath9k_ani_reset_old(struct ath_hw *ah, bool is_scanning)
472 struct ar5416AniState *aniState;
473 struct ath9k_channel *chan = ah->curchan;
474 struct ath_common *common = ath9k_hw_common(ah);
479 aniState = &ah->curchan->ani;
481 if (ah->opmode != NL80211_IFTYPE_STATION
482 && ah->opmode != NL80211_IFTYPE_ADHOC) {
483 ath_dbg(common, ATH_DBG_ANI,
484 "Reset ANI state opmode %u\n", ah->opmode);
485 ah->stats.ast_ani_reset++;
487 if (ah->opmode == NL80211_IFTYPE_AP) {
489 * ath9k_hw_ani_control() will only process items set on
492 if (IS_CHAN_2GHZ(chan))
493 ah->ani_function = (ATH9K_ANI_SPUR_IMMUNITY_LEVEL |
494 ATH9K_ANI_FIRSTEP_LEVEL);
496 ah->ani_function = 0;
499 ath9k_hw_ani_control(ah, ATH9K_ANI_NOISE_IMMUNITY_LEVEL, 0);
500 ath9k_hw_ani_control(ah, ATH9K_ANI_SPUR_IMMUNITY_LEVEL, 0);
501 ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL, 0);
502 ath9k_hw_ani_control(ah, ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION,
503 !ATH9K_ANI_USE_OFDM_WEAK_SIG);
504 ath9k_hw_ani_control(ah, ATH9K_ANI_CCK_WEAK_SIGNAL_THR,
505 ATH9K_ANI_CCK_WEAK_SIG_THR);
507 ath9k_hw_setrxfilter(ah, ath9k_hw_getrxfilter(ah) |
508 ATH9K_RX_FILTER_PHYERR);
510 ath9k_ani_restart(ah);
514 if (aniState->noiseImmunityLevel != 0)
515 ath9k_hw_ani_control(ah, ATH9K_ANI_NOISE_IMMUNITY_LEVEL,
516 aniState->noiseImmunityLevel);
517 if (aniState->spurImmunityLevel != 0)
518 ath9k_hw_ani_control(ah, ATH9K_ANI_SPUR_IMMUNITY_LEVEL,
519 aniState->spurImmunityLevel);
520 if (aniState->ofdmWeakSigDetectOff)
521 ath9k_hw_ani_control(ah, ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION,
522 !aniState->ofdmWeakSigDetectOff);
523 if (aniState->cckWeakSigThreshold)
524 ath9k_hw_ani_control(ah, ATH9K_ANI_CCK_WEAK_SIGNAL_THR,
525 aniState->cckWeakSigThreshold);
526 if (aniState->firstepLevel != 0)
527 ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL,
528 aniState->firstepLevel);
530 ath9k_hw_setrxfilter(ah, ath9k_hw_getrxfilter(ah) &
531 ~ATH9K_RX_FILTER_PHYERR);
532 ath9k_ani_restart(ah);
534 ENABLE_REGWRITE_BUFFER(ah);
536 REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING);
537 REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING);
539 REGWRITE_BUFFER_FLUSH(ah);
543 * Restore the ANI parameters in the HAL and reset the statistics.
544 * This routine should be called for every hardware reset and for
545 * every channel change.
547 void ath9k_ani_reset(struct ath_hw *ah, bool is_scanning)
549 struct ar5416AniState *aniState = &ah->curchan->ani;
550 struct ath9k_channel *chan = ah->curchan;
551 struct ath_common *common = ath9k_hw_common(ah);
556 if (!use_new_ani(ah))
557 return ath9k_ani_reset_old(ah, is_scanning);
559 BUG_ON(aniState == NULL);
560 ah->stats.ast_ani_reset++;
562 /* only allow a subset of functions in AP mode */
563 if (ah->opmode == NL80211_IFTYPE_AP) {
564 if (IS_CHAN_2GHZ(chan)) {
565 ah->ani_function = (ATH9K_ANI_SPUR_IMMUNITY_LEVEL |
566 ATH9K_ANI_FIRSTEP_LEVEL);
567 if (AR_SREV_9300_20_OR_LATER(ah))
568 ah->ani_function |= ATH9K_ANI_MRC_CCK;
570 ah->ani_function = 0;
573 /* always allow mode (on/off) to be controlled */
574 ah->ani_function |= ATH9K_ANI_MODE;
577 (ah->opmode != NL80211_IFTYPE_STATION &&
578 ah->opmode != NL80211_IFTYPE_ADHOC)) {
580 * If we're scanning or in AP mode, the defaults (ini)
581 * should be in place. For an AP we assume the historical
582 * levels for this channel are probably outdated so start
583 * from defaults instead.
585 if (aniState->ofdmNoiseImmunityLevel !=
586 ATH9K_ANI_OFDM_DEF_LEVEL ||
587 aniState->cckNoiseImmunityLevel !=
588 ATH9K_ANI_CCK_DEF_LEVEL) {
589 ath_dbg(common, ATH_DBG_ANI,
590 "Restore defaults: opmode %u chan %d Mhz/0x%x is_scanning=%d ofdm:%d cck:%d\n",
595 aniState->ofdmNoiseImmunityLevel,
596 aniState->cckNoiseImmunityLevel);
598 aniState->update_ani = false;
599 ath9k_hw_set_ofdm_nil(ah, ATH9K_ANI_OFDM_DEF_LEVEL);
600 ath9k_hw_set_cck_nil(ah, ATH9K_ANI_CCK_DEF_LEVEL);
604 * restore historical levels for this channel
606 ath_dbg(common, ATH_DBG_ANI,
607 "Restore history: opmode %u chan %d Mhz/0x%x is_scanning=%d ofdm:%d cck:%d\n",
612 aniState->ofdmNoiseImmunityLevel,
613 aniState->cckNoiseImmunityLevel);
615 aniState->update_ani = true;
616 ath9k_hw_set_ofdm_nil(ah,
617 aniState->ofdmNoiseImmunityLevel);
618 ath9k_hw_set_cck_nil(ah,
619 aniState->cckNoiseImmunityLevel);
623 * enable phy counters if hw supports or if not, enable phy
624 * interrupts (so we can count each one)
626 ath9k_ani_restart(ah);
628 ENABLE_REGWRITE_BUFFER(ah);
630 REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING);
631 REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING);
633 REGWRITE_BUFFER_FLUSH(ah);
636 static bool ath9k_hw_ani_read_counters(struct ath_hw *ah)
638 struct ath_common *common = ath9k_hw_common(ah);
639 struct ar5416AniState *aniState = &ah->curchan->ani;
642 u32 ofdmPhyErrCnt, cckPhyErrCnt;
643 u32 phyCnt1, phyCnt2;
646 ath_hw_cycle_counters_update(common);
647 listenTime = ath_hw_get_listen_time(common);
649 if (listenTime <= 0) {
650 ah->stats.ast_ani_lneg_or_lzero++;
651 ath9k_ani_restart(ah);
655 if (!use_new_ani(ah)) {
656 ofdm_base = AR_PHY_COUNTMAX - ah->config.ofdm_trig_high;
657 cck_base = AR_PHY_COUNTMAX - ah->config.cck_trig_high;
660 aniState->listenTime += listenTime;
662 ath9k_hw_update_mibstats(ah, &ah->ah_mibStats);
664 phyCnt1 = REG_READ(ah, AR_PHY_ERR_1);
665 phyCnt2 = REG_READ(ah, AR_PHY_ERR_2);
667 if (!use_new_ani(ah) && (phyCnt1 < ofdm_base || phyCnt2 < cck_base)) {
668 if (phyCnt1 < ofdm_base) {
669 ath_dbg(common, ATH_DBG_ANI,
670 "phyCnt1 0x%x, resetting counter value to 0x%x\n",
672 REG_WRITE(ah, AR_PHY_ERR_1, ofdm_base);
673 REG_WRITE(ah, AR_PHY_ERR_MASK_1,
674 AR_PHY_ERR_OFDM_TIMING);
676 if (phyCnt2 < cck_base) {
677 ath_dbg(common, ATH_DBG_ANI,
678 "phyCnt2 0x%x, resetting counter value to 0x%x\n",
680 REG_WRITE(ah, AR_PHY_ERR_2, cck_base);
681 REG_WRITE(ah, AR_PHY_ERR_MASK_2,
682 AR_PHY_ERR_CCK_TIMING);
687 ofdmPhyErrCnt = phyCnt1 - ofdm_base;
688 ah->stats.ast_ani_ofdmerrs +=
689 ofdmPhyErrCnt - aniState->ofdmPhyErrCount;
690 aniState->ofdmPhyErrCount = ofdmPhyErrCnt;
692 cckPhyErrCnt = phyCnt2 - cck_base;
693 ah->stats.ast_ani_cckerrs +=
694 cckPhyErrCnt - aniState->cckPhyErrCount;
695 aniState->cckPhyErrCount = cckPhyErrCnt;
699 void ath9k_hw_ani_monitor(struct ath_hw *ah, struct ath9k_channel *chan)
701 struct ar5416AniState *aniState;
702 struct ath_common *common = ath9k_hw_common(ah);
703 u32 ofdmPhyErrRate, cckPhyErrRate;
708 aniState = &ah->curchan->ani;
709 if (WARN_ON(!aniState))
712 if (!ath9k_hw_ani_read_counters(ah))
715 ofdmPhyErrRate = aniState->ofdmPhyErrCount * 1000 /
716 aniState->listenTime;
717 cckPhyErrRate = aniState->cckPhyErrCount * 1000 /
718 aniState->listenTime;
720 ath_dbg(common, ATH_DBG_ANI,
721 "listenTime=%d OFDM:%d errs=%d/s CCK:%d errs=%d/s ofdm_turn=%d\n",
722 aniState->listenTime,
723 aniState->ofdmNoiseImmunityLevel,
724 ofdmPhyErrRate, aniState->cckNoiseImmunityLevel,
725 cckPhyErrRate, aniState->ofdmsTurn);
727 if (aniState->listenTime > 5 * ah->aniperiod) {
728 if (ofdmPhyErrRate <= ah->config.ofdm_trig_low &&
729 cckPhyErrRate <= ah->config.cck_trig_low) {
730 ath9k_hw_ani_lower_immunity(ah);
731 aniState->ofdmsTurn = !aniState->ofdmsTurn;
733 ath9k_ani_restart(ah);
734 } else if (aniState->listenTime > ah->aniperiod) {
735 /* check to see if need to raise immunity */
736 if (ofdmPhyErrRate > ah->config.ofdm_trig_high &&
737 (cckPhyErrRate <= ah->config.cck_trig_high ||
738 aniState->ofdmsTurn)) {
739 ath9k_hw_ani_ofdm_err_trigger(ah);
740 ath9k_ani_restart(ah);
741 aniState->ofdmsTurn = false;
742 } else if (cckPhyErrRate > ah->config.cck_trig_high) {
743 ath9k_hw_ani_cck_err_trigger(ah);
744 ath9k_ani_restart(ah);
745 aniState->ofdmsTurn = true;
749 EXPORT_SYMBOL(ath9k_hw_ani_monitor);
751 void ath9k_enable_mib_counters(struct ath_hw *ah)
753 struct ath_common *common = ath9k_hw_common(ah);
755 ath_dbg(common, ATH_DBG_ANI, "Enable MIB counters\n");
757 ath9k_hw_update_mibstats(ah, &ah->ah_mibStats);
759 ENABLE_REGWRITE_BUFFER(ah);
761 REG_WRITE(ah, AR_FILT_OFDM, 0);
762 REG_WRITE(ah, AR_FILT_CCK, 0);
763 REG_WRITE(ah, AR_MIBC,
764 ~(AR_MIBC_COW | AR_MIBC_FMC | AR_MIBC_CMC | AR_MIBC_MCS)
766 REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING);
767 REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING);
769 REGWRITE_BUFFER_FLUSH(ah);
772 /* Freeze the MIB counters, get the stats and then clear them */
773 void ath9k_hw_disable_mib_counters(struct ath_hw *ah)
775 struct ath_common *common = ath9k_hw_common(ah);
777 ath_dbg(common, ATH_DBG_ANI, "Disable MIB counters\n");
779 REG_WRITE(ah, AR_MIBC, AR_MIBC_FMC);
780 ath9k_hw_update_mibstats(ah, &ah->ah_mibStats);
781 REG_WRITE(ah, AR_MIBC, AR_MIBC_CMC);
782 REG_WRITE(ah, AR_FILT_OFDM, 0);
783 REG_WRITE(ah, AR_FILT_CCK, 0);
785 EXPORT_SYMBOL(ath9k_hw_disable_mib_counters);
788 * Process a MIB interrupt. We may potentially be invoked because
789 * any of the MIB counters overflow/trigger so don't assume we're
790 * here because a PHY error counter triggered.
792 void ath9k_hw_proc_mib_event(struct ath_hw *ah)
794 u32 phyCnt1, phyCnt2;
796 /* Reset these counters regardless */
797 REG_WRITE(ah, AR_FILT_OFDM, 0);
798 REG_WRITE(ah, AR_FILT_CCK, 0);
799 if (!(REG_READ(ah, AR_SLP_MIB_CTRL) & AR_SLP_MIB_PENDING))
800 REG_WRITE(ah, AR_SLP_MIB_CTRL, AR_SLP_MIB_CLEAR);
802 /* Clear the mib counters and save them in the stats */
803 ath9k_hw_update_mibstats(ah, &ah->ah_mibStats);
807 * We must always clear the interrupt cause by
808 * resetting the phy error regs.
810 REG_WRITE(ah, AR_PHY_ERR_1, 0);
811 REG_WRITE(ah, AR_PHY_ERR_2, 0);
815 /* NB: these are not reset-on-read */
816 phyCnt1 = REG_READ(ah, AR_PHY_ERR_1);
817 phyCnt2 = REG_READ(ah, AR_PHY_ERR_2);
818 if (((phyCnt1 & AR_MIBCNT_INTRMASK) == AR_MIBCNT_INTRMASK) ||
819 ((phyCnt2 & AR_MIBCNT_INTRMASK) == AR_MIBCNT_INTRMASK)) {
821 if (!use_new_ani(ah))
822 ath9k_hw_ani_read_counters(ah);
824 /* NB: always restart to insure the h/w counters are reset */
825 ath9k_ani_restart(ah);
828 EXPORT_SYMBOL(ath9k_hw_proc_mib_event);
830 void ath9k_hw_ani_setup(struct ath_hw *ah)
834 static const int totalSizeDesired[] = { -55, -55, -55, -55, -62 };
835 static const int coarseHigh[] = { -14, -14, -14, -14, -12 };
836 static const int coarseLow[] = { -64, -64, -64, -64, -70 };
837 static const int firpwr[] = { -78, -78, -78, -78, -80 };
839 for (i = 0; i < 5; i++) {
840 ah->totalSizeDesired[i] = totalSizeDesired[i];
841 ah->coarse_high[i] = coarseHigh[i];
842 ah->coarse_low[i] = coarseLow[i];
843 ah->firpwr[i] = firpwr[i];
847 void ath9k_hw_ani_init(struct ath_hw *ah)
849 struct ath_common *common = ath9k_hw_common(ah);
852 ath_dbg(common, ATH_DBG_ANI, "Initialize ANI\n");
854 if (use_new_ani(ah)) {
855 ah->config.ofdm_trig_high = ATH9K_ANI_OFDM_TRIG_HIGH_NEW;
856 ah->config.ofdm_trig_low = ATH9K_ANI_OFDM_TRIG_LOW_NEW;
858 ah->config.cck_trig_high = ATH9K_ANI_CCK_TRIG_HIGH_NEW;
859 ah->config.cck_trig_low = ATH9K_ANI_CCK_TRIG_LOW_NEW;
861 ah->config.ofdm_trig_high = ATH9K_ANI_OFDM_TRIG_HIGH_OLD;
862 ah->config.ofdm_trig_low = ATH9K_ANI_OFDM_TRIG_LOW_OLD;
864 ah->config.cck_trig_high = ATH9K_ANI_CCK_TRIG_HIGH_OLD;
865 ah->config.cck_trig_low = ATH9K_ANI_CCK_TRIG_LOW_OLD;
868 for (i = 0; i < ARRAY_SIZE(ah->channels); i++) {
869 struct ath9k_channel *chan = &ah->channels[i];
870 struct ar5416AniState *ani = &chan->ani;
872 if (use_new_ani(ah)) {
873 ani->spurImmunityLevel =
874 ATH9K_ANI_SPUR_IMMUNE_LVL_NEW;
876 ani->firstepLevel = ATH9K_ANI_FIRSTEP_LVL_NEW;
878 if (AR_SREV_9300_20_OR_LATER(ah))
880 !ATH9K_ANI_ENABLE_MRC_CCK;
882 ani->mrcCCKOff = true;
884 ani->ofdmsTurn = true;
886 ani->spurImmunityLevel =
887 ATH9K_ANI_SPUR_IMMUNE_LVL_OLD;
888 ani->firstepLevel = ATH9K_ANI_FIRSTEP_LVL_OLD;
890 ani->cckWeakSigThreshold =
891 ATH9K_ANI_CCK_WEAK_SIG_THR;
894 ani->rssiThrHigh = ATH9K_ANI_RSSI_THR_HIGH;
895 ani->rssiThrLow = ATH9K_ANI_RSSI_THR_LOW;
896 ani->ofdmWeakSigDetectOff =
897 !ATH9K_ANI_USE_OFDM_WEAK_SIG;
898 ani->cckNoiseImmunityLevel = ATH9K_ANI_CCK_DEF_LEVEL;
899 ani->ofdmNoiseImmunityLevel = ATH9K_ANI_OFDM_DEF_LEVEL;
900 ani->update_ani = false;
904 * since we expect some ongoing maintenance on the tables, let's sanity
905 * check here default level should not modify INI setting.
907 if (use_new_ani(ah)) {
908 ah->aniperiod = ATH9K_ANI_PERIOD_NEW;
909 ah->config.ani_poll_interval = ATH9K_ANI_POLLINTERVAL_NEW;
911 ah->aniperiod = ATH9K_ANI_PERIOD_OLD;
912 ah->config.ani_poll_interval = ATH9K_ANI_POLLINTERVAL_OLD;
915 if (ah->config.enable_ani)
916 ah->proc_phyerr |= HAL_PROCESS_ANI;
918 ath9k_ani_restart(ah);
919 ath9k_enable_mib_counters(ah);