2 * RDC R6040 Fast Ethernet MAC support
4 * Copyright (C) 2004 Sten Wang <sten.wang@rdc.com.tw>
6 * Daniel Gimpelevich <daniel@gimpelevich.san-francisco.ca.us>
7 * Florian Fainelli <florian@openwrt.org>
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version 2
12 * of the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the
21 * Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
22 * Boston, MA 02110-1301, USA.
25 #include <linux/kernel.h>
26 #include <linux/module.h>
27 #include <linux/version.h>
28 #include <linux/moduleparam.h>
29 #include <linux/string.h>
30 #include <linux/timer.h>
31 #include <linux/errno.h>
32 #include <linux/ioport.h>
33 #include <linux/slab.h>
34 #include <linux/interrupt.h>
35 #include <linux/pci.h>
36 #include <linux/netdevice.h>
37 #include <linux/etherdevice.h>
38 #include <linux/skbuff.h>
39 #include <linux/init.h>
40 #include <linux/delay.h>
41 #include <linux/mii.h>
42 #include <linux/ethtool.h>
43 #include <linux/crc32.h>
44 #include <linux/spinlock.h>
45 #include <linux/bitops.h>
47 #include <linux/irq.h>
48 #include <linux/uaccess.h>
50 #include <asm/processor.h>
52 #define DRV_NAME "r6040"
53 #define DRV_VERSION "0.16"
54 #define DRV_RELDATE "10Nov2007"
56 /* PHY CHIP Address */
57 #define PHY1_ADDR 1 /* For MAC1 */
58 #define PHY2_ADDR 2 /* For MAC2 */
59 #define PHY_MODE 0x3100 /* PHY CHIP Register 0 */
60 #define PHY_CAP 0x01E1 /* PHY CHIP Register 4 */
62 /* Time in jiffies before concluding the transmitter is hung. */
63 #define TX_TIMEOUT (6000 * HZ / 1000)
64 #define TIMER_WUT (jiffies + HZ * 1)/* timer wakeup time : 1 second */
66 /* RDC MAC I/O Size */
67 #define R6040_IO_SIZE 256
73 #define MCR0 0x00 /* Control register 0 */
74 #define MCR1 0x04 /* Control register 1 */
75 #define MAC_RST 0x0001 /* Reset the MAC */
76 #define MBCR 0x08 /* Bus control */
77 #define MT_ICR 0x0C /* TX interrupt control */
78 #define MR_ICR 0x10 /* RX interrupt control */
79 #define MTPR 0x14 /* TX poll command register */
80 #define MR_BSR 0x18 /* RX buffer size */
81 #define MR_DCR 0x1A /* RX descriptor control */
82 #define MLSR 0x1C /* Last status */
83 #define MMDIO 0x20 /* MDIO control register */
84 #define MDIO_WRITE 0x4000 /* MDIO write */
85 #define MDIO_READ 0x2000 /* MDIO read */
86 #define MMRD 0x24 /* MDIO read data register */
87 #define MMWD 0x28 /* MDIO write data register */
88 #define MTD_SA0 0x2C /* TX descriptor start address 0 */
89 #define MTD_SA1 0x30 /* TX descriptor start address 1 */
90 #define MRD_SA0 0x34 /* RX descriptor start address 0 */
91 #define MRD_SA1 0x38 /* RX descriptor start address 1 */
92 #define MISR 0x3C /* Status register */
93 #define MIER 0x40 /* INT enable register */
94 #define MSK_INT 0x0000 /* Mask off interrupts */
95 #define ME_CISR 0x44 /* Event counter INT status */
96 #define ME_CIER 0x48 /* Event counter INT enable */
97 #define MR_CNT 0x50 /* Successfully received packet counter */
98 #define ME_CNT0 0x52 /* Event counter 0 */
99 #define ME_CNT1 0x54 /* Event counter 1 */
100 #define ME_CNT2 0x56 /* Event counter 2 */
101 #define ME_CNT3 0x58 /* Event counter 3 */
102 #define MT_CNT 0x5A /* Successfully transmit packet counter */
103 #define ME_CNT4 0x5C /* Event counter 4 */
104 #define MP_CNT 0x5E /* Pause frame counter register */
105 #define MAR0 0x60 /* Hash table 0 */
106 #define MAR1 0x62 /* Hash table 1 */
107 #define MAR2 0x64 /* Hash table 2 */
108 #define MAR3 0x66 /* Hash table 3 */
109 #define MID_0L 0x68 /* Multicast address MID0 Low */
110 #define MID_0M 0x6A /* Multicast address MID0 Medium */
111 #define MID_0H 0x6C /* Multicast address MID0 High */
112 #define MID_1L 0x70 /* MID1 Low */
113 #define MID_1M 0x72 /* MID1 Medium */
114 #define MID_1H 0x74 /* MID1 High */
115 #define MID_2L 0x78 /* MID2 Low */
116 #define MID_2M 0x7A /* MID2 Medium */
117 #define MID_2H 0x7C /* MID2 High */
118 #define MID_3L 0x80 /* MID3 Low */
119 #define MID_3M 0x82 /* MID3 Medium */
120 #define MID_3H 0x84 /* MID3 High */
121 #define PHY_CC 0x88 /* PHY status change configuration register */
122 #define PHY_ST 0x8A /* PHY status register */
123 #define MAC_SM 0xAC /* MAC status machine */
124 #define MAC_ID 0xBE /* Identifier register */
126 #define TX_DCNT 0x80 /* TX descriptor count */
127 #define RX_DCNT 0x80 /* RX descriptor count */
128 #define MAX_BUF_SIZE 0x600
129 #define RX_DESC_SIZE (RX_DCNT * sizeof(struct r6040_descriptor))
130 #define TX_DESC_SIZE (TX_DCNT * sizeof(struct r6040_descriptor))
131 #define MBCR_DEFAULT 0x012A /* MAC Bus Control Register */
132 #define MCAST_MAX 4 /* Max number multicast addresses to filter */
135 #define ICPLUS_PHY_ID 0x0243
137 MODULE_AUTHOR("Sten Wang <sten.wang@rdc.com.tw>,"
138 "Daniel Gimpelevich <daniel@gimpelevich.san-francisco.ca.us>,"
139 "Florian Fainelli <florian@openwrt.org>");
140 MODULE_LICENSE("GPL");
141 MODULE_DESCRIPTION("RDC R6040 NAPI PCI FastEthernet driver");
143 #define RX_INT 0x0001
144 #define TX_INT 0x0010
145 #define RX_NO_DESC_INT 0x0002
146 #define INT_MASK (RX_INT | TX_INT)
148 struct r6040_descriptor {
149 u16 status, len; /* 0-3 */
150 __le32 buf; /* 4-7 */
151 __le32 ndesc; /* 8-B */
153 char *vbufp; /* 10-13 */
154 struct r6040_descriptor *vndescp; /* 14-17 */
155 struct sk_buff *skb_ptr; /* 18-1B */
156 u32 rev2; /* 1C-1F */
157 } __attribute__((aligned(32)));
159 struct r6040_private {
160 spinlock_t lock; /* driver lock */
161 struct timer_list timer;
162 struct pci_dev *pdev;
163 struct r6040_descriptor *rx_insert_ptr;
164 struct r6040_descriptor *rx_remove_ptr;
165 struct r6040_descriptor *tx_insert_ptr;
166 struct r6040_descriptor *tx_remove_ptr;
167 struct r6040_descriptor *rx_ring;
168 struct r6040_descriptor *tx_ring;
169 dma_addr_t rx_ring_dma;
170 dma_addr_t tx_ring_dma;
171 u16 tx_free_desc, rx_free_desc, phy_addr, phy_mode;
174 struct net_device *dev;
175 struct mii_if_info mii_if;
176 struct napi_struct napi;
181 static char version[] __devinitdata = KERN_INFO DRV_NAME
182 ": RDC R6040 NAPI net driver,"
183 "version "DRV_VERSION " (" DRV_RELDATE ")\n";
185 static int phy_table[] = { PHY1_ADDR, PHY2_ADDR };
187 /* Read a word data from PHY Chip */
188 static int phy_read(void __iomem *ioaddr, int phy_addr, int reg)
193 iowrite16(MDIO_READ + reg + (phy_addr << 8), ioaddr + MMDIO);
194 /* Wait for the read bit to be cleared */
196 cmd = ioread16(ioaddr + MMDIO);
201 return ioread16(ioaddr + MMRD);
204 /* Write a word data from PHY Chip */
205 static void phy_write(void __iomem *ioaddr, int phy_addr, int reg, u16 val)
210 iowrite16(val, ioaddr + MMWD);
211 /* Write the command to the MDIO bus */
212 iowrite16(MDIO_WRITE + reg + (phy_addr << 8), ioaddr + MMDIO);
213 /* Wait for the write bit to be cleared */
215 cmd = ioread16(ioaddr + MMDIO);
216 if (cmd & MDIO_WRITE)
221 static int mdio_read(struct net_device *dev, int mii_id, int reg)
223 struct r6040_private *lp = netdev_priv(dev);
224 void __iomem *ioaddr = lp->base;
226 return (phy_read(ioaddr, lp->phy_addr, reg));
229 static void mdio_write(struct net_device *dev, int mii_id, int reg, int val)
231 struct r6040_private *lp = netdev_priv(dev);
232 void __iomem *ioaddr = lp->base;
234 phy_write(ioaddr, lp->phy_addr, reg, val);
237 static void r6040_free_txbufs(struct net_device *dev)
239 struct r6040_private *lp = netdev_priv(dev);
242 for (i = 0; i < TX_DCNT; i++) {
243 if (lp->tx_insert_ptr->skb_ptr) {
244 pci_unmap_single(lp->pdev, lp->tx_insert_ptr->buf,
245 MAX_BUF_SIZE, PCI_DMA_TODEVICE);
246 dev_kfree_skb(lp->tx_insert_ptr->skb_ptr);
247 lp->rx_insert_ptr->skb_ptr = NULL;
249 lp->tx_insert_ptr = lp->tx_insert_ptr->vndescp;
253 static void r6040_free_rxbufs(struct net_device *dev)
255 struct r6040_private *lp = netdev_priv(dev);
258 for (i = 0; i < RX_DCNT; i++) {
259 if (lp->rx_insert_ptr->skb_ptr) {
260 pci_unmap_single(lp->pdev, lp->rx_insert_ptr->buf,
261 MAX_BUF_SIZE, PCI_DMA_FROMDEVICE);
262 dev_kfree_skb(lp->rx_insert_ptr->skb_ptr);
263 lp->rx_insert_ptr->skb_ptr = NULL;
265 lp->rx_insert_ptr = lp->rx_insert_ptr->vndescp;
269 static void r6040_tx_timeout(struct net_device *dev)
271 struct r6040_private *priv = netdev_priv(dev);
273 disable_irq(dev->irq);
274 napi_disable(&priv->napi);
275 spin_lock(&priv->lock);
276 dev->stats.tx_errors++;
277 spin_unlock(&priv->lock);
279 netif_stop_queue(dev);
282 static void r6040_init_ring_desc(struct r6040_descriptor *desc_ring,
283 dma_addr_t desc_dma, int size)
285 struct r6040_descriptor *desc = desc_ring;
286 dma_addr_t mapping = desc_dma;
289 mapping += sizeof(sizeof(*desc));
290 desc->ndesc = cpu_to_le32(mapping);
291 desc->vndescp = desc + 1;
295 desc->ndesc = cpu_to_le32(desc_dma);
296 desc->vndescp = desc_ring;
299 /* Allocate skb buffer for rx descriptor */
300 static void rx_buf_alloc(struct r6040_private *lp, struct net_device *dev)
302 struct r6040_descriptor *descptr;
303 void __iomem *ioaddr = lp->base;
305 descptr = lp->rx_insert_ptr;
306 while (lp->rx_free_desc < RX_DCNT) {
307 descptr->skb_ptr = dev_alloc_skb(MAX_BUF_SIZE);
309 if (!descptr->skb_ptr)
311 descptr->buf = cpu_to_le32(pci_map_single(lp->pdev,
312 descptr->skb_ptr->data,
313 MAX_BUF_SIZE, PCI_DMA_FROMDEVICE));
314 descptr->status = 0x8000;
315 descptr = descptr->vndescp;
318 iowrite16(lp->mcr0 | 0x0002, ioaddr);
320 lp->rx_insert_ptr = descptr;
323 static void r6040_alloc_txbufs(struct net_device *dev)
325 struct r6040_private *lp = netdev_priv(dev);
326 void __iomem *ioaddr = lp->base;
328 lp->tx_free_desc = TX_DCNT;
330 lp->tx_remove_ptr = lp->tx_insert_ptr = lp->tx_ring;
331 r6040_init_ring_desc(lp->tx_ring, lp->tx_ring_dma, TX_DCNT);
333 iowrite16(lp->tx_ring_dma, ioaddr + MTD_SA0);
334 iowrite16(lp->tx_ring_dma >> 16, ioaddr + MTD_SA1);
337 static void r6040_alloc_rxbufs(struct net_device *dev)
339 struct r6040_private *lp = netdev_priv(dev);
340 void __iomem *ioaddr = lp->base;
342 lp->rx_free_desc = 0;
344 lp->rx_remove_ptr = lp->rx_insert_ptr = lp->rx_ring;
345 r6040_init_ring_desc(lp->rx_ring, lp->rx_ring_dma, RX_DCNT);
347 rx_buf_alloc(lp, dev);
349 iowrite16(lp->rx_ring_dma, ioaddr + MRD_SA0);
350 iowrite16(lp->rx_ring_dma >> 16, ioaddr + MRD_SA1);
353 static struct net_device_stats *r6040_get_stats(struct net_device *dev)
355 struct r6040_private *priv = netdev_priv(dev);
356 void __iomem *ioaddr = priv->base;
359 spin_lock_irqsave(&priv->lock, flags);
360 dev->stats.rx_crc_errors += ioread8(ioaddr + ME_CNT1);
361 dev->stats.multicast += ioread8(ioaddr + ME_CNT0);
362 spin_unlock_irqrestore(&priv->lock, flags);
367 /* Stop RDC MAC and Free the allocated resource */
368 static void r6040_down(struct net_device *dev)
370 struct r6040_private *lp = netdev_priv(dev);
371 void __iomem *ioaddr = lp->base;
372 struct pci_dev *pdev = lp->pdev;
378 iowrite16(MSK_INT, ioaddr + MIER); /* Mask Off Interrupt */
379 iowrite16(MAC_RST, ioaddr + MCR1); /* Reset RDC MAC */
381 cmd = ioread16(ioaddr + MCR1);
386 /* Restore MAC Address to MIDx */
387 adrp = (u16 *) dev->dev_addr;
388 iowrite16(adrp[0], ioaddr + MID_0L);
389 iowrite16(adrp[1], ioaddr + MID_0M);
390 iowrite16(adrp[2], ioaddr + MID_0H);
391 free_irq(dev->irq, dev);
394 r6040_free_rxbufs(dev);
397 r6040_free_txbufs(dev);
399 /* Free Descriptor memory */
400 pci_free_consistent(pdev, RX_DESC_SIZE, lp->rx_ring, lp->rx_ring_dma);
401 pci_free_consistent(pdev, TX_DESC_SIZE, lp->tx_ring, lp->tx_ring_dma);
404 static int r6040_close(struct net_device *dev)
406 struct r6040_private *lp = netdev_priv(dev);
409 del_timer_sync(&lp->timer);
411 spin_lock_irq(&lp->lock);
412 netif_stop_queue(dev);
414 spin_unlock_irq(&lp->lock);
419 /* Status of PHY CHIP */
420 static int phy_mode_chk(struct net_device *dev)
422 struct r6040_private *lp = netdev_priv(dev);
423 void __iomem *ioaddr = lp->base;
426 /* PHY Link Status Check */
427 phy_dat = phy_read(ioaddr, lp->phy_addr, 1);
428 if (!(phy_dat & 0x4))
429 phy_dat = 0x8000; /* Link Failed, full duplex */
431 /* PHY Chip Auto-Negotiation Status */
432 phy_dat = phy_read(ioaddr, lp->phy_addr, 1);
433 if (phy_dat & 0x0020) {
434 /* Auto Negotiation Mode */
435 phy_dat = phy_read(ioaddr, lp->phy_addr, 5);
436 phy_dat &= phy_read(ioaddr, lp->phy_addr, 4);
438 /* Force full duplex */
444 phy_dat = phy_read(ioaddr, lp->phy_addr, 0);
454 static void r6040_set_carrier(struct mii_if_info *mii)
456 if (phy_mode_chk(mii->dev)) {
457 /* autoneg is off: Link is always assumed to be up */
458 if (!netif_carrier_ok(mii->dev))
459 netif_carrier_on(mii->dev);
461 phy_mode_chk(mii->dev);
464 static int r6040_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
466 struct r6040_private *lp = netdev_priv(dev);
467 struct mii_ioctl_data *data = if_mii(rq);
470 if (!netif_running(dev))
472 spin_lock_irq(&lp->lock);
473 rc = generic_mii_ioctl(&lp->mii_if, data, cmd, NULL);
474 spin_unlock_irq(&lp->lock);
475 r6040_set_carrier(&lp->mii_if);
479 static int r6040_rx(struct net_device *dev, int limit)
481 struct r6040_private *priv = netdev_priv(dev);
483 void __iomem *ioaddr = priv->base;
486 for (count = 0; count < limit; ++count) {
487 struct r6040_descriptor *descptr = priv->rx_remove_ptr;
488 struct sk_buff *skb_ptr;
490 /* Disable RX interrupt */
491 iowrite16(ioread16(ioaddr + MIER) & (~RX_INT), ioaddr + MIER);
492 descptr = priv->rx_remove_ptr;
494 /* Check for errors */
495 err = ioread16(ioaddr + MLSR);
497 dev->stats.rx_errors++;
498 /* RX FIFO over-run */
500 dev->stats.rx_fifo_errors++;
501 /* RX descriptor unavailable */
503 dev->stats.rx_frame_errors++;
504 /* Received packet with length over buffer lenght */
506 dev->stats.rx_over_errors++;
507 /* Received packet with too long or short */
508 if (err & (0x0010 | 0x0008))
509 dev->stats.rx_length_errors++;
510 /* Received packet with CRC errors */
512 spin_lock(&priv->lock);
513 dev->stats.rx_crc_errors++;
514 spin_unlock(&priv->lock);
517 while (priv->rx_free_desc) {
519 if (descptr->status & 0x8000)
521 skb_ptr = descptr->skb_ptr;
523 printk(KERN_ERR "%s: Inconsistent RX"
524 "descriptor chain\n",
528 descptr->skb_ptr = NULL;
529 skb_ptr->dev = priv->dev;
530 /* Do not count the CRC */
531 skb_put(skb_ptr, descptr->len - 4);
532 pci_unmap_single(priv->pdev, descptr->buf,
533 MAX_BUF_SIZE, PCI_DMA_FROMDEVICE);
534 skb_ptr->protocol = eth_type_trans(skb_ptr, priv->dev);
535 /* Send to upper layer */
536 netif_receive_skb(skb_ptr);
537 dev->last_rx = jiffies;
538 dev->stats.rx_packets++;
539 dev->stats.rx_bytes += descptr->len;
540 /* To next descriptor */
541 descptr = descptr->vndescp;
542 priv->rx_free_desc--;
544 priv->rx_remove_ptr = descptr;
546 /* Allocate new RX buffer */
547 if (priv->rx_free_desc < RX_DCNT)
548 rx_buf_alloc(priv, priv->dev);
553 static void r6040_tx(struct net_device *dev)
555 struct r6040_private *priv = netdev_priv(dev);
556 struct r6040_descriptor *descptr;
557 void __iomem *ioaddr = priv->base;
558 struct sk_buff *skb_ptr;
561 spin_lock(&priv->lock);
562 descptr = priv->tx_remove_ptr;
563 while (priv->tx_free_desc < TX_DCNT) {
564 /* Check for errors */
565 err = ioread16(ioaddr + MLSR);
568 dev->stats.rx_fifo_errors++;
569 if (err & (0x2000 | 0x4000))
570 dev->stats.tx_carrier_errors++;
572 if (descptr->status & 0x8000)
573 break; /* Not complte */
574 skb_ptr = descptr->skb_ptr;
575 pci_unmap_single(priv->pdev, descptr->buf,
576 skb_ptr->len, PCI_DMA_TODEVICE);
578 dev_kfree_skb_irq(skb_ptr);
579 descptr->skb_ptr = NULL;
580 /* To next descriptor */
581 descptr = descptr->vndescp;
582 priv->tx_free_desc++;
584 priv->tx_remove_ptr = descptr;
586 if (priv->tx_free_desc)
587 netif_wake_queue(dev);
588 spin_unlock(&priv->lock);
591 static int r6040_poll(struct napi_struct *napi, int budget)
593 struct r6040_private *priv =
594 container_of(napi, struct r6040_private, napi);
595 struct net_device *dev = priv->dev;
596 void __iomem *ioaddr = priv->base;
599 work_done = r6040_rx(dev, budget);
601 if (work_done < budget) {
602 netif_rx_complete(dev, napi);
603 /* Enable RX interrupt */
604 iowrite16(ioread16(ioaddr + MIER) | RX_INT, ioaddr + MIER);
609 /* The RDC interrupt handler. */
610 static irqreturn_t r6040_interrupt(int irq, void *dev_id)
612 struct net_device *dev = dev_id;
613 struct r6040_private *lp = netdev_priv(dev);
614 void __iomem *ioaddr = lp->base;
618 /* Mask off RDC MAC interrupt */
619 iowrite16(MSK_INT, ioaddr + MIER);
620 /* Read MISR status and clear */
621 status = ioread16(ioaddr + MISR);
623 if (status == 0x0000 || status == 0xffff)
626 /* RX interrupt request */
628 netif_rx_schedule(dev, &lp->napi);
629 iowrite16(TX_INT, ioaddr + MIER);
632 /* TX interrupt request */
636 return IRQ_RETVAL(handled);
639 #ifdef CONFIG_NET_POLL_CONTROLLER
640 static void r6040_poll_controller(struct net_device *dev)
642 disable_irq(dev->irq);
643 r6040_interrupt(dev->irq, dev);
644 enable_irq(dev->irq);
649 static void r6040_up(struct net_device *dev)
651 struct r6040_private *lp = netdev_priv(dev);
652 void __iomem *ioaddr = lp->base;
654 /* Initialise and alloc RX/TX buffers */
655 r6040_alloc_txbufs(dev);
656 r6040_alloc_rxbufs(dev);
658 /* Buffer Size Register */
659 iowrite16(MAX_BUF_SIZE, ioaddr + MR_BSR);
660 /* Read the PHY ID */
661 lp->switch_sig = phy_read(ioaddr, 0, 2);
663 if (lp->switch_sig == ICPLUS_PHY_ID) {
664 phy_write(ioaddr, 29, 31, 0x175C); /* Enable registers */
665 lp->phy_mode = 0x8000;
668 phy_write(ioaddr, lp->phy_addr, 4, PHY_CAP);
669 phy_write(ioaddr, lp->phy_addr, 0, PHY_MODE);
671 if (PHY_MODE == 0x3100)
672 lp->phy_mode = phy_mode_chk(dev);
674 lp->phy_mode = (PHY_MODE & 0x0100) ? 0x8000:0x0;
676 /* MAC Bus Control Register */
677 iowrite16(MBCR_DEFAULT, ioaddr + MBCR);
679 /* MAC TX/RX Enable */
680 lp->mcr0 |= lp->phy_mode;
681 iowrite16(lp->mcr0, ioaddr);
683 /* set interrupt waiting time and packet numbers */
684 iowrite16(0x0F06, ioaddr + MT_ICR);
685 iowrite16(0x0F06, ioaddr + MR_ICR);
687 /* improve performance (by RDC guys) */
688 phy_write(ioaddr, 30, 17, (phy_read(ioaddr, 30, 17) | 0x4000));
689 phy_write(ioaddr, 30, 17, ~((~phy_read(ioaddr, 30, 17)) | 0x2000));
690 phy_write(ioaddr, 0, 19, 0x0000);
691 phy_write(ioaddr, 0, 30, 0x01F0);
693 /* Interrupt Mask Register */
694 iowrite16(INT_MASK, ioaddr + MIER);
698 A periodic timer routine
699 Polling PHY Chip Link Status
701 static void r6040_timer(unsigned long data)
703 struct net_device *dev = (struct net_device *)data;
704 struct r6040_private *lp = netdev_priv(dev);
705 void __iomem *ioaddr = lp->base;
708 /* Polling PHY Chip Status */
709 if (PHY_MODE == 0x3100)
710 phy_mode = phy_mode_chk(dev);
712 phy_mode = (PHY_MODE & 0x0100) ? 0x8000:0x0;
714 if (phy_mode != lp->phy_mode) {
715 lp->phy_mode = phy_mode;
716 lp->mcr0 = (lp->mcr0 & 0x7fff) | phy_mode;
717 iowrite16(lp->mcr0, ioaddr);
718 printk(KERN_INFO "Link Change %x \n", ioread16(ioaddr));
721 /* Timer active again */
722 lp->timer.expires = TIMER_WUT;
723 add_timer(&lp->timer);
726 /* Read/set MAC address routines */
727 static void r6040_mac_address(struct net_device *dev)
729 struct r6040_private *lp = netdev_priv(dev);
730 void __iomem *ioaddr = lp->base;
733 /* MAC operation register */
734 iowrite16(0x01, ioaddr + MCR1); /* Reset MAC */
735 iowrite16(2, ioaddr + MAC_SM); /* Reset internal state machine */
736 iowrite16(0, ioaddr + MAC_SM);
739 /* Restore MAC Address */
740 adrp = (u16 *) dev->dev_addr;
741 iowrite16(adrp[0], ioaddr + MID_0L);
742 iowrite16(adrp[1], ioaddr + MID_0M);
743 iowrite16(adrp[2], ioaddr + MID_0H);
746 static int r6040_open(struct net_device *dev)
748 struct r6040_private *lp = netdev_priv(dev);
751 /* Request IRQ and Register interrupt handler */
752 ret = request_irq(dev->irq, &r6040_interrupt,
753 IRQF_SHARED, dev->name, dev);
757 /* Set MAC address */
758 r6040_mac_address(dev);
760 /* Allocate Descriptor memory */
762 pci_alloc_consistent(lp->pdev, RX_DESC_SIZE, &lp->rx_ring_dma);
767 pci_alloc_consistent(lp->pdev, TX_DESC_SIZE, &lp->tx_ring_dma);
769 pci_free_consistent(lp->pdev, RX_DESC_SIZE, lp->rx_ring,
776 napi_enable(&lp->napi);
777 netif_start_queue(dev);
779 if (lp->switch_sig != ICPLUS_PHY_ID) {
780 /* set and active a timer process */
781 init_timer(&lp->timer);
782 lp->timer.expires = TIMER_WUT;
783 lp->timer.data = (unsigned long)dev;
784 lp->timer.function = &r6040_timer;
785 add_timer(&lp->timer);
790 static int r6040_start_xmit(struct sk_buff *skb, struct net_device *dev)
792 struct r6040_private *lp = netdev_priv(dev);
793 struct r6040_descriptor *descptr;
794 void __iomem *ioaddr = lp->base;
796 int ret = NETDEV_TX_OK;
798 /* Critical Section */
799 spin_lock_irqsave(&lp->lock, flags);
801 /* TX resource check */
802 if (!lp->tx_free_desc) {
803 spin_unlock_irqrestore(&lp->lock, flags);
804 netif_stop_queue(dev);
805 printk(KERN_ERR DRV_NAME ": no tx descriptor\n");
806 ret = NETDEV_TX_BUSY;
810 /* Statistic Counter */
811 dev->stats.tx_packets++;
812 dev->stats.tx_bytes += skb->len;
813 /* Set TX descriptor & Transmit it */
815 descptr = lp->tx_insert_ptr;
819 descptr->len = skb->len;
821 descptr->skb_ptr = skb;
822 descptr->buf = cpu_to_le32(pci_map_single(lp->pdev,
823 skb->data, skb->len, PCI_DMA_TODEVICE));
824 descptr->status = 0x8000;
825 /* Trigger the MAC to check the TX descriptor */
826 iowrite16(0x01, ioaddr + MTPR);
827 lp->tx_insert_ptr = descptr->vndescp;
829 /* If no tx resource, stop */
830 if (!lp->tx_free_desc)
831 netif_stop_queue(dev);
833 dev->trans_start = jiffies;
834 spin_unlock_irqrestore(&lp->lock, flags);
838 static void r6040_multicast_list(struct net_device *dev)
840 struct r6040_private *lp = netdev_priv(dev);
841 void __iomem *ioaddr = lp->base;
845 struct dev_mc_list *dmi = dev->mc_list;
849 adrp = (u16 *)dev->dev_addr;
850 iowrite16(adrp[0], ioaddr + MID_0L);
851 iowrite16(adrp[1], ioaddr + MID_0M);
852 iowrite16(adrp[2], ioaddr + MID_0H);
854 /* Promiscous Mode */
855 spin_lock_irqsave(&lp->lock, flags);
857 /* Clear AMCP & PROM bits */
858 reg = ioread16(ioaddr) & ~0x0120;
859 if (dev->flags & IFF_PROMISC) {
863 /* Too many multicast addresses
864 * accept all traffic */
865 else if ((dev->mc_count > MCAST_MAX)
866 || (dev->flags & IFF_ALLMULTI))
869 iowrite16(reg, ioaddr);
870 spin_unlock_irqrestore(&lp->lock, flags);
872 /* Build the hash table */
873 if (dev->mc_count > MCAST_MAX) {
877 for (i = 0; i < 4; i++)
880 for (i = 0; i < dev->mc_count; i++) {
881 char *addrs = dmi->dmi_addr;
888 crc = ether_crc_le(6, addrs);
890 hash_table[crc >> 4] |= 1 << (15 - (crc & 0xf));
892 /* Write the index of the hash table */
893 for (i = 0; i < 4; i++)
894 iowrite16(hash_table[i] << 14, ioaddr + MCR1);
895 /* Fill the MAC hash tables with their values */
896 iowrite16(hash_table[0], ioaddr + MAR0);
897 iowrite16(hash_table[1], ioaddr + MAR1);
898 iowrite16(hash_table[2], ioaddr + MAR2);
899 iowrite16(hash_table[3], ioaddr + MAR3);
901 /* Multicast Address 1~4 case */
902 for (i = 0, dmi; (i < dev->mc_count) && (i < MCAST_MAX); i++) {
903 adrp = (u16 *)dmi->dmi_addr;
904 iowrite16(adrp[0], ioaddr + MID_1L + 8*i);
905 iowrite16(adrp[1], ioaddr + MID_1M + 8*i);
906 iowrite16(adrp[2], ioaddr + MID_1H + 8*i);
909 for (i = dev->mc_count; i < MCAST_MAX; i++) {
910 iowrite16(0xffff, ioaddr + MID_0L + 8*i);
911 iowrite16(0xffff, ioaddr + MID_0M + 8*i);
912 iowrite16(0xffff, ioaddr + MID_0H + 8*i);
916 static void netdev_get_drvinfo(struct net_device *dev,
917 struct ethtool_drvinfo *info)
919 struct r6040_private *rp = netdev_priv(dev);
921 strcpy(info->driver, DRV_NAME);
922 strcpy(info->version, DRV_VERSION);
923 strcpy(info->bus_info, pci_name(rp->pdev));
926 static int netdev_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
928 struct r6040_private *rp = netdev_priv(dev);
931 spin_lock_irq(&rp->lock);
932 rc = mii_ethtool_gset(&rp->mii_if, cmd);
933 spin_unlock_irq(&rp->lock);
938 static int netdev_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
940 struct r6040_private *rp = netdev_priv(dev);
943 spin_lock_irq(&rp->lock);
944 rc = mii_ethtool_sset(&rp->mii_if, cmd);
945 spin_unlock_irq(&rp->lock);
946 r6040_set_carrier(&rp->mii_if);
951 static u32 netdev_get_link(struct net_device *dev)
953 struct r6040_private *rp = netdev_priv(dev);
955 return mii_link_ok(&rp->mii_if);
958 static struct ethtool_ops netdev_ethtool_ops = {
959 .get_drvinfo = netdev_get_drvinfo,
960 .get_settings = netdev_get_settings,
961 .set_settings = netdev_set_settings,
962 .get_link = netdev_get_link,
965 static int __devinit r6040_init_one(struct pci_dev *pdev,
966 const struct pci_device_id *ent)
968 struct net_device *dev;
969 struct r6040_private *lp;
970 void __iomem *ioaddr;
971 int err, io_size = R6040_IO_SIZE;
972 static int card_idx = -1;
977 printk(KERN_INFO "%s\n", version);
979 err = pci_enable_device(pdev);
983 /* this should always be supported */
984 if (pci_set_dma_mask(pdev, DMA_32BIT_MASK)) {
985 printk(KERN_ERR DRV_NAME "32-bit PCI DMA addresses"
986 "not supported by the card\n");
989 if (pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK)) {
990 printk(KERN_ERR DRV_NAME "32-bit PCI DMA addresses"
991 "not supported by the card\n");
996 if (pci_resource_len(pdev, 0) < io_size) {
997 printk(KERN_ERR "Insufficient PCI resources, aborting\n");
1001 pioaddr = pci_resource_start(pdev, 0); /* IO map base address */
1002 pci_set_master(pdev);
1004 dev = alloc_etherdev(sizeof(struct r6040_private));
1006 printk(KERN_ERR "Failed to allocate etherdev\n");
1009 SET_NETDEV_DEV(dev, &pdev->dev);
1010 lp = netdev_priv(dev);
1013 if (pci_request_regions(pdev, DRV_NAME)) {
1014 printk(KERN_ERR DRV_NAME ": Failed to request PCI regions\n");
1016 goto err_out_disable;
1019 ioaddr = pci_iomap(pdev, bar, io_size);
1021 printk(KERN_ERR "ioremap failed for device %s\n",
1026 /* Init system & device */
1028 dev->irq = pdev->irq;
1030 spin_lock_init(&lp->lock);
1031 pci_set_drvdata(pdev, dev);
1033 /* Set MAC address */
1036 adrp = (u16 *)dev->dev_addr;
1037 adrp[0] = ioread16(ioaddr + MID_0L);
1038 adrp[1] = ioread16(ioaddr + MID_0M);
1039 adrp[2] = ioread16(ioaddr + MID_0H);
1041 /* Link new device into r6040_root_dev */
1044 /* Init RDC private data */
1046 lp->phy_addr = phy_table[card_idx];
1049 /* The RDC-specific entries in the device structure. */
1050 dev->open = &r6040_open;
1051 dev->hard_start_xmit = &r6040_start_xmit;
1052 dev->stop = &r6040_close;
1053 dev->get_stats = r6040_get_stats;
1054 dev->set_multicast_list = &r6040_multicast_list;
1055 dev->do_ioctl = &r6040_ioctl;
1056 dev->ethtool_ops = &netdev_ethtool_ops;
1057 dev->tx_timeout = &r6040_tx_timeout;
1058 dev->watchdog_timeo = TX_TIMEOUT;
1059 #ifdef CONFIG_NET_POLL_CONTROLLER
1060 dev->poll_controller = r6040_poll_controller;
1062 netif_napi_add(dev, &lp->napi, r6040_poll, 64);
1063 lp->mii_if.dev = dev;
1064 lp->mii_if.mdio_read = mdio_read;
1065 lp->mii_if.mdio_write = mdio_write;
1066 lp->mii_if.phy_id = lp->phy_addr;
1067 lp->mii_if.phy_id_mask = 0x1f;
1068 lp->mii_if.reg_num_mask = 0x1f;
1070 /* Register net device. After this dev->name assign */
1071 err = register_netdev(dev);
1073 printk(KERN_ERR DRV_NAME ": Failed to register net device\n");
1079 pci_release_regions(pdev);
1081 pci_disable_device(pdev);
1082 pci_set_drvdata(pdev, NULL);
1088 static void __devexit r6040_remove_one(struct pci_dev *pdev)
1090 struct net_device *dev = pci_get_drvdata(pdev);
1092 unregister_netdev(dev);
1093 pci_release_regions(pdev);
1095 pci_disable_device(pdev);
1096 pci_set_drvdata(pdev, NULL);
1100 static struct pci_device_id r6040_pci_tbl[] = {
1101 { PCI_DEVICE(PCI_VENDOR_ID_RDC, 0x6040) },
1104 MODULE_DEVICE_TABLE(pci, r6040_pci_tbl);
1106 static struct pci_driver r6040_driver = {
1108 .id_table = r6040_pci_tbl,
1109 .probe = r6040_init_one,
1110 .remove = __devexit_p(r6040_remove_one),
1114 static int __init r6040_init(void)
1116 return pci_register_driver(&r6040_driver);
1120 static void __exit r6040_cleanup(void)
1122 pci_unregister_driver(&r6040_driver);
1125 module_init(r6040_init);
1126 module_exit(r6040_cleanup);