1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2014 Panasonic Corporation
4 * Copyright (C) 2013-2014, Altera Corporation <www.altera.com>
5 * Copyright (C) 2009-2010, Intel Corporation and its suppliers.
10 #include <linux/bitfield.h>
11 #include <linux/dma-direction.h>
12 #include <linux/errno.h>
14 #include <linux/mtd/mtd.h>
15 #include <linux/mtd/rawnand.h>
19 static dma_addr_t dma_map_single(void *dev, void *ptr, size_t size,
20 enum dma_data_direction dir)
22 unsigned long addr = (unsigned long)ptr;
24 size = ALIGN(size, ARCH_DMA_MINALIGN);
26 if (dir == DMA_FROM_DEVICE)
27 invalidate_dcache_range(addr, addr + size);
29 flush_dcache_range(addr, addr + size);
34 static void dma_unmap_single(void *dev, dma_addr_t addr, size_t size,
35 enum dma_data_direction dir)
37 size = ALIGN(size, ARCH_DMA_MINALIGN);
39 if (dir != DMA_TO_DEVICE)
40 invalidate_dcache_range(addr, addr + size);
43 static int dma_mapping_error(void *dev, dma_addr_t addr)
48 #define DENALI_NAND_NAME "denali-nand"
50 /* for Indexed Addressing */
51 #define DENALI_INDEXED_CTRL 0x00
52 #define DENALI_INDEXED_DATA 0x10
54 #define DENALI_MAP00 (0 << 26) /* direct access to buffer */
55 #define DENALI_MAP01 (1 << 26) /* read/write pages in PIO */
56 #define DENALI_MAP10 (2 << 26) /* high-level control plane */
57 #define DENALI_MAP11 (3 << 26) /* direct controller access */
59 /* MAP11 access cycle type */
60 #define DENALI_MAP11_CMD ((DENALI_MAP11) | 0) /* command cycle */
61 #define DENALI_MAP11_ADDR ((DENALI_MAP11) | 1) /* address cycle */
62 #define DENALI_MAP11_DATA ((DENALI_MAP11) | 2) /* data cycle */
65 #define DENALI_ERASE 0x01
67 #define DENALI_BANK(denali) ((denali)->active_bank << 24)
69 #define DENALI_INVALID_BANK -1
70 #define DENALI_NR_BANKS 4
72 static inline struct denali_nand_info *mtd_to_denali(struct mtd_info *mtd)
74 return container_of(mtd_to_nand(mtd), struct denali_nand_info, nand);
78 * Direct Addressing - the slave address forms the control information (command
79 * type, bank, block, and page address). The slave data is the actual data to
80 * be transferred. This mode requires 28 bits of address region allocated.
82 static u32 denali_direct_read(struct denali_nand_info *denali, u32 addr)
84 return ioread32(denali->host + addr);
87 static void denali_direct_write(struct denali_nand_info *denali, u32 addr,
90 iowrite32(data, denali->host + addr);
94 * Indexed Addressing - address translation module intervenes in passing the
95 * control information. This mode reduces the required address range. The
96 * control information and transferred data are latched by the registers in
97 * the translation module.
99 static u32 denali_indexed_read(struct denali_nand_info *denali, u32 addr)
101 iowrite32(addr, denali->host + DENALI_INDEXED_CTRL);
102 return ioread32(denali->host + DENALI_INDEXED_DATA);
105 static void denali_indexed_write(struct denali_nand_info *denali, u32 addr,
108 iowrite32(addr, denali->host + DENALI_INDEXED_CTRL);
109 iowrite32(data, denali->host + DENALI_INDEXED_DATA);
113 * Use the configuration feature register to determine the maximum number of
114 * banks that the hardware supports.
116 static void denali_detect_max_banks(struct denali_nand_info *denali)
118 uint32_t features = ioread32(denali->reg + FEATURES);
120 denali->max_banks = 1 << FIELD_GET(FEATURES__N_BANKS, features);
122 /* the encoding changed from rev 5.0 to 5.1 */
123 if (denali->revision < 0x0501)
124 denali->max_banks <<= 1;
127 static void __maybe_unused denali_enable_irq(struct denali_nand_info *denali)
131 for (i = 0; i < DENALI_NR_BANKS; i++)
132 iowrite32(U32_MAX, denali->reg + INTR_EN(i));
133 iowrite32(GLOBAL_INT_EN_FLAG, denali->reg + GLOBAL_INT_ENABLE);
136 static void __maybe_unused denali_disable_irq(struct denali_nand_info *denali)
140 for (i = 0; i < DENALI_NR_BANKS; i++)
141 iowrite32(0, denali->reg + INTR_EN(i));
142 iowrite32(0, denali->reg + GLOBAL_INT_ENABLE);
145 static void denali_clear_irq(struct denali_nand_info *denali,
146 int bank, uint32_t irq_status)
148 /* write one to clear bits */
149 iowrite32(irq_status, denali->reg + INTR_STATUS(bank));
152 static void denali_clear_irq_all(struct denali_nand_info *denali)
156 for (i = 0; i < DENALI_NR_BANKS; i++)
157 denali_clear_irq(denali, i, U32_MAX);
160 static void __denali_check_irq(struct denali_nand_info *denali)
165 for (i = 0; i < DENALI_NR_BANKS; i++) {
166 irq_status = ioread32(denali->reg + INTR_STATUS(i));
167 denali_clear_irq(denali, i, irq_status);
169 if (i != denali->active_bank)
172 denali->irq_status |= irq_status;
176 static void denali_reset_irq(struct denali_nand_info *denali)
178 denali->irq_status = 0;
179 denali->irq_mask = 0;
182 static uint32_t denali_wait_for_irq(struct denali_nand_info *denali,
185 unsigned long time_left = 1000000;
188 __denali_check_irq(denali);
190 if (irq_mask & denali->irq_status)
191 return denali->irq_status;
197 dev_err(denali->dev, "timeout while waiting for irq 0x%x\n",
202 return denali->irq_status;
205 static uint32_t denali_check_irq(struct denali_nand_info *denali)
207 __denali_check_irq(denali);
209 return denali->irq_status;
212 static void denali_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
214 struct denali_nand_info *denali = mtd_to_denali(mtd);
215 u32 addr = DENALI_MAP11_DATA | DENALI_BANK(denali);
218 for (i = 0; i < len; i++)
219 buf[i] = denali->host_read(denali, addr);
222 static void denali_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
224 struct denali_nand_info *denali = mtd_to_denali(mtd);
225 u32 addr = DENALI_MAP11_DATA | DENALI_BANK(denali);
228 for (i = 0; i < len; i++)
229 denali->host_write(denali, addr, buf[i]);
232 static void denali_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)
234 struct denali_nand_info *denali = mtd_to_denali(mtd);
235 u32 addr = DENALI_MAP11_DATA | DENALI_BANK(denali);
236 uint16_t *buf16 = (uint16_t *)buf;
239 for (i = 0; i < len / 2; i++)
240 buf16[i] = denali->host_read(denali, addr);
243 static void denali_write_buf16(struct mtd_info *mtd, const uint8_t *buf,
246 struct denali_nand_info *denali = mtd_to_denali(mtd);
247 u32 addr = DENALI_MAP11_DATA | DENALI_BANK(denali);
248 const uint16_t *buf16 = (const uint16_t *)buf;
251 for (i = 0; i < len / 2; i++)
252 denali->host_write(denali, addr, buf16[i]);
255 static uint8_t denali_read_byte(struct mtd_info *mtd)
259 denali_read_buf(mtd, &byte, 1);
264 static void denali_write_byte(struct mtd_info *mtd, uint8_t byte)
266 denali_write_buf(mtd, &byte, 1);
269 static uint16_t denali_read_word(struct mtd_info *mtd)
273 denali_read_buf16(mtd, (uint8_t *)&word, 2);
278 static void denali_cmd_ctrl(struct mtd_info *mtd, int dat, unsigned int ctrl)
280 struct denali_nand_info *denali = mtd_to_denali(mtd);
284 type = DENALI_MAP11_CMD;
285 else if (ctrl & NAND_ALE)
286 type = DENALI_MAP11_ADDR;
291 * Some commands are followed by chip->dev_ready or chip->waitfunc.
292 * irq_status must be cleared here to catch the R/B# interrupt later.
294 if (ctrl & NAND_CTRL_CHANGE)
295 denali_reset_irq(denali);
297 denali->host_write(denali, DENALI_BANK(denali) | type, dat);
300 static int denali_dev_ready(struct mtd_info *mtd)
302 struct denali_nand_info *denali = mtd_to_denali(mtd);
304 return !!(denali_check_irq(denali) & INTR__INT_ACT);
307 static int denali_check_erased_page(struct mtd_info *mtd,
308 struct nand_chip *chip, uint8_t *buf,
309 unsigned long uncor_ecc_flags,
310 unsigned int max_bitflips)
312 uint8_t *ecc_code = chip->buffers->ecccode;
313 int ecc_steps = chip->ecc.steps;
314 int ecc_size = chip->ecc.size;
315 int ecc_bytes = chip->ecc.bytes;
318 ret = mtd_ooblayout_get_eccbytes(mtd, ecc_code, chip->oob_poi, 0,
323 for (i = 0; i < ecc_steps; i++) {
324 if (!(uncor_ecc_flags & BIT(i)))
327 stat = nand_check_erased_ecc_chunk(buf, ecc_size,
332 mtd->ecc_stats.failed++;
334 mtd->ecc_stats.corrected += stat;
335 max_bitflips = max_t(unsigned int, max_bitflips, stat);
339 ecc_code += ecc_bytes;
345 static int denali_hw_ecc_fixup(struct mtd_info *mtd,
346 struct denali_nand_info *denali,
347 unsigned long *uncor_ecc_flags)
349 struct nand_chip *chip = mtd_to_nand(mtd);
350 int bank = denali->active_bank;
352 unsigned int max_bitflips;
354 ecc_cor = ioread32(denali->reg + ECC_COR_INFO(bank));
355 ecc_cor >>= ECC_COR_INFO__SHIFT(bank);
357 if (ecc_cor & ECC_COR_INFO__UNCOR_ERR) {
359 * This flag is set when uncorrectable error occurs at least in
360 * one ECC sector. We can not know "how many sectors", or
361 * "which sector(s)". We need erase-page check for all sectors.
363 *uncor_ecc_flags = GENMASK(chip->ecc.steps - 1, 0);
367 max_bitflips = FIELD_GET(ECC_COR_INFO__MAX_ERRORS, ecc_cor);
370 * The register holds the maximum of per-sector corrected bitflips.
371 * This is suitable for the return value of the ->read_page() callback.
372 * Unfortunately, we can not know the total number of corrected bits in
373 * the page. Increase the stats by max_bitflips. (compromised solution)
375 mtd->ecc_stats.corrected += max_bitflips;
380 static int denali_sw_ecc_fixup(struct mtd_info *mtd,
381 struct denali_nand_info *denali,
382 unsigned long *uncor_ecc_flags, uint8_t *buf)
384 unsigned int ecc_size = denali->nand.ecc.size;
385 unsigned int bitflips = 0;
386 unsigned int max_bitflips = 0;
387 uint32_t err_addr, err_cor_info;
388 unsigned int err_byte, err_sector, err_device;
389 uint8_t err_cor_value;
390 unsigned int prev_sector = 0;
393 denali_reset_irq(denali);
396 err_addr = ioread32(denali->reg + ECC_ERROR_ADDRESS);
397 err_sector = FIELD_GET(ECC_ERROR_ADDRESS__SECTOR, err_addr);
398 err_byte = FIELD_GET(ECC_ERROR_ADDRESS__OFFSET, err_addr);
400 err_cor_info = ioread32(denali->reg + ERR_CORRECTION_INFO);
401 err_cor_value = FIELD_GET(ERR_CORRECTION_INFO__BYTE,
403 err_device = FIELD_GET(ERR_CORRECTION_INFO__DEVICE,
406 /* reset the bitflip counter when crossing ECC sector */
407 if (err_sector != prev_sector)
410 if (err_cor_info & ERR_CORRECTION_INFO__UNCOR) {
412 * Check later if this is a real ECC error, or
415 *uncor_ecc_flags |= BIT(err_sector);
416 } else if (err_byte < ecc_size) {
418 * If err_byte is larger than ecc_size, means error
419 * happened in OOB, so we ignore it. It's no need for
420 * us to correct it err_device is represented the NAND
421 * error bits are happened in if there are more than
422 * one NAND connected.
425 unsigned int flips_in_byte;
427 offset = (err_sector * ecc_size + err_byte) *
428 denali->devs_per_cs + err_device;
430 /* correct the ECC error */
431 flips_in_byte = hweight8(buf[offset] ^ err_cor_value);
432 buf[offset] ^= err_cor_value;
433 mtd->ecc_stats.corrected += flips_in_byte;
434 bitflips += flips_in_byte;
436 max_bitflips = max(max_bitflips, bitflips);
439 prev_sector = err_sector;
440 } while (!(err_cor_info & ERR_CORRECTION_INFO__LAST_ERR));
443 * Once handle all ECC errors, controller will trigger an
444 * ECC_TRANSACTION_DONE interrupt.
446 irq_status = denali_wait_for_irq(denali, INTR__ECC_TRANSACTION_DONE);
447 if (!(irq_status & INTR__ECC_TRANSACTION_DONE))
453 static void denali_setup_dma64(struct denali_nand_info *denali,
454 dma_addr_t dma_addr, int page, int write)
457 const int page_count = 1;
459 mode = DENALI_MAP10 | DENALI_BANK(denali) | page;
461 /* DMA is a three step process */
464 * 1. setup transfer type, interrupt when complete,
465 * burst len = 64 bytes, the number of pages
467 denali->host_write(denali, mode,
468 0x01002000 | (64 << 16) | (write << 8) | page_count);
470 /* 2. set memory low address */
471 denali->host_write(denali, mode, lower_32_bits(dma_addr));
473 /* 3. set memory high address */
474 denali->host_write(denali, mode, upper_32_bits(dma_addr));
477 static void denali_setup_dma32(struct denali_nand_info *denali,
478 dma_addr_t dma_addr, int page, int write)
481 const int page_count = 1;
483 mode = DENALI_MAP10 | DENALI_BANK(denali);
485 /* DMA is a four step process */
487 /* 1. setup transfer type and # of pages */
488 denali->host_write(denali, mode | page,
489 0x2000 | (write << 8) | page_count);
491 /* 2. set memory high address bits 23:8 */
492 denali->host_write(denali, mode | ((dma_addr >> 16) << 8), 0x2200);
494 /* 3. set memory low address bits 23:8 */
495 denali->host_write(denali, mode | ((dma_addr & 0xffff) << 8), 0x2300);
497 /* 4. interrupt when complete, burst len = 64 bytes */
498 denali->host_write(denali, mode | 0x14000, 0x2400);
501 static int denali_pio_read(struct denali_nand_info *denali, void *buf,
502 size_t size, int page, int raw)
504 u32 addr = DENALI_MAP01 | DENALI_BANK(denali) | page;
505 uint32_t *buf32 = (uint32_t *)buf;
506 uint32_t irq_status, ecc_err_mask;
509 if (denali->caps & DENALI_CAP_HW_ECC_FIXUP)
510 ecc_err_mask = INTR__ECC_UNCOR_ERR;
512 ecc_err_mask = INTR__ECC_ERR;
514 denali_reset_irq(denali);
516 for (i = 0; i < size / 4; i++)
517 *buf32++ = denali->host_read(denali, addr);
519 irq_status = denali_wait_for_irq(denali, INTR__PAGE_XFER_INC);
520 if (!(irq_status & INTR__PAGE_XFER_INC))
523 if (irq_status & INTR__ERASED_PAGE)
524 memset(buf, 0xff, size);
526 return irq_status & ecc_err_mask ? -EBADMSG : 0;
529 static int denali_pio_write(struct denali_nand_info *denali,
530 const void *buf, size_t size, int page, int raw)
532 u32 addr = DENALI_MAP01 | DENALI_BANK(denali) | page;
533 const uint32_t *buf32 = (uint32_t *)buf;
537 denali_reset_irq(denali);
539 for (i = 0; i < size / 4; i++)
540 denali->host_write(denali, addr, *buf32++);
542 irq_status = denali_wait_for_irq(denali,
543 INTR__PROGRAM_COMP | INTR__PROGRAM_FAIL);
544 if (!(irq_status & INTR__PROGRAM_COMP))
550 static int denali_pio_xfer(struct denali_nand_info *denali, void *buf,
551 size_t size, int page, int raw, int write)
554 return denali_pio_write(denali, buf, size, page, raw);
556 return denali_pio_read(denali, buf, size, page, raw);
559 static int denali_dma_xfer(struct denali_nand_info *denali, void *buf,
560 size_t size, int page, int raw, int write)
563 uint32_t irq_mask, irq_status, ecc_err_mask;
564 enum dma_data_direction dir = write ? DMA_TO_DEVICE : DMA_FROM_DEVICE;
567 dma_addr = dma_map_single(denali->dev, buf, size, dir);
568 if (dma_mapping_error(denali->dev, dma_addr)) {
569 dev_dbg(denali->dev, "Failed to DMA-map buffer. Trying PIO.\n");
570 return denali_pio_xfer(denali, buf, size, page, raw, write);
575 * INTR__PROGRAM_COMP is never asserted for the DMA transfer.
576 * We can use INTR__DMA_CMD_COMP instead. This flag is asserted
577 * when the page program is completed.
579 irq_mask = INTR__DMA_CMD_COMP | INTR__PROGRAM_FAIL;
581 } else if (denali->caps & DENALI_CAP_HW_ECC_FIXUP) {
582 irq_mask = INTR__DMA_CMD_COMP;
583 ecc_err_mask = INTR__ECC_UNCOR_ERR;
585 irq_mask = INTR__DMA_CMD_COMP;
586 ecc_err_mask = INTR__ECC_ERR;
589 iowrite32(DMA_ENABLE__FLAG, denali->reg + DMA_ENABLE);
591 * The ->setup_dma() hook kicks DMA by using the data/command
592 * interface, which belongs to a different AXI port from the
593 * register interface. Read back the register to avoid a race.
595 ioread32(denali->reg + DMA_ENABLE);
597 denali_reset_irq(denali);
598 denali->setup_dma(denali, dma_addr, page, write);
600 irq_status = denali_wait_for_irq(denali, irq_mask);
601 if (!(irq_status & INTR__DMA_CMD_COMP))
603 else if (irq_status & ecc_err_mask)
606 iowrite32(0, denali->reg + DMA_ENABLE);
608 dma_unmap_single(denali->dev, dma_addr, size, dir);
610 if (irq_status & INTR__ERASED_PAGE)
611 memset(buf, 0xff, size);
616 static int denali_data_xfer(struct denali_nand_info *denali, void *buf,
617 size_t size, int page, int raw, int write)
619 iowrite32(raw ? 0 : ECC_ENABLE__FLAG, denali->reg + ECC_ENABLE);
620 iowrite32(raw ? TRANSFER_SPARE_REG__FLAG : 0,
621 denali->reg + TRANSFER_SPARE_REG);
623 if (denali->dma_avail)
624 return denali_dma_xfer(denali, buf, size, page, raw, write);
626 return denali_pio_xfer(denali, buf, size, page, raw, write);
629 static void denali_oob_xfer(struct mtd_info *mtd, struct nand_chip *chip,
632 struct denali_nand_info *denali = mtd_to_denali(mtd);
633 unsigned int start_cmd = write ? NAND_CMD_SEQIN : NAND_CMD_READ0;
634 unsigned int rnd_cmd = write ? NAND_CMD_RNDIN : NAND_CMD_RNDOUT;
635 int writesize = mtd->writesize;
636 int oobsize = mtd->oobsize;
637 uint8_t *bufpoi = chip->oob_poi;
638 int ecc_steps = chip->ecc.steps;
639 int ecc_size = chip->ecc.size;
640 int ecc_bytes = chip->ecc.bytes;
641 int oob_skip = denali->oob_skip_bytes;
642 size_t size = writesize + oobsize;
645 /* BBM at the beginning of the OOB area */
646 chip->cmdfunc(mtd, start_cmd, writesize, page);
648 chip->write_buf(mtd, bufpoi, oob_skip);
650 chip->read_buf(mtd, bufpoi, oob_skip);
654 for (i = 0; i < ecc_steps; i++) {
655 pos = ecc_size + i * (ecc_size + ecc_bytes);
658 if (pos >= writesize)
660 else if (pos + len > writesize)
661 len = writesize - pos;
663 chip->cmdfunc(mtd, rnd_cmd, pos, -1);
665 chip->write_buf(mtd, bufpoi, len);
667 chip->read_buf(mtd, bufpoi, len);
669 if (len < ecc_bytes) {
670 len = ecc_bytes - len;
671 chip->cmdfunc(mtd, rnd_cmd, writesize + oob_skip, -1);
673 chip->write_buf(mtd, bufpoi, len);
675 chip->read_buf(mtd, bufpoi, len);
681 len = oobsize - (bufpoi - chip->oob_poi);
682 chip->cmdfunc(mtd, rnd_cmd, size - len, -1);
684 chip->write_buf(mtd, bufpoi, len);
686 chip->read_buf(mtd, bufpoi, len);
689 static int denali_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
690 uint8_t *buf, int oob_required, int page)
692 struct denali_nand_info *denali = mtd_to_denali(mtd);
693 int writesize = mtd->writesize;
694 int oobsize = mtd->oobsize;
695 int ecc_steps = chip->ecc.steps;
696 int ecc_size = chip->ecc.size;
697 int ecc_bytes = chip->ecc.bytes;
698 void *tmp_buf = denali->buf;
699 int oob_skip = denali->oob_skip_bytes;
700 size_t size = writesize + oobsize;
701 int ret, i, pos, len;
703 ret = denali_data_xfer(denali, tmp_buf, size, page, 1, 0);
707 /* Arrange the buffer for syndrome payload/ecc layout */
709 for (i = 0; i < ecc_steps; i++) {
710 pos = i * (ecc_size + ecc_bytes);
713 if (pos >= writesize)
715 else if (pos + len > writesize)
716 len = writesize - pos;
718 memcpy(buf, tmp_buf + pos, len);
720 if (len < ecc_size) {
721 len = ecc_size - len;
722 memcpy(buf, tmp_buf + writesize + oob_skip,
730 uint8_t *oob = chip->oob_poi;
732 /* BBM at the beginning of the OOB area */
733 memcpy(oob, tmp_buf + writesize, oob_skip);
737 for (i = 0; i < ecc_steps; i++) {
738 pos = ecc_size + i * (ecc_size + ecc_bytes);
741 if (pos >= writesize)
743 else if (pos + len > writesize)
744 len = writesize - pos;
746 memcpy(oob, tmp_buf + pos, len);
748 if (len < ecc_bytes) {
749 len = ecc_bytes - len;
750 memcpy(oob, tmp_buf + writesize + oob_skip,
757 len = oobsize - (oob - chip->oob_poi);
758 memcpy(oob, tmp_buf + size - len, len);
764 static int denali_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
767 denali_oob_xfer(mtd, chip, page, 0);
772 static int denali_write_oob(struct mtd_info *mtd, struct nand_chip *chip,
775 struct denali_nand_info *denali = mtd_to_denali(mtd);
778 denali_reset_irq(denali);
780 denali_oob_xfer(mtd, chip, page, 1);
782 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
783 status = chip->waitfunc(mtd, chip);
785 return status & NAND_STATUS_FAIL ? -EIO : 0;
788 static int denali_read_page(struct mtd_info *mtd, struct nand_chip *chip,
789 uint8_t *buf, int oob_required, int page)
791 struct denali_nand_info *denali = mtd_to_denali(mtd);
792 unsigned long uncor_ecc_flags = 0;
796 ret = denali_data_xfer(denali, buf, mtd->writesize, page, 0, 0);
797 if (ret && ret != -EBADMSG)
800 if (denali->caps & DENALI_CAP_HW_ECC_FIXUP)
801 stat = denali_hw_ecc_fixup(mtd, denali, &uncor_ecc_flags);
802 else if (ret == -EBADMSG)
803 stat = denali_sw_ecc_fixup(mtd, denali, &uncor_ecc_flags, buf);
808 if (uncor_ecc_flags) {
809 ret = denali_read_oob(mtd, chip, page);
813 stat = denali_check_erased_page(mtd, chip, buf,
814 uncor_ecc_flags, stat);
820 static int denali_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
821 const uint8_t *buf, int oob_required, int page)
823 struct denali_nand_info *denali = mtd_to_denali(mtd);
824 int writesize = mtd->writesize;
825 int oobsize = mtd->oobsize;
826 int ecc_steps = chip->ecc.steps;
827 int ecc_size = chip->ecc.size;
828 int ecc_bytes = chip->ecc.bytes;
829 void *tmp_buf = denali->buf;
830 int oob_skip = denali->oob_skip_bytes;
831 size_t size = writesize + oobsize;
835 * Fill the buffer with 0xff first except the full page transfer.
836 * This simplifies the logic.
838 if (!buf || !oob_required)
839 memset(tmp_buf, 0xff, size);
841 /* Arrange the buffer for syndrome payload/ecc layout */
843 for (i = 0; i < ecc_steps; i++) {
844 pos = i * (ecc_size + ecc_bytes);
847 if (pos >= writesize)
849 else if (pos + len > writesize)
850 len = writesize - pos;
852 memcpy(tmp_buf + pos, buf, len);
854 if (len < ecc_size) {
855 len = ecc_size - len;
856 memcpy(tmp_buf + writesize + oob_skip, buf,
864 const uint8_t *oob = chip->oob_poi;
866 /* BBM at the beginning of the OOB area */
867 memcpy(tmp_buf + writesize, oob, oob_skip);
871 for (i = 0; i < ecc_steps; i++) {
872 pos = ecc_size + i * (ecc_size + ecc_bytes);
875 if (pos >= writesize)
877 else if (pos + len > writesize)
878 len = writesize - pos;
880 memcpy(tmp_buf + pos, oob, len);
882 if (len < ecc_bytes) {
883 len = ecc_bytes - len;
884 memcpy(tmp_buf + writesize + oob_skip, oob,
891 len = oobsize - (oob - chip->oob_poi);
892 memcpy(tmp_buf + size - len, oob, len);
895 return denali_data_xfer(denali, tmp_buf, size, page, 1, 1);
898 static int denali_write_page(struct mtd_info *mtd, struct nand_chip *chip,
899 const uint8_t *buf, int oob_required, int page)
901 struct denali_nand_info *denali = mtd_to_denali(mtd);
903 return denali_data_xfer(denali, (void *)buf, mtd->writesize,
907 static void denali_select_chip(struct mtd_info *mtd, int chip)
909 struct denali_nand_info *denali = mtd_to_denali(mtd);
911 denali->active_bank = chip;
914 static int denali_waitfunc(struct mtd_info *mtd, struct nand_chip *chip)
916 struct denali_nand_info *denali = mtd_to_denali(mtd);
919 /* R/B# pin transitioned from low to high? */
920 irq_status = denali_wait_for_irq(denali, INTR__INT_ACT);
922 return irq_status & INTR__INT_ACT ? 0 : NAND_STATUS_FAIL;
925 static int denali_erase(struct mtd_info *mtd, int page)
927 struct denali_nand_info *denali = mtd_to_denali(mtd);
930 denali_reset_irq(denali);
932 denali->host_write(denali, DENALI_MAP10 | DENALI_BANK(denali) | page,
935 /* wait for erase to complete or failure to occur */
936 irq_status = denali_wait_for_irq(denali,
937 INTR__ERASE_COMP | INTR__ERASE_FAIL);
939 return irq_status & INTR__ERASE_COMP ? 0 : NAND_STATUS_FAIL;
942 static int denali_setup_data_interface(struct mtd_info *mtd, int chipnr,
943 const struct nand_data_interface *conf)
945 struct denali_nand_info *denali = mtd_to_denali(mtd);
946 const struct nand_sdr_timings *timings;
947 unsigned long t_x, mult_x;
948 int acc_clks, re_2_we, re_2_re, we_2_re, addr_2_data;
949 int rdwr_en_lo, rdwr_en_hi, rdwr_en_lo_hi, cs_setup;
950 int addr_2_data_mask;
953 timings = nand_get_sdr_timings(conf);
955 return PTR_ERR(timings);
957 /* clk_x period in picoseconds */
958 t_x = DIV_ROUND_DOWN_ULL(1000000000000ULL, denali->clk_x_rate);
963 * The bus interface clock, clk_x, is phase aligned with the core clock.
964 * The clk_x is an integral multiple N of the core clk. The value N is
965 * configured at IP delivery time, and its available value is 4, 5, 6.
967 mult_x = DIV_ROUND_CLOSEST_ULL(denali->clk_x_rate, denali->clk_rate);
968 if (mult_x < 4 || mult_x > 6)
971 if (chipnr == NAND_DATA_IFACE_CHECK_ONLY)
974 /* tREA -> ACC_CLKS */
975 acc_clks = DIV_ROUND_UP(timings->tREA_max, t_x);
976 acc_clks = min_t(int, acc_clks, ACC_CLKS__VALUE);
978 tmp = ioread32(denali->reg + ACC_CLKS);
979 tmp &= ~ACC_CLKS__VALUE;
980 tmp |= FIELD_PREP(ACC_CLKS__VALUE, acc_clks);
981 iowrite32(tmp, denali->reg + ACC_CLKS);
983 /* tRWH -> RE_2_WE */
984 re_2_we = DIV_ROUND_UP(timings->tRHW_min, t_x);
985 re_2_we = min_t(int, re_2_we, RE_2_WE__VALUE);
987 tmp = ioread32(denali->reg + RE_2_WE);
988 tmp &= ~RE_2_WE__VALUE;
989 tmp |= FIELD_PREP(RE_2_WE__VALUE, re_2_we);
990 iowrite32(tmp, denali->reg + RE_2_WE);
992 /* tRHZ -> RE_2_RE */
993 re_2_re = DIV_ROUND_UP(timings->tRHZ_max, t_x);
994 re_2_re = min_t(int, re_2_re, RE_2_RE__VALUE);
996 tmp = ioread32(denali->reg + RE_2_RE);
997 tmp &= ~RE_2_RE__VALUE;
998 tmp |= FIELD_PREP(RE_2_RE__VALUE, re_2_re);
999 iowrite32(tmp, denali->reg + RE_2_RE);
1002 * tCCS, tWHR -> WE_2_RE
1004 * With WE_2_RE properly set, the Denali controller automatically takes
1005 * care of the delay; the driver need not set NAND_WAIT_TCCS.
1007 we_2_re = DIV_ROUND_UP(max(timings->tCCS_min, timings->tWHR_min), t_x);
1008 we_2_re = min_t(int, we_2_re, TWHR2_AND_WE_2_RE__WE_2_RE);
1010 tmp = ioread32(denali->reg + TWHR2_AND_WE_2_RE);
1011 tmp &= ~TWHR2_AND_WE_2_RE__WE_2_RE;
1012 tmp |= FIELD_PREP(TWHR2_AND_WE_2_RE__WE_2_RE, we_2_re);
1013 iowrite32(tmp, denali->reg + TWHR2_AND_WE_2_RE);
1015 /* tADL -> ADDR_2_DATA */
1017 /* for older versions, ADDR_2_DATA is only 6 bit wide */
1018 addr_2_data_mask = TCWAW_AND_ADDR_2_DATA__ADDR_2_DATA;
1019 if (denali->revision < 0x0501)
1020 addr_2_data_mask >>= 1;
1022 addr_2_data = DIV_ROUND_UP(timings->tADL_min, t_x);
1023 addr_2_data = min_t(int, addr_2_data, addr_2_data_mask);
1025 tmp = ioread32(denali->reg + TCWAW_AND_ADDR_2_DATA);
1026 tmp &= ~TCWAW_AND_ADDR_2_DATA__ADDR_2_DATA;
1027 tmp |= FIELD_PREP(TCWAW_AND_ADDR_2_DATA__ADDR_2_DATA, addr_2_data);
1028 iowrite32(tmp, denali->reg + TCWAW_AND_ADDR_2_DATA);
1030 /* tREH, tWH -> RDWR_EN_HI_CNT */
1031 rdwr_en_hi = DIV_ROUND_UP(max(timings->tREH_min, timings->tWH_min),
1033 rdwr_en_hi = min_t(int, rdwr_en_hi, RDWR_EN_HI_CNT__VALUE);
1035 tmp = ioread32(denali->reg + RDWR_EN_HI_CNT);
1036 tmp &= ~RDWR_EN_HI_CNT__VALUE;
1037 tmp |= FIELD_PREP(RDWR_EN_HI_CNT__VALUE, rdwr_en_hi);
1038 iowrite32(tmp, denali->reg + RDWR_EN_HI_CNT);
1040 /* tRP, tWP -> RDWR_EN_LO_CNT */
1041 rdwr_en_lo = DIV_ROUND_UP(max(timings->tRP_min, timings->tWP_min), t_x);
1042 rdwr_en_lo_hi = DIV_ROUND_UP(max(timings->tRC_min, timings->tWC_min),
1044 rdwr_en_lo_hi = max_t(int, rdwr_en_lo_hi, mult_x);
1045 rdwr_en_lo = max(rdwr_en_lo, rdwr_en_lo_hi - rdwr_en_hi);
1046 rdwr_en_lo = min_t(int, rdwr_en_lo, RDWR_EN_LO_CNT__VALUE);
1048 tmp = ioread32(denali->reg + RDWR_EN_LO_CNT);
1049 tmp &= ~RDWR_EN_LO_CNT__VALUE;
1050 tmp |= FIELD_PREP(RDWR_EN_LO_CNT__VALUE, rdwr_en_lo);
1051 iowrite32(tmp, denali->reg + RDWR_EN_LO_CNT);
1053 /* tCS, tCEA -> CS_SETUP_CNT */
1054 cs_setup = max3((int)DIV_ROUND_UP(timings->tCS_min, t_x) - rdwr_en_lo,
1055 (int)DIV_ROUND_UP(timings->tCEA_max, t_x) - acc_clks,
1057 cs_setup = min_t(int, cs_setup, CS_SETUP_CNT__VALUE);
1059 tmp = ioread32(denali->reg + CS_SETUP_CNT);
1060 tmp &= ~CS_SETUP_CNT__VALUE;
1061 tmp |= FIELD_PREP(CS_SETUP_CNT__VALUE, cs_setup);
1062 iowrite32(tmp, denali->reg + CS_SETUP_CNT);
1067 static void denali_reset_banks(struct denali_nand_info *denali)
1072 for (i = 0; i < denali->max_banks; i++) {
1073 denali->active_bank = i;
1075 denali_reset_irq(denali);
1077 iowrite32(DEVICE_RESET__BANK(i),
1078 denali->reg + DEVICE_RESET);
1080 irq_status = denali_wait_for_irq(denali,
1081 INTR__RST_COMP | INTR__INT_ACT | INTR__TIME_OUT);
1082 if (!(irq_status & INTR__INT_ACT))
1086 dev_dbg(denali->dev, "%d chips connected\n", i);
1087 denali->max_banks = i;
1090 static void denali_hw_init(struct denali_nand_info *denali)
1093 * The REVISION register may not be reliable. Platforms are allowed to
1096 if (!denali->revision)
1097 denali->revision = swab16(ioread32(denali->reg + REVISION));
1100 * tell driver how many bit controller will skip before writing
1101 * ECC code in OOB. This is normally used for bad block marker
1103 denali->oob_skip_bytes = CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES;
1104 iowrite32(denali->oob_skip_bytes, denali->reg + SPARE_AREA_SKIP_BYTES);
1105 denali_detect_max_banks(denali);
1106 iowrite32(0x0F, denali->reg + RB_PIN_ENABLED);
1107 iowrite32(CHIP_EN_DONT_CARE__FLAG, denali->reg + CHIP_ENABLE_DONT_CARE);
1109 iowrite32(0xffff, denali->reg + SPARE_AREA_MARKER);
1112 int denali_calc_ecc_bytes(int step_size, int strength)
1114 /* BCH code. Denali requires ecc.bytes to be multiple of 2 */
1115 return DIV_ROUND_UP(strength * fls(step_size * 8), 16) * 2;
1117 EXPORT_SYMBOL(denali_calc_ecc_bytes);
1119 static int denali_ecc_setup(struct mtd_info *mtd, struct nand_chip *chip,
1120 struct denali_nand_info *denali)
1122 int oobavail = mtd->oobsize - denali->oob_skip_bytes;
1126 * If .size and .strength are already set (usually by DT),
1127 * check if they are supported by this controller.
1129 if (chip->ecc.size && chip->ecc.strength)
1130 return nand_check_ecc_caps(chip, denali->ecc_caps, oobavail);
1133 * We want .size and .strength closest to the chip's requirement
1134 * unless NAND_ECC_MAXIMIZE is requested.
1136 if (!(chip->ecc.options & NAND_ECC_MAXIMIZE)) {
1137 ret = nand_match_ecc_req(chip, denali->ecc_caps, oobavail);
1142 /* Max ECC strength is the last thing we can do */
1143 return nand_maximize_ecc(chip, denali->ecc_caps, oobavail);
1146 static struct nand_ecclayout nand_oob;
1148 static int denali_ooblayout_ecc(struct mtd_info *mtd, int section,
1149 struct mtd_oob_region *oobregion)
1151 struct denali_nand_info *denali = mtd_to_denali(mtd);
1152 struct nand_chip *chip = mtd_to_nand(mtd);
1157 oobregion->offset = denali->oob_skip_bytes;
1158 oobregion->length = chip->ecc.total;
1163 static int denali_ooblayout_free(struct mtd_info *mtd, int section,
1164 struct mtd_oob_region *oobregion)
1166 struct denali_nand_info *denali = mtd_to_denali(mtd);
1167 struct nand_chip *chip = mtd_to_nand(mtd);
1172 oobregion->offset = chip->ecc.total + denali->oob_skip_bytes;
1173 oobregion->length = mtd->oobsize - oobregion->offset;
1178 static const struct mtd_ooblayout_ops denali_ooblayout_ops = {
1179 .ecc = denali_ooblayout_ecc,
1180 .free = denali_ooblayout_free,
1183 static int denali_multidev_fixup(struct denali_nand_info *denali)
1185 struct nand_chip *chip = &denali->nand;
1186 struct mtd_info *mtd = nand_to_mtd(chip);
1189 * Support for multi device:
1190 * When the IP configuration is x16 capable and two x8 chips are
1191 * connected in parallel, DEVICES_CONNECTED should be set to 2.
1192 * In this case, the core framework knows nothing about this fact,
1193 * so we should tell it the _logical_ pagesize and anything necessary.
1195 denali->devs_per_cs = ioread32(denali->reg + DEVICES_CONNECTED);
1198 * On some SoCs, DEVICES_CONNECTED is not auto-detected.
1199 * For those, DEVICES_CONNECTED is left to 0. Set 1 if it is the case.
1201 if (denali->devs_per_cs == 0) {
1202 denali->devs_per_cs = 1;
1203 iowrite32(1, denali->reg + DEVICES_CONNECTED);
1206 if (denali->devs_per_cs == 1)
1209 if (denali->devs_per_cs != 2) {
1210 dev_err(denali->dev, "unsupported number of devices %d\n",
1211 denali->devs_per_cs);
1215 /* 2 chips in parallel */
1217 mtd->erasesize <<= 1;
1218 mtd->writesize <<= 1;
1220 chip->chipsize <<= 1;
1221 chip->page_shift += 1;
1222 chip->phys_erase_shift += 1;
1223 chip->bbt_erase_shift += 1;
1224 chip->chip_shift += 1;
1225 chip->pagemask <<= 1;
1226 chip->ecc.size <<= 1;
1227 chip->ecc.bytes <<= 1;
1228 chip->ecc.strength <<= 1;
1229 denali->oob_skip_bytes <<= 1;
1234 int denali_init(struct denali_nand_info *denali)
1236 struct nand_chip *chip = &denali->nand;
1237 struct mtd_info *mtd = nand_to_mtd(chip);
1238 u32 features = ioread32(denali->reg + FEATURES);
1241 denali_hw_init(denali);
1243 denali_clear_irq_all(denali);
1245 denali_reset_banks(denali);
1247 denali->active_bank = DENALI_INVALID_BANK;
1249 chip->flash_node = dev_of_offset(denali->dev);
1250 /* Fallback to the default name if DT did not give "label" property */
1252 mtd->name = "denali-nand";
1254 chip->select_chip = denali_select_chip;
1255 chip->read_byte = denali_read_byte;
1256 chip->write_byte = denali_write_byte;
1257 chip->read_word = denali_read_word;
1258 chip->cmd_ctrl = denali_cmd_ctrl;
1259 chip->dev_ready = denali_dev_ready;
1260 chip->waitfunc = denali_waitfunc;
1262 if (features & FEATURES__INDEX_ADDR) {
1263 denali->host_read = denali_indexed_read;
1264 denali->host_write = denali_indexed_write;
1266 denali->host_read = denali_direct_read;
1267 denali->host_write = denali_direct_write;
1270 /* clk rate info is needed for setup_data_interface */
1271 if (denali->clk_x_rate)
1272 chip->setup_data_interface = denali_setup_data_interface;
1274 ret = nand_scan_ident(mtd, denali->max_banks, NULL);
1278 if (ioread32(denali->reg + FEATURES) & FEATURES__DMA)
1279 denali->dma_avail = 1;
1281 if (denali->dma_avail) {
1282 chip->buf_align = ARCH_DMA_MINALIGN;
1283 if (denali->caps & DENALI_CAP_DMA_64BIT)
1284 denali->setup_dma = denali_setup_dma64;
1286 denali->setup_dma = denali_setup_dma32;
1288 chip->buf_align = 4;
1291 chip->options |= NAND_USE_BOUNCE_BUFFER;
1292 chip->bbt_options |= NAND_BBT_USE_FLASH;
1293 chip->bbt_options |= NAND_BBT_NO_OOB;
1294 denali->nand.ecc.mode = NAND_ECC_HW_SYNDROME;
1296 /* no subpage writes on denali */
1297 chip->options |= NAND_NO_SUBPAGE_WRITE;
1299 ret = denali_ecc_setup(mtd, chip, denali);
1301 dev_err(denali->dev, "Failed to setup ECC settings.\n");
1305 dev_dbg(denali->dev,
1306 "chosen ECC settings: step=%d, strength=%d, bytes=%d\n",
1307 chip->ecc.size, chip->ecc.strength, chip->ecc.bytes);
1309 iowrite32(FIELD_PREP(ECC_CORRECTION__ERASE_THRESHOLD, 1) |
1310 FIELD_PREP(ECC_CORRECTION__VALUE, chip->ecc.strength),
1311 denali->reg + ECC_CORRECTION);
1312 iowrite32(mtd->erasesize / mtd->writesize,
1313 denali->reg + PAGES_PER_BLOCK);
1314 iowrite32(chip->options & NAND_BUSWIDTH_16 ? 1 : 0,
1315 denali->reg + DEVICE_WIDTH);
1316 iowrite32(chip->options & NAND_ROW_ADDR_3 ? 0 : TWO_ROW_ADDR_CYCLES__FLAG,
1317 denali->reg + TWO_ROW_ADDR_CYCLES);
1318 iowrite32(mtd->writesize, denali->reg + DEVICE_MAIN_AREA_SIZE);
1319 iowrite32(mtd->oobsize, denali->reg + DEVICE_SPARE_AREA_SIZE);
1321 iowrite32(chip->ecc.size, denali->reg + CFG_DATA_BLOCK_SIZE);
1322 iowrite32(chip->ecc.size, denali->reg + CFG_LAST_DATA_BLOCK_SIZE);
1323 /* chip->ecc.steps is set by nand_scan_tail(); not available here */
1324 iowrite32(mtd->writesize / chip->ecc.size,
1325 denali->reg + CFG_NUM_DATA_BLOCKS);
1327 mtd_set_ooblayout(mtd, &denali_ooblayout_ops);
1329 nand_oob.eccbytes = denali->nand.ecc.bytes;
1330 denali->nand.ecc.layout = &nand_oob;
1332 if (chip->options & NAND_BUSWIDTH_16) {
1333 chip->read_buf = denali_read_buf16;
1334 chip->write_buf = denali_write_buf16;
1336 chip->read_buf = denali_read_buf;
1337 chip->write_buf = denali_write_buf;
1339 chip->ecc.options |= NAND_ECC_CUSTOM_PAGE_ACCESS;
1340 chip->ecc.read_page = denali_read_page;
1341 chip->ecc.read_page_raw = denali_read_page_raw;
1342 chip->ecc.write_page = denali_write_page;
1343 chip->ecc.write_page_raw = denali_write_page_raw;
1344 chip->ecc.read_oob = denali_read_oob;
1345 chip->ecc.write_oob = denali_write_oob;
1346 chip->erase = denali_erase;
1348 ret = denali_multidev_fixup(denali);
1353 * This buffer is DMA-mapped by denali_{read,write}_page_raw. Do not
1354 * use devm_kmalloc() because the memory allocated by devm_ does not
1355 * guarantee DMA-safe alignment.
1357 denali->buf = kmalloc(mtd->writesize + mtd->oobsize, GFP_KERNEL);
1361 ret = nand_scan_tail(mtd);
1365 ret = nand_register(0, mtd);
1367 dev_err(denali->dev, "Failed to register MTD: %d\n", ret);