2 * (C) Copyright 2004 Texas Instruments
3 * Jian Zhang <jzhang@ti.com>
5 * Samsung K9F1G08R0AQ0C NAND chip driver for an OMAP2420 board
7 * This file is based on the following u-boot file:
10 * See file CREDITS for list of people who contributed to this
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of
16 * the License, or (at your option) any later version.
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31 #include <asm/arch/sys_proto.h>
32 #include <asm/arch/sys_info.h>
34 #ifdef CFG_NAND_K9F1G08R0A
36 #define K9F1G08R0A_MFR 0xec /* Samsung */
37 #define K9F1G08R0A_ID 0xa1 /* part # */
39 /* Since Micron and Samsung parts are similar in geometry and bus width
40 * we can use the same driver. Need to revisit to make this file independent
41 * of part/manufacturer
43 #define MT29F1G_MFR 0x2c /* Micron */
44 #define MT29F1G_MFR2 0x20 /* numonyx */
45 #define MT29F1G_MFR3 0xad /* Hynix */
46 #define MT29F1G_ID 0xa1 /* x8, 1GiB */
47 #define MT29F2G_ID 0xba /* x16, 2GiB */
48 #define MT29F4G_ID 0xbc /* x16, 4GiB */
52 #define ADDR_COLUMN_PAGE (ADDR_COLUMN | ADDR_PAGE)
54 #define ADDR_OOB (0x4 | ADDR_COLUMN_PAGE)
56 #define PAGE_SIZE 2048
58 #define MAX_NUM_PAGES 64
60 #define ECC_CHECK_ENABLE
64 /*******************************************************
66 * Description: spinning delay to use before udelay works
67 ******************************************************/
68 static inline void delay (unsigned long loops)
70 __asm__ volatile ("1:\n"
72 "bne 1b":"=r" (loops):"0" (loops));
75 static int nand_read_page(u_char *buf, ulong page_addr);
76 static int nand_read_oob(u_char * buf, ulong page_addr);
78 /* JFFS2 large page layout for 3-byte ECC per 256 bytes ECC layout */
79 /* This is the only SW ECC supported by u-boot. So to load u-boot
80 * this should be supported */
81 static u_char ecc_pos[] =
82 {40, 41, 42, 43, 44, 45, 46, 47,
83 48, 49, 50, 51, 52, 53, 54, 55,
84 56, 57, 58, 59, 60, 61, 62, 63};
85 static u_char eccvalid_pos = 4;
87 static unsigned long chipsize = (256 << 20);
90 static int bus_width = 16;
92 static int bus_width = 8;
95 /* NanD_Command: Send a flash command to the flash chip */
96 static int NanD_Command(unsigned char command)
98 NAND_CTL_SETCLE(NAND_ADDR);
100 WRITE_NAND_COMMAND(command, NAND_ADDR);
101 NAND_CTL_CLRCLE(NAND_ADDR);
103 if(command == NAND_CMD_RESET){
104 unsigned char ret_val;
105 NanD_Command(NAND_CMD_STATUS);
107 ret_val = READ_NAND(NAND_ADDR);/* wait till ready */
108 } while((ret_val & 0x40) != 0x40);
116 /* NanD_Address: Set the current address for the flash chip */
117 static int NanD_Address(unsigned int numbytes, unsigned long ofs)
121 NAND_CTL_SETALE(NAND_ADDR);
123 if (numbytes == ADDR_COLUMN || numbytes == ADDR_COLUMN_PAGE
124 || numbytes == ADDR_OOB)
129 WRITE_NAND_ADDRESS(u, NAND_ADDR);
131 u = (col >> 8) & 0x07;
132 if (numbytes == ADDR_OOB)
133 u = u | ((bus_width == 16) ? (1 << 2) : (1 << 3));
134 WRITE_NAND_ADDRESS(u, NAND_ADDR);
137 if (numbytes == ADDR_PAGE || numbytes == ADDR_COLUMN_PAGE
138 || numbytes == ADDR_OOB)
140 u = (ofs >> 11) & 0xff;
141 WRITE_NAND_ADDRESS(u, NAND_ADDR);
142 u = (ofs >> 19) & 0xff;
143 WRITE_NAND_ADDRESS(u, NAND_ADDR);
145 /* One more address cycle for devices > 128MiB */
146 if (chipsize > (128 << 20)) {
147 u = (ofs >> 27) & 0xff;
148 WRITE_NAND_ADDRESS(u, NAND_ADDR);
152 NAND_CTL_CLRALE(NAND_ADDR);
158 int nand_readid(int *mfr, int *id)
162 if (NanD_Command(NAND_CMD_RESET)) {
167 if (NanD_Command(NAND_CMD_READID)) {
172 NanD_Address(ADDR_COLUMN, 0);
174 *mfr = READ_NAND(NAND_ADDR);
175 *id = READ_NAND(NAND_ADDR);
181 /* read chip mfr and id
182 * return 0 if they match board config
191 if (NanD_Command(NAND_CMD_RESET)) {
192 printf("Err: RESET\n");
197 if (NanD_Command(NAND_CMD_READID)) {
198 printf("Err: READID\n");
203 NanD_Address(ADDR_COLUMN, 0);
205 mfr = READ_NAND(NAND_ADDR);
206 id = READ_NAND(NAND_ADDR);
210 if (((mfr == MT29F1G_MFR || mfr == MT29F1G_MFR2 || mfr == MT29F1G_MFR3) &&
211 (id == MT29F1G_ID || id == MT29F2G_ID || id == MT29F4G_ID)) ||
212 (mfr == K9F1G08R0A_MFR && (id == K9F1G08R0A_ID))) {
215 if ((mfr == 0) && (id == 0)) {
216 printf("No NAND detected\n");
219 printf("Unknown chip: mfr was 0x%02x, id was 0x%02x\n", mfr, id);
225 /* read a block data to buf
226 * return 1 if the block is bad or ECC error can't be corrected for any page
229 int nand_read_block(unsigned char *buf, ulong block_addr)
233 #ifdef ECC_CHECK_ENABLE
234 u16 oob_buf[OOB_SIZE >> 1];
236 /* check bad block */
237 /* 0th word in spare area needs be 0xff */
238 if (nand_read_oob(oob_buf, block_addr) || (oob_buf[0] & 0xff) != 0xff){
239 printf("Skipped bad block at 0x%x\n", block_addr);
240 return 1; /* skip bad block */
243 /* read the block page by page*/
244 for (i=0; i<MAX_NUM_PAGES; i++){
245 if (nand_read_page(buf+offset, block_addr + offset))
253 /* read a page with ECC */
254 static int nand_read_page(u_char *buf, ulong page_addr)
256 #ifdef ECC_CHECK_ENABLE
257 u_char ecc_code[ECC_SIZE];
258 u_char ecc_calc[ECC_STEPS];
259 u_char oob_buf[OOB_SIZE];
272 NanD_Command(NAND_CMD_READ0);
273 NanD_Address(ADDR_COLUMN_PAGE, page_addr);
274 NanD_Command(NAND_CMD_READSTART);
277 /* A delay seems to be helping here. needs more investigation */
279 len = (bus_width == 16) ? PAGE_SIZE >> 1 : PAGE_SIZE;
281 for (cntr = 0; cntr < len; cntr++){
282 *p++ = READ_NAND(NAND_ADDR);
286 #ifdef ECC_CHECK_ENABLE
288 len = (bus_width == 16) ? OOB_SIZE >> 1 : OOB_SIZE;
289 for (cntr = 0; cntr < len; cntr++){
290 *p++ = READ_NAND(NAND_ADDR);
294 NAND_DISABLE_CE(); /* set pin high */
296 /* Pick the ECC bytes out of the oob data */
297 for (cntr = 0; cntr < ECC_SIZE; cntr++)
298 ecc_code[cntr] = oob_buf[ecc_pos[cntr]];
300 for(count = 0; count < ECC_SIZE; count += ECC_STEPS) {
301 nand_calculate_ecc (buf, &ecc_calc[0]);
302 if (nand_correct_data (buf, &ecc_code[count], &ecc_calc[0]) == -1) {
303 printf ("ECC Failed, page 0x%08x\n", page_addr);
304 for (val=0; val <256; val++)
305 printf("%x ", buf[val]);
317 /* read from the 16 bytes of oob data that correspond to a 512 / 2048 byte page.
319 static int nand_read_oob(u_char *buf, ulong page_addr)
331 len = (bus_width == 16) ? OOB_SIZE >> 1 : OOB_SIZE;
333 NAND_ENABLE_CE(); /* set pin low */
334 NanD_Command(NAND_CMD_READ0);
335 NanD_Address(ADDR_OOB, page_addr);
336 NanD_Command(NAND_CMD_READSTART);
339 /* A delay seems to be helping here. needs more investigation */
341 for (cntr = 0; cntr < len; cntr++)
342 *p++ = READ_NAND(NAND_ADDR);
345 NAND_DISABLE_CE(); /* set pin high */