drivers/gpu/drm/radeon/radeon_combios.c

   1 /*
   2  * Copyright 2004 ATI Technologies Inc., Markham, Ontario
   3  * Copyright 2007-8 Advanced Micro Devices, Inc.
   4  * Copyright 2008 Red Hat Inc.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  */
  27 #include "drmP.h"
  28 #include "radeon_drm.h"
  29 #include "radeon.h"
  30 #include "atom.h"
  31
  32 #ifdef CONFIG_PPC_PMAC
  33 /* not sure which of these are needed */
  34 #include <asm/machdep.h>
  35 #include <asm/pmac_feature.h>
  36 #include <asm/prom.h>
  37 #include <asm/pci-bridge.h>
  38 #endif /* CONFIG_PPC_PMAC */
  39
  40 /* from radeon_encoder.c */
  41 extern uint32_t
  42 radeon_get_encoder_enum(struct drm_device *dev, uint32_t supported_device,
  43                         uint8_t dac);
  44 extern void radeon_link_encoder_connector(struct drm_device *dev);
  45
  46 /* from radeon_connector.c */
  47 extern void
  48 radeon_add_legacy_connector(struct drm_device *dev,
  49                             uint32_t connector_id,
  50                             uint32_t supported_device,
  51                             int connector_type,
  52                             struct radeon_i2c_bus_rec *i2c_bus,
  53                             uint16_t connector_object_id,
  54                             struct radeon_hpd *hpd);
  55
  56 /* from radeon_legacy_encoder.c */
  57 extern void
  58 radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_enum,
  59                           uint32_t supported_device);
  60
  61 /* old legacy ATI BIOS routines */
  62
  63 /* COMBIOS table offsets */
  64 enum radeon_combios_table_offset {
  65         /* absolute offset tables */
  66         COMBIOS_ASIC_INIT_1_TABLE,
  67         COMBIOS_BIOS_SUPPORT_TABLE,
  68         COMBIOS_DAC_PROGRAMMING_TABLE,
  69         COMBIOS_MAX_COLOR_DEPTH_TABLE,
  70         COMBIOS_CRTC_INFO_TABLE,
  71         COMBIOS_PLL_INFO_TABLE,
  72         COMBIOS_TV_INFO_TABLE,
  73         COMBIOS_DFP_INFO_TABLE,
  74         COMBIOS_HW_CONFIG_INFO_TABLE,
  75         COMBIOS_MULTIMEDIA_INFO_TABLE,
  76         COMBIOS_TV_STD_PATCH_TABLE,
  77         COMBIOS_LCD_INFO_TABLE,
  78         COMBIOS_MOBILE_INFO_TABLE,
  79         COMBIOS_PLL_INIT_TABLE,
  80         COMBIOS_MEM_CONFIG_TABLE,
  81         COMBIOS_SAVE_MASK_TABLE,
  82         COMBIOS_HARDCODED_EDID_TABLE,
  83         COMBIOS_ASIC_INIT_2_TABLE,
  84         COMBIOS_CONNECTOR_INFO_TABLE,
  85         COMBIOS_DYN_CLK_1_TABLE,
  86         COMBIOS_RESERVED_MEM_TABLE,
  87         COMBIOS_EXT_TMDS_INFO_TABLE,
  88         COMBIOS_MEM_CLK_INFO_TABLE,
  89         COMBIOS_EXT_DAC_INFO_TABLE,
  90         COMBIOS_MISC_INFO_TABLE,
  91         COMBIOS_CRT_INFO_TABLE,
  92         COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE,
  93         COMBIOS_COMPONENT_VIDEO_INFO_TABLE,
  94         COMBIOS_FAN_SPEED_INFO_TABLE,
  95         COMBIOS_OVERDRIVE_INFO_TABLE,
  96         COMBIOS_OEM_INFO_TABLE,
  97         COMBIOS_DYN_CLK_2_TABLE,
  98         COMBIOS_POWER_CONNECTOR_INFO_TABLE,
  99         COMBIOS_I2C_INFO_TABLE,
 100         /* relative offset tables */
 101         COMBIOS_ASIC_INIT_3_TABLE,      /* offset from misc info */
 102         COMBIOS_ASIC_INIT_4_TABLE,      /* offset from misc info */
 103         COMBIOS_DETECTED_MEM_TABLE,     /* offset from misc info */
 104         COMBIOS_ASIC_INIT_5_TABLE,      /* offset from misc info */
 105         COMBIOS_RAM_RESET_TABLE,        /* offset from mem config */
 106         COMBIOS_POWERPLAY_INFO_TABLE,   /* offset from mobile info */
 107         COMBIOS_GPIO_INFO_TABLE,        /* offset from mobile info */
 108         COMBIOS_LCD_DDC_INFO_TABLE,     /* offset from mobile info */
 109         COMBIOS_TMDS_POWER_TABLE,       /* offset from mobile info */
 110         COMBIOS_TMDS_POWER_ON_TABLE,    /* offset from tmds power */
 111         COMBIOS_TMDS_POWER_OFF_TABLE,   /* offset from tmds power */
 112 };
 113
 114 enum radeon_combios_ddc {
 115         DDC_NONE_DETECTED,
 116         DDC_MONID,
 117         DDC_DVI,
 118         DDC_VGA,
 119         DDC_CRT2,
 120         DDC_LCD,
 121         DDC_GPIO,
 122 };
 123
 124 enum radeon_combios_connector {
 125         CONNECTOR_NONE_LEGACY,
 126         CONNECTOR_PROPRIETARY_LEGACY,
 127         CONNECTOR_CRT_LEGACY,
 128         CONNECTOR_DVI_I_LEGACY,
 129         CONNECTOR_DVI_D_LEGACY,
 130         CONNECTOR_CTV_LEGACY,
 131         CONNECTOR_STV_LEGACY,
 132         CONNECTOR_UNSUPPORTED_LEGACY
 133 };
 134
 135 const int legacy_connector_convert[] = {
 136         DRM_MODE_CONNECTOR_Unknown,
 137         DRM_MODE_CONNECTOR_DVID,
 138         DRM_MODE_CONNECTOR_VGA,
 139         DRM_MODE_CONNECTOR_DVII,
 140         DRM_MODE_CONNECTOR_DVID,
 141         DRM_MODE_CONNECTOR_Composite,
 142         DRM_MODE_CONNECTOR_SVIDEO,
 143         DRM_MODE_CONNECTOR_Unknown,
 144 };
 145
 146 static uint16_t combios_get_table_offset(struct drm_device *dev,
 147                                          enum radeon_combios_table_offset table)
 148 {
 149         struct radeon_device *rdev = dev->dev_private;
 150         int rev;
 151         uint16_t offset = 0, check_offset;
 152
 153         if (!rdev->bios)
 154                 return 0;
 155
 156         switch (table) {
 157                 /* absolute offset tables */
 158         case COMBIOS_ASIC_INIT_1_TABLE:
 159                 check_offset = RBIOS16(rdev->bios_header_start + 0xc);
 160                 if (check_offset)
 161                         offset = check_offset;
 162                 break;
 163         case COMBIOS_BIOS_SUPPORT_TABLE:
 164                 check_offset = RBIOS16(rdev->bios_header_start + 0x14);
 165                 if (check_offset)
 166                         offset = check_offset;
 167                 break;
 168         case COMBIOS_DAC_PROGRAMMING_TABLE:
 169                 check_offset = RBIOS16(rdev->bios_header_start + 0x2a);
 170                 if (check_offset)
 171                         offset = check_offset;
 172                 break;
 173         case COMBIOS_MAX_COLOR_DEPTH_TABLE:
 174                 check_offset = RBIOS16(rdev->bios_header_start + 0x2c);
 175                 if (check_offset)
 176                         offset = check_offset;
 177                 break;
 178         case COMBIOS_CRTC_INFO_TABLE:
 179                 check_offset = RBIOS16(rdev->bios_header_start + 0x2e);
 180                 if (check_offset)
 181                         offset = check_offset;
 182                 break;
 183         case COMBIOS_PLL_INFO_TABLE:
 184                 check_offset = RBIOS16(rdev->bios_header_start + 0x30);
 185                 if (check_offset)
 186                         offset = check_offset;
 187                 break;
 188         case COMBIOS_TV_INFO_TABLE:
 189                 check_offset = RBIOS16(rdev->bios_header_start + 0x32);
 190                 if (check_offset)
 191                         offset = check_offset;
 192                 break;
 193         case COMBIOS_DFP_INFO_TABLE:
 194                 check_offset = RBIOS16(rdev->bios_header_start + 0x34);
 195                 if (check_offset)
 196                         offset = check_offset;
 197                 break;
 198         case COMBIOS_HW_CONFIG_INFO_TABLE:
 199                 check_offset = RBIOS16(rdev->bios_header_start + 0x36);
 200                 if (check_offset)
 201                         offset = check_offset;
 202                 break;
 203         case COMBIOS_MULTIMEDIA_INFO_TABLE:
 204                 check_offset = RBIOS16(rdev->bios_header_start + 0x38);
 205                 if (check_offset)
 206                         offset = check_offset;
 207                 break;
 208         case COMBIOS_TV_STD_PATCH_TABLE:
 209                 check_offset = RBIOS16(rdev->bios_header_start + 0x3e);
 210                 if (check_offset)
 211                         offset = check_offset;
 212                 break;
 213         case COMBIOS_LCD_INFO_TABLE:
 214                 check_offset = RBIOS16(rdev->bios_header_start + 0x40);
 215                 if (check_offset)
 216                         offset = check_offset;
 217                 break;
 218         case COMBIOS_MOBILE_INFO_TABLE:
 219                 check_offset = RBIOS16(rdev->bios_header_start + 0x42);
 220                 if (check_offset)
 221                         offset = check_offset;
 222                 break;
 223         case COMBIOS_PLL_INIT_TABLE:
 224                 check_offset = RBIOS16(rdev->bios_header_start + 0x46);
 225                 if (check_offset)
 226                         offset = check_offset;
 227                 break;
 228         case COMBIOS_MEM_CONFIG_TABLE:
 229                 check_offset = RBIOS16(rdev->bios_header_start + 0x48);
 230                 if (check_offset)
 231                         offset = check_offset;
 232                 break;
 233         case COMBIOS_SAVE_MASK_TABLE:
 234                 check_offset = RBIOS16(rdev->bios_header_start + 0x4a);
 235                 if (check_offset)
 236                         offset = check_offset;
 237                 break;
 238         case COMBIOS_HARDCODED_EDID_TABLE:
 239                 check_offset = RBIOS16(rdev->bios_header_start + 0x4c);
 240                 if (check_offset)
 241                         offset = check_offset;
 242                 break;
 243         case COMBIOS_ASIC_INIT_2_TABLE:
 244                 check_offset = RBIOS16(rdev->bios_header_start + 0x4e);
 245                 if (check_offset)
 246                         offset = check_offset;
 247                 break;
 248         case COMBIOS_CONNECTOR_INFO_TABLE:
 249                 check_offset = RBIOS16(rdev->bios_header_start + 0x50);
 250                 if (check_offset)
 251                         offset = check_offset;
 252                 break;
 253         case COMBIOS_DYN_CLK_1_TABLE:
 254                 check_offset = RBIOS16(rdev->bios_header_start + 0x52);
 255                 if (check_offset)
 256                         offset = check_offset;
 257                 break;
 258         case COMBIOS_RESERVED_MEM_TABLE:
 259                 check_offset = RBIOS16(rdev->bios_header_start + 0x54);
 260                 if (check_offset)
 261                         offset = check_offset;
 262                 break;
 263         case COMBIOS_EXT_TMDS_INFO_TABLE:
 264                 check_offset = RBIOS16(rdev->bios_header_start + 0x58);
 265                 if (check_offset)
 266                         offset = check_offset;
 267                 break;
 268         case COMBIOS_MEM_CLK_INFO_TABLE:
 269                 check_offset = RBIOS16(rdev->bios_header_start + 0x5a);
 270                 if (check_offset)
 271                         offset = check_offset;
 272                 break;
 273         case COMBIOS_EXT_DAC_INFO_TABLE:
 274                 check_offset = RBIOS16(rdev->bios_header_start + 0x5c);
 275                 if (check_offset)
 276                         offset = check_offset;
 277                 break;
 278         case COMBIOS_MISC_INFO_TABLE:
 279                 check_offset = RBIOS16(rdev->bios_header_start + 0x5e);
 280                 if (check_offset)
 281                         offset = check_offset;
 282                 break;
 283         case COMBIOS_CRT_INFO_TABLE:
 284                 check_offset = RBIOS16(rdev->bios_header_start + 0x60);
 285                 if (check_offset)
 286                         offset = check_offset;
 287                 break;
 288         case COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE:
 289                 check_offset = RBIOS16(rdev->bios_header_start + 0x62);
 290                 if (check_offset)
 291                         offset = check_offset;
 292                 break;
 293         case COMBIOS_COMPONENT_VIDEO_INFO_TABLE:
 294                 check_offset = RBIOS16(rdev->bios_header_start + 0x64);
 295                 if (check_offset)
 296                         offset = check_offset;
 297                 break;
 298         case COMBIOS_FAN_SPEED_INFO_TABLE:
 299                 check_offset = RBIOS16(rdev->bios_header_start + 0x66);
 300                 if (check_offset)
 301                         offset = check_offset;
 302                 break;
 303         case COMBIOS_OVERDRIVE_INFO_TABLE:
 304                 check_offset = RBIOS16(rdev->bios_header_start + 0x68);
 305                 if (check_offset)
 306                         offset = check_offset;
 307                 break;
 308         case COMBIOS_OEM_INFO_TABLE:
 309                 check_offset = RBIOS16(rdev->bios_header_start + 0x6a);
 310                 if (check_offset)
 311                         offset = check_offset;
 312                 break;
 313         case COMBIOS_DYN_CLK_2_TABLE:
 314                 check_offset = RBIOS16(rdev->bios_header_start + 0x6c);
 315                 if (check_offset)
 316                         offset = check_offset;
 317                 break;
 318         case COMBIOS_POWER_CONNECTOR_INFO_TABLE:
 319                 check_offset = RBIOS16(rdev->bios_header_start + 0x6e);
 320                 if (check_offset)
 321                         offset = check_offset;
 322                 break;
 323         case COMBIOS_I2C_INFO_TABLE:
 324                 check_offset = RBIOS16(rdev->bios_header_start + 0x70);
 325                 if (check_offset)
 326                         offset = check_offset;
 327                 break;
 328                 /* relative offset tables */
 329         case COMBIOS_ASIC_INIT_3_TABLE: /* offset from misc info */
 330                 check_offset =
 331                     combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
 332                 if (check_offset) {
 333                         rev = RBIOS8(check_offset);
 334                         if (rev > 0) {
 335                                 check_offset = RBIOS16(check_offset + 0x3);
 336                                 if (check_offset)
 337                                         offset = check_offset;
 338                         }
 339                 }
 340                 break;
 341         case COMBIOS_ASIC_INIT_4_TABLE: /* offset from misc info */
 342                 check_offset =
 343                     combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
 344                 if (check_offset) {
 345                         rev = RBIOS8(check_offset);
 346                         if (rev > 0) {
 347                                 check_offset = RBIOS16(check_offset + 0x5);
 348                                 if (check_offset)
 349                                         offset = check_offset;
 350                         }
 351                 }
 352                 break;
 353         case COMBIOS_DETECTED_MEM_TABLE:        /* offset from misc info */
 354                 check_offset =
 355                     combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
 356                 if (check_offset) {
 357                         rev = RBIOS8(check_offset);
 358                         if (rev > 0) {
 359                                 check_offset = RBIOS16(check_offset + 0x7);
 360                                 if (check_offset)
 361                                         offset = check_offset;
 362                         }
 363                 }
 364                 break;
 365         case COMBIOS_ASIC_INIT_5_TABLE: /* offset from misc info */
 366                 check_offset =
 367                     combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
 368                 if (check_offset) {
 369                         rev = RBIOS8(check_offset);
 370                         if (rev == 2) {
 371                                 check_offset = RBIOS16(check_offset + 0x9);
 372                                 if (check_offset)
 373                                         offset = check_offset;
 374                         }
 375                 }
 376                 break;
 377         case COMBIOS_RAM_RESET_TABLE:   /* offset from mem config */
 378                 check_offset =
 379                     combios_get_table_offset(dev, COMBIOS_MEM_CONFIG_TABLE);
 380                 if (check_offset) {
 381                         while (RBIOS8(check_offset++));
 382                         check_offset += 2;
 383                         if (check_offset)
 384                                 offset = check_offset;
 385                 }
 386                 break;
 387         case COMBIOS_POWERPLAY_INFO_TABLE:      /* offset from mobile info */
 388                 check_offset =
 389                     combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
 390                 if (check_offset) {
 391                         check_offset = RBIOS16(check_offset + 0x11);
 392                         if (check_offset)
 393                                 offset = check_offset;
 394                 }
 395                 break;
 396         case COMBIOS_GPIO_INFO_TABLE:   /* offset from mobile info */
 397                 check_offset =
 398                     combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
 399                 if (check_offset) {
 400                         check_offset = RBIOS16(check_offset + 0x13);
 401                         if (check_offset)
 402                                 offset = check_offset;
 403                 }
 404                 break;
 405         case COMBIOS_LCD_DDC_INFO_TABLE:        /* offset from mobile info */
 406                 check_offset =
 407                     combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
 408                 if (check_offset) {
 409                         check_offset = RBIOS16(check_offset + 0x15);
 410                         if (check_offset)
 411                                 offset = check_offset;
 412                 }
 413                 break;
 414         case COMBIOS_TMDS_POWER_TABLE:  /* offset from mobile info */
 415                 check_offset =
 416                     combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
 417                 if (check_offset) {
 418                         check_offset = RBIOS16(check_offset + 0x17);
 419                         if (check_offset)
 420                                 offset = check_offset;
 421                 }
 422                 break;
 423         case COMBIOS_TMDS_POWER_ON_TABLE:       /* offset from tmds power */
 424                 check_offset =
 425                     combios_get_table_offset(dev, COMBIOS_TMDS_POWER_TABLE);
 426                 if (check_offset) {
 427                         check_offset = RBIOS16(check_offset + 0x2);
 428                         if (check_offset)
 429                                 offset = check_offset;
 430                 }
 431                 break;
 432         case COMBIOS_TMDS_POWER_OFF_TABLE:      /* offset from tmds power */
 433                 check_offset =
 434                     combios_get_table_offset(dev, COMBIOS_TMDS_POWER_TABLE);
 435                 if (check_offset) {
 436                         check_offset = RBIOS16(check_offset + 0x4);
 437                         if (check_offset)
 438                                 offset = check_offset;
 439                 }
 440                 break;
 441         default:
 442                 break;
 443         }
 444
 445         return offset;
 446
 447 }
 448
 449 bool radeon_combios_check_hardcoded_edid(struct radeon_device *rdev)
 450 {
 451         int edid_info, size;
 452         struct edid *edid;
 453         unsigned char *raw;
 454         edid_info = combios_get_table_offset(rdev->ddev, COMBIOS_HARDCODED_EDID_TABLE);
 455         if (!edid_info)
 456                 return false;
 457
 458         raw = rdev->bios + edid_info;
 459         size = EDID_LENGTH * (raw[0x7e] + 1);
 460         edid = kmalloc(size, GFP_KERNEL);
 461         if (edid == NULL)
 462                 return false;
 463
 464         memcpy((unsigned char *)edid, raw, size);
 465
 466         if (!drm_edid_is_valid(edid)) {
 467                 kfree(edid);
 468                 return false;
 469         }
 470
 471         rdev->mode_info.bios_hardcoded_edid = edid;
 472         rdev->mode_info.bios_hardcoded_edid_size = size;
 473         return true;
 474 }
 475
 476 /* this is used for atom LCDs as well */
 477 struct edid *
 478 radeon_bios_get_hardcoded_edid(struct radeon_device *rdev)
 479 {
 480         struct edid *edid;
 481
 482         if (rdev->mode_info.bios_hardcoded_edid) {
 483                 edid = kmalloc(rdev->mode_info.bios_hardcoded_edid_size, GFP_KERNEL);
 484                 if (edid) {
 485                         memcpy((unsigned char *)edid,
 486                                (unsigned char *)rdev->mode_info.bios_hardcoded_edid,
 487                                rdev->mode_info.bios_hardcoded_edid_size);
 488                         return edid;
 489                 }
 490         }
 491         return NULL;
 492 }
 493
 494 static struct radeon_i2c_bus_rec combios_setup_i2c_bus(struct radeon_device *rdev,
 495                                                        enum radeon_combios_ddc ddc,
 496                                                        u32 clk_mask,
 497                                                        u32 data_mask)
 498 {
 499         struct radeon_i2c_bus_rec i2c;
 500         int ddc_line = 0;
 501
 502         /* ddc id            = mask reg
 503          * DDC_NONE_DETECTED = none
 504          * DDC_DVI           = RADEON_GPIO_DVI_DDC
 505          * DDC_VGA           = RADEON_GPIO_VGA_DDC
 506          * DDC_LCD           = RADEON_GPIOPAD_MASK
 507          * DDC_GPIO          = RADEON_MDGPIO_MASK
 508          * r1xx
 509          * DDC_MONID         = RADEON_GPIO_MONID
 510          * DDC_CRT2          = RADEON_GPIO_CRT2_DDC
 511          * r200
 512          * DDC_MONID         = RADEON_GPIO_MONID
 513          * DDC_CRT2          = RADEON_GPIO_DVI_DDC
 514          * r300/r350
 515          * DDC_MONID         = RADEON_GPIO_DVI_DDC
 516          * DDC_CRT2          = RADEON_GPIO_DVI_DDC
 517          * rv2xx/rv3xx
 518          * DDC_MONID         = RADEON_GPIO_MONID
 519          * DDC_CRT2          = RADEON_GPIO_MONID
 520          * rs3xx/rs4xx
 521          * DDC_MONID         = RADEON_GPIOPAD_MASK
 522          * DDC_CRT2          = RADEON_GPIO_MONID
 523          */
 524         switch (ddc) {
 525         case DDC_NONE_DETECTED:
 526         default:
 527                 ddc_line = 0;
 528                 break;
 529         case DDC_DVI:
 530                 ddc_line = RADEON_GPIO_DVI_DDC;
 531                 break;
 532         case DDC_VGA:
 533                 ddc_line = RADEON_GPIO_VGA_DDC;
 534                 break;
 535         case DDC_LCD:
 536                 ddc_line = RADEON_GPIOPAD_MASK;
 537                 break;
 538         case DDC_GPIO:
 539                 ddc_line = RADEON_MDGPIO_MASK;
 540                 break;
 541         case DDC_MONID:
 542                 if (rdev->family == CHIP_RS300 ||
 543                     rdev->family == CHIP_RS400 ||
 544                     rdev->family == CHIP_RS480)
 545                         ddc_line = RADEON_GPIOPAD_MASK;
 546                 else if (rdev->family == CHIP_R300 ||
 547                          rdev->family == CHIP_R350) {
 548                         ddc_line = RADEON_GPIO_DVI_DDC;
 549                         ddc = DDC_DVI;
 550                 } else
 551                         ddc_line = RADEON_GPIO_MONID;
 552                 break;
 553         case DDC_CRT2:
 554                 if (rdev->family == CHIP_R200 ||
 555                     rdev->family == CHIP_R300 ||
 556                     rdev->family == CHIP_R350) {
 557                         ddc_line = RADEON_GPIO_DVI_DDC;
 558                         ddc = DDC_DVI;
 559                 } else if (rdev->family == CHIP_RS300 ||
 560                            rdev->family == CHIP_RS400 ||
 561                            rdev->family == CHIP_RS480)
 562                         ddc_line = RADEON_GPIO_MONID;
 563                 else if (rdev->family >= CHIP_RV350) {
 564                         ddc_line = RADEON_GPIO_MONID;
 565                         ddc = DDC_MONID;
 566                 } else
 567                         ddc_line = RADEON_GPIO_CRT2_DDC;
 568                 break;
 569         }
 570
 571         if (ddc_line == RADEON_GPIOPAD_MASK) {
 572                 i2c.mask_clk_reg = RADEON_GPIOPAD_MASK;
 573                 i2c.mask_data_reg = RADEON_GPIOPAD_MASK;
 574                 i2c.a_clk_reg = RADEON_GPIOPAD_A;
 575                 i2c.a_data_reg = RADEON_GPIOPAD_A;
 576                 i2c.en_clk_reg = RADEON_GPIOPAD_EN;
 577                 i2c.en_data_reg = RADEON_GPIOPAD_EN;
 578                 i2c.y_clk_reg = RADEON_GPIOPAD_Y;
 579                 i2c.y_data_reg = RADEON_GPIOPAD_Y;
 580         } else if (ddc_line == RADEON_MDGPIO_MASK) {
 581                 i2c.mask_clk_reg = RADEON_MDGPIO_MASK;
 582                 i2c.mask_data_reg = RADEON_MDGPIO_MASK;
 583                 i2c.a_clk_reg = RADEON_MDGPIO_A;
 584                 i2c.a_data_reg = RADEON_MDGPIO_A;
 585                 i2c.en_clk_reg = RADEON_MDGPIO_EN;
 586                 i2c.en_data_reg = RADEON_MDGPIO_EN;
 587                 i2c.y_clk_reg = RADEON_MDGPIO_Y;
 588                 i2c.y_data_reg = RADEON_MDGPIO_Y;
 589         } else {
 590                 i2c.mask_clk_reg = ddc_line;
 591                 i2c.mask_data_reg = ddc_line;
 592                 i2c.a_clk_reg = ddc_line;
 593                 i2c.a_data_reg = ddc_line;
 594                 i2c.en_clk_reg = ddc_line;
 595                 i2c.en_data_reg = ddc_line;
 596                 i2c.y_clk_reg = ddc_line;
 597                 i2c.y_data_reg = ddc_line;
 598         }
 599
 600         if (clk_mask && data_mask) {
 601                 /* system specific masks */
 602                 i2c.mask_clk_mask = clk_mask;
 603                 i2c.mask_data_mask = data_mask;
 604                 i2c.a_clk_mask = clk_mask;
 605                 i2c.a_data_mask = data_mask;
 606                 i2c.en_clk_mask = clk_mask;
 607                 i2c.en_data_mask = data_mask;
 608                 i2c.y_clk_mask = clk_mask;
 609                 i2c.y_data_mask = data_mask;
 610         } else if ((ddc_line == RADEON_GPIOPAD_MASK) ||
 611                    (ddc_line == RADEON_MDGPIO_MASK)) {
 612                 /* default gpiopad masks */
 613                 i2c.mask_clk_mask = (0x20 << 8);
 614                 i2c.mask_data_mask = 0x80;
 615                 i2c.a_clk_mask = (0x20 << 8);
 616                 i2c.a_data_mask = 0x80;
 617                 i2c.en_clk_mask = (0x20 << 8);
 618                 i2c.en_data_mask = 0x80;
 619                 i2c.y_clk_mask = (0x20 << 8);
 620                 i2c.y_data_mask = 0x80;
 621         } else {
 622                 /* default masks for ddc pads */
 623                 i2c.mask_clk_mask = RADEON_GPIO_MASK_1;
 624                 i2c.mask_data_mask = RADEON_GPIO_MASK_0;
 625                 i2c.a_clk_mask = RADEON_GPIO_A_1;
 626                 i2c.a_data_mask = RADEON_GPIO_A_0;
 627                 i2c.en_clk_mask = RADEON_GPIO_EN_1;
 628                 i2c.en_data_mask = RADEON_GPIO_EN_0;
 629                 i2c.y_clk_mask = RADEON_GPIO_Y_1;
 630                 i2c.y_data_mask = RADEON_GPIO_Y_0;
 631         }
 632
 633         switch (rdev->family) {
 634         case CHIP_R100:
 635         case CHIP_RV100:
 636         case CHIP_RS100:
 637         case CHIP_RV200:
 638         case CHIP_RS200:
 639         case CHIP_RS300:
 640                 switch (ddc_line) {
 641                 case RADEON_GPIO_DVI_DDC:
 642                         i2c.hw_capable = true;
 643                         break;
 644                 default:
 645                         i2c.hw_capable = false;
 646                         break;
 647                 }
 648                 break;
 649         case CHIP_R200:
 650                 switch (ddc_line) {
 651                 case RADEON_GPIO_DVI_DDC:
 652                 case RADEON_GPIO_MONID:
 653                         i2c.hw_capable = true;
 654                         break;
 655                 default:
 656                         i2c.hw_capable = false;
 657                         break;
 658                 }
 659                 break;
 660         case CHIP_RV250:
 661         case CHIP_RV280:
 662                 switch (ddc_line) {
 663                 case RADEON_GPIO_VGA_DDC:
 664                 case RADEON_GPIO_DVI_DDC:
 665                 case RADEON_GPIO_CRT2_DDC:
 666                         i2c.hw_capable = true;
 667                         break;
 668                 default:
 669                         i2c.hw_capable = false;
 670                         break;
 671                 }
 672                 break;
 673         case CHIP_R300:
 674         case CHIP_R350:
 675                 switch (ddc_line) {
 676                 case RADEON_GPIO_VGA_DDC:
 677                 case RADEON_GPIO_DVI_DDC:
 678                         i2c.hw_capable = true;
 679                         break;
 680                 default:
 681                         i2c.hw_capable = false;
 682                         break;
 683                 }
 684                 break;
 685         case CHIP_RV350:
 686         case CHIP_RV380:
 687         case CHIP_RS400:
 688         case CHIP_RS480:
 689                 switch (ddc_line) {
 690                 case RADEON_GPIO_VGA_DDC:
 691                 case RADEON_GPIO_DVI_DDC:
 692                         i2c.hw_capable = true;
 693                         break;
 694                 case RADEON_GPIO_MONID:
 695                         /* hw i2c on RADEON_GPIO_MONID doesn't seem to work
 696                          * reliably on some pre-r4xx hardware; not sure why.
 697                          */
 698                         i2c.hw_capable = false;
 699                         break;
 700                 default:
 701                         i2c.hw_capable = false;
 702                         break;
 703                 }
 704                 break;
 705         default:
 706                 i2c.hw_capable = false;
 707                 break;
 708         }
 709         i2c.mm_i2c = false;
 710
 711         i2c.i2c_id = ddc;
 712         i2c.hpd = RADEON_HPD_NONE;
 713
 714         if (ddc_line)
 715                 i2c.valid = true;
 716         else
 717                 i2c.valid = false;
 718
 719         return i2c;
 720 }
 721
 722 void radeon_combios_i2c_init(struct radeon_device *rdev)
 723 {
 724         struct drm_device *dev = rdev->ddev;
 725         struct radeon_i2c_bus_rec i2c;
 726
 727         /* actual hw pads
 728          * r1xx/rs2xx/rs3xx
 729          * 0x60, 0x64, 0x68, 0x6c, gpiopads, mm
 730          * r200
 731          * 0x60, 0x64, 0x68, mm
 732          * r300/r350
 733          * 0x60, 0x64, mm
 734          * rv2xx/rv3xx/rs4xx
 735          * 0x60, 0x64, 0x68, gpiopads, mm
 736          */
 737
 738         /* 0x60 */
 739         i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
 740         rdev->i2c_bus[0] = radeon_i2c_create(dev, &i2c, "DVI_DDC");
 741         /* 0x64 */
 742         i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
 743         rdev->i2c_bus[1] = radeon_i2c_create(dev, &i2c, "VGA_DDC");
 744
 745         /* mm i2c */
 746         i2c.valid = true;
 747         i2c.hw_capable = true;
 748         i2c.mm_i2c = true;
 749         i2c.i2c_id = 0xa0;
 750         rdev->i2c_bus[2] = radeon_i2c_create(dev, &i2c, "MM_I2C");
 751
 752         if (rdev->family == CHIP_R300 ||
 753             rdev->family == CHIP_R350) {
 754                 /* only 2 sw i2c pads */
 755         } else if (rdev->family == CHIP_RS300 ||
 756                    rdev->family == CHIP_RS400 ||
 757                    rdev->family == CHIP_RS480) {
 758                 u16 offset;
 759                 u8 id, blocks, clk, data;
 760                 int i;
 761
 762                 /* 0x68 */
 763                 i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
 764                 rdev->i2c_bus[3] = radeon_i2c_create(dev, &i2c, "MONID");
 765
 766                 offset = combios_get_table_offset(dev, COMBIOS_I2C_INFO_TABLE);
 767                 if (offset) {
 768                         blocks = RBIOS8(offset + 2);
 769                         for (i = 0; i < blocks; i++) {
 770                                 id = RBIOS8(offset + 3 + (i * 5) + 0);
 771                                 if (id == 136) {
 772                                         clk = RBIOS8(offset + 3 + (i * 5) + 3);
 773                                         data = RBIOS8(offset + 3 + (i * 5) + 4);
 774                                         /* gpiopad */
 775                                         i2c = combios_setup_i2c_bus(rdev, DDC_MONID,
 776                                                                     (1 << clk), (1 << data));
 777                                         rdev->i2c_bus[4] = radeon_i2c_create(dev, &i2c, "GPIOPAD_MASK");
 778                                         break;
 779                                 }
 780                         }
 781                 }
 782         } else if ((rdev->family == CHIP_R200) ||
 783                    (rdev->family >= CHIP_R300)) {
 784                 /* 0x68 */
 785                 i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
 786                 rdev->i2c_bus[3] = radeon_i2c_create(dev, &i2c, "MONID");
 787         } else {
 788                 /* 0x68 */
 789                 i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
 790                 rdev->i2c_bus[3] = radeon_i2c_create(dev, &i2c, "MONID");
 791                 /* 0x6c */
 792                 i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
 793                 rdev->i2c_bus[4] = radeon_i2c_create(dev, &i2c, "CRT2_DDC");
 794         }
 795 }
 796
 797 bool radeon_combios_get_clock_info(struct drm_device *dev)
 798 {
 799         struct radeon_device *rdev = dev->dev_private;
 800         uint16_t pll_info;
 801         struct radeon_pll *p1pll = &rdev->clock.p1pll;
 802         struct radeon_pll *p2pll = &rdev->clock.p2pll;
 803         struct radeon_pll *spll = &rdev->clock.spll;
 804         struct radeon_pll *mpll = &rdev->clock.mpll;
 805         int8_t rev;
 806         uint16_t sclk, mclk;
 807
 808         pll_info = combios_get_table_offset(dev, COMBIOS_PLL_INFO_TABLE);
 809         if (pll_info) {
 810                 rev = RBIOS8(pll_info);
 811
 812                 /* pixel clocks */
 813                 p1pll->reference_freq = RBIOS16(pll_info + 0xe);
 814                 p1pll->reference_div = RBIOS16(pll_info + 0x10);
 815                 p1pll->pll_out_min = RBIOS32(pll_info + 0x12);
 816                 p1pll->pll_out_max = RBIOS32(pll_info + 0x16);
 817                 p1pll->lcd_pll_out_min = p1pll->pll_out_min;
 818                 p1pll->lcd_pll_out_max = p1pll->pll_out_max;
 819
 820                 if (rev > 9) {
 821                         p1pll->pll_in_min = RBIOS32(pll_info + 0x36);
 822                         p1pll->pll_in_max = RBIOS32(pll_info + 0x3a);
 823                 } else {
 824                         p1pll->pll_in_min = 40;
 825                         p1pll->pll_in_max = 500;
 826                 }
 827                 *p2pll = *p1pll;
 828
 829                 /* system clock */
 830                 spll->reference_freq = RBIOS16(pll_info + 0x1a);
 831                 spll->reference_div = RBIOS16(pll_info + 0x1c);
 832                 spll->pll_out_min = RBIOS32(pll_info + 0x1e);
 833                 spll->pll_out_max = RBIOS32(pll_info + 0x22);
 834
 835                 if (rev > 10) {
 836                         spll->pll_in_min = RBIOS32(pll_info + 0x48);
 837                         spll->pll_in_max = RBIOS32(pll_info + 0x4c);
 838                 } else {
 839                         /* ??? */
 840                         spll->pll_in_min = 40;
 841                         spll->pll_in_max = 500;
 842                 }
 843
 844                 /* memory clock */
 845                 mpll->reference_freq = RBIOS16(pll_info + 0x26);
 846                 mpll->reference_div = RBIOS16(pll_info + 0x28);
 847                 mpll->pll_out_min = RBIOS32(pll_info + 0x2a);
 848                 mpll->pll_out_max = RBIOS32(pll_info + 0x2e);
 849
 850                 if (rev > 10) {
 851                         mpll->pll_in_min = RBIOS32(pll_info + 0x5a);
 852                         mpll->pll_in_max = RBIOS32(pll_info + 0x5e);
 853                 } else {
 854                         /* ??? */
 855                         mpll->pll_in_min = 40;
 856                         mpll->pll_in_max = 500;
 857                 }
 858
 859                 /* default sclk/mclk */
 860                 sclk = RBIOS16(pll_info + 0xa);
 861                 mclk = RBIOS16(pll_info + 0x8);
 862                 if (sclk == 0)
 863                         sclk = 200 * 100;
 864                 if (mclk == 0)
 865                         mclk = 200 * 100;
 866
 867                 rdev->clock.default_sclk = sclk;
 868                 rdev->clock.default_mclk = mclk;
 869
 870                 if (RBIOS32(pll_info + 0x16))
 871                         rdev->clock.max_pixel_clock = RBIOS32(pll_info + 0x16);
 872                 else
 873                         rdev->clock.max_pixel_clock = 35000; /* might need something asic specific */
 874
 875                 return true;
 876         }
 877         return false;
 878 }
 879
 880 bool radeon_combios_sideport_present(struct radeon_device *rdev)
 881 {
 882         struct drm_device *dev = rdev->ddev;
 883         u16 igp_info;
 884
 885         /* sideport is AMD only */
 886         if (rdev->family == CHIP_RS400)
 887                 return false;
 888
 889         igp_info = combios_get_table_offset(dev, COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE);
 890
 891         if (igp_info) {
 892                 if (RBIOS16(igp_info + 0x4))
 893                         return true;
 894         }
 895         return false;
 896 }
 897
 898 static const uint32_t default_primarydac_adj[CHIP_LAST] = {
 899         0x00000808,             /* r100  */
 900         0x00000808,             /* rv100 */
 901         0x00000808,             /* rs100 */
 902         0x00000808,             /* rv200 */
 903         0x00000808,             /* rs200 */
 904         0x00000808,             /* r200  */
 905         0x00000808,             /* rv250 */
 906         0x00000000,             /* rs300 */
 907         0x00000808,             /* rv280 */
 908         0x00000808,             /* r300  */
 909         0x00000808,             /* r350  */
 910         0x00000808,             /* rv350 */
 911         0x00000808,             /* rv380 */
 912         0x00000808,             /* r420  */
 913         0x00000808,             /* r423  */
 914         0x00000808,             /* rv410 */
 915         0x00000000,             /* rs400 */
 916         0x00000000,             /* rs480 */
 917 };
 918
 919 static void radeon_legacy_get_primary_dac_info_from_table(struct radeon_device *rdev,
 920                                                           struct radeon_encoder_primary_dac *p_dac)
 921 {
 922         p_dac->ps2_pdac_adj = default_primarydac_adj[rdev->family];
 923         return;
 924 }
 925
 926 struct radeon_encoder_primary_dac *radeon_combios_get_primary_dac_info(struct
 927                                                                        radeon_encoder
 928                                                                        *encoder)
 929 {
 930         struct drm_device *dev = encoder->base.dev;
 931         struct radeon_device *rdev = dev->dev_private;
 932         uint16_t dac_info;
 933         uint8_t rev, bg, dac;
 934         struct radeon_encoder_primary_dac *p_dac = NULL;
 935         int found = 0;
 936
 937         p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac),
 938                         GFP_KERNEL);
 939
 940         if (!p_dac)
 941                 return NULL;
 942
 943         /* check CRT table */
 944         dac_info = combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
 945         if (dac_info) {
 946                 rev = RBIOS8(dac_info) & 0x3;
 947                 if (rev < 2) {
 948                         bg = RBIOS8(dac_info + 0x2) & 0xf;
 949                         dac = (RBIOS8(dac_info + 0x2) >> 4) & 0xf;
 950                         p_dac->ps2_pdac_adj = (bg << 8) | (dac);
 951                 } else {
 952                         bg = RBIOS8(dac_info + 0x2) & 0xf;
 953                         dac = RBIOS8(dac_info + 0x3) & 0xf;
 954                         p_dac->ps2_pdac_adj = (bg << 8) | (dac);
 955                 }
 956                 /* if the values are all zeros, use the table */
 957                 if (p_dac->ps2_pdac_adj)
 958                         found = 1;
 959         }
 960
 961         /* quirks */
 962         /* Radeon 9100 (R200) */
 963         if ((dev->pdev->device == 0x514D) &&
 964             (dev->pdev->subsystem_vendor == 0x174B) &&
 965             (dev->pdev->subsystem_device == 0x7149)) {
 966                 /* vbios value is bad, use the default */
 967                 found = 0;
 968         }
 969
 970         if (!found) /* fallback to defaults */
 971                 radeon_legacy_get_primary_dac_info_from_table(rdev, p_dac);
 972
 973         return p_dac;
 974 }
 975
 976 enum radeon_tv_std
 977 radeon_combios_get_tv_info(struct radeon_device *rdev)
 978 {
 979         struct drm_device *dev = rdev->ddev;
 980         uint16_t tv_info;
 981         enum radeon_tv_std tv_std = TV_STD_NTSC;
 982
 983         tv_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
 984         if (tv_info) {
 985                 if (RBIOS8(tv_info + 6) == 'T') {
 986                         switch (RBIOS8(tv_info + 7) & 0xf) {
 987                         case 1:
 988                                 tv_std = TV_STD_NTSC;
 989                                 DRM_DEBUG_KMS("Default TV standard: NTSC\n");
 990                                 break;
 991                         case 2:
 992                                 tv_std = TV_STD_PAL;
 993                                 DRM_DEBUG_KMS("Default TV standard: PAL\n");
 994                                 break;
 995                         case 3:
 996                                 tv_std = TV_STD_PAL_M;
 997                                 DRM_DEBUG_KMS("Default TV standard: PAL-M\n");
 998                                 break;
 999                         case 4:
1000                                 tv_std = TV_STD_PAL_60;
1001                                 DRM_DEBUG_KMS("Default TV standard: PAL-60\n");
1002                                 break;
1003                         case 5:
1004                                 tv_std = TV_STD_NTSC_J;
1005                                 DRM_DEBUG_KMS("Default TV standard: NTSC-J\n");
1006                                 break;
1007                         case 6:
1008                                 tv_std = TV_STD_SCART_PAL;
1009                                 DRM_DEBUG_KMS("Default TV standard: SCART-PAL\n");
1010                                 break;
1011                         default:
1012                                 tv_std = TV_STD_NTSC;
1013                                 DRM_DEBUG_KMS
1014                                     ("Unknown TV standard; defaulting to NTSC\n");
1015                                 break;
1016                         }
1017
1018                         switch ((RBIOS8(tv_info + 9) >> 2) & 0x3) {
1019                         case 0:
1020                                 DRM_DEBUG_KMS("29.498928713 MHz TV ref clk\n");
1021                                 break;
1022                         case 1:
1023                                 DRM_DEBUG_KMS("28.636360000 MHz TV ref clk\n");
1024                                 break;
1025                         case 2:
1026                                 DRM_DEBUG_KMS("14.318180000 MHz TV ref clk\n");
1027                                 break;
1028                         case 3:
1029                                 DRM_DEBUG_KMS("27.000000000 MHz TV ref clk\n");
1030                                 break;
1031                         default:
1032                                 break;
1033                         }
1034                 }
1035         }
1036         return tv_std;
1037 }
1038
1039 static const uint32_t default_tvdac_adj[CHIP_LAST] = {
1040         0x00000000,             /* r100  */
1041         0x00280000,             /* rv100 */
1042         0x00000000,             /* rs100 */
1043         0x00880000,             /* rv200 */
1044         0x00000000,             /* rs200 */
1045         0x00000000,             /* r200  */
1046         0x00770000,             /* rv250 */
1047         0x00290000,             /* rs300 */
1048         0x00560000,             /* rv280 */
1049         0x00780000,             /* r300  */
1050         0x00770000,             /* r350  */
1051         0x00780000,             /* rv350 */
1052         0x00780000,             /* rv380 */
1053         0x01080000,             /* r420  */
1054         0x01080000,             /* r423  */
1055         0x01080000,             /* rv410 */
1056         0x00780000,             /* rs400 */
1057         0x00780000,             /* rs480 */
1058 };
1059
1060 static void radeon_legacy_get_tv_dac_info_from_table(struct radeon_device *rdev,
1061                                                      struct radeon_encoder_tv_dac *tv_dac)
1062 {
1063         tv_dac->ps2_tvdac_adj = default_tvdac_adj[rdev->family];
1064         if ((rdev->flags & RADEON_IS_MOBILITY) && (rdev->family == CHIP_RV250))
1065                 tv_dac->ps2_tvdac_adj = 0x00880000;
1066         tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
1067         tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
1068         return;
1069 }
1070
1071 struct radeon_encoder_tv_dac *radeon_combios_get_tv_dac_info(struct
1072                                                              radeon_encoder
1073                                                              *encoder)
1074 {
1075         struct drm_device *dev = encoder->base.dev;
1076         struct radeon_device *rdev = dev->dev_private;
1077         uint16_t dac_info;
1078         uint8_t rev, bg, dac;
1079         struct radeon_encoder_tv_dac *tv_dac = NULL;
1080         int found = 0;
1081
1082         tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL);
1083         if (!tv_dac)
1084                 return NULL;
1085
1086         /* first check TV table */
1087         dac_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
1088         if (dac_info) {
1089                 rev = RBIOS8(dac_info + 0x3);
1090                 if (rev > 4) {
1091                         bg = RBIOS8(dac_info + 0xc) & 0xf;
1092                         dac = RBIOS8(dac_info + 0xd) & 0xf;
1093                         tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
1094
1095                         bg = RBIOS8(dac_info + 0xe) & 0xf;
1096                         dac = RBIOS8(dac_info + 0xf) & 0xf;
1097                         tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
1098
1099                         bg = RBIOS8(dac_info + 0x10) & 0xf;
1100                         dac = RBIOS8(dac_info + 0x11) & 0xf;
1101                         tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
1102                         /* if the values are all zeros, use the table */
1103                         if (tv_dac->ps2_tvdac_adj)
1104                                 found = 1;
1105                 } else if (rev > 1) {
1106                         bg = RBIOS8(dac_info + 0xc) & 0xf;
1107                         dac = (RBIOS8(dac_info + 0xc) >> 4) & 0xf;
1108                         tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
1109
1110                         bg = RBIOS8(dac_info + 0xd) & 0xf;
1111                         dac = (RBIOS8(dac_info + 0xd) >> 4) & 0xf;
1112                         tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
1113
1114                         bg = RBIOS8(dac_info + 0xe) & 0xf;
1115                         dac = (RBIOS8(dac_info + 0xe) >> 4) & 0xf;
1116                         tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
1117                         /* if the values are all zeros, use the table */
1118                         if (tv_dac->ps2_tvdac_adj)
1119                                 found = 1;
1120                 }
1121                 tv_dac->tv_std = radeon_combios_get_tv_info(rdev);
1122         }
1123         if (!found) {
1124                 /* then check CRT table */
1125                 dac_info =
1126                     combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
1127                 if (dac_info) {
1128                         rev = RBIOS8(dac_info) & 0x3;
1129                         if (rev < 2) {
1130                                 bg = RBIOS8(dac_info + 0x3) & 0xf;
1131                                 dac = (RBIOS8(dac_info + 0x3) >> 4) & 0xf;
1132                                 tv_dac->ps2_tvdac_adj =
1133                                     (bg << 16) | (dac << 20);
1134                                 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
1135                                 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
1136                                 /* if the values are all zeros, use the table */
1137                                 if (tv_dac->ps2_tvdac_adj)
1138                                         found = 1;
1139                         } else {
1140                                 bg = RBIOS8(dac_info + 0x4) & 0xf;
1141                                 dac = RBIOS8(dac_info + 0x5) & 0xf;
1142                                 tv_dac->ps2_tvdac_adj =
1143                                     (bg << 16) | (dac << 20);
1144                                 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
1145                                 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
1146                                 /* if the values are all zeros, use the table */
1147                                 if (tv_dac->ps2_tvdac_adj)
1148                                         found = 1;
1149                         }
1150                 } else {
1151                         DRM_INFO("No TV DAC info found in BIOS\n");
1152                 }
1153         }
1154
1155         if (!found) /* fallback to defaults */
1156                 radeon_legacy_get_tv_dac_info_from_table(rdev, tv_dac);
1157
1158         return tv_dac;
1159 }
1160
1161 static struct radeon_encoder_lvds *radeon_legacy_get_lvds_info_from_regs(struct
1162                                                                          radeon_device
1163                                                                          *rdev)
1164 {
1165         struct radeon_encoder_lvds *lvds = NULL;
1166         uint32_t fp_vert_stretch, fp_horz_stretch;
1167         uint32_t ppll_div_sel, ppll_val;
1168         uint32_t lvds_ss_gen_cntl = RREG32(RADEON_LVDS_SS_GEN_CNTL);
1169
1170         lvds = kzalloc(sizeof(struct radeon_encoder_lvds), GFP_KERNEL);
1171
1172         if (!lvds)
1173                 return NULL;
1174
1175         fp_vert_stretch = RREG32(RADEON_FP_VERT_STRETCH);
1176         fp_horz_stretch = RREG32(RADEON_FP_HORZ_STRETCH);
1177
1178         /* These should be fail-safe defaults, fingers crossed */
1179         lvds->panel_pwr_delay = 200;
1180         lvds->panel_vcc_delay = 2000;
1181
1182         lvds->lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
1183         lvds->panel_digon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) & 0xf;
1184         lvds->panel_blon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY2_SHIFT) & 0xf;
1185
1186         if (fp_vert_stretch & RADEON_VERT_STRETCH_ENABLE)
1187                 lvds->native_mode.vdisplay =
1188                     ((fp_vert_stretch & RADEON_VERT_PANEL_SIZE) >>
1189                      RADEON_VERT_PANEL_SHIFT) + 1;
1190         else
1191                 lvds->native_mode.vdisplay =
1192                     (RREG32(RADEON_CRTC_V_TOTAL_DISP) >> 16) + 1;
1193
1194         if (fp_horz_stretch & RADEON_HORZ_STRETCH_ENABLE)
1195                 lvds->native_mode.hdisplay =
1196                     (((fp_horz_stretch & RADEON_HORZ_PANEL_SIZE) >>
1197                       RADEON_HORZ_PANEL_SHIFT) + 1) * 8;
1198         else
1199                 lvds->native_mode.hdisplay =
1200                     ((RREG32(RADEON_CRTC_H_TOTAL_DISP) >> 16) + 1) * 8;
1201
1202         if ((lvds->native_mode.hdisplay < 640) ||
1203             (lvds->native_mode.vdisplay < 480)) {
1204                 lvds->native_mode.hdisplay = 640;
1205                 lvds->native_mode.vdisplay = 480;
1206         }
1207
1208         ppll_div_sel = RREG8(RADEON_CLOCK_CNTL_INDEX + 1) & 0x3;
1209         ppll_val = RREG32_PLL(RADEON_PPLL_DIV_0 + ppll_div_sel);
1210         if ((ppll_val & 0x000707ff) == 0x1bb)
1211                 lvds->use_bios_dividers = false;
1212         else {
1213                 lvds->panel_ref_divider =
1214                     RREG32_PLL(RADEON_PPLL_REF_DIV) & 0x3ff;
1215                 lvds->panel_post_divider = (ppll_val >> 16) & 0x7;
1216                 lvds->panel_fb_divider = ppll_val & 0x7ff;
1217
1218                 if ((lvds->panel_ref_divider != 0) &&
1219                     (lvds->panel_fb_divider > 3))
1220                         lvds->use_bios_dividers = true;
1221         }
1222         lvds->panel_vcc_delay = 200;
1223
1224         DRM_INFO("Panel info derived from registers\n");
1225         DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.hdisplay,
1226                  lvds->native_mode.vdisplay);
1227
1228         return lvds;
1229 }
1230
1231 struct radeon_encoder_lvds *radeon_combios_get_lvds_info(struct radeon_encoder
1232                                                          *encoder)
1233 {
1234         struct drm_device *dev = encoder->base.dev;
1235         struct radeon_device *rdev = dev->dev_private;
1236         uint16_t lcd_info;
1237         uint32_t panel_setup;
1238         char stmp[30];
1239         int tmp, i;
1240         struct radeon_encoder_lvds *lvds = NULL;
1241
1242         lcd_info = combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE);
1243
1244         if (lcd_info) {
1245                 lvds = kzalloc(sizeof(struct radeon_encoder_lvds), GFP_KERNEL);
1246
1247                 if (!lvds)
1248                         return NULL;
1249
1250                 for (i = 0; i < 24; i++)
1251                         stmp[i] = RBIOS8(lcd_info + i + 1);
1252                 stmp[24] = 0;
1253
1254                 DRM_INFO("Panel ID String: %s\n", stmp);
1255
1256                 lvds->native_mode.hdisplay = RBIOS16(lcd_info + 0x19);
1257                 lvds->native_mode.vdisplay = RBIOS16(lcd_info + 0x1b);
1258
1259                 DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.hdisplay,
1260                          lvds->native_mode.vdisplay);
1261
1262                 lvds->panel_vcc_delay = RBIOS16(lcd_info + 0x2c);
1263                 lvds->panel_vcc_delay = min_t(u16, lvds->panel_vcc_delay, 2000);
1264
1265                 lvds->panel_pwr_delay = RBIOS8(lcd_info + 0x24);
1266                 lvds->panel_digon_delay = RBIOS16(lcd_info + 0x38) & 0xf;
1267                 lvds->panel_blon_delay = (RBIOS16(lcd_info + 0x38) >> 4) & 0xf;
1268
1269                 lvds->panel_ref_divider = RBIOS16(lcd_info + 0x2e);
1270                 lvds->panel_post_divider = RBIOS8(lcd_info + 0x30);
1271                 lvds->panel_fb_divider = RBIOS16(lcd_info + 0x31);
1272                 if ((lvds->panel_ref_divider != 0) &&
1273                     (lvds->panel_fb_divider > 3))
1274                         lvds->use_bios_dividers = true;
1275
1276                 panel_setup = RBIOS32(lcd_info + 0x39);
1277                 lvds->lvds_gen_cntl = 0xff00;
1278                 if (panel_setup & 0x1)
1279                         lvds->lvds_gen_cntl |= RADEON_LVDS_PANEL_FORMAT;
1280
1281                 if ((panel_setup >> 4) & 0x1)
1282                         lvds->lvds_gen_cntl |= RADEON_LVDS_PANEL_TYPE;
1283
1284                 switch ((panel_setup >> 8) & 0x7) {
1285                 case 0:
1286                         lvds->lvds_gen_cntl |= RADEON_LVDS_NO_FM;
1287                         break;
1288                 case 1:
1289                         lvds->lvds_gen_cntl |= RADEON_LVDS_2_GREY;
1290                         break;
1291                 case 2:
1292                         lvds->lvds_gen_cntl |= RADEON_LVDS_4_GREY;
1293                         break;
1294                 default:
1295                         break;
1296                 }
1297
1298                 if ((panel_setup >> 16) & 0x1)
1299                         lvds->lvds_gen_cntl |= RADEON_LVDS_FP_POL_LOW;
1300
1301                 if ((panel_setup >> 17) & 0x1)
1302                         lvds->lvds_gen_cntl |= RADEON_LVDS_LP_POL_LOW;
1303
1304                 if ((panel_setup >> 18) & 0x1)
1305                         lvds->lvds_gen_cntl |= RADEON_LVDS_DTM_POL_LOW;
1306
1307                 if ((panel_setup >> 23) & 0x1)
1308                         lvds->lvds_gen_cntl |= RADEON_LVDS_BL_CLK_SEL;
1309
1310                 lvds->lvds_gen_cntl |= (panel_setup & 0xf0000000);
1311
1312                 for (i = 0; i < 32; i++) {
1313                         tmp = RBIOS16(lcd_info + 64 + i * 2);
1314                         if (tmp == 0)
1315                                 break;
1316
1317                         if ((RBIOS16(tmp) == lvds->native_mode.hdisplay) &&
1318                             (RBIOS16(tmp + 2) == lvds->native_mode.vdisplay)) {
1319                                 lvds->native_mode.htotal = lvds->native_mode.hdisplay +
1320                                         (RBIOS16(tmp + 17) - RBIOS16(tmp + 19)) * 8;
1321                                 lvds->native_mode.hsync_start = lvds->native_mode.hdisplay +
1322                                         (RBIOS16(tmp + 21) - RBIOS16(tmp + 19) - 1) * 8;
1323                                 lvds->native_mode.hsync_end = lvds->native_mode.hsync_start +
1324                                         (RBIOS8(tmp + 23) * 8);
1325
1326                                 lvds->native_mode.vtotal = lvds->native_mode.vdisplay +
1327                                         (RBIOS16(tmp + 24) - RBIOS16(tmp + 26));
1328                                 lvds->native_mode.vsync_start = lvds->native_mode.vdisplay +
1329                                         ((RBIOS16(tmp + 28) & 0x7ff) - RBIOS16(tmp + 26));
1330                                 lvds->native_mode.vsync_end = lvds->native_mode.vsync_start +
1331                                         ((RBIOS16(tmp + 28) & 0xf800) >> 11);
1332
1333                                 lvds->native_mode.clock = RBIOS16(tmp + 9) * 10;
1334                                 lvds->native_mode.flags = 0;
1335                                 /* set crtc values */
1336                                 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V);
1337
1338                         }
1339                 }
1340         } else {
1341                 DRM_INFO("No panel info found in BIOS\n");
1342                 lvds = radeon_legacy_get_lvds_info_from_regs(rdev);
1343         }
1344
1345         if (lvds)
1346                 encoder->native_mode = lvds->native_mode;
1347         return lvds;
1348 }
1349
1350 static const struct radeon_tmds_pll default_tmds_pll[CHIP_LAST][4] = {
1351         {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}},  /* CHIP_R100  */
1352         {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}},  /* CHIP_RV100 */
1353         {{0, 0}, {0, 0}, {0, 0}, {0, 0}},       /* CHIP_RS100 */
1354         {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}},  /* CHIP_RV200 */
1355         {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}},  /* CHIP_RS200 */
1356         {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}},  /* CHIP_R200  */
1357         {{15500, 0x81b}, {0xffffffff, 0x83f}, {0, 0}, {0, 0}},  /* CHIP_RV250 */
1358         {{0, 0}, {0, 0}, {0, 0}, {0, 0}},       /* CHIP_RS300 */
1359         {{13000, 0x400f4}, {15000, 0x400f7}, {0xffffffff, 0x40111}, {0, 0}},    /* CHIP_RV280 */
1360         {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}},        /* CHIP_R300  */
1361         {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}},        /* CHIP_R350  */
1362         {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}},      /* CHIP_RV350 */
1363         {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}},      /* CHIP_RV380 */
1364         {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}},        /* CHIP_R420  */
1365         {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}},        /* CHIP_R423  */
1366         {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}},        /* CHIP_RV410 */
1367         { {0, 0}, {0, 0}, {0, 0}, {0, 0} },     /* CHIP_RS400 */
1368         { {0, 0}, {0, 0}, {0, 0}, {0, 0} },     /* CHIP_RS480 */
1369 };
1370
1371 bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder,
1372                                             struct radeon_encoder_int_tmds *tmds)
1373 {
1374         struct drm_device *dev = encoder->base.dev;
1375         struct radeon_device *rdev = dev->dev_private;
1376         int i;
1377
1378         for (i = 0; i < 4; i++) {
1379                 tmds->tmds_pll[i].value =
1380                         default_tmds_pll[rdev->family][i].value;
1381                 tmds->tmds_pll[i].freq = default_tmds_pll[rdev->family][i].freq;
1382         }
1383
1384         return true;
1385 }
1386
1387 bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder,
1388                                               struct radeon_encoder_int_tmds *tmds)
1389 {
1390         struct drm_device *dev = encoder->base.dev;
1391         struct radeon_device *rdev = dev->dev_private;
1392         uint16_t tmds_info;
1393         int i, n;
1394         uint8_t ver;
1395
1396         tmds_info = combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE);
1397
1398         if (tmds_info) {
1399                 ver = RBIOS8(tmds_info);
1400                 DRM_DEBUG_KMS("DFP table revision: %d\n", ver);
1401                 if (ver == 3) {
1402                         n = RBIOS8(tmds_info + 5) + 1;
1403                         if (n > 4)
1404                                 n = 4;
1405                         for (i = 0; i < n; i++) {
1406                                 tmds->tmds_pll[i].value =
1407                                     RBIOS32(tmds_info + i * 10 + 0x08);
1408                                 tmds->tmds_pll[i].freq =
1409                                     RBIOS16(tmds_info + i * 10 + 0x10);
1410                                 DRM_DEBUG_KMS("TMDS PLL From COMBIOS %u %x\n",
1411                                           tmds->tmds_pll[i].freq,
1412                                           tmds->tmds_pll[i].value);
1413                         }
1414                 } else if (ver == 4) {
1415                         int stride = 0;
1416                         n = RBIOS8(tmds_info + 5) + 1;
1417                         if (n > 4)
1418                                 n = 4;
1419                         for (i = 0; i < n; i++) {
1420                                 tmds->tmds_pll[i].value =
1421                                     RBIOS32(tmds_info + stride + 0x08);
1422                                 tmds->tmds_pll[i].freq =
1423                                     RBIOS16(tmds_info + stride + 0x10);
1424                                 if (i == 0)
1425                                         stride += 10;
1426                                 else
1427                                         stride += 6;
1428                                 DRM_DEBUG_KMS("TMDS PLL From COMBIOS %u %x\n",
1429                                           tmds->tmds_pll[i].freq,
1430                                           tmds->tmds_pll[i].value);
1431                         }
1432                 }
1433         } else {
1434                 DRM_INFO("No TMDS info found in BIOS\n");
1435                 return false;
1436         }
1437         return true;
1438 }
1439
1440 bool radeon_legacy_get_ext_tmds_info_from_table(struct radeon_encoder *encoder,
1441                                                 struct radeon_encoder_ext_tmds *tmds)
1442 {
1443         struct drm_device *dev = encoder->base.dev;
1444         struct radeon_device *rdev = dev->dev_private;
1445         struct radeon_i2c_bus_rec i2c_bus;
1446
1447         /* default for macs */
1448         i2c_bus = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
1449         tmds->i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
1450
1451         /* XXX some macs have duallink chips */
1452         switch (rdev->mode_info.connector_table) {
1453         case CT_POWERBOOK_EXTERNAL:
1454         case CT_MINI_EXTERNAL:
1455         default:
1456                 tmds->dvo_chip = DVO_SIL164;
1457                 tmds->slave_addr = 0x70 >> 1; /* 7 bit addressing */
1458                 break;
1459         }
1460
1461         return true;
1462 }
1463
1464 bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder *encoder,
1465                                                   struct radeon_encoder_ext_tmds *tmds)
1466 {
1467         struct drm_device *dev = encoder->base.dev;
1468         struct radeon_device *rdev = dev->dev_private;
1469         uint16_t offset;
1470         uint8_t ver;
1471         enum radeon_combios_ddc gpio;
1472         struct radeon_i2c_bus_rec i2c_bus;
1473
1474         tmds->i2c_bus = NULL;
1475         if (rdev->flags & RADEON_IS_IGP) {
1476                 i2c_bus = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
1477                 tmds->i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
1478                 tmds->dvo_chip = DVO_SIL164;
1479                 tmds->slave_addr = 0x70 >> 1; /* 7 bit addressing */
1480         } else {
1481                 offset = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
1482                 if (offset) {
1483                         ver = RBIOS8(offset);
1484                         DRM_DEBUG_KMS("External TMDS Table revision: %d\n", ver);
1485                         tmds->slave_addr = RBIOS8(offset + 4 + 2);
1486                         tmds->slave_addr >>= 1; /* 7 bit addressing */
1487                         gpio = RBIOS8(offset + 4 + 3);
1488                         if (gpio == DDC_LCD) {
1489                                 /* MM i2c */
1490                                 i2c_bus.valid = true;
1491                                 i2c_bus.hw_capable = true;
1492                                 i2c_bus.mm_i2c = true;
1493                                 i2c_bus.i2c_id = 0xa0;
1494                         } else
1495                                 i2c_bus = combios_setup_i2c_bus(rdev, gpio, 0, 0);
1496                         tmds->i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
1497                 }
1498         }
1499
1500         if (!tmds->i2c_bus) {
1501                 DRM_INFO("No valid Ext TMDS info found in BIOS\n");
1502                 return false;
1503         }
1504
1505         return true;
1506 }
1507
1508 bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
1509 {
1510         struct radeon_device *rdev = dev->dev_private;
1511         struct radeon_i2c_bus_rec ddc_i2c;
1512         struct radeon_hpd hpd;
1513
1514         rdev->mode_info.connector_table = radeon_connector_table;
1515         if (rdev->mode_info.connector_table == CT_NONE) {
1516 #ifdef CONFIG_PPC_PMAC
1517                 if (of_machine_is_compatible("PowerBook3,3")) {
1518                         /* powerbook with VGA */
1519                         rdev->mode_info.connector_table = CT_POWERBOOK_VGA;
1520                 } else if (of_machine_is_compatible("PowerBook3,4") ||
1521                            of_machine_is_compatible("PowerBook3,5")) {
1522                         /* powerbook with internal tmds */
1523                         rdev->mode_info.connector_table = CT_POWERBOOK_INTERNAL;
1524                 } else if (of_machine_is_compatible("PowerBook5,1") ||
1525                            of_machine_is_compatible("PowerBook5,2") ||
1526                            of_machine_is_compatible("PowerBook5,3") ||
1527                            of_machine_is_compatible("PowerBook5,4") ||
1528                            of_machine_is_compatible("PowerBook5,5")) {
1529                         /* powerbook with external single link tmds (sil164) */
1530                         rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
1531                 } else if (of_machine_is_compatible("PowerBook5,6")) {
1532                         /* powerbook with external dual or single link tmds */
1533                         rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
1534                 } else if (of_machine_is_compatible("PowerBook5,7") ||
1535                            of_machine_is_compatible("PowerBook5,8") ||
1536                            of_machine_is_compatible("PowerBook5,9")) {
1537                         /* PowerBook6,2 ? */
1538                         /* powerbook with external dual link tmds (sil1178?) */
1539                         rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
1540                 } else if (of_machine_is_compatible("PowerBook4,1") ||
1541                            of_machine_is_compatible("PowerBook4,2") ||
1542                            of_machine_is_compatible("PowerBook4,3") ||
1543                            of_machine_is_compatible("PowerBook6,3") ||
1544                            of_machine_is_compatible("PowerBook6,5") ||
1545                            of_machine_is_compatible("PowerBook6,7")) {
1546                         /* ibook */
1547                         rdev->mode_info.connector_table = CT_IBOOK;
1548                 } else if (of_machine_is_compatible("PowerMac3,5")) {
1549                         /* PowerMac G4 Silver radeon 7500 */
1550                         rdev->mode_info.connector_table = CT_MAC_G4_SILVER;
1551                 } else if (of_machine_is_compatible("PowerMac4,4")) {
1552                         /* emac */
1553                         rdev->mode_info.connector_table = CT_EMAC;
1554                 } else if (of_machine_is_compatible("PowerMac10,1")) {
1555                         /* mini with internal tmds */
1556                         rdev->mode_info.connector_table = CT_MINI_INTERNAL;
1557                 } else if (of_machine_is_compatible("PowerMac10,2")) {
1558                         /* mini with external tmds */
1559                         rdev->mode_info.connector_table = CT_MINI_EXTERNAL;
1560                 } else if (of_machine_is_compatible("PowerMac12,1")) {
1561                         /* PowerMac8,1 ? */
1562                         /* imac g5 isight */
1563                         rdev->mode_info.connector_table = CT_IMAC_G5_ISIGHT;
1564                 } else if ((rdev->pdev->device == 0x4a48) &&
1565                            (rdev->pdev->subsystem_vendor == 0x1002) &&
1566                            (rdev->pdev->subsystem_device == 0x4a48)) {
1567                         /* Mac X800 */
1568                         rdev->mode_info.connector_table = CT_MAC_X800;
1569                 } else if ((of_machine_is_compatible("PowerMac7,2") ||
1570                             of_machine_is_compatible("PowerMac7,3")) &&
1571                            (rdev->pdev->device == 0x4150) &&
1572                            (rdev->pdev->subsystem_vendor == 0x1002) &&
1573                            (rdev->pdev->subsystem_device == 0x4150)) {
1574                         /* Mac G5 tower 9600 */
1575                         rdev->mode_info.connector_table = CT_MAC_G5_9600;
1576                 } else if ((rdev->pdev->device == 0x4c66) &&
1577                            (rdev->pdev->subsystem_vendor == 0x1002) &&
1578                            (rdev->pdev->subsystem_device == 0x4c66)) {
1579                         /* SAM440ep RV250 embedded board */
1580                         rdev->mode_info.connector_table = CT_SAM440EP;
1581                 } else
1582 #endif /* CONFIG_PPC_PMAC */
1583 #ifdef CONFIG_PPC64
1584                 if (ASIC_IS_RN50(rdev))
1585                         rdev->mode_info.connector_table = CT_RN50_POWER;
1586                 else
1587 #endif
1588                         rdev->mode_info.connector_table = CT_GENERIC;
1589         }
1590
1591         switch (rdev->mode_info.connector_table) {
1592         case CT_GENERIC:
1593                 DRM_INFO("Connector Table: %d (generic)\n",
1594                          rdev->mode_info.connector_table);
1595                 /* these are the most common settings */
1596                 if (rdev->flags & RADEON_SINGLE_CRTC) {
1597                         /* VGA - primary dac */
1598                         ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1599                         hpd.hpd = RADEON_HPD_NONE;
1600                         radeon_add_legacy_encoder(dev,
1601                                                   radeon_get_encoder_enum(dev,
1602                                                                         ATOM_DEVICE_CRT1_SUPPORT,
1603                                                                         1),
1604                                                   ATOM_DEVICE_CRT1_SUPPORT);
1605                         radeon_add_legacy_connector(dev, 0,
1606                                                     ATOM_DEVICE_CRT1_SUPPORT,
1607                                                     DRM_MODE_CONNECTOR_VGA,
1608                                                     &ddc_i2c,
1609                                                     CONNECTOR_OBJECT_ID_VGA,
1610                                                     &hpd);
1611                 } else if (rdev->flags & RADEON_IS_MOBILITY) {
1612                         /* LVDS */
1613                         ddc_i2c = combios_setup_i2c_bus(rdev, DDC_NONE_DETECTED, 0, 0);
1614                         hpd.hpd = RADEON_HPD_NONE;
1615                         radeon_add_legacy_encoder(dev,
1616                                                   radeon_get_encoder_enum(dev,
1617                                                                         ATOM_DEVICE_LCD1_SUPPORT,
1618                                                                         0),
1619                                                   ATOM_DEVICE_LCD1_SUPPORT);
1620                         radeon_add_legacy_connector(dev, 0,
1621                                                     ATOM_DEVICE_LCD1_SUPPORT,
1622                                                     DRM_MODE_CONNECTOR_LVDS,
1623                                                     &ddc_i2c,
1624                                                     CONNECTOR_OBJECT_ID_LVDS,
1625                                                     &hpd);
1626
1627                         /* VGA - primary dac */
1628                         ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1629                         hpd.hpd = RADEON_HPD_NONE;
1630                         radeon_add_legacy_encoder(dev,
1631                                                   radeon_get_encoder_enum(dev,
1632                                                                         ATOM_DEVICE_CRT1_SUPPORT,
1633                                                                         1),
1634                                                   ATOM_DEVICE_CRT1_SUPPORT);
1635                         radeon_add_legacy_connector(dev, 1,
1636                                                     ATOM_DEVICE_CRT1_SUPPORT,
1637                                                     DRM_MODE_CONNECTOR_VGA,
1638                                                     &ddc_i2c,
1639                                                     CONNECTOR_OBJECT_ID_VGA,
1640                                                     &hpd);
1641                 } else {
1642                         /* DVI-I - tv dac, int tmds */
1643                         ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1644                         hpd.hpd = RADEON_HPD_1;
1645                         radeon_add_legacy_encoder(dev,
1646                                                   radeon_get_encoder_enum(dev,
1647                                                                         ATOM_DEVICE_DFP1_SUPPORT,
1648                                                                         0),
1649                                                   ATOM_DEVICE_DFP1_SUPPORT);
1650                         radeon_add_legacy_encoder(dev,
1651                                                   radeon_get_encoder_enum(dev,
1652                                                                         ATOM_DEVICE_CRT2_SUPPORT,
1653                                                                         2),
1654                                                   ATOM_DEVICE_CRT2_SUPPORT);
1655                         radeon_add_legacy_connector(dev, 0,
1656                                                     ATOM_DEVICE_DFP1_SUPPORT |
1657                                                     ATOM_DEVICE_CRT2_SUPPORT,
1658                                                     DRM_MODE_CONNECTOR_DVII,
1659                                                     &ddc_i2c,
1660                                                     CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1661                                                     &hpd);
1662
1663                         /* VGA - primary dac */
1664                         ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1665                         hpd.hpd = RADEON_HPD_NONE;
1666                         radeon_add_legacy_encoder(dev,
1667                                                   radeon_get_encoder_enum(dev,
1668                                                                         ATOM_DEVICE_CRT1_SUPPORT,
1669                                                                         1),
1670                                                   ATOM_DEVICE_CRT1_SUPPORT);
1671                         radeon_add_legacy_connector(dev, 1,
1672                                                     ATOM_DEVICE_CRT1_SUPPORT,
1673                                                     DRM_MODE_CONNECTOR_VGA,
1674                                                     &ddc_i2c,
1675                                                     CONNECTOR_OBJECT_ID_VGA,
1676                                                     &hpd);
1677                 }
1678
1679                 if (rdev->family != CHIP_R100 && rdev->family != CHIP_R200) {
1680                         /* TV - tv dac */
1681                         ddc_i2c.valid = false;
1682                         hpd.hpd = RADEON_HPD_NONE;
1683                         radeon_add_legacy_encoder(dev,
1684                                                   radeon_get_encoder_enum(dev,
1685                                                                         ATOM_DEVICE_TV1_SUPPORT,
1686                                                                         2),
1687                                                   ATOM_DEVICE_TV1_SUPPORT);
1688                         radeon_add_legacy_connector(dev, 2,
1689                                                     ATOM_DEVICE_TV1_SUPPORT,
1690                                                     DRM_MODE_CONNECTOR_SVIDEO,
1691                                                     &ddc_i2c,
1692                                                     CONNECTOR_OBJECT_ID_SVIDEO,
1693                                                     &hpd);
1694                 }
1695                 break;
1696         case CT_IBOOK:
1697                 DRM_INFO("Connector Table: %d (ibook)\n",
1698                          rdev->mode_info.connector_table);
1699                 /* LVDS */
1700                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1701                 hpd.hpd = RADEON_HPD_NONE;
1702                 radeon_add_legacy_encoder(dev,
1703                                           radeon_get_encoder_enum(dev,
1704                                                                 ATOM_DEVICE_LCD1_SUPPORT,
1705                                                                 0),
1706                                           ATOM_DEVICE_LCD1_SUPPORT);
1707                 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1708                                             DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1709                                             CONNECTOR_OBJECT_ID_LVDS,
1710                                             &hpd);
1711                 /* VGA - TV DAC */
1712                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1713                 hpd.hpd = RADEON_HPD_NONE;
1714                 radeon_add_legacy_encoder(dev,
1715                                           radeon_get_encoder_enum(dev,
1716                                                                 ATOM_DEVICE_CRT2_SUPPORT,
1717                                                                 2),
1718                                           ATOM_DEVICE_CRT2_SUPPORT);
1719                 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
1720                                             DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1721                                             CONNECTOR_OBJECT_ID_VGA,
1722                                             &hpd);
1723                 /* TV - TV DAC */
1724                 ddc_i2c.valid = false;
1725                 hpd.hpd = RADEON_HPD_NONE;
1726                 radeon_add_legacy_encoder(dev,
1727                                           radeon_get_encoder_enum(dev,
1728                                                                 ATOM_DEVICE_TV1_SUPPORT,
1729                                                                 2),
1730                                           ATOM_DEVICE_TV1_SUPPORT);
1731                 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1732                                             DRM_MODE_CONNECTOR_SVIDEO,
1733                                             &ddc_i2c,
1734                                             CONNECTOR_OBJECT_ID_SVIDEO,
1735                                             &hpd);
1736                 break;
1737         case CT_POWERBOOK_EXTERNAL:
1738                 DRM_INFO("Connector Table: %d (powerbook external tmds)\n",
1739                          rdev->mode_info.connector_table);
1740                 /* LVDS */
1741                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1742                 hpd.hpd = RADEON_HPD_NONE;
1743                 radeon_add_legacy_encoder(dev,
1744                                           radeon_get_encoder_enum(dev,
1745                                                                 ATOM_DEVICE_LCD1_SUPPORT,
1746                                                                 0),
1747                                           ATOM_DEVICE_LCD1_SUPPORT);
1748                 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1749                                             DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1750                                             CONNECTOR_OBJECT_ID_LVDS,
1751                                             &hpd);
1752                 /* DVI-I - primary dac, ext tmds */
1753                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1754                 hpd.hpd = RADEON_HPD_2; /* ??? */
1755                 radeon_add_legacy_encoder(dev,
1756                                           radeon_get_encoder_enum(dev,
1757                                                                 ATOM_DEVICE_DFP2_SUPPORT,
1758                                                                 0),
1759                                           ATOM_DEVICE_DFP2_SUPPORT);
1760                 radeon_add_legacy_encoder(dev,
1761                                           radeon_get_encoder_enum(dev,
1762                                                                 ATOM_DEVICE_CRT1_SUPPORT,
1763                                                                 1),
1764                                           ATOM_DEVICE_CRT1_SUPPORT);
1765                 /* XXX some are SL */
1766                 radeon_add_legacy_connector(dev, 1,
1767                                             ATOM_DEVICE_DFP2_SUPPORT |
1768                                             ATOM_DEVICE_CRT1_SUPPORT,
1769                                             DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1770                                             CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I,
1771                                             &hpd);
1772                 /* TV - TV DAC */
1773                 ddc_i2c.valid = false;
1774                 hpd.hpd = RADEON_HPD_NONE;
1775                 radeon_add_legacy_encoder(dev,
1776                                           radeon_get_encoder_enum(dev,
1777                                                                 ATOM_DEVICE_TV1_SUPPORT,
1778                                                                 2),
1779                                           ATOM_DEVICE_TV1_SUPPORT);
1780                 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1781                                             DRM_MODE_CONNECTOR_SVIDEO,
1782                                             &ddc_i2c,
1783                                             CONNECTOR_OBJECT_ID_SVIDEO,
1784                                             &hpd);
1785                 break;
1786         case CT_POWERBOOK_INTERNAL:
1787                 DRM_INFO("Connector Table: %d (powerbook internal tmds)\n",
1788                          rdev->mode_info.connector_table);
1789                 /* LVDS */
1790                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1791                 hpd.hpd = RADEON_HPD_NONE;
1792                 radeon_add_legacy_encoder(dev,
1793                                           radeon_get_encoder_enum(dev,
1794                                                                 ATOM_DEVICE_LCD1_SUPPORT,
1795                                                                 0),
1796                                           ATOM_DEVICE_LCD1_SUPPORT);
1797                 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1798                                             DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1799                                             CONNECTOR_OBJECT_ID_LVDS,
1800                                             &hpd);
1801                 /* DVI-I - primary dac, int tmds */
1802                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1803                 hpd.hpd = RADEON_HPD_1; /* ??? */
1804                 radeon_add_legacy_encoder(dev,
1805                                           radeon_get_encoder_enum(dev,
1806                                                                 ATOM_DEVICE_DFP1_SUPPORT,
1807                                                                 0),
1808                                           ATOM_DEVICE_DFP1_SUPPORT);
1809                 radeon_add_legacy_encoder(dev,
1810                                           radeon_get_encoder_enum(dev,
1811                                                                 ATOM_DEVICE_CRT1_SUPPORT,
1812                                                                 1),
1813                                           ATOM_DEVICE_CRT1_SUPPORT);
1814                 radeon_add_legacy_connector(dev, 1,
1815                                             ATOM_DEVICE_DFP1_SUPPORT |
1816                                             ATOM_DEVICE_CRT1_SUPPORT,
1817                                             DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1818                                             CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1819                                             &hpd);
1820                 /* TV - TV DAC */
1821                 ddc_i2c.valid = false;
1822                 hpd.hpd = RADEON_HPD_NONE;
1823                 radeon_add_legacy_encoder(dev,
1824                                           radeon_get_encoder_enum(dev,
1825                                                                 ATOM_DEVICE_TV1_SUPPORT,
1826                                                                 2),
1827                                           ATOM_DEVICE_TV1_SUPPORT);
1828                 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1829                                             DRM_MODE_CONNECTOR_SVIDEO,
1830                                             &ddc_i2c,
1831                                             CONNECTOR_OBJECT_ID_SVIDEO,
1832                                             &hpd);
1833                 break;
1834         case CT_POWERBOOK_VGA:
1835                 DRM_INFO("Connector Table: %d (powerbook vga)\n",
1836                          rdev->mode_info.connector_table);
1837                 /* LVDS */
1838                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1839                 hpd.hpd = RADEON_HPD_NONE;
1840                 radeon_add_legacy_encoder(dev,
1841                                           radeon_get_encoder_enum(dev,
1842                                                                 ATOM_DEVICE_LCD1_SUPPORT,
1843                                                                 0),
1844                                           ATOM_DEVICE_LCD1_SUPPORT);
1845                 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1846                                             DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1847                                             CONNECTOR_OBJECT_ID_LVDS,
1848                                             &hpd);
1849                 /* VGA - primary dac */
1850                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1851                 hpd.hpd = RADEON_HPD_NONE;
1852                 radeon_add_legacy_encoder(dev,
1853                                           radeon_get_encoder_enum(dev,
1854                                                                 ATOM_DEVICE_CRT1_SUPPORT,
1855                                                                 1),
1856                                           ATOM_DEVICE_CRT1_SUPPORT);
1857                 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT1_SUPPORT,
1858                                             DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1859                                             CONNECTOR_OBJECT_ID_VGA,
1860                                             &hpd);
1861                 /* TV - TV DAC */
1862                 ddc_i2c.valid = false;
1863                 hpd.hpd = RADEON_HPD_NONE;
1864                 radeon_add_legacy_encoder(dev,
1865                                           radeon_get_encoder_enum(dev,
1866                                                                 ATOM_DEVICE_TV1_SUPPORT,
1867                                                                 2),
1868                                           ATOM_DEVICE_TV1_SUPPORT);
1869                 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1870                                             DRM_MODE_CONNECTOR_SVIDEO,
1871                                             &ddc_i2c,
1872                                             CONNECTOR_OBJECT_ID_SVIDEO,
1873                                             &hpd);
1874                 break;
1875         case CT_MINI_EXTERNAL:
1876                 DRM_INFO("Connector Table: %d (mini external tmds)\n",
1877                          rdev->mode_info.connector_table);
1878                 /* DVI-I - tv dac, ext tmds */
1879                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
1880                 hpd.hpd = RADEON_HPD_2; /* ??? */
1881                 radeon_add_legacy_encoder(dev,
1882                                           radeon_get_encoder_enum(dev,
1883                                                                 ATOM_DEVICE_DFP2_SUPPORT,
1884                                                                 0),
1885                                           ATOM_DEVICE_DFP2_SUPPORT);
1886                 radeon_add_legacy_encoder(dev,
1887                                           radeon_get_encoder_enum(dev,
1888                                                                 ATOM_DEVICE_CRT2_SUPPORT,
1889                                                                 2),
1890                                           ATOM_DEVICE_CRT2_SUPPORT);
1891                 /* XXX are any DL? */
1892                 radeon_add_legacy_connector(dev, 0,
1893                                             ATOM_DEVICE_DFP2_SUPPORT |
1894                                             ATOM_DEVICE_CRT2_SUPPORT,
1895                                             DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1896                                             CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1897                                             &hpd);
1898                 /* TV - TV DAC */
1899                 ddc_i2c.valid = false;
1900                 hpd.hpd = RADEON_HPD_NONE;
1901                 radeon_add_legacy_encoder(dev,
1902                                           radeon_get_encoder_enum(dev,
1903                                                                 ATOM_DEVICE_TV1_SUPPORT,
1904                                                                 2),
1905                                           ATOM_DEVICE_TV1_SUPPORT);
1906                 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_TV1_SUPPORT,
1907                                             DRM_MODE_CONNECTOR_SVIDEO,
1908                                             &ddc_i2c,
1909                                             CONNECTOR_OBJECT_ID_SVIDEO,
1910                                             &hpd);
1911                 break;
1912         case CT_MINI_INTERNAL:
1913                 DRM_INFO("Connector Table: %d (mini internal tmds)\n",
1914                          rdev->mode_info.connector_table);
1915                 /* DVI-I - tv dac, int tmds */
1916                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
1917                 hpd.hpd = RADEON_HPD_1; /* ??? */
1918                 radeon_add_legacy_encoder(dev,
1919                                           radeon_get_encoder_enum(dev,
1920                                                                 ATOM_DEVICE_DFP1_SUPPORT,
1921                                                                 0),
1922                                           ATOM_DEVICE_DFP1_SUPPORT);
1923                 radeon_add_legacy_encoder(dev,
1924                                           radeon_get_encoder_enum(dev,
1925                                                                 ATOM_DEVICE_CRT2_SUPPORT,
1926                                                                 2),
1927                                           ATOM_DEVICE_CRT2_SUPPORT);
1928                 radeon_add_legacy_connector(dev, 0,
1929                                             ATOM_DEVICE_DFP1_SUPPORT |
1930                                             ATOM_DEVICE_CRT2_SUPPORT,
1931                                             DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1932                                             CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1933                                             &hpd);
1934                 /* TV - TV DAC */
1935                 ddc_i2c.valid = false;
1936                 hpd.hpd = RADEON_HPD_NONE;
1937                 radeon_add_legacy_encoder(dev,
1938                                           radeon_get_encoder_enum(dev,
1939                                                                 ATOM_DEVICE_TV1_SUPPORT,
1940                                                                 2),
1941                                           ATOM_DEVICE_TV1_SUPPORT);
1942                 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_TV1_SUPPORT,
1943                                             DRM_MODE_CONNECTOR_SVIDEO,
1944                                             &ddc_i2c,
1945                                             CONNECTOR_OBJECT_ID_SVIDEO,
1946                                             &hpd);
1947                 break;
1948         case CT_IMAC_G5_ISIGHT:
1949                 DRM_INFO("Connector Table: %d (imac g5 isight)\n",
1950                          rdev->mode_info.connector_table);
1951                 /* DVI-D - int tmds */
1952                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
1953                 hpd.hpd = RADEON_HPD_1; /* ??? */
1954                 radeon_add_legacy_encoder(dev,
1955                                           radeon_get_encoder_enum(dev,
1956                                                                 ATOM_DEVICE_DFP1_SUPPORT,
1957                                                                 0),
1958                                           ATOM_DEVICE_DFP1_SUPPORT);
1959                 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_DFP1_SUPPORT,
1960                                             DRM_MODE_CONNECTOR_DVID, &ddc_i2c,
1961                                             CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D,
1962                                             &hpd);
1963                 /* VGA - tv dac */
1964                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1965                 hpd.hpd = RADEON_HPD_NONE;
1966                 radeon_add_legacy_encoder(dev,
1967                                           radeon_get_encoder_enum(dev,
1968                                                                 ATOM_DEVICE_CRT2_SUPPORT,
1969                                                                 2),
1970                                           ATOM_DEVICE_CRT2_SUPPORT);
1971                 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
1972                                             DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1973                                             CONNECTOR_OBJECT_ID_VGA,
1974                                             &hpd);
1975                 /* TV - TV DAC */
1976                 ddc_i2c.valid = false;
1977                 hpd.hpd = RADEON_HPD_NONE;
1978                 radeon_add_legacy_encoder(dev,
1979                                           radeon_get_encoder_enum(dev,
1980                                                                 ATOM_DEVICE_TV1_SUPPORT,
1981                                                                 2),
1982                                           ATOM_DEVICE_TV1_SUPPORT);
1983                 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1984                                             DRM_MODE_CONNECTOR_SVIDEO,
1985                                             &ddc_i2c,
1986                                             CONNECTOR_OBJECT_ID_SVIDEO,
1987                                             &hpd);
1988                 break;
1989         case CT_EMAC:
1990                 DRM_INFO("Connector Table: %d (emac)\n",
1991                          rdev->mode_info.connector_table);
1992                 /* VGA - primary dac */
1993                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1994                 hpd.hpd = RADEON_HPD_NONE;
1995                 radeon_add_legacy_encoder(dev,
1996                                           radeon_get_encoder_enum(dev,
1997                                                                 ATOM_DEVICE_CRT1_SUPPORT,
1998                                                                 1),
1999                                           ATOM_DEVICE_CRT1_SUPPORT);
2000                 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_CRT1_SUPPORT,
2001                                             DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
2002                                             CONNECTOR_OBJECT_ID_VGA,
2003                                             &hpd);
2004                 /* VGA - tv dac */
2005                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
2006                 hpd.hpd = RADEON_HPD_NONE;
2007                 radeon_add_legacy_encoder(dev,
2008                                           radeon_get_encoder_enum(dev,
2009                                                                 ATOM_DEVICE_CRT2_SUPPORT,
2010                                                                 2),
2011                                           ATOM_DEVICE_CRT2_SUPPORT);
2012                 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
2013                                             DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
2014                                             CONNECTOR_OBJECT_ID_VGA,
2015                                             &hpd);
2016                 /* TV - TV DAC */
2017                 ddc_i2c.valid = false;
2018                 hpd.hpd = RADEON_HPD_NONE;
2019                 radeon_add_legacy_encoder(dev,
2020                                           radeon_get_encoder_enum(dev,
2021                                                                 ATOM_DEVICE_TV1_SUPPORT,
2022                                                                 2),
2023                                           ATOM_DEVICE_TV1_SUPPORT);
2024                 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
2025                                             DRM_MODE_CONNECTOR_SVIDEO,
2026                                             &ddc_i2c,
2027                                             CONNECTOR_OBJECT_ID_SVIDEO,
2028                                             &hpd);
2029                 break;
2030         case CT_RN50_POWER:
2031                 DRM_INFO("Connector Table: %d (rn50-power)\n",
2032                          rdev->mode_info.connector_table);
2033                 /* VGA - primary dac */
2034                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
2035                 hpd.hpd = RADEON_HPD_NONE;
2036                 radeon_add_legacy_encoder(dev,
2037                                           radeon_get_encoder_enum(dev,
2038                                                                 ATOM_DEVICE_CRT1_SUPPORT,
2039                                                                 1),
2040                                           ATOM_DEVICE_CRT1_SUPPORT);
2041                 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_CRT1_SUPPORT,
2042                                             DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
2043                                             CONNECTOR_OBJECT_ID_VGA,
2044                                             &hpd);
2045                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
2046                 hpd.hpd = RADEON_HPD_NONE;
2047                 radeon_add_legacy_encoder(dev,
2048                                           radeon_get_encoder_enum(dev,
2049                                                                 ATOM_DEVICE_CRT2_SUPPORT,
2050                                                                 2),
2051                                           ATOM_DEVICE_CRT2_SUPPORT);
2052                 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
2053                                             DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
2054                                             CONNECTOR_OBJECT_ID_VGA,
2055                                             &hpd);
2056                 break;
2057         case CT_MAC_X800:
2058                 DRM_INFO("Connector Table: %d (mac x800)\n",
2059                          rdev->mode_info.connector_table);
2060                 /* DVI - primary dac, internal tmds */
2061                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
2062                 hpd.hpd = RADEON_HPD_1; /* ??? */
2063                 radeon_add_legacy_encoder(dev,
2064                                           radeon_get_encoder_enum(dev,
2065                                                                   ATOM_DEVICE_DFP1_SUPPORT,
2066                                                                   0),
2067                                           ATOM_DEVICE_DFP1_SUPPORT);
2068                 radeon_add_legacy_encoder(dev,
2069                                           radeon_get_encoder_enum(dev,
2070                                                                   ATOM_DEVICE_CRT1_SUPPORT,
2071                                                                   1),
2072                                           ATOM_DEVICE_CRT1_SUPPORT);
2073                 radeon_add_legacy_connector(dev, 0,
2074                                             ATOM_DEVICE_DFP1_SUPPORT |
2075                                             ATOM_DEVICE_CRT1_SUPPORT,
2076                                             DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
2077                                             CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
2078                                             &hpd);
2079                 /* DVI - tv dac, dvo */
2080                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
2081                 hpd.hpd = RADEON_HPD_2; /* ??? */
2082                 radeon_add_legacy_encoder(dev,
2083                                           radeon_get_encoder_enum(dev,
2084                                                                   ATOM_DEVICE_DFP2_SUPPORT,
2085                                                                   0),
2086                                           ATOM_DEVICE_DFP2_SUPPORT);
2087                 radeon_add_legacy_encoder(dev,
2088                                           radeon_get_encoder_enum(dev,
2089                                                                   ATOM_DEVICE_CRT2_SUPPORT,
2090                                                                   2),
2091                                           ATOM_DEVICE_CRT2_SUPPORT);
2092                 radeon_add_legacy_connector(dev, 1,
2093                                             ATOM_DEVICE_DFP2_SUPPORT |
2094                                             ATOM_DEVICE_CRT2_SUPPORT,
2095                                             DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
2096                                             CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I,
2097                                             &hpd);
2098                 break;
2099         case CT_MAC_G5_9600:
2100                 DRM_INFO("Connector Table: %d (mac g5 9600)\n",
2101                          rdev->mode_info.connector_table);
2102                 /* DVI - tv dac, dvo */
2103                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
2104                 hpd.hpd = RADEON_HPD_1; /* ??? */
2105                 radeon_add_legacy_encoder(dev,
2106                                           radeon_get_encoder_enum(dev,
2107                                                                   ATOM_DEVICE_DFP2_SUPPORT,
2108                                                                   0),
2109                                           ATOM_DEVICE_DFP2_SUPPORT);
2110                 radeon_add_legacy_encoder(dev,
2111                                           radeon_get_encoder_enum(dev,
2112                                                                   ATOM_DEVICE_CRT2_SUPPORT,
2113                                                                   2),
2114                                           ATOM_DEVICE_CRT2_SUPPORT);
2115                 radeon_add_legacy_connector(dev, 0,
2116                                             ATOM_DEVICE_DFP2_SUPPORT |
2117                                             ATOM_DEVICE_CRT2_SUPPORT,
2118                                             DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
2119                                             CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
2120                                             &hpd);
2121                 /* ADC - primary dac, internal tmds */
2122                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
2123                 hpd.hpd = RADEON_HPD_2; /* ??? */
2124                 radeon_add_legacy_encoder(dev,
2125                                           radeon_get_encoder_enum(dev,
2126                                                                   ATOM_DEVICE_DFP1_SUPPORT,
2127                                                                   0),
2128                                           ATOM_DEVICE_DFP1_SUPPORT);
2129                 radeon_add_legacy_encoder(dev,
2130                                           radeon_get_encoder_enum(dev,
2131                                                                   ATOM_DEVICE_CRT1_SUPPORT,
2132                                                                   1),
2133                                           ATOM_DEVICE_CRT1_SUPPORT);
2134                 radeon_add_legacy_connector(dev, 1,
2135                                             ATOM_DEVICE_DFP1_SUPPORT |
2136                                             ATOM_DEVICE_CRT1_SUPPORT,
2137                                             DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
2138                                             CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
2139                                             &hpd);
2140                 /* TV - TV DAC */
2141                 ddc_i2c.valid = false;
2142                 hpd.hpd = RADEON_HPD_NONE;
2143                 radeon_add_legacy_encoder(dev,
2144                                           radeon_get_encoder_enum(dev,
2145                                                                 ATOM_DEVICE_TV1_SUPPORT,
2146                                                                 2),
2147                                           ATOM_DEVICE_TV1_SUPPORT);
2148                 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
2149                                             DRM_MODE_CONNECTOR_SVIDEO,
2150                                             &ddc_i2c,
2151                                             CONNECTOR_OBJECT_ID_SVIDEO,
2152                                             &hpd);
2153                 break;
2154         case CT_SAM440EP:
2155                 DRM_INFO("Connector Table: %d (SAM440ep embedded board)\n",
2156                          rdev->mode_info.connector_table);
2157                 /* LVDS */
2158                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_NONE_DETECTED, 0, 0);
2159                 hpd.hpd = RADEON_HPD_NONE;
2160                 radeon_add_legacy_encoder(dev,
2161                                           radeon_get_encoder_enum(dev,
2162                                                                 ATOM_DEVICE_LCD1_SUPPORT,
2163                                                                 0),
2164                                           ATOM_DEVICE_LCD1_SUPPORT);
2165                 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
2166                                             DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
2167                                             CONNECTOR_OBJECT_ID_LVDS,
2168                                             &hpd);
2169                 /* DVI-I - secondary dac, int tmds */
2170                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
2171                 hpd.hpd = RADEON_HPD_1; /* ??? */
2172                 radeon_add_legacy_encoder(dev,
2173                                           radeon_get_encoder_enum(dev,
2174                                                                 ATOM_DEVICE_DFP1_SUPPORT,
2175                                                                 0),
2176                                           ATOM_DEVICE_DFP1_SUPPORT);
2177                 radeon_add_legacy_encoder(dev,
2178                                           radeon_get_encoder_enum(dev,
2179                                                                 ATOM_DEVICE_CRT2_SUPPORT,
2180                                                                 2),
2181                                           ATOM_DEVICE_CRT2_SUPPORT);
2182                 radeon_add_legacy_connector(dev, 1,
2183                                             ATOM_DEVICE_DFP1_SUPPORT |
2184                                             ATOM_DEVICE_CRT2_SUPPORT,
2185                                             DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
2186                                             CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
2187                                             &hpd);
2188                 /* VGA - primary dac */
2189                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
2190                 hpd.hpd = RADEON_HPD_NONE;
2191                 radeon_add_legacy_encoder(dev,
2192                                           radeon_get_encoder_enum(dev,
2193                                                                 ATOM_DEVICE_CRT1_SUPPORT,
2194                                                                 1),
2195                                           ATOM_DEVICE_CRT1_SUPPORT);
2196                 radeon_add_legacy_connector(dev, 2,
2197                                             ATOM_DEVICE_CRT1_SUPPORT,
2198                                             DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
2199                                             CONNECTOR_OBJECT_ID_VGA,
2200                                             &hpd);
2201                 /* TV - TV DAC */
2202                 ddc_i2c.valid = false;
2203                 hpd.hpd = RADEON_HPD_NONE;
2204                 radeon_add_legacy_encoder(dev,
2205                                           radeon_get_encoder_enum(dev,
2206                                                                 ATOM_DEVICE_TV1_SUPPORT,
2207                                                                 2),
2208                                           ATOM_DEVICE_TV1_SUPPORT);
2209                 radeon_add_legacy_connector(dev, 3, ATOM_DEVICE_TV1_SUPPORT,
2210                                             DRM_MODE_CONNECTOR_SVIDEO,
2211                                             &ddc_i2c,
2212                                             CONNECTOR_OBJECT_ID_SVIDEO,
2213                                             &hpd);
2214                 break;
2215         case CT_MAC_G4_SILVER:
2216                 DRM_INFO("Connector Table: %d (mac g4 silver)\n",
2217                          rdev->mode_info.connector_table);
2218                 /* DVI-I - tv dac, int tmds */
2219                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
2220                 hpd.hpd = RADEON_HPD_1; /* ??? */
2221                 radeon_add_legacy_encoder(dev,
2222                                           radeon_get_encoder_enum(dev,
2223                                                                 ATOM_DEVICE_DFP1_SUPPORT,
2224                                                                 0),
2225                                           ATOM_DEVICE_DFP1_SUPPORT);
2226                 radeon_add_legacy_encoder(dev,
2227                                           radeon_get_encoder_enum(dev,
2228                                                                 ATOM_DEVICE_CRT2_SUPPORT,
2229                                                                 2),
2230                                           ATOM_DEVICE_CRT2_SUPPORT);
2231                 radeon_add_legacy_connector(dev, 0,
2232                                             ATOM_DEVICE_DFP1_SUPPORT |
2233                                             ATOM_DEVICE_CRT2_SUPPORT,
2234                                             DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
2235                                             CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
2236                                             &hpd);
2237                 /* VGA - primary dac */
2238                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
2239                 hpd.hpd = RADEON_HPD_NONE;
2240                 radeon_add_legacy_encoder(dev,
2241                                           radeon_get_encoder_enum(dev,
2242                                                                 ATOM_DEVICE_CRT1_SUPPORT,
2243                                                                 1),
2244                                           ATOM_DEVICE_CRT1_SUPPORT);
2245                 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT1_SUPPORT,
2246                                             DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
2247                                             CONNECTOR_OBJECT_ID_VGA,
2248                                             &hpd);
2249                 /* TV - TV DAC */
2250                 ddc_i2c.valid = false;
2251                 hpd.hpd = RADEON_HPD_NONE;
2252                 radeon_add_legacy_encoder(dev,
2253                                           radeon_get_encoder_enum(dev,
2254                                                                 ATOM_DEVICE_TV1_SUPPORT,
2255                                                                 2),
2256                                           ATOM_DEVICE_TV1_SUPPORT);
2257                 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
2258                                             DRM_MODE_CONNECTOR_SVIDEO,
2259                                             &ddc_i2c,
2260                                             CONNECTOR_OBJECT_ID_SVIDEO,
2261                                             &hpd);
2262                 break;
2263         default:
2264                 DRM_INFO("Connector table: %d (invalid)\n",
2265                          rdev->mode_info.connector_table);
2266                 return false;
2267         }
2268
2269         radeon_link_encoder_connector(dev);
2270
2271         return true;
2272 }
2273
2274 static bool radeon_apply_legacy_quirks(struct drm_device *dev,
2275                                        int bios_index,
2276                                        enum radeon_combios_connector
2277                                        *legacy_connector,
2278                                        struct radeon_i2c_bus_rec *ddc_i2c,
2279                                        struct radeon_hpd *hpd)
2280 {
2281
2282         /* Certain IBM chipset RN50s have a BIOS reporting two VGAs,
2283            one with VGA DDC and one with CRT2 DDC. - kill the CRT2 DDC one */
2284         if (dev->pdev->device == 0x515e &&
2285             dev->pdev->subsystem_vendor == 0x1014) {
2286                 if (*legacy_connector == CONNECTOR_CRT_LEGACY &&
2287                     ddc_i2c->mask_clk_reg == RADEON_GPIO_CRT2_DDC)
2288                         return false;
2289         }
2290
2291         /* X300 card with extra non-existent DVI port */
2292         if (dev->pdev->device == 0x5B60 &&
2293             dev->pdev->subsystem_vendor == 0x17af &&
2294             dev->pdev->subsystem_device == 0x201e && bios_index == 2) {
2295                 if (*legacy_connector == CONNECTOR_DVI_I_LEGACY)
2296                         return false;
2297         }
2298
2299         return true;
2300 }
2301
2302 static bool radeon_apply_legacy_tv_quirks(struct drm_device *dev)
2303 {
2304         /* Acer 5102 has non-existent TV port */
2305         if (dev->pdev->device == 0x5975 &&
2306             dev->pdev->subsystem_vendor == 0x1025 &&
2307             dev->pdev->subsystem_device == 0x009f)
2308                 return false;
2309
2310         /* HP dc5750 has non-existent TV port */
2311         if (dev->pdev->device == 0x5974 &&
2312             dev->pdev->subsystem_vendor == 0x103c &&
2313             dev->pdev->subsystem_device == 0x280a)
2314                 return false;
2315
2316         /* MSI S270 has non-existent TV port */
2317         if (dev->pdev->device == 0x5955 &&
2318             dev->pdev->subsystem_vendor == 0x1462 &&
2319             dev->pdev->subsystem_device == 0x0131)
2320                 return false;
2321
2322         return true;
2323 }
2324
2325 static uint16_t combios_check_dl_dvi(struct drm_device *dev, int is_dvi_d)
2326 {
2327         struct radeon_device *rdev = dev->dev_private;
2328         uint32_t ext_tmds_info;
2329
2330         if (rdev->flags & RADEON_IS_IGP) {
2331                 if (is_dvi_d)
2332                         return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
2333                 else
2334                         return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
2335         }
2336         ext_tmds_info = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
2337         if (ext_tmds_info) {
2338                 uint8_t rev = RBIOS8(ext_tmds_info);
2339                 uint8_t flags = RBIOS8(ext_tmds_info + 4 + 5);
2340                 if (rev >= 3) {
2341                         if (is_dvi_d)
2342                                 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
2343                         else
2344                                 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
2345                 } else {
2346                         if (flags & 1) {
2347                                 if (is_dvi_d)
2348                                         return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
2349                                 else
2350                                         return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
2351                         }
2352                 }
2353         }
2354         if (is_dvi_d)
2355                 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
2356         else
2357                 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
2358 }
2359
2360 bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev)
2361 {
2362         struct radeon_device *rdev = dev->dev_private;
2363         uint32_t conn_info, entry, devices;
2364         uint16_t tmp, connector_object_id;
2365         enum radeon_combios_ddc ddc_type;
2366         enum radeon_combios_connector connector;
2367         int i = 0;
2368         struct radeon_i2c_bus_rec ddc_i2c;
2369         struct radeon_hpd hpd;
2370
2371         conn_info = combios_get_table_offset(dev, COMBIOS_CONNECTOR_INFO_TABLE);
2372         if (conn_info) {
2373                 for (i = 0; i < 4; i++) {
2374                         entry = conn_info + 2 + i * 2;
2375
2376                         if (!RBIOS16(entry))
2377                                 break;
2378
2379                         tmp = RBIOS16(entry);
2380
2381                         connector = (tmp >> 12) & 0xf;
2382
2383                         ddc_type = (tmp >> 8) & 0xf;
2384                         ddc_i2c = combios_setup_i2c_bus(rdev, ddc_type, 0, 0);
2385
2386                         switch (connector) {
2387                         case CONNECTOR_PROPRIETARY_LEGACY:
2388                         case CONNECTOR_DVI_I_LEGACY:
2389                         case CONNECTOR_DVI_D_LEGACY:
2390                                 if ((tmp >> 4) & 0x1)
2391                                         hpd.hpd = RADEON_HPD_2;
2392                                 else
2393                                         hpd.hpd = RADEON_HPD_1;
2394                                 break;
2395                         default:
2396                                 hpd.hpd = RADEON_HPD_NONE;
2397                                 break;
2398                         }
2399
2400                         if (!radeon_apply_legacy_quirks(dev, i, &connector,
2401                                                         &ddc_i2c, &hpd))
2402                                 continue;
2403
2404                         switch (connector) {
2405                         case CONNECTOR_PROPRIETARY_LEGACY:
2406                                 if ((tmp >> 4) & 0x1)
2407                                         devices = ATOM_DEVICE_DFP2_SUPPORT;
2408                                 else
2409                                         devices = ATOM_DEVICE_DFP1_SUPPORT;
2410                                 radeon_add_legacy_encoder(dev,
2411                                                           radeon_get_encoder_enum
2412                                                           (dev, devices, 0),
2413                                                           devices);
2414                                 radeon_add_legacy_connector(dev, i, devices,
2415                                                             legacy_connector_convert
2416                                                             [connector],
2417                                                             &ddc_i2c,
2418                                                             CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D,
2419                                                             &hpd);
2420                                 break;
2421                         case CONNECTOR_CRT_LEGACY:
2422                                 if (tmp & 0x1) {
2423                                         devices = ATOM_DEVICE_CRT2_SUPPORT;
2424                                         radeon_add_legacy_encoder(dev,
2425                                                                   radeon_get_encoder_enum
2426                                                                   (dev,
2427                                                                    ATOM_DEVICE_CRT2_SUPPORT,
2428                                                                    2),
2429                                                                   ATOM_DEVICE_CRT2_SUPPORT);
2430                                 } else {
2431                                         devices = ATOM_DEVICE_CRT1_SUPPORT;
2432                                         radeon_add_legacy_encoder(dev,
2433                                                                   radeon_get_encoder_enum
2434                                                                   (dev,
2435                                                                    ATOM_DEVICE_CRT1_SUPPORT,
2436                                                                    1),
2437                                                                   ATOM_DEVICE_CRT1_SUPPORT);
2438                                 }
2439                                 radeon_add_legacy_connector(dev,
2440                                                             i,
2441                                                             devices,
2442                                                             legacy_connector_convert
2443                                                             [connector],
2444                                                             &ddc_i2c,
2445                                                             CONNECTOR_OBJECT_ID_VGA,
2446                                                             &hpd);
2447                                 break;
2448                         case CONNECTOR_DVI_I_LEGACY:
2449                                 devices = 0;
2450                                 if (tmp & 0x1) {
2451                                         devices |= ATOM_DEVICE_CRT2_SUPPORT;
2452                                         radeon_add_legacy_encoder(dev,
2453                                                                   radeon_get_encoder_enum
2454                                                                   (dev,
2455                                                                    ATOM_DEVICE_CRT2_SUPPORT,
2456                                                                    2),
2457                                                                   ATOM_DEVICE_CRT2_SUPPORT);
2458                                 } else {
2459                                         devices |= ATOM_DEVICE_CRT1_SUPPORT;
2460                                         radeon_add_legacy_encoder(dev,
2461                                                                   radeon_get_encoder_enum
2462                                                                   (dev,
2463                                                                    ATOM_DEVICE_CRT1_SUPPORT,
2464                                                                    1),
2465                                                                   ATOM_DEVICE_CRT1_SUPPORT);
2466                                 }
2467                                 /* RV100 board with external TDMS bit mis-set.
2468                                  * Actually uses internal TMDS, clear the bit.
2469                                  */
2470                                 if (dev->pdev->device == 0x5159 &&
2471                                     dev->pdev->subsystem_vendor == 0x1014 &&
2472                                     dev->pdev->subsystem_device == 0x029A) {
2473                                         tmp &= ~(1 << 4);
2474                                 }
2475                                 if ((tmp >> 4) & 0x1) {
2476                                         devices |= ATOM_DEVICE_DFP2_SUPPORT;
2477                                         radeon_add_legacy_encoder(dev,
2478                                                                   radeon_get_encoder_enum
2479                                                                   (dev,
2480                                                                    ATOM_DEVICE_DFP2_SUPPORT,
2481                                                                    0),
2482                                                                   ATOM_DEVICE_DFP2_SUPPORT);
2483                                         connector_object_id = combios_check_dl_dvi(dev, 0);
2484                                 } else {
2485                                         devices |= ATOM_DEVICE_DFP1_SUPPORT;
2486                                         radeon_add_legacy_encoder(dev,
2487                                                                   radeon_get_encoder_enum
2488                                                                   (dev,
2489                                                                    ATOM_DEVICE_DFP1_SUPPORT,
2490                                                                    0),
2491                                                                   ATOM_DEVICE_DFP1_SUPPORT);
2492                                         connector_object_id = CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
2493                                 }
2494                                 radeon_add_legacy_connector(dev,
2495                                                             i,
2496                                                             devices,
2497                                                             legacy_connector_convert
2498                                                             [connector],
2499                                                             &ddc_i2c,
2500                                                             connector_object_id,
2501                                                             &hpd);
2502                                 break;
2503                         case CONNECTOR_DVI_D_LEGACY:
2504                                 if ((tmp >> 4) & 0x1) {
2505                                         devices = ATOM_DEVICE_DFP2_SUPPORT;
2506                                         connector_object_id = combios_check_dl_dvi(dev, 1);
2507                                 } else {
2508                                         devices = ATOM_DEVICE_DFP1_SUPPORT;
2509                                         connector_object_id = CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
2510                                 }
2511                                 radeon_add_legacy_encoder(dev,
2512                                                           radeon_get_encoder_enum
2513                                                           (dev, devices, 0),
2514                                                           devices);
2515                                 radeon_add_legacy_connector(dev, i, devices,
2516                                                             legacy_connector_convert
2517                                                             [connector],
2518                                                             &ddc_i2c,
2519                                                             connector_object_id,
2520                                                             &hpd);
2521                                 break;
2522                         case CONNECTOR_CTV_LEGACY:
2523                         case CONNECTOR_STV_LEGACY:
2524                                 radeon_add_legacy_encoder(dev,
2525                                                           radeon_get_encoder_enum
2526                                                           (dev,
2527                                                            ATOM_DEVICE_TV1_SUPPORT,
2528                                                            2),
2529                                                           ATOM_DEVICE_TV1_SUPPORT);
2530                                 radeon_add_legacy_connector(dev, i,
2531                                                             ATOM_DEVICE_TV1_SUPPORT,
2532                                                             legacy_connector_convert
2533                                                             [connector],
2534                                                             &ddc_i2c,
2535                                                             CONNECTOR_OBJECT_ID_SVIDEO,
2536                                                             &hpd);
2537                                 break;
2538                         default:
2539                                 DRM_ERROR("Unknown connector type: %d\n",
2540                                           connector);
2541                                 continue;
2542                         }
2543
2544                 }
2545         } else {
2546                 uint16_t tmds_info =
2547                     combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE);
2548                 if (tmds_info) {
2549                         DRM_DEBUG_KMS("Found DFP table, assuming DVI connector\n");
2550
2551                         radeon_add_legacy_encoder(dev,
2552                                                   radeon_get_encoder_enum(dev,
2553                                                                         ATOM_DEVICE_CRT1_SUPPORT,
2554                                                                         1),
2555                                                   ATOM_DEVICE_CRT1_SUPPORT);
2556                         radeon_add_legacy_encoder(dev,
2557                                                   radeon_get_encoder_enum(dev,
2558                                                                         ATOM_DEVICE_DFP1_SUPPORT,
2559                                                                         0),
2560                                                   ATOM_DEVICE_DFP1_SUPPORT);
2561
2562                         ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
2563                         hpd.hpd = RADEON_HPD_1;
2564                         radeon_add_legacy_connector(dev,
2565                                                     0,
2566                                                     ATOM_DEVICE_CRT1_SUPPORT |
2567                                                     ATOM_DEVICE_DFP1_SUPPORT,
2568                                                     DRM_MODE_CONNECTOR_DVII,
2569                                                     &ddc_i2c,
2570                                                     CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
2571                                                     &hpd);
2572                 } else {
2573                         uint16_t crt_info =
2574                                 combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
2575                         DRM_DEBUG_KMS("Found CRT table, assuming VGA connector\n");
2576                         if (crt_info) {
2577                                 radeon_add_legacy_encoder(dev,
2578                                                           radeon_get_encoder_enum(dev,
2579                                                                                 ATOM_DEVICE_CRT1_SUPPORT,
2580                                                                                 1),
2581                                                           ATOM_DEVICE_CRT1_SUPPORT);
2582                                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
2583                                 hpd.hpd = RADEON_HPD_NONE;
2584                                 radeon_add_legacy_connector(dev,
2585                                                             0,
2586                                                             ATOM_DEVICE_CRT1_SUPPORT,
2587                                                             DRM_MODE_CONNECTOR_VGA,
2588                                                             &ddc_i2c,
2589                                                             CONNECTOR_OBJECT_ID_VGA,
2590                                                             &hpd);
2591                         } else {
2592                                 DRM_DEBUG_KMS("No connector info found\n");
2593                                 return false;
2594                         }
2595                 }
2596         }
2597
2598         if (rdev->flags & RADEON_IS_MOBILITY || rdev->flags & RADEON_IS_IGP) {
2599                 uint16_t lcd_info =
2600                     combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE);
2601                 if (lcd_info) {
2602                         uint16_t lcd_ddc_info =
2603                             combios_get_table_offset(dev,
2604                                                      COMBIOS_LCD_DDC_INFO_TABLE);
2605
2606                         radeon_add_legacy_encoder(dev,
2607                                                   radeon_get_encoder_enum(dev,
2608                                                                         ATOM_DEVICE_LCD1_SUPPORT,
2609                                                                         0),
2610                                                   ATOM_DEVICE_LCD1_SUPPORT);
2611
2612                         if (lcd_ddc_info) {
2613                                 ddc_type = RBIOS8(lcd_ddc_info + 2);
2614                                 switch (ddc_type) {
2615                                 case DDC_LCD:
2616                                         ddc_i2c =
2617                                                 combios_setup_i2c_bus(rdev,
2618                                                                       DDC_LCD,
2619                                                                       RBIOS32(lcd_ddc_info + 3),
2620                                                                       RBIOS32(lcd_ddc_info + 7));
2621                                         radeon_i2c_add(rdev, &ddc_i2c, "LCD");
2622                                         break;
2623                                 case DDC_GPIO:
2624                                         ddc_i2c =
2625                                                 combios_setup_i2c_bus(rdev,
2626                                                                       DDC_GPIO,
2627                                                                       RBIOS32(lcd_ddc_info + 3),
2628                                                                       RBIOS32(lcd_ddc_info + 7));
2629                                         radeon_i2c_add(rdev, &ddc_i2c, "LCD");
2630                                         break;
2631                                 default:
2632                                         ddc_i2c =
2633                                                 combios_setup_i2c_bus(rdev, ddc_type, 0, 0);
2634                                         break;
2635                                 }
2636                                 DRM_DEBUG_KMS("LCD DDC Info Table found!\n");
2637                         } else
2638                                 ddc_i2c.valid = false;
2639
2640                         hpd.hpd = RADEON_HPD_NONE;
2641                         radeon_add_legacy_connector(dev,
2642                                                     5,
2643                                                     ATOM_DEVICE_LCD1_SUPPORT,
2644                                                     DRM_MODE_CONNECTOR_LVDS,
2645                                                     &ddc_i2c,
2646                                                     CONNECTOR_OBJECT_ID_LVDS,
2647                                                     &hpd);
2648                 }
2649         }
2650
2651         /* check TV table */
2652         if (rdev->family != CHIP_R100 && rdev->family != CHIP_R200) {
2653                 uint32_t tv_info =
2654                     combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
2655                 if (tv_info) {
2656                         if (RBIOS8(tv_info + 6) == 'T') {
2657                                 if (radeon_apply_legacy_tv_quirks(dev)) {
2658                                         hpd.hpd = RADEON_HPD_NONE;
2659                                         ddc_i2c.valid = false;
2660                                         radeon_add_legacy_encoder(dev,
2661                                                                   radeon_get_encoder_enum
2662                                                                   (dev,
2663                                                                    ATOM_DEVICE_TV1_SUPPORT,
2664                                                                    2),
2665                                                                   ATOM_DEVICE_TV1_SUPPORT);
2666                                         radeon_add_legacy_connector(dev, 6,
2667                                                                     ATOM_DEVICE_TV1_SUPPORT,
2668                                                                     DRM_MODE_CONNECTOR_SVIDEO,
2669                                                                     &ddc_i2c,
2670                                                                     CONNECTOR_OBJECT_ID_SVIDEO,
2671                                                                     &hpd);
2672                                 }
2673                         }
2674                 }
2675         }
2676
2677         radeon_link_encoder_connector(dev);
2678
2679         return true;
2680 }
2681
2682 static const char *thermal_controller_names[] = {
2683         "NONE",
2684         "lm63",
2685         "adm1032",
2686 };
2687
2688 void radeon_combios_get_power_modes(struct radeon_device *rdev)
2689 {
2690         struct drm_device *dev = rdev->ddev;
2691         u16 offset, misc, misc2 = 0;
2692         u8 rev, blocks, tmp;
2693         int state_index = 0;
2694         struct radeon_i2c_bus_rec i2c_bus;
2695
2696         rdev->pm.default_power_state_index = -1;
2697
2698         /* allocate 2 power states */
2699         rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) * 2, GFP_KERNEL);
2700         if (rdev->pm.power_state) {
2701                 /* allocate 1 clock mode per state */
2702                 rdev->pm.power_state[0].clock_info =
2703                         kzalloc(sizeof(struct radeon_pm_clock_info) * 1, GFP_KERNEL);
2704                 rdev->pm.power_state[1].clock_info =
2705                         kzalloc(sizeof(struct radeon_pm_clock_info) * 1, GFP_KERNEL);
2706                 if (!rdev->pm.power_state[0].clock_info ||
2707                     !rdev->pm.power_state[1].clock_info)
2708                         goto pm_failed;
2709         } else
2710                 goto pm_failed;
2711
2712         /* check for a thermal chip */
2713         offset = combios_get_table_offset(dev, COMBIOS_OVERDRIVE_INFO_TABLE);
2714         if (offset) {
2715                 u8 thermal_controller = 0, gpio = 0, i2c_addr = 0, clk_bit = 0, data_bit = 0;
2716
2717                 rev = RBIOS8(offset);
2718
2719                 if (rev == 0) {
2720                         thermal_controller = RBIOS8(offset + 3);
2721                         gpio = RBIOS8(offset + 4) & 0x3f;
2722                         i2c_addr = RBIOS8(offset + 5);
2723                 } else if (rev == 1) {
2724                         thermal_controller = RBIOS8(offset + 4);
2725                         gpio = RBIOS8(offset + 5) & 0x3f;
2726                         i2c_addr = RBIOS8(offset + 6);
2727                 } else if (rev == 2) {
2728                         thermal_controller = RBIOS8(offset + 4);
2729                         gpio = RBIOS8(offset + 5) & 0x3f;
2730                         i2c_addr = RBIOS8(offset + 6);
2731                         clk_bit = RBIOS8(offset + 0xa);
2732                         data_bit = RBIOS8(offset + 0xb);
2733                 }
2734                 if ((thermal_controller > 0) && (thermal_controller < 3)) {
2735                         DRM_INFO("Possible %s thermal controller at 0x%02x\n",
2736                                  thermal_controller_names[thermal_controller],
2737                                  i2c_addr >> 1);
2738                         if (gpio == DDC_LCD) {
2739                                 /* MM i2c */
2740                                 i2c_bus.valid = true;
2741                                 i2c_bus.hw_capable = true;
2742                                 i2c_bus.mm_i2c = true;
2743                                 i2c_bus.i2c_id = 0xa0;
2744                         } else if (gpio == DDC_GPIO)
2745                                 i2c_bus = combios_setup_i2c_bus(rdev, gpio, 1 << clk_bit, 1 << data_bit);
2746                         else
2747                                 i2c_bus = combios_setup_i2c_bus(rdev, gpio, 0, 0);
2748                         rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
2749                         if (rdev->pm.i2c_bus) {
2750                                 struct i2c_board_info info = { };
2751                                 const char *name = thermal_controller_names[thermal_controller];
2752                                 info.addr = i2c_addr >> 1;
2753                                 strlcpy(info.type, name, sizeof(info.type));
2754                                 i2c_new_device(&rdev->pm.i2c_bus->adapter, &info);
2755                         }
2756                 }
2757         } else {
2758                 /* boards with a thermal chip, but no overdrive table */
2759
2760                 /* Asus 9600xt has an f75375 on the monid bus */
2761                 if ((dev->pdev->device == 0x4152) &&
2762                     (dev->pdev->subsystem_vendor == 0x1043) &&
2763                     (dev->pdev->subsystem_device == 0xc002)) {
2764                         i2c_bus = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
2765                         rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
2766                         if (rdev->pm.i2c_bus) {
2767                                 struct i2c_board_info info = { };
2768                                 const char *name = "f75375";
2769                                 info.addr = 0x28;
2770                                 strlcpy(info.type, name, sizeof(info.type));
2771                                 i2c_new_device(&rdev->pm.i2c_bus->adapter, &info);
2772                                 DRM_INFO("Possible %s thermal controller at 0x%02x\n",
2773                                          name, info.addr);
2774                         }
2775                 }
2776         }
2777
2778         if (rdev->flags & RADEON_IS_MOBILITY) {
2779                 offset = combios_get_table_offset(dev, COMBIOS_POWERPLAY_INFO_TABLE);
2780                 if (offset) {
2781                         rev = RBIOS8(offset);
2782                         blocks = RBIOS8(offset + 0x2);
2783                         /* power mode 0 tends to be the only valid one */
2784                         rdev->pm.power_state[state_index].num_clock_modes = 1;
2785                         rdev->pm.power_state[state_index].clock_info[0].mclk = RBIOS32(offset + 0x5 + 0x2);
2786                         rdev->pm.power_state[state_index].clock_info[0].sclk = RBIOS32(offset + 0x5 + 0x6);
2787                         if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2788                             (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2789                                 goto default_mode;
2790                         rdev->pm.power_state[state_index].type =
2791                                 POWER_STATE_TYPE_BATTERY;
2792                         misc = RBIOS16(offset + 0x5 + 0x0);
2793                         if (rev > 4)
2794                                 misc2 = RBIOS16(offset + 0x5 + 0xe);
2795                         rdev->pm.power_state[state_index].misc = misc;
2796                         rdev->pm.power_state[state_index].misc2 = misc2;
2797                         if (misc & 0x4) {
2798                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_GPIO;
2799                                 if (misc & 0x8)
2800                                         rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2801                                                 true;
2802                                 else
2803                                         rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2804                                                 false;
2805                                 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.valid = true;
2806                                 if (rev < 6) {
2807                                         rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.reg =
2808                                                 RBIOS16(offset + 0x5 + 0xb) * 4;
2809                                         tmp = RBIOS8(offset + 0x5 + 0xd);
2810                                         rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.mask = (1 << tmp);
2811                                 } else {
2812                                         u8 entries = RBIOS8(offset + 0x5 + 0xb);
2813                                         u16 voltage_table_offset = RBIOS16(offset + 0x5 + 0xc);
2814                                         if (entries && voltage_table_offset) {
2815                                                 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.reg =
2816                                                         RBIOS16(voltage_table_offset) * 4;
2817                                                 tmp = RBIOS8(voltage_table_offset + 0x2);
2818                                                 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.mask = (1 << tmp);
2819                                         } else
2820                                                 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.valid = false;
2821                                 }
2822                                 switch ((misc2 & 0x700) >> 8) {
2823                                 case 0:
2824                                 default:
2825                                         rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 0;
2826                                         break;
2827                                 case 1:
2828                                         rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 33;
2829                                         break;
2830                                 case 2:
2831                                         rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 66;
2832                                         break;
2833                                 case 3:
2834                                         rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 99;
2835                                         break;
2836                                 case 4:
2837                                         rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 132;
2838                                         break;
2839                                 }
2840                         } else
2841                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2842                         if (rev > 6)
2843                                 rdev->pm.power_state[state_index].pcie_lanes =
2844                                         RBIOS8(offset + 0x5 + 0x10);
2845                         rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2846                         state_index++;
2847                 } else {
2848                         /* XXX figure out some good default low power mode for mobility cards w/out power tables */
2849                 }
2850         } else {
2851                 /* XXX figure out some good default low power mode for desktop cards */
2852         }
2853
2854 default_mode:
2855         /* add the default mode */
2856         rdev->pm.power_state[state_index].type =
2857                 POWER_STATE_TYPE_DEFAULT;
2858         rdev->pm.power_state[state_index].num_clock_modes = 1;
2859         rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk;
2860         rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk;
2861         rdev->pm.power_state[state_index].default_clock_mode = &rdev->pm.power_state[state_index].clock_info[0];
2862         if ((state_index > 0) &&
2863             (rdev->pm.power_state[0].clock_info[0].voltage.type == VOLTAGE_GPIO))
2864                 rdev->pm.power_state[state_index].clock_info[0].voltage =
2865                         rdev->pm.power_state[0].clock_info[0].voltage;
2866         else
2867                 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2868         rdev->pm.power_state[state_index].pcie_lanes = 16;
2869         rdev->pm.power_state[state_index].flags = 0;
2870         rdev->pm.default_power_state_index = state_index;
2871         rdev->pm.num_power_states = state_index + 1;
2872
2873         rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
2874         rdev->pm.current_clock_mode_index = 0;
2875         return;
2876
2877 pm_failed:
2878         rdev->pm.default_power_state_index = state_index;
2879         rdev->pm.num_power_states = 0;
2880
2881         rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
2882         rdev->pm.current_clock_mode_index = 0;
2883 }
2884
2885 void radeon_external_tmds_setup(struct drm_encoder *encoder)
2886 {
2887         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2888         struct radeon_encoder_ext_tmds *tmds = radeon_encoder->enc_priv;
2889
2890         if (!tmds)
2891                 return;
2892
2893         switch (tmds->dvo_chip) {
2894         case DVO_SIL164:
2895                 /* sil 164 */
2896                 radeon_i2c_put_byte(tmds->i2c_bus,
2897                                     tmds->slave_addr,
2898                                     0x08, 0x30);
2899                 radeon_i2c_put_byte(tmds->i2c_bus,
2900                                        tmds->slave_addr,
2901                                        0x09, 0x00);
2902                 radeon_i2c_put_byte(tmds->i2c_bus,
2903                                     tmds->slave_addr,
2904                                     0x0a, 0x90);
2905                 radeon_i2c_put_byte(tmds->i2c_bus,
2906                                     tmds->slave_addr,
2907                                     0x0c, 0x89);
2908                 radeon_i2c_put_byte(tmds->i2c_bus,
2909                                        tmds->slave_addr,
2910                                        0x08, 0x3b);
2911                 break;
2912         case DVO_SIL1178:
2913                 /* sil 1178 - untested */
2914                 /*
2915                  * 0x0f, 0x44
2916                  * 0x0f, 0x4c
2917                  * 0x0e, 0x01
2918                  * 0x0a, 0x80
2919                  * 0x09, 0x30
2920                  * 0x0c, 0xc9
2921                  * 0x0d, 0x70
2922                  * 0x08, 0x32
2923                  * 0x08, 0x33
2924                  */
2925                 break;
2926         default:
2927                 break;
2928         }
2929
2930 }
2931
2932 bool radeon_combios_external_tmds_setup(struct drm_encoder *encoder)
2933 {
2934         struct drm_device *dev = encoder->dev;
2935         struct radeon_device *rdev = dev->dev_private;
2936         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2937         uint16_t offset;
2938         uint8_t blocks, slave_addr, rev;
2939         uint32_t index, id;
2940         uint32_t reg, val, and_mask, or_mask;
2941         struct radeon_encoder_ext_tmds *tmds = radeon_encoder->enc_priv;
2942
2943         if (!tmds)
2944                 return false;
2945
2946         if (rdev->flags & RADEON_IS_IGP) {
2947                 offset = combios_get_table_offset(dev, COMBIOS_TMDS_POWER_ON_TABLE);
2948                 rev = RBIOS8(offset);
2949                 if (offset) {
2950                         rev = RBIOS8(offset);
2951                         if (rev > 1) {
2952                                 blocks = RBIOS8(offset + 3);
2953                                 index = offset + 4;
2954                                 while (blocks > 0) {
2955                                         id = RBIOS16(index);
2956                                         index += 2;
2957                                         switch (id >> 13) {
2958                                         case 0:
2959                                                 reg = (id & 0x1fff) * 4;
2960                                                 val = RBIOS32(index);
2961                                                 index += 4;
2962                                                 WREG32(reg, val);
2963                                                 break;
2964                                         case 2:
2965                                                 reg = (id & 0x1fff) * 4;
2966                                                 and_mask = RBIOS32(index);
2967                                                 index += 4;
2968                                                 or_mask = RBIOS32(index);
2969                                                 index += 4;
2970                                                 val = RREG32(reg);
2971                                                 val = (val & and_mask) | or_mask;
2972                                                 WREG32(reg, val);
2973                                                 break;
2974                                         case 3:
2975                                                 val = RBIOS16(index);
2976                                                 index += 2;
2977                                                 udelay(val);
2978                                                 break;
2979                                         case 4:
2980                                                 val = RBIOS16(index);
2981                                                 index += 2;
2982                                                 udelay(val * 1000);
2983                                                 break;
2984                                         case 6:
2985                                                 slave_addr = id & 0xff;
2986                                                 slave_addr >>= 1; /* 7 bit addressing */
2987                                                 index++;
2988                                                 reg = RBIOS8(index);
2989                                                 index++;
2990                                                 val = RBIOS8(index);
2991                                                 index++;
2992                                                 radeon_i2c_put_byte(tmds->i2c_bus,
2993                                                                     slave_addr,
2994                                                                     reg, val);
2995                                                 break;
2996                                         default:
2997                                                 DRM_ERROR("Unknown id %d\n", id >> 13);
2998                                                 break;
2999                                         }
3000                                         blocks--;
3001                                 }
3002                                 return true;
3003                         }
3004                 }
3005         } else {
3006                 offset = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
3007                 if (offset) {
3008                         index = offset + 10;
3009                         id = RBIOS16(index);
3010                         while (id != 0xffff) {
3011                                 index += 2;
3012                                 switch (id >> 13) {
3013                                 case 0:
3014                                         reg = (id & 0x1fff) * 4;
3015                                         val = RBIOS32(index);
3016                                         WREG32(reg, val);
3017                                         break;
3018                                 case 2:
3019                                         reg = (id & 0x1fff) * 4;
3020                                         and_mask = RBIOS32(index);
3021                                         index += 4;
3022                                         or_mask = RBIOS32(index);
3023                                         index += 4;
3024                                         val = RREG32(reg);
3025                                         val = (val & and_mask) | or_mask;
3026                                         WREG32(reg, val);
3027                                         break;
3028                                 case 4:
3029                                         val = RBIOS16(index);
3030                                         index += 2;
3031                                         udelay(val);
3032                                         break;
3033                                 case 5:
3034                                         reg = id & 0x1fff;
3035                                         and_mask = RBIOS32(index);
3036                                         index += 4;
3037                                         or_mask = RBIOS32(index);
3038                                         index += 4;
3039                                         val = RREG32_PLL(reg);
3040                                         val = (val & and_mask) | or_mask;
3041                                         WREG32_PLL(reg, val);
3042                                         break;
3043                                 case 6:
3044                                         reg = id & 0x1fff;
3045                                         val = RBIOS8(index);
3046                                         index += 1;
3047                                         radeon_i2c_put_byte(tmds->i2c_bus,
3048                                                             tmds->slave_addr,
3049                                                             reg, val);
3050                                         break;
3051                                 default:
3052                                         DRM_ERROR("Unknown id %d\n", id >> 13);
3053                                         break;
3054                                 }
3055                                 id = RBIOS16(index);
3056                         }
3057                         return true;
3058                 }
3059         }
3060         return false;
3061 }
3062
3063 static void combios_parse_mmio_table(struct drm_device *dev, uint16_t offset)
3064 {
3065         struct radeon_device *rdev = dev->dev_private;
3066
3067         if (offset) {
3068                 while (RBIOS16(offset)) {
3069                         uint16_t cmd = ((RBIOS16(offset) & 0xe000) >> 13);
3070                         uint32_t addr = (RBIOS16(offset) & 0x1fff);
3071                         uint32_t val, and_mask, or_mask;
3072                         uint32_t tmp;
3073
3074                         offset += 2;
3075                         switch (cmd) {
3076                         case 0:
3077                                 val = RBIOS32(offset);
3078                                 offset += 4;
3079                                 WREG32(addr, val);
3080                                 break;
3081                         case 1:
3082                                 val = RBIOS32(offset);
3083                                 offset += 4;
3084                                 WREG32(addr, val);
3085                                 break;
3086                         case 2:
3087                                 and_mask = RBIOS32(offset);
3088                                 offset += 4;
3089                                 or_mask = RBIOS32(offset);
3090                                 offset += 4;
3091                                 tmp = RREG32(addr);
3092                                 tmp &= and_mask;
3093                                 tmp |= or_mask;
3094                                 WREG32(addr, tmp);
3095                                 break;
3096                         case 3:
3097                                 and_mask = RBIOS32(offset);
3098                                 offset += 4;
3099                                 or_mask = RBIOS32(offset);
3100                                 offset += 4;
3101                                 tmp = RREG32(addr);
3102                                 tmp &= and_mask;
3103                                 tmp |= or_mask;
3104                                 WREG32(addr, tmp);
3105                                 break;
3106                         case 4:
3107                                 val = RBIOS16(offset);
3108                                 offset += 2;
3109                                 udelay(val);
3110                                 break;
3111                         case 5:
3112                                 val = RBIOS16(offset);
3113                                 offset += 2;
3114                                 switch (addr) {
3115                                 case 8:
3116                                         while (val--) {
3117                                                 if (!
3118                                                     (RREG32_PLL
3119                                                      (RADEON_CLK_PWRMGT_CNTL) &
3120                                                      RADEON_MC_BUSY))
3121                                                         break;
3122                                         }
3123                                         break;
3124                                 case 9:
3125                                         while (val--) {
3126                                                 if ((RREG32(RADEON_MC_STATUS) &
3127                                                      RADEON_MC_IDLE))
3128                                                         break;
3129                                         }
3130                                         break;
3131                                 default:
3132                                         break;
3133                                 }
3134                                 break;
3135                         default:
3136                                 break;
3137                         }
3138                 }
3139         }
3140 }
3141
3142 static void combios_parse_pll_table(struct drm_device *dev, uint16_t offset)
3143 {
3144         struct radeon_device *rdev = dev->dev_private;
3145
3146         if (offset) {
3147                 while (RBIOS8(offset)) {
3148                         uint8_t cmd = ((RBIOS8(offset) & 0xc0) >> 6);
3149                         uint8_t addr = (RBIOS8(offset) & 0x3f);
3150                         uint32_t val, shift, tmp;
3151                         uint32_t and_mask, or_mask;
3152
3153                         offset++;
3154                         switch (cmd) {
3155                         case 0:
3156                                 val = RBIOS32(offset);
3157                                 offset += 4;
3158                                 WREG32_PLL(addr, val);
3159                                 break;
3160                         case 1:
3161                                 shift = RBIOS8(offset) * 8;
3162                                 offset++;
3163                                 and_mask = RBIOS8(offset) << shift;
3164                                 and_mask |= ~(0xff << shift);
3165                                 offset++;
3166                                 or_mask = RBIOS8(offset) << shift;
3167                                 offset++;
3168                                 tmp = RREG32_PLL(addr);
3169                                 tmp &= and_mask;
3170                                 tmp |= or_mask;
3171                                 WREG32_PLL(addr, tmp);
3172                                 break;
3173                         case 2:
3174                         case 3:
3175                                 tmp = 1000;
3176                                 switch (addr) {
3177                                 case 1:
3178                                         udelay(150);
3179                                         break;
3180                                 case 2:
3181                                         udelay(1000);
3182                                         break;
3183                                 case 3:
3184                                         while (tmp--) {
3185                                                 if (!
3186                                                     (RREG32_PLL
3187                                                      (RADEON_CLK_PWRMGT_CNTL) &
3188                                                      RADEON_MC_BUSY))
3189                                                         break;
3190                                         }
3191                                         break;
3192                                 case 4:
3193                                         while (tmp--) {
3194                                                 if (RREG32_PLL
3195                                                     (RADEON_CLK_PWRMGT_CNTL) &
3196                                                     RADEON_DLL_READY)
3197                                                         break;
3198                                         }
3199                                         break;
3200                                 case 5:
3201                                         tmp =
3202                                             RREG32_PLL(RADEON_CLK_PWRMGT_CNTL);
3203                                         if (tmp & RADEON_CG_NO1_DEBUG_0) {
3204 #if 0
3205                                                 uint32_t mclk_cntl =
3206                                                     RREG32_PLL
3207                                                     (RADEON_MCLK_CNTL);
3208                                                 mclk_cntl &= 0xffff0000;
3209                                                 /*mclk_cntl |= 0x00001111;*//* ??? */
3210                                                 WREG32_PLL(RADEON_MCLK_CNTL,
3211                                                            mclk_cntl);
3212                                                 udelay(10000);
3213 #endif
3214                                                 WREG32_PLL
3215                                                     (RADEON_CLK_PWRMGT_CNTL,
3216                                                      tmp &
3217                                                      ~RADEON_CG_NO1_DEBUG_0);
3218                                                 udelay(10000);
3219                                         }
3220                                         break;
3221                                 default:
3222                                         break;
3223                                 }
3224                                 break;
3225                         default:
3226                                 break;
3227                         }
3228                 }
3229         }
3230 }
3231
3232 static void combios_parse_ram_reset_table(struct drm_device *dev,
3233                                           uint16_t offset)
3234 {
3235         struct radeon_device *rdev = dev->dev_private;
3236         uint32_t tmp;
3237
3238         if (offset) {
3239                 uint8_t val = RBIOS8(offset);
3240                 while (val != 0xff) {
3241                         offset++;
3242
3243                         if (val == 0x0f) {
3244                                 uint32_t channel_complete_mask;
3245
3246                                 if (ASIC_IS_R300(rdev))
3247                                         channel_complete_mask =
3248                                             R300_MEM_PWRUP_COMPLETE;
3249                                 else
3250                                         channel_complete_mask =
3251                                             RADEON_MEM_PWRUP_COMPLETE;
3252                                 tmp = 20000;
3253                                 while (tmp--) {
3254                                         if ((RREG32(RADEON_MEM_STR_CNTL) &
3255                                              channel_complete_mask) ==
3256                                             channel_complete_mask)
3257                                                 break;
3258                                 }
3259                         } else {
3260                                 uint32_t or_mask = RBIOS16(offset);
3261                                 offset += 2;
3262
3263                                 tmp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
3264                                 tmp &= RADEON_SDRAM_MODE_MASK;
3265                                 tmp |= or_mask;
3266                                 WREG32(RADEON_MEM_SDRAM_MODE_REG, tmp);
3267
3268                                 or_mask = val << 24;
3269                                 tmp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
3270                                 tmp &= RADEON_B3MEM_RESET_MASK;
3271                                 tmp |= or_mask;
3272                                 WREG32(RADEON_MEM_SDRAM_MODE_REG, tmp);
3273                         }
3274                         val = RBIOS8(offset);
3275                 }
3276         }
3277 }
3278
3279 static uint32_t combios_detect_ram(struct drm_device *dev, int ram,
3280                                    int mem_addr_mapping)
3281 {
3282         struct radeon_device *rdev = dev->dev_private;
3283         uint32_t mem_cntl;
3284         uint32_t mem_size;
3285         uint32_t addr = 0;
3286
3287         mem_cntl = RREG32(RADEON_MEM_CNTL);
3288         if (mem_cntl & RV100_HALF_MODE)
3289                 ram /= 2;
3290         mem_size = ram;
3291         mem_cntl &= ~(0xff << 8);
3292         mem_cntl |= (mem_addr_mapping & 0xff) << 8;
3293         WREG32(RADEON_MEM_CNTL, mem_cntl);
3294         RREG32(RADEON_MEM_CNTL);
3295
3296         /* sdram reset ? */
3297
3298         /* something like this????  */
3299         while (ram--) {
3300                 addr = ram * 1024 * 1024;
3301                 /* write to each page */
3302                 WREG32(RADEON_MM_INDEX, (addr) | RADEON_MM_APER);
3303                 WREG32(RADEON_MM_DATA, 0xdeadbeef);
3304                 /* read back and verify */
3305                 WREG32(RADEON_MM_INDEX, (addr) | RADEON_MM_APER);
3306                 if (RREG32(RADEON_MM_DATA) != 0xdeadbeef)
3307                         return 0;
3308         }
3309
3310         return mem_size;
3311 }
3312
3313 static void combios_write_ram_size(struct drm_device *dev)
3314 {
3315         struct radeon_device *rdev = dev->dev_private;
3316         uint8_t rev;
3317         uint16_t offset;
3318         uint32_t mem_size = 0;
3319         uint32_t mem_cntl = 0;
3320
3321         /* should do something smarter here I guess... */
3322         if (rdev->flags & RADEON_IS_IGP)
3323                 return;
3324
3325         /* first check detected mem table */
3326         offset = combios_get_table_offset(dev, COMBIOS_DETECTED_MEM_TABLE);
3327         if (offset) {
3328                 rev = RBIOS8(offset);
3329                 if (rev < 3) {
3330                         mem_cntl = RBIOS32(offset + 1);
3331                         mem_size = RBIOS16(offset + 5);
3332                         if ((rdev->family < CHIP_R200) &&
3333                             !ASIC_IS_RN50(rdev))
3334                                 WREG32(RADEON_MEM_CNTL, mem_cntl);
3335                 }
3336         }
3337
3338         if (!mem_size) {
3339                 offset =
3340                     combios_get_table_offset(dev, COMBIOS_MEM_CONFIG_TABLE);
3341                 if (offset) {
3342                         rev = RBIOS8(offset - 1);
3343                         if (rev < 1) {
3344                                 if ((rdev->family < CHIP_R200)
3345                                     && !ASIC_IS_RN50(rdev)) {
3346                                         int ram = 0;
3347                                         int mem_addr_mapping = 0;
3348
3349                                         while (RBIOS8(offset)) {
3350                                                 ram = RBIOS8(offset);
3351                                                 mem_addr_mapping =
3352                                                     RBIOS8(offset + 1);
3353                                                 if (mem_addr_mapping != 0x25)
3354                                                         ram *= 2;
3355                                                 mem_size =
3356                                                     combios_detect_ram(dev, ram,
3357                                                                        mem_addr_mapping);
3358                                                 if (mem_size)
3359                                                         break;
3360                                                 offset += 2;
3361                                         }
3362                                 } else
3363                                         mem_size = RBIOS8(offset);
3364                         } else {
3365                                 mem_size = RBIOS8(offset);
3366                                 mem_size *= 2;  /* convert to MB */
3367                         }
3368                 }
3369         }
3370
3371         mem_size *= (1024 * 1024);      /* convert to bytes */
3372         WREG32(RADEON_CONFIG_MEMSIZE, mem_size);
3373 }
3374
3375 void radeon_combios_dyn_clk_setup(struct drm_device *dev, int enable)
3376 {
3377         uint16_t dyn_clk_info =
3378             combios_get_table_offset(dev, COMBIOS_DYN_CLK_1_TABLE);
3379
3380         if (dyn_clk_info)
3381                 combios_parse_pll_table(dev, dyn_clk_info);
3382 }
3383
3384 void radeon_combios_asic_init(struct drm_device *dev)
3385 {
3386         struct radeon_device *rdev = dev->dev_private;
3387         uint16_t table;
3388
3389         /* port hardcoded mac stuff from radeonfb */
3390         if (rdev->bios == NULL)
3391                 return;
3392
3393         /* ASIC INIT 1 */
3394         table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_1_TABLE);
3395         if (table)
3396                 combios_parse_mmio_table(dev, table);
3397
3398         /* PLL INIT */
3399         table = combios_get_table_offset(dev, COMBIOS_PLL_INIT_TABLE);
3400         if (table)
3401                 combios_parse_pll_table(dev, table);
3402
3403         /* ASIC INIT 2 */
3404         table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_2_TABLE);
3405         if (table)
3406                 combios_parse_mmio_table(dev, table);
3407
3408         if (!(rdev->flags & RADEON_IS_IGP)) {
3409                 /* ASIC INIT 4 */
3410                 table =
3411                     combios_get_table_offset(dev, COMBIOS_ASIC_INIT_4_TABLE);
3412                 if (table)
3413                         combios_parse_mmio_table(dev, table);
3414
3415                 /* RAM RESET */
3416                 table = combios_get_table_offset(dev, COMBIOS_RAM_RESET_TABLE);
3417                 if (table)
3418                         combios_parse_ram_reset_table(dev, table);
3419
3420                 /* ASIC INIT 3 */
3421                 table =
3422                     combios_get_table_offset(dev, COMBIOS_ASIC_INIT_3_TABLE);
3423                 if (table)
3424                         combios_parse_mmio_table(dev, table);
3425
3426                 /* write CONFIG_MEMSIZE */
3427                 combios_write_ram_size(dev);
3428         }
3429
3430         /* quirk for rs4xx HP nx6125 laptop to make it resume
3431          * - it hangs on resume inside the dynclk 1 table.
3432          */
3433         if (rdev->family == CHIP_RS480 &&
3434             rdev->pdev->subsystem_vendor == 0x103c &&
3435             rdev->pdev->subsystem_device == 0x308b)
3436                 return;
3437
3438         /* quirk for rs4xx HP dv5000 laptop to make it resume
3439          * - it hangs on resume inside the dynclk 1 table.
3440          */
3441         if (rdev->family == CHIP_RS480 &&
3442             rdev->pdev->subsystem_vendor == 0x103c &&
3443             rdev->pdev->subsystem_device == 0x30a4)
3444                 return;
3445
3446         /* quirk for rs4xx Compaq Presario V5245EU laptop to make it resume
3447          * - it hangs on resume inside the dynclk 1 table.
3448          */
3449         if (rdev->family == CHIP_RS480 &&
3450             rdev->pdev->subsystem_vendor == 0x103c &&
3451             rdev->pdev->subsystem_device == 0x30ae)
3452                 return;
3453
3454         /* DYN CLK 1 */
3455         table = combios_get_table_offset(dev, COMBIOS_DYN_CLK_1_TABLE);
3456         if (table)
3457                 combios_parse_pll_table(dev, table);
3458
3459 }
3460
3461 void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev)
3462 {
3463         struct radeon_device *rdev = dev->dev_private;
3464         uint32_t bios_0_scratch, bios_6_scratch, bios_7_scratch;
3465
3466         bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
3467         bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
3468         bios_7_scratch = RREG32(RADEON_BIOS_7_SCRATCH);
3469
3470         /* let the bios control the backlight */
3471         bios_0_scratch &= ~RADEON_DRIVER_BRIGHTNESS_EN;
3472
3473         /* tell the bios not to handle mode switching */
3474         bios_6_scratch |= (RADEON_DISPLAY_SWITCHING_DIS |
3475                            RADEON_ACC_MODE_CHANGE);
3476
3477         /* tell the bios a driver is loaded */
3478         bios_7_scratch |= RADEON_DRV_LOADED;
3479
3480         WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch);
3481         WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
3482         WREG32(RADEON_BIOS_7_SCRATCH, bios_7_scratch);
3483 }
3484
3485 void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock)
3486 {
3487         struct drm_device *dev = encoder->dev;
3488         struct radeon_device *rdev = dev->dev_private;
3489         uint32_t bios_6_scratch;
3490
3491         bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
3492
3493         if (lock)
3494                 bios_6_scratch |= RADEON_DRIVER_CRITICAL;
3495         else
3496                 bios_6_scratch &= ~RADEON_DRIVER_CRITICAL;
3497
3498         WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
3499 }
3500
3501 void
3502 radeon_combios_connected_scratch_regs(struct drm_connector *connector,
3503                                       struct drm_encoder *encoder,
3504                                       bool connected)
3505 {
3506         struct drm_device *dev = connector->dev;
3507         struct radeon_device *rdev = dev->dev_private;
3508         struct radeon_connector *radeon_connector =
3509             to_radeon_connector(connector);
3510         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3511         uint32_t bios_4_scratch = RREG32(RADEON_BIOS_4_SCRATCH);
3512         uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH);
3513
3514         if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) &&
3515             (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) {
3516                 if (connected) {
3517                         DRM_DEBUG_KMS("TV1 connected\n");
3518                         /* fix me */
3519                         bios_4_scratch |= RADEON_TV1_ATTACHED_SVIDEO;
3520                         /*save->bios_4_scratch |= RADEON_TV1_ATTACHED_COMP; */
3521                         bios_5_scratch |= RADEON_TV1_ON;
3522                         bios_5_scratch |= RADEON_ACC_REQ_TV1;
3523                 } else {
3524                         DRM_DEBUG_KMS("TV1 disconnected\n");
3525                         bios_4_scratch &= ~RADEON_TV1_ATTACHED_MASK;
3526                         bios_5_scratch &= ~RADEON_TV1_ON;
3527                         bios_5_scratch &= ~RADEON_ACC_REQ_TV1;
3528                 }
3529         }
3530         if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) &&
3531             (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) {
3532                 if (connected) {
3533                         DRM_DEBUG_KMS("LCD1 connected\n");
3534                         bios_4_scratch |= RADEON_LCD1_ATTACHED;
3535                         bios_5_scratch |= RADEON_LCD1_ON;
3536                         bios_5_scratch |= RADEON_ACC_REQ_LCD1;
3537                 } else {
3538                         DRM_DEBUG_KMS("LCD1 disconnected\n");
3539                         bios_4_scratch &= ~RADEON_LCD1_ATTACHED;
3540                         bios_5_scratch &= ~RADEON_LCD1_ON;
3541                         bios_5_scratch &= ~RADEON_ACC_REQ_LCD1;
3542                 }
3543         }
3544         if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) &&
3545             (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) {
3546                 if (connected) {
3547                         DRM_DEBUG_KMS("CRT1 connected\n");
3548                         bios_4_scratch |= RADEON_CRT1_ATTACHED_COLOR;
3549                         bios_5_scratch |= RADEON_CRT1_ON;
3550                         bios_5_scratch |= RADEON_ACC_REQ_CRT1;
3551                 } else {
3552                         DRM_DEBUG_KMS("CRT1 disconnected\n");
3553                         bios_4_scratch &= ~RADEON_CRT1_ATTACHED_MASK;
3554                         bios_5_scratch &= ~RADEON_CRT1_ON;
3555                         bios_5_scratch &= ~RADEON_ACC_REQ_CRT1;
3556                 }
3557         }
3558         if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) &&
3559             (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) {
3560                 if (connected) {
3561                         DRM_DEBUG_KMS("CRT2 connected\n");
3562                         bios_4_scratch |= RADEON_CRT2_ATTACHED_COLOR;
3563                         bios_5_scratch |= RADEON_CRT2_ON;
3564                         bios_5_scratch |= RADEON_ACC_REQ_CRT2;
3565                 } else {
3566                         DRM_DEBUG_KMS("CRT2 disconnected\n");
3567                         bios_4_scratch &= ~RADEON_CRT2_ATTACHED_MASK;
3568                         bios_5_scratch &= ~RADEON_CRT2_ON;
3569                         bios_5_scratch &= ~RADEON_ACC_REQ_CRT2;
3570                 }
3571         }
3572         if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) &&
3573             (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) {
3574                 if (connected) {
3575                         DRM_DEBUG_KMS("DFP1 connected\n");
3576                         bios_4_scratch |= RADEON_DFP1_ATTACHED;
3577                         bios_5_scratch |= RADEON_DFP1_ON;
3578                         bios_5_scratch |= RADEON_ACC_REQ_DFP1;
3579                 } else {
3580                         DRM_DEBUG_KMS("DFP1 disconnected\n");
3581                         bios_4_scratch &= ~RADEON_DFP1_ATTACHED;
3582                         bios_5_scratch &= ~RADEON_DFP1_ON;
3583                         bios_5_scratch &= ~RADEON_ACC_REQ_DFP1;
3584                 }
3585         }
3586         if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) &&
3587             (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) {
3588                 if (connected) {
3589                         DRM_DEBUG_KMS("DFP2 connected\n");
3590                         bios_4_scratch |= RADEON_DFP2_ATTACHED;
3591                         bios_5_scratch |= RADEON_DFP2_ON;
3592                         bios_5_scratch |= RADEON_ACC_REQ_DFP2;
3593                 } else {
3594                         DRM_DEBUG_KMS("DFP2 disconnected\n");
3595                         bios_4_scratch &= ~RADEON_DFP2_ATTACHED;
3596                         bios_5_scratch &= ~RADEON_DFP2_ON;
3597                         bios_5_scratch &= ~RADEON_ACC_REQ_DFP2;
3598                 }
3599         }
3600         WREG32(RADEON_BIOS_4_SCRATCH, bios_4_scratch);
3601         WREG32(RADEON_BIOS_5_SCRATCH, bios_5_scratch);
3602 }
3603
3604 void
3605 radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc)
3606 {
3607         struct drm_device *dev = encoder->dev;
3608         struct radeon_device *rdev = dev->dev_private;
3609         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3610         uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH);
3611
3612         if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
3613                 bios_5_scratch &= ~RADEON_TV1_CRTC_MASK;
3614                 bios_5_scratch |= (crtc << RADEON_TV1_CRTC_SHIFT);
3615         }
3616         if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
3617                 bios_5_scratch &= ~RADEON_CRT1_CRTC_MASK;
3618                 bios_5_scratch |= (crtc << RADEON_CRT1_CRTC_SHIFT);
3619         }
3620         if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
3621                 bios_5_scratch &= ~RADEON_CRT2_CRTC_MASK;
3622                 bios_5_scratch |= (crtc << RADEON_CRT2_CRTC_SHIFT);
3623         }
3624         if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
3625                 bios_5_scratch &= ~RADEON_LCD1_CRTC_MASK;
3626                 bios_5_scratch |= (crtc << RADEON_LCD1_CRTC_SHIFT);
3627         }
3628         if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
3629                 bios_5_scratch &= ~RADEON_DFP1_CRTC_MASK;
3630                 bios_5_scratch |= (crtc << RADEON_DFP1_CRTC_SHIFT);
3631         }
3632         if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
3633                 bios_5_scratch &= ~RADEON_DFP2_CRTC_MASK;
3634                 bios_5_scratch |= (crtc << RADEON_DFP2_CRTC_SHIFT);
3635         }
3636         WREG32(RADEON_BIOS_5_SCRATCH, bios_5_scratch);
3637 }
3638
3639 void
3640 radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on)
3641 {
3642         struct drm_device *dev = encoder->dev;
3643         struct radeon_device *rdev = dev->dev_private;
3644         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3645         uint32_t bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
3646
3647         if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) {
3648                 if (on)
3649                         bios_6_scratch |= RADEON_TV_DPMS_ON;
3650                 else
3651                         bios_6_scratch &= ~RADEON_TV_DPMS_ON;
3652         }
3653         if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
3654                 if (on)
3655                         bios_6_scratch |= RADEON_CRT_DPMS_ON;
3656                 else
3657                         bios_6_scratch &= ~RADEON_CRT_DPMS_ON;
3658         }
3659         if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
3660                 if (on)
3661                         bios_6_scratch |= RADEON_LCD_DPMS_ON;
3662                 else
3663                         bios_6_scratch &= ~RADEON_LCD_DPMS_ON;
3664         }
3665         if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
3666                 if (on)
3667                         bios_6_scratch |= RADEON_DFP_DPMS_ON;
3668                 else
3669                         bios_6_scratch &= ~RADEON_DFP_DPMS_ON;
3670         }
3671         WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
3672 }