drivers/gpu/drm/radeon/radeon_atombios.c

   1 /*
   2  * Copyright 2007-8 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  */
  26 #include "drmP.h"
  27 #include "radeon_drm.h"
  28 #include "radeon.h"
  29
  30 #include "atom.h"
  31 #include "atom-bits.h"
  32
  33 /* from radeon_encoder.c */
  34 extern uint32_t
  35 radeon_get_encoder_enum(struct drm_device *dev, uint32_t supported_device,
  36                         uint8_t dac);
  37 extern void radeon_link_encoder_connector(struct drm_device *dev);
  38 extern void
  39 radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_enum,
  40                         uint32_t supported_device);
  41
  42 /* from radeon_connector.c */
  43 extern void
  44 radeon_add_atom_connector(struct drm_device *dev,
  45                           uint32_t connector_id,
  46                           uint32_t supported_device,
  47                           int connector_type,
  48                           struct radeon_i2c_bus_rec *i2c_bus,
  49                           uint32_t igp_lane_info,
  50                           uint16_t connector_object_id,
  51                           struct radeon_hpd *hpd,
  52                           struct radeon_router *router);
  53
  54 /* from radeon_legacy_encoder.c */
  55 extern void
  56 radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_enum,
  57                           uint32_t supported_device);
  58
  59 union atom_supported_devices {
  60         struct _ATOM_SUPPORTED_DEVICES_INFO info;
  61         struct _ATOM_SUPPORTED_DEVICES_INFO_2 info_2;
  62         struct _ATOM_SUPPORTED_DEVICES_INFO_2d1 info_2d1;
  63 };
  64
  65 static inline struct radeon_i2c_bus_rec radeon_lookup_i2c_gpio(struct radeon_device *rdev,
  66                                                                uint8_t id)
  67 {
  68         struct atom_context *ctx = rdev->mode_info.atom_context;
  69         ATOM_GPIO_I2C_ASSIGMENT *gpio;
  70         struct radeon_i2c_bus_rec i2c;
  71         int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
  72         struct _ATOM_GPIO_I2C_INFO *i2c_info;
  73         uint16_t data_offset, size;
  74         int i, num_indices;
  75
  76         memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
  77         i2c.valid = false;
  78
  79         if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
  80                 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
  81
  82                 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
  83                         sizeof(ATOM_GPIO_I2C_ASSIGMENT);
  84
  85                 for (i = 0; i < num_indices; i++) {
  86                         gpio = &i2c_info->asGPIO_Info[i];
  87
  88                         /* some evergreen boards have bad data for this entry */
  89                         if (ASIC_IS_DCE4(rdev)) {
  90                                 if ((i == 7) &&
  91                                     (gpio->usClkMaskRegisterIndex == 0x1936) &&
  92                                     (gpio->sucI2cId.ucAccess == 0)) {
  93                                         gpio->sucI2cId.ucAccess = 0x97;
  94                                         gpio->ucDataMaskShift = 8;
  95                                         gpio->ucDataEnShift = 8;
  96                                         gpio->ucDataY_Shift = 8;
  97                                         gpio->ucDataA_Shift = 8;
  98                                 }
  99                         }
 100
 101                         /* some DCE3 boards have bad data for this entry */
 102                         if (ASIC_IS_DCE3(rdev)) {
 103                                 if ((i == 4) &&
 104                                     (gpio->usClkMaskRegisterIndex == 0x1fda) &&
 105                                     (gpio->sucI2cId.ucAccess == 0x94))
 106                                         gpio->sucI2cId.ucAccess = 0x14;
 107                         }
 108
 109                         if (gpio->sucI2cId.ucAccess == id) {
 110                                 i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex) * 4;
 111                                 i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex) * 4;
 112                                 i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex) * 4;
 113                                 i2c.en_data_reg = le16_to_cpu(gpio->usDataEnRegisterIndex) * 4;
 114                                 i2c.y_clk_reg = le16_to_cpu(gpio->usClkY_RegisterIndex) * 4;
 115                                 i2c.y_data_reg = le16_to_cpu(gpio->usDataY_RegisterIndex) * 4;
 116                                 i2c.a_clk_reg = le16_to_cpu(gpio->usClkA_RegisterIndex) * 4;
 117                                 i2c.a_data_reg = le16_to_cpu(gpio->usDataA_RegisterIndex) * 4;
 118                                 i2c.mask_clk_mask = (1 << gpio->ucClkMaskShift);
 119                                 i2c.mask_data_mask = (1 << gpio->ucDataMaskShift);
 120                                 i2c.en_clk_mask = (1 << gpio->ucClkEnShift);
 121                                 i2c.en_data_mask = (1 << gpio->ucDataEnShift);
 122                                 i2c.y_clk_mask = (1 << gpio->ucClkY_Shift);
 123                                 i2c.y_data_mask = (1 << gpio->ucDataY_Shift);
 124                                 i2c.a_clk_mask = (1 << gpio->ucClkA_Shift);
 125                                 i2c.a_data_mask = (1 << gpio->ucDataA_Shift);
 126
 127                                 if (gpio->sucI2cId.sbfAccess.bfHW_Capable)
 128                                         i2c.hw_capable = true;
 129                                 else
 130                                         i2c.hw_capable = false;
 131
 132                                 if (gpio->sucI2cId.ucAccess == 0xa0)
 133                                         i2c.mm_i2c = true;
 134                                 else
 135                                         i2c.mm_i2c = false;
 136
 137                                 i2c.i2c_id = gpio->sucI2cId.ucAccess;
 138
 139                                 if (i2c.mask_clk_reg)
 140                                         i2c.valid = true;
 141                                 break;
 142                         }
 143                 }
 144         }
 145
 146         return i2c;
 147 }
 148
 149 void radeon_atombios_i2c_init(struct radeon_device *rdev)
 150 {
 151         struct atom_context *ctx = rdev->mode_info.atom_context;
 152         ATOM_GPIO_I2C_ASSIGMENT *gpio;
 153         struct radeon_i2c_bus_rec i2c;
 154         int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
 155         struct _ATOM_GPIO_I2C_INFO *i2c_info;
 156         uint16_t data_offset, size;
 157         int i, num_indices;
 158         char stmp[32];
 159
 160         memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
 161
 162         if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
 163                 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
 164
 165                 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
 166                         sizeof(ATOM_GPIO_I2C_ASSIGMENT);
 167
 168                 for (i = 0; i < num_indices; i++) {
 169                         gpio = &i2c_info->asGPIO_Info[i];
 170                         i2c.valid = false;
 171
 172                         /* some evergreen boards have bad data for this entry */
 173                         if (ASIC_IS_DCE4(rdev)) {
 174                                 if ((i == 7) &&
 175                                     (gpio->usClkMaskRegisterIndex == 0x1936) &&
 176                                     (gpio->sucI2cId.ucAccess == 0)) {
 177                                         gpio->sucI2cId.ucAccess = 0x97;
 178                                         gpio->ucDataMaskShift = 8;
 179                                         gpio->ucDataEnShift = 8;
 180                                         gpio->ucDataY_Shift = 8;
 181                                         gpio->ucDataA_Shift = 8;
 182                                 }
 183                         }
 184
 185                         /* some DCE3 boards have bad data for this entry */
 186                         if (ASIC_IS_DCE3(rdev)) {
 187                                 if ((i == 4) &&
 188                                     (gpio->usClkMaskRegisterIndex == 0x1fda) &&
 189                                     (gpio->sucI2cId.ucAccess == 0x94))
 190                                         gpio->sucI2cId.ucAccess = 0x14;
 191                         }
 192
 193                         i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex) * 4;
 194                         i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex) * 4;
 195                         i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex) * 4;
 196                         i2c.en_data_reg = le16_to_cpu(gpio->usDataEnRegisterIndex) * 4;
 197                         i2c.y_clk_reg = le16_to_cpu(gpio->usClkY_RegisterIndex) * 4;
 198                         i2c.y_data_reg = le16_to_cpu(gpio->usDataY_RegisterIndex) * 4;
 199                         i2c.a_clk_reg = le16_to_cpu(gpio->usClkA_RegisterIndex) * 4;
 200                         i2c.a_data_reg = le16_to_cpu(gpio->usDataA_RegisterIndex) * 4;
 201                         i2c.mask_clk_mask = (1 << gpio->ucClkMaskShift);
 202                         i2c.mask_data_mask = (1 << gpio->ucDataMaskShift);
 203                         i2c.en_clk_mask = (1 << gpio->ucClkEnShift);
 204                         i2c.en_data_mask = (1 << gpio->ucDataEnShift);
 205                         i2c.y_clk_mask = (1 << gpio->ucClkY_Shift);
 206                         i2c.y_data_mask = (1 << gpio->ucDataY_Shift);
 207                         i2c.a_clk_mask = (1 << gpio->ucClkA_Shift);
 208                         i2c.a_data_mask = (1 << gpio->ucDataA_Shift);
 209
 210                         if (gpio->sucI2cId.sbfAccess.bfHW_Capable)
 211                                 i2c.hw_capable = true;
 212                         else
 213                                 i2c.hw_capable = false;
 214
 215                         if (gpio->sucI2cId.ucAccess == 0xa0)
 216                                 i2c.mm_i2c = true;
 217                         else
 218                                 i2c.mm_i2c = false;
 219
 220                         i2c.i2c_id = gpio->sucI2cId.ucAccess;
 221
 222                         if (i2c.mask_clk_reg) {
 223                                 i2c.valid = true;
 224                                 sprintf(stmp, "0x%x", i2c.i2c_id);
 225                                 rdev->i2c_bus[i] = radeon_i2c_create(rdev->ddev, &i2c, stmp);
 226                         }
 227                 }
 228         }
 229 }
 230
 231 static inline struct radeon_gpio_rec radeon_lookup_gpio(struct radeon_device *rdev,
 232                                                         u8 id)
 233 {
 234         struct atom_context *ctx = rdev->mode_info.atom_context;
 235         struct radeon_gpio_rec gpio;
 236         int index = GetIndexIntoMasterTable(DATA, GPIO_Pin_LUT);
 237         struct _ATOM_GPIO_PIN_LUT *gpio_info;
 238         ATOM_GPIO_PIN_ASSIGNMENT *pin;
 239         u16 data_offset, size;
 240         int i, num_indices;
 241
 242         memset(&gpio, 0, sizeof(struct radeon_gpio_rec));
 243         gpio.valid = false;
 244
 245         if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
 246                 gpio_info = (struct _ATOM_GPIO_PIN_LUT *)(ctx->bios + data_offset);
 247
 248                 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
 249                         sizeof(ATOM_GPIO_PIN_ASSIGNMENT);
 250
 251                 for (i = 0; i < num_indices; i++) {
 252                         pin = &gpio_info->asGPIO_Pin[i];
 253                         if (id == pin->ucGPIO_ID) {
 254                                 gpio.id = pin->ucGPIO_ID;
 255                                 gpio.reg = pin->usGpioPin_AIndex * 4;
 256                                 gpio.mask = (1 << pin->ucGpioPinBitShift);
 257                                 gpio.valid = true;
 258                                 break;
 259                         }
 260                 }
 261         }
 262
 263         return gpio;
 264 }
 265
 266 static struct radeon_hpd radeon_atom_get_hpd_info_from_gpio(struct radeon_device *rdev,
 267                                                             struct radeon_gpio_rec *gpio)
 268 {
 269         struct radeon_hpd hpd;
 270         u32 reg;
 271
 272         memset(&hpd, 0, sizeof(struct radeon_hpd));
 273
 274         if (ASIC_IS_DCE4(rdev))
 275                 reg = EVERGREEN_DC_GPIO_HPD_A;
 276         else
 277                 reg = AVIVO_DC_GPIO_HPD_A;
 278
 279         hpd.gpio = *gpio;
 280         if (gpio->reg == reg) {
 281                 switch(gpio->mask) {
 282                 case (1 << 0):
 283                         hpd.hpd = RADEON_HPD_1;
 284                         break;
 285                 case (1 << 8):
 286                         hpd.hpd = RADEON_HPD_2;
 287                         break;
 288                 case (1 << 16):
 289                         hpd.hpd = RADEON_HPD_3;
 290                         break;
 291                 case (1 << 24):
 292                         hpd.hpd = RADEON_HPD_4;
 293                         break;
 294                 case (1 << 26):
 295                         hpd.hpd = RADEON_HPD_5;
 296                         break;
 297                 case (1 << 28):
 298                         hpd.hpd = RADEON_HPD_6;
 299                         break;
 300                 default:
 301                         hpd.hpd = RADEON_HPD_NONE;
 302                         break;
 303                 }
 304         } else
 305                 hpd.hpd = RADEON_HPD_NONE;
 306         return hpd;
 307 }
 308
 309 static bool radeon_atom_apply_quirks(struct drm_device *dev,
 310                                      uint32_t supported_device,
 311                                      int *connector_type,
 312                                      struct radeon_i2c_bus_rec *i2c_bus,
 313                                      uint16_t *line_mux,
 314                                      struct radeon_hpd *hpd)
 315 {
 316
 317         /* Asus M2A-VM HDMI board lists the DVI port as HDMI */
 318         if ((dev->pdev->device == 0x791e) &&
 319             (dev->pdev->subsystem_vendor == 0x1043) &&
 320             (dev->pdev->subsystem_device == 0x826d)) {
 321                 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
 322                     (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
 323                         *connector_type = DRM_MODE_CONNECTOR_DVID;
 324         }
 325
 326         /* Asrock RS600 board lists the DVI port as HDMI */
 327         if ((dev->pdev->device == 0x7941) &&
 328             (dev->pdev->subsystem_vendor == 0x1849) &&
 329             (dev->pdev->subsystem_device == 0x7941)) {
 330                 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
 331                     (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
 332                         *connector_type = DRM_MODE_CONNECTOR_DVID;
 333         }
 334
 335         /* MSI K9A2GM V2/V3 board has no HDMI or DVI */
 336         if ((dev->pdev->device == 0x796e) &&
 337             (dev->pdev->subsystem_vendor == 0x1462) &&
 338             (dev->pdev->subsystem_device == 0x7302)) {
 339                 if ((supported_device == ATOM_DEVICE_DFP2_SUPPORT) ||
 340                     (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
 341                         return false;
 342         }
 343
 344         /* a-bit f-i90hd - ciaranm on #radeonhd - this board has no DVI */
 345         if ((dev->pdev->device == 0x7941) &&
 346             (dev->pdev->subsystem_vendor == 0x147b) &&
 347             (dev->pdev->subsystem_device == 0x2412)) {
 348                 if (*connector_type == DRM_MODE_CONNECTOR_DVII)
 349                         return false;
 350         }
 351
 352         /* Falcon NW laptop lists vga ddc line for LVDS */
 353         if ((dev->pdev->device == 0x5653) &&
 354             (dev->pdev->subsystem_vendor == 0x1462) &&
 355             (dev->pdev->subsystem_device == 0x0291)) {
 356                 if (*connector_type == DRM_MODE_CONNECTOR_LVDS) {
 357                         i2c_bus->valid = false;
 358                         *line_mux = 53;
 359                 }
 360         }
 361
 362         /* HIS X1300 is DVI+VGA, not DVI+DVI */
 363         if ((dev->pdev->device == 0x7146) &&
 364             (dev->pdev->subsystem_vendor == 0x17af) &&
 365             (dev->pdev->subsystem_device == 0x2058)) {
 366                 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
 367                         return false;
 368         }
 369
 370         /* Gigabyte X1300 is DVI+VGA, not DVI+DVI */
 371         if ((dev->pdev->device == 0x7142) &&
 372             (dev->pdev->subsystem_vendor == 0x1458) &&
 373             (dev->pdev->subsystem_device == 0x2134)) {
 374                 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
 375                         return false;
 376         }
 377
 378
 379         /* Funky macbooks */
 380         if ((dev->pdev->device == 0x71C5) &&
 381             (dev->pdev->subsystem_vendor == 0x106b) &&
 382             (dev->pdev->subsystem_device == 0x0080)) {
 383                 if ((supported_device == ATOM_DEVICE_CRT1_SUPPORT) ||
 384                     (supported_device == ATOM_DEVICE_DFP2_SUPPORT))
 385                         return false;
 386                 if (supported_device == ATOM_DEVICE_CRT2_SUPPORT)
 387                         *line_mux = 0x90;
 388         }
 389
 390         /* mac rv630, rv730, others */
 391         if ((supported_device == ATOM_DEVICE_TV1_SUPPORT) &&
 392             (*connector_type == DRM_MODE_CONNECTOR_DVII)) {
 393                 *connector_type = DRM_MODE_CONNECTOR_9PinDIN;
 394                 *line_mux = CONNECTOR_7PIN_DIN_ENUM_ID1;
 395         }
 396
 397         /* ASUS HD 3600 XT board lists the DVI port as HDMI */
 398         if ((dev->pdev->device == 0x9598) &&
 399             (dev->pdev->subsystem_vendor == 0x1043) &&
 400             (dev->pdev->subsystem_device == 0x01da)) {
 401                 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
 402                         *connector_type = DRM_MODE_CONNECTOR_DVII;
 403                 }
 404         }
 405
 406         /* ASUS HD 3600 board lists the DVI port as HDMI */
 407         if ((dev->pdev->device == 0x9598) &&
 408             (dev->pdev->subsystem_vendor == 0x1043) &&
 409             (dev->pdev->subsystem_device == 0x01e4)) {
 410                 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
 411                         *connector_type = DRM_MODE_CONNECTOR_DVII;
 412                 }
 413         }
 414
 415         /* ASUS HD 3450 board lists the DVI port as HDMI */
 416         if ((dev->pdev->device == 0x95C5) &&
 417             (dev->pdev->subsystem_vendor == 0x1043) &&
 418             (dev->pdev->subsystem_device == 0x01e2)) {
 419                 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
 420                         *connector_type = DRM_MODE_CONNECTOR_DVII;
 421                 }
 422         }
 423
 424         /* some BIOSes seem to report DAC on HDMI - usually this is a board with
 425          * HDMI + VGA reporting as HDMI
 426          */
 427         if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
 428                 if (supported_device & (ATOM_DEVICE_CRT_SUPPORT)) {
 429                         *connector_type = DRM_MODE_CONNECTOR_VGA;
 430                         *line_mux = 0;
 431                 }
 432         }
 433
 434         /* Acer laptop (Acer TravelMate 5730G) has an HDMI port
 435          * on the laptop and a DVI port on the docking station and
 436          * both share the same encoder, hpd pin, and ddc line.
 437          * So while the bios table is technically correct,
 438          * we drop the DVI port here since xrandr has no concept of
 439          * encoders and will try and drive both connectors
 440          * with different crtcs which isn't possible on the hardware
 441          * side and leaves no crtcs for LVDS or VGA.
 442          */
 443         if ((dev->pdev->device == 0x95c4) &&
 444             (dev->pdev->subsystem_vendor == 0x1025) &&
 445             (dev->pdev->subsystem_device == 0x013c)) {
 446                 if ((*connector_type == DRM_MODE_CONNECTOR_DVII) &&
 447                     (supported_device == ATOM_DEVICE_DFP1_SUPPORT)) {
 448                         /* actually it's a DVI-D port not DVI-I */
 449                         *connector_type = DRM_MODE_CONNECTOR_DVID;
 450                         return false;
 451                 }
 452         }
 453
 454         /* XFX Pine Group device rv730 reports no VGA DDC lines
 455          * even though they are wired up to record 0x93
 456          */
 457         if ((dev->pdev->device == 0x9498) &&
 458             (dev->pdev->subsystem_vendor == 0x1682) &&
 459             (dev->pdev->subsystem_device == 0x2452)) {
 460                 struct radeon_device *rdev = dev->dev_private;
 461                 *i2c_bus = radeon_lookup_i2c_gpio(rdev, 0x93);
 462         }
 463         return true;
 464 }
 465
 466 const int supported_devices_connector_convert[] = {
 467         DRM_MODE_CONNECTOR_Unknown,
 468         DRM_MODE_CONNECTOR_VGA,
 469         DRM_MODE_CONNECTOR_DVII,
 470         DRM_MODE_CONNECTOR_DVID,
 471         DRM_MODE_CONNECTOR_DVIA,
 472         DRM_MODE_CONNECTOR_SVIDEO,
 473         DRM_MODE_CONNECTOR_Composite,
 474         DRM_MODE_CONNECTOR_LVDS,
 475         DRM_MODE_CONNECTOR_Unknown,
 476         DRM_MODE_CONNECTOR_Unknown,
 477         DRM_MODE_CONNECTOR_HDMIA,
 478         DRM_MODE_CONNECTOR_HDMIB,
 479         DRM_MODE_CONNECTOR_Unknown,
 480         DRM_MODE_CONNECTOR_Unknown,
 481         DRM_MODE_CONNECTOR_9PinDIN,
 482         DRM_MODE_CONNECTOR_DisplayPort
 483 };
 484
 485 const uint16_t supported_devices_connector_object_id_convert[] = {
 486         CONNECTOR_OBJECT_ID_NONE,
 487         CONNECTOR_OBJECT_ID_VGA,
 488         CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I, /* not all boards support DL */
 489         CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D, /* not all boards support DL */
 490         CONNECTOR_OBJECT_ID_VGA, /* technically DVI-A */
 491         CONNECTOR_OBJECT_ID_COMPOSITE,
 492         CONNECTOR_OBJECT_ID_SVIDEO,
 493         CONNECTOR_OBJECT_ID_LVDS,
 494         CONNECTOR_OBJECT_ID_9PIN_DIN,
 495         CONNECTOR_OBJECT_ID_9PIN_DIN,
 496         CONNECTOR_OBJECT_ID_DISPLAYPORT,
 497         CONNECTOR_OBJECT_ID_HDMI_TYPE_A,
 498         CONNECTOR_OBJECT_ID_HDMI_TYPE_B,
 499         CONNECTOR_OBJECT_ID_SVIDEO
 500 };
 501
 502 const int object_connector_convert[] = {
 503         DRM_MODE_CONNECTOR_Unknown,
 504         DRM_MODE_CONNECTOR_DVII,
 505         DRM_MODE_CONNECTOR_DVII,
 506         DRM_MODE_CONNECTOR_DVID,
 507         DRM_MODE_CONNECTOR_DVID,
 508         DRM_MODE_CONNECTOR_VGA,
 509         DRM_MODE_CONNECTOR_Composite,
 510         DRM_MODE_CONNECTOR_SVIDEO,
 511         DRM_MODE_CONNECTOR_Unknown,
 512         DRM_MODE_CONNECTOR_Unknown,
 513         DRM_MODE_CONNECTOR_9PinDIN,
 514         DRM_MODE_CONNECTOR_Unknown,
 515         DRM_MODE_CONNECTOR_HDMIA,
 516         DRM_MODE_CONNECTOR_HDMIB,
 517         DRM_MODE_CONNECTOR_LVDS,
 518         DRM_MODE_CONNECTOR_9PinDIN,
 519         DRM_MODE_CONNECTOR_Unknown,
 520         DRM_MODE_CONNECTOR_Unknown,
 521         DRM_MODE_CONNECTOR_Unknown,
 522         DRM_MODE_CONNECTOR_DisplayPort,
 523         DRM_MODE_CONNECTOR_eDP,
 524         DRM_MODE_CONNECTOR_Unknown
 525 };
 526
 527 bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev)
 528 {
 529         struct radeon_device *rdev = dev->dev_private;
 530         struct radeon_mode_info *mode_info = &rdev->mode_info;
 531         struct atom_context *ctx = mode_info->atom_context;
 532         int index = GetIndexIntoMasterTable(DATA, Object_Header);
 533         u16 size, data_offset;
 534         u8 frev, crev;
 535         ATOM_CONNECTOR_OBJECT_TABLE *con_obj;
 536         ATOM_OBJECT_TABLE *router_obj;
 537         ATOM_DISPLAY_OBJECT_PATH_TABLE *path_obj;
 538         ATOM_OBJECT_HEADER *obj_header;
 539         int i, j, k, path_size, device_support;
 540         int connector_type;
 541         u16 igp_lane_info, conn_id, connector_object_id;
 542         struct radeon_i2c_bus_rec ddc_bus;
 543         struct radeon_router router;
 544         struct radeon_gpio_rec gpio;
 545         struct radeon_hpd hpd;
 546
 547         if (!atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset))
 548                 return false;
 549
 550         if (crev < 2)
 551                 return false;
 552
 553         obj_header = (ATOM_OBJECT_HEADER *) (ctx->bios + data_offset);
 554         path_obj = (ATOM_DISPLAY_OBJECT_PATH_TABLE *)
 555             (ctx->bios + data_offset +
 556              le16_to_cpu(obj_header->usDisplayPathTableOffset));
 557         con_obj = (ATOM_CONNECTOR_OBJECT_TABLE *)
 558             (ctx->bios + data_offset +
 559              le16_to_cpu(obj_header->usConnectorObjectTableOffset));
 560         router_obj = (ATOM_OBJECT_TABLE *)
 561                 (ctx->bios + data_offset +
 562                  le16_to_cpu(obj_header->usRouterObjectTableOffset));
 563         device_support = le16_to_cpu(obj_header->usDeviceSupport);
 564
 565         path_size = 0;
 566         for (i = 0; i < path_obj->ucNumOfDispPath; i++) {
 567                 uint8_t *addr = (uint8_t *) path_obj->asDispPath;
 568                 ATOM_DISPLAY_OBJECT_PATH *path;
 569                 addr += path_size;
 570                 path = (ATOM_DISPLAY_OBJECT_PATH *) addr;
 571                 path_size += le16_to_cpu(path->usSize);
 572
 573                 if (device_support & le16_to_cpu(path->usDeviceTag)) {
 574                         uint8_t con_obj_id, con_obj_num, con_obj_type;
 575
 576                         con_obj_id =
 577                             (le16_to_cpu(path->usConnObjectId) & OBJECT_ID_MASK)
 578                             >> OBJECT_ID_SHIFT;
 579                         con_obj_num =
 580                             (le16_to_cpu(path->usConnObjectId) & ENUM_ID_MASK)
 581                             >> ENUM_ID_SHIFT;
 582                         con_obj_type =
 583                             (le16_to_cpu(path->usConnObjectId) &
 584                              OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
 585
 586                         /* TODO CV support */
 587                         if (le16_to_cpu(path->usDeviceTag) ==
 588                                 ATOM_DEVICE_CV_SUPPORT)
 589                                 continue;
 590
 591                         /* IGP chips */
 592                         if ((rdev->flags & RADEON_IS_IGP) &&
 593                             (con_obj_id ==
 594                              CONNECTOR_OBJECT_ID_PCIE_CONNECTOR)) {
 595                                 uint16_t igp_offset = 0;
 596                                 ATOM_INTEGRATED_SYSTEM_INFO_V2 *igp_obj;
 597
 598                                 index =
 599                                     GetIndexIntoMasterTable(DATA,
 600                                                             IntegratedSystemInfo);
 601
 602                                 if (atom_parse_data_header(ctx, index, &size, &frev,
 603                                                            &crev, &igp_offset)) {
 604
 605                                         if (crev >= 2) {
 606                                                 igp_obj =
 607                                                         (ATOM_INTEGRATED_SYSTEM_INFO_V2
 608                                                          *) (ctx->bios + igp_offset);
 609
 610                                                 if (igp_obj) {
 611                                                         uint32_t slot_config, ct;
 612
 613                                                         if (con_obj_num == 1)
 614                                                                 slot_config =
 615                                                                         igp_obj->
 616                                                                         ulDDISlot1Config;
 617                                                         else
 618                                                                 slot_config =
 619                                                                         igp_obj->
 620                                                                         ulDDISlot2Config;
 621
 622                                                         ct = (slot_config >> 16) & 0xff;
 623                                                         connector_type =
 624                                                                 object_connector_convert
 625                                                                 [ct];
 626                                                         connector_object_id = ct;
 627                                                         igp_lane_info =
 628                                                                 slot_config & 0xffff;
 629                                                 } else
 630                                                         continue;
 631                                         } else
 632                                                 continue;
 633                                 } else {
 634                                         igp_lane_info = 0;
 635                                         connector_type =
 636                                                 object_connector_convert[con_obj_id];
 637                                         connector_object_id = con_obj_id;
 638                                 }
 639                         } else {
 640                                 igp_lane_info = 0;
 641                                 connector_type =
 642                                     object_connector_convert[con_obj_id];
 643                                 connector_object_id = con_obj_id;
 644                         }
 645
 646                         if (connector_type == DRM_MODE_CONNECTOR_Unknown)
 647                                 continue;
 648
 649                         router.ddc_valid = false;
 650                         router.cd_valid = false;
 651                         for (j = 0; j < ((le16_to_cpu(path->usSize) - 8) / 2); j++) {
 652                                 uint8_t grph_obj_id, grph_obj_num, grph_obj_type;
 653
 654                                 grph_obj_id =
 655                                     (le16_to_cpu(path->usGraphicObjIds[j]) &
 656                                      OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
 657                                 grph_obj_num =
 658                                     (le16_to_cpu(path->usGraphicObjIds[j]) &
 659                                      ENUM_ID_MASK) >> ENUM_ID_SHIFT;
 660                                 grph_obj_type =
 661                                     (le16_to_cpu(path->usGraphicObjIds[j]) &
 662                                      OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
 663
 664                                 if (grph_obj_type == GRAPH_OBJECT_TYPE_ENCODER) {
 665                                         u16 encoder_obj = le16_to_cpu(path->usGraphicObjIds[j]);
 666
 667                                         radeon_add_atom_encoder(dev,
 668                                                                 encoder_obj,
 669                                                                 le16_to_cpu
 670                                                                 (path->
 671                                                                  usDeviceTag));
 672
 673                                 } else if (grph_obj_type == GRAPH_OBJECT_TYPE_ROUTER) {
 674                                         for (k = 0; k < router_obj->ucNumberOfObjects; k++) {
 675                                                 u16 router_obj_id = le16_to_cpu(router_obj->asObjects[k].usObjectID);
 676                                                 if (le16_to_cpu(path->usGraphicObjIds[j]) == router_obj_id) {
 677                                                         ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *)
 678                                                                 (ctx->bios + data_offset +
 679                                                                  le16_to_cpu(router_obj->asObjects[k].usRecordOffset));
 680                                                         ATOM_I2C_RECORD *i2c_record;
 681                                                         ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
 682                                                         ATOM_ROUTER_DDC_PATH_SELECT_RECORD *ddc_path;
 683                                                         ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *cd_path;
 684                                                         ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *router_src_dst_table =
 685                                                                 (ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *)
 686                                                                 (ctx->bios + data_offset +
 687                                                                  le16_to_cpu(router_obj->asObjects[k].usSrcDstTableOffset));
 688                                                         int enum_id;
 689
 690                                                         router.router_id = router_obj_id;
 691                                                         for (enum_id = 0; enum_id < router_src_dst_table->ucNumberOfDst;
 692                                                              enum_id++) {
 693                                                                 if (le16_to_cpu(path->usConnObjectId) ==
 694                                                                     le16_to_cpu(router_src_dst_table->usDstObjectID[enum_id]))
 695                                                                         break;
 696                                                         }
 697
 698                                                         while (record->ucRecordType > 0 &&
 699                                                                record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
 700                                                                 switch (record->ucRecordType) {
 701                                                                 case ATOM_I2C_RECORD_TYPE:
 702                                                                         i2c_record =
 703                                                                                 (ATOM_I2C_RECORD *)
 704                                                                                 record;
 705                                                                         i2c_config =
 706                                                                                 (ATOM_I2C_ID_CONFIG_ACCESS *)
 707                                                                                 &i2c_record->sucI2cId;
 708                                                                         router.i2c_info =
 709                                                                                 radeon_lookup_i2c_gpio(rdev,
 710                                                                                                        i2c_config->
 711                                                                                                        ucAccess);
 712                                                                         router.i2c_addr = i2c_record->ucI2CAddr >> 1;
 713                                                                         break;
 714                                                                 case ATOM_ROUTER_DDC_PATH_SELECT_RECORD_TYPE:
 715                                                                         ddc_path = (ATOM_ROUTER_DDC_PATH_SELECT_RECORD *)
 716                                                                                 record;
 717                                                                         router.ddc_valid = true;
 718                                                                         router.ddc_mux_type = ddc_path->ucMuxType;
 719                                                                         router.ddc_mux_control_pin = ddc_path->ucMuxControlPin;
 720                                                                         router.ddc_mux_state = ddc_path->ucMuxState[enum_id];
 721                                                                         break;
 722                                                                 case ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD_TYPE:
 723                                                                         cd_path = (ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *)
 724                                                                                 record;
 725                                                                         router.cd_valid = true;
 726                                                                         router.cd_mux_type = cd_path->ucMuxType;
 727                                                                         router.cd_mux_control_pin = cd_path->ucMuxControlPin;
 728                                                                         router.cd_mux_state = cd_path->ucMuxState[enum_id];
 729                                                                         break;
 730                                                                 }
 731                                                                 record = (ATOM_COMMON_RECORD_HEADER *)
 732                                                                         ((char *)record + record->ucRecordSize);
 733                                                         }
 734                                                 }
 735                                         }
 736                                 }
 737                         }
 738
 739                         /* look up gpio for ddc, hpd */
 740                         ddc_bus.valid = false;
 741                         hpd.hpd = RADEON_HPD_NONE;
 742                         if ((le16_to_cpu(path->usDeviceTag) &
 743                              (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) == 0) {
 744                                 for (j = 0; j < con_obj->ucNumberOfObjects; j++) {
 745                                         if (le16_to_cpu(path->usConnObjectId) ==
 746                                             le16_to_cpu(con_obj->asObjects[j].
 747                                                         usObjectID)) {
 748                                                 ATOM_COMMON_RECORD_HEADER
 749                                                     *record =
 750                                                     (ATOM_COMMON_RECORD_HEADER
 751                                                      *)
 752                                                     (ctx->bios + data_offset +
 753                                                      le16_to_cpu(con_obj->
 754                                                                  asObjects[j].
 755                                                                  usRecordOffset));
 756                                                 ATOM_I2C_RECORD *i2c_record;
 757                                                 ATOM_HPD_INT_RECORD *hpd_record;
 758                                                 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
 759
 760                                                 while (record->ucRecordType > 0
 761                                                        && record->
 762                                                        ucRecordType <=
 763                                                        ATOM_MAX_OBJECT_RECORD_NUMBER) {
 764                                                         switch (record->ucRecordType) {
 765                                                         case ATOM_I2C_RECORD_TYPE:
 766                                                                 i2c_record =
 767                                                                     (ATOM_I2C_RECORD *)
 768                                                                         record;
 769                                                                 i2c_config =
 770                                                                         (ATOM_I2C_ID_CONFIG_ACCESS *)
 771                                                                         &i2c_record->sucI2cId;
 772                                                                 ddc_bus = radeon_lookup_i2c_gpio(rdev,
 773                                                                                                  i2c_config->
 774                                                                                                  ucAccess);
 775                                                                 break;
 776                                                         case ATOM_HPD_INT_RECORD_TYPE:
 777                                                                 hpd_record =
 778                                                                         (ATOM_HPD_INT_RECORD *)
 779                                                                         record;
 780                                                                 gpio = radeon_lookup_gpio(rdev,
 781                                                                                           hpd_record->ucHPDIntGPIOID);
 782                                                                 hpd = radeon_atom_get_hpd_info_from_gpio(rdev, &gpio);
 783                                                                 hpd.plugged_state = hpd_record->ucPlugged_PinState;
 784                                                                 break;
 785                                                         }
 786                                                         record =
 787                                                             (ATOM_COMMON_RECORD_HEADER
 788                                                              *) ((char *)record
 789                                                                  +
 790                                                                  record->
 791                                                                  ucRecordSize);
 792                                                 }
 793                                                 break;
 794                                         }
 795                                 }
 796                         }
 797
 798                         /* needed for aux chan transactions */
 799                         ddc_bus.hpd = hpd.hpd;
 800
 801                         conn_id = le16_to_cpu(path->usConnObjectId);
 802
 803                         if (!radeon_atom_apply_quirks
 804                             (dev, le16_to_cpu(path->usDeviceTag), &connector_type,
 805                              &ddc_bus, &conn_id, &hpd))
 806                                 continue;
 807
 808                         radeon_add_atom_connector(dev,
 809                                                   conn_id,
 810                                                   le16_to_cpu(path->
 811                                                               usDeviceTag),
 812                                                   connector_type, &ddc_bus,
 813                                                   igp_lane_info,
 814                                                   connector_object_id,
 815                                                   &hpd,
 816                                                   &router);
 817
 818                 }
 819         }
 820
 821         radeon_link_encoder_connector(dev);
 822
 823         return true;
 824 }
 825
 826 static uint16_t atombios_get_connector_object_id(struct drm_device *dev,
 827                                                  int connector_type,
 828                                                  uint16_t devices)
 829 {
 830         struct radeon_device *rdev = dev->dev_private;
 831
 832         if (rdev->flags & RADEON_IS_IGP) {
 833                 return supported_devices_connector_object_id_convert
 834                         [connector_type];
 835         } else if (((connector_type == DRM_MODE_CONNECTOR_DVII) ||
 836                     (connector_type == DRM_MODE_CONNECTOR_DVID)) &&
 837                    (devices & ATOM_DEVICE_DFP2_SUPPORT))  {
 838                 struct radeon_mode_info *mode_info = &rdev->mode_info;
 839                 struct atom_context *ctx = mode_info->atom_context;
 840                 int index = GetIndexIntoMasterTable(DATA, XTMDS_Info);
 841                 uint16_t size, data_offset;
 842                 uint8_t frev, crev;
 843                 ATOM_XTMDS_INFO *xtmds;
 844
 845                 if (atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset)) {
 846                         xtmds = (ATOM_XTMDS_INFO *)(ctx->bios + data_offset);
 847
 848                         if (xtmds->ucSupportedLink & ATOM_XTMDS_SUPPORTED_DUALLINK) {
 849                                 if (connector_type == DRM_MODE_CONNECTOR_DVII)
 850                                         return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
 851                                 else
 852                                         return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
 853                         } else {
 854                                 if (connector_type == DRM_MODE_CONNECTOR_DVII)
 855                                         return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
 856                                 else
 857                                         return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
 858                         }
 859                 } else
 860                         return supported_devices_connector_object_id_convert
 861                                 [connector_type];
 862         } else {
 863                 return supported_devices_connector_object_id_convert
 864                         [connector_type];
 865         }
 866 }
 867
 868 struct bios_connector {
 869         bool valid;
 870         uint16_t line_mux;
 871         uint16_t devices;
 872         int connector_type;
 873         struct radeon_i2c_bus_rec ddc_bus;
 874         struct radeon_hpd hpd;
 875 };
 876
 877 bool radeon_get_atom_connector_info_from_supported_devices_table(struct
 878                                                                  drm_device
 879                                                                  *dev)
 880 {
 881         struct radeon_device *rdev = dev->dev_private;
 882         struct radeon_mode_info *mode_info = &rdev->mode_info;
 883         struct atom_context *ctx = mode_info->atom_context;
 884         int index = GetIndexIntoMasterTable(DATA, SupportedDevicesInfo);
 885         uint16_t size, data_offset;
 886         uint8_t frev, crev;
 887         uint16_t device_support;
 888         uint8_t dac;
 889         union atom_supported_devices *supported_devices;
 890         int i, j, max_device;
 891         struct bios_connector *bios_connectors;
 892         size_t bc_size = sizeof(*bios_connectors) * ATOM_MAX_SUPPORTED_DEVICE;
 893         struct radeon_router router;
 894
 895         router.ddc_valid = false;
 896         router.cd_valid = false;
 897
 898         bios_connectors = kzalloc(bc_size, GFP_KERNEL);
 899         if (!bios_connectors)
 900                 return false;
 901
 902         if (!atom_parse_data_header(ctx, index, &size, &frev, &crev,
 903                                     &data_offset)) {
 904                 kfree(bios_connectors);
 905                 return false;
 906         }
 907
 908         supported_devices =
 909             (union atom_supported_devices *)(ctx->bios + data_offset);
 910
 911         device_support = le16_to_cpu(supported_devices->info.usDeviceSupport);
 912
 913         if (frev > 1)
 914                 max_device = ATOM_MAX_SUPPORTED_DEVICE;
 915         else
 916                 max_device = ATOM_MAX_SUPPORTED_DEVICE_INFO;
 917
 918         for (i = 0; i < max_device; i++) {
 919                 ATOM_CONNECTOR_INFO_I2C ci =
 920                     supported_devices->info.asConnInfo[i];
 921
 922                 bios_connectors[i].valid = false;
 923
 924                 if (!(device_support & (1 << i))) {
 925                         continue;
 926                 }
 927
 928                 if (i == ATOM_DEVICE_CV_INDEX) {
 929                         DRM_DEBUG_KMS("Skipping Component Video\n");
 930                         continue;
 931                 }
 932
 933                 bios_connectors[i].connector_type =
 934                     supported_devices_connector_convert[ci.sucConnectorInfo.
 935                                                         sbfAccess.
 936                                                         bfConnectorType];
 937
 938                 if (bios_connectors[i].connector_type ==
 939                     DRM_MODE_CONNECTOR_Unknown)
 940                         continue;
 941
 942                 dac = ci.sucConnectorInfo.sbfAccess.bfAssociatedDAC;
 943
 944                 bios_connectors[i].line_mux =
 945                         ci.sucI2cId.ucAccess;
 946
 947                 /* give tv unique connector ids */
 948                 if (i == ATOM_DEVICE_TV1_INDEX) {
 949                         bios_connectors[i].ddc_bus.valid = false;
 950                         bios_connectors[i].line_mux = 50;
 951                 } else if (i == ATOM_DEVICE_TV2_INDEX) {
 952                         bios_connectors[i].ddc_bus.valid = false;
 953                         bios_connectors[i].line_mux = 51;
 954                 } else if (i == ATOM_DEVICE_CV_INDEX) {
 955                         bios_connectors[i].ddc_bus.valid = false;
 956                         bios_connectors[i].line_mux = 52;
 957                 } else
 958                         bios_connectors[i].ddc_bus =
 959                             radeon_lookup_i2c_gpio(rdev,
 960                                                    bios_connectors[i].line_mux);
 961
 962                 if ((crev > 1) && (frev > 1)) {
 963                         u8 isb = supported_devices->info_2d1.asIntSrcInfo[i].ucIntSrcBitmap;
 964                         switch (isb) {
 965                         case 0x4:
 966                                 bios_connectors[i].hpd.hpd = RADEON_HPD_1;
 967                                 break;
 968                         case 0xa:
 969                                 bios_connectors[i].hpd.hpd = RADEON_HPD_2;
 970                                 break;
 971                         default:
 972                                 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE;
 973                                 break;
 974                         }
 975                 } else {
 976                         if (i == ATOM_DEVICE_DFP1_INDEX)
 977                                 bios_connectors[i].hpd.hpd = RADEON_HPD_1;
 978                         else if (i == ATOM_DEVICE_DFP2_INDEX)
 979                                 bios_connectors[i].hpd.hpd = RADEON_HPD_2;
 980                         else
 981                                 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE;
 982                 }
 983
 984                 /* Always set the connector type to VGA for CRT1/CRT2. if they are
 985                  * shared with a DVI port, we'll pick up the DVI connector when we
 986                  * merge the outputs.  Some bioses incorrectly list VGA ports as DVI.
 987                  */
 988                 if (i == ATOM_DEVICE_CRT1_INDEX || i == ATOM_DEVICE_CRT2_INDEX)
 989                         bios_connectors[i].connector_type =
 990                             DRM_MODE_CONNECTOR_VGA;
 991
 992                 if (!radeon_atom_apply_quirks
 993                     (dev, (1 << i), &bios_connectors[i].connector_type,
 994                      &bios_connectors[i].ddc_bus, &bios_connectors[i].line_mux,
 995                      &bios_connectors[i].hpd))
 996                         continue;
 997
 998                 bios_connectors[i].valid = true;
 999                 bios_connectors[i].devices = (1 << i);
1000
1001                 if (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom)
1002                         radeon_add_atom_encoder(dev,
1003                                                 radeon_get_encoder_enum(dev,
1004                                                                       (1 << i),
1005                                                                       dac),
1006                                                 (1 << i));
1007                 else
1008                         radeon_add_legacy_encoder(dev,
1009                                                   radeon_get_encoder_enum(dev,
1010                                                                         (1 << i),
1011                                                                         dac),
1012                                                   (1 << i));
1013         }
1014
1015         /* combine shared connectors */
1016         for (i = 0; i < max_device; i++) {
1017                 if (bios_connectors[i].valid) {
1018                         for (j = 0; j < max_device; j++) {
1019                                 if (bios_connectors[j].valid && (i != j)) {
1020                                         if (bios_connectors[i].line_mux ==
1021                                             bios_connectors[j].line_mux) {
1022                                                 /* make sure not to combine LVDS */
1023                                                 if (bios_connectors[i].devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1024                                                         bios_connectors[i].line_mux = 53;
1025                                                         bios_connectors[i].ddc_bus.valid = false;
1026                                                         continue;
1027                                                 }
1028                                                 if (bios_connectors[j].devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1029                                                         bios_connectors[j].line_mux = 53;
1030                                                         bios_connectors[j].ddc_bus.valid = false;
1031                                                         continue;
1032                                                 }
1033                                                 /* combine analog and digital for DVI-I */
1034                                                 if (((bios_connectors[i].devices & (ATOM_DEVICE_DFP_SUPPORT)) &&
1035                                                      (bios_connectors[j].devices & (ATOM_DEVICE_CRT_SUPPORT))) ||
1036                                                     ((bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT)) &&
1037                                                      (bios_connectors[i].devices & (ATOM_DEVICE_CRT_SUPPORT)))) {
1038                                                         bios_connectors[i].devices |=
1039                                                                 bios_connectors[j].devices;
1040                                                         bios_connectors[i].connector_type =
1041                                                                 DRM_MODE_CONNECTOR_DVII;
1042                                                         if (bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT))
1043                                                                 bios_connectors[i].hpd =
1044                                                                         bios_connectors[j].hpd;
1045                                                         bios_connectors[j].valid = false;
1046                                                 }
1047                                         }
1048                                 }
1049                         }
1050                 }
1051         }
1052
1053         /* add the connectors */
1054         for (i = 0; i < max_device; i++) {
1055                 if (bios_connectors[i].valid) {
1056                         uint16_t connector_object_id =
1057                                 atombios_get_connector_object_id(dev,
1058                                                       bios_connectors[i].connector_type,
1059                                                       bios_connectors[i].devices);
1060                         radeon_add_atom_connector(dev,
1061                                                   bios_connectors[i].line_mux,
1062                                                   bios_connectors[i].devices,
1063                                                   bios_connectors[i].
1064                                                   connector_type,
1065                                                   &bios_connectors[i].ddc_bus,
1066                                                   0,
1067                                                   connector_object_id,
1068                                                   &bios_connectors[i].hpd,
1069                                                   &router);
1070                 }
1071         }
1072
1073         radeon_link_encoder_connector(dev);
1074
1075         kfree(bios_connectors);
1076         return true;
1077 }
1078
1079 union firmware_info {
1080         ATOM_FIRMWARE_INFO info;
1081         ATOM_FIRMWARE_INFO_V1_2 info_12;
1082         ATOM_FIRMWARE_INFO_V1_3 info_13;
1083         ATOM_FIRMWARE_INFO_V1_4 info_14;
1084         ATOM_FIRMWARE_INFO_V2_1 info_21;
1085 };
1086
1087 bool radeon_atom_get_clock_info(struct drm_device *dev)
1088 {
1089         struct radeon_device *rdev = dev->dev_private;
1090         struct radeon_mode_info *mode_info = &rdev->mode_info;
1091         int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
1092         union firmware_info *firmware_info;
1093         uint8_t frev, crev;
1094         struct radeon_pll *p1pll = &rdev->clock.p1pll;
1095         struct radeon_pll *p2pll = &rdev->clock.p2pll;
1096         struct radeon_pll *dcpll = &rdev->clock.dcpll;
1097         struct radeon_pll *spll = &rdev->clock.spll;
1098         struct radeon_pll *mpll = &rdev->clock.mpll;
1099         uint16_t data_offset;
1100
1101         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1102                                    &frev, &crev, &data_offset)) {
1103                 firmware_info =
1104                         (union firmware_info *)(mode_info->atom_context->bios +
1105                                                 data_offset);
1106                 /* pixel clocks */
1107                 p1pll->reference_freq =
1108                     le16_to_cpu(firmware_info->info.usReferenceClock);
1109                 p1pll->reference_div = 0;
1110
1111                 if (crev < 2)
1112                         p1pll->pll_out_min =
1113                                 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Output);
1114                 else
1115                         p1pll->pll_out_min =
1116                                 le32_to_cpu(firmware_info->info_12.ulMinPixelClockPLL_Output);
1117                 p1pll->pll_out_max =
1118                     le32_to_cpu(firmware_info->info.ulMaxPixelClockPLL_Output);
1119
1120                 if (crev >= 4) {
1121                         p1pll->lcd_pll_out_min =
1122                                 le16_to_cpu(firmware_info->info_14.usLcdMinPixelClockPLL_Output) * 100;
1123                         if (p1pll->lcd_pll_out_min == 0)
1124                                 p1pll->lcd_pll_out_min = p1pll->pll_out_min;
1125                         p1pll->lcd_pll_out_max =
1126                                 le16_to_cpu(firmware_info->info_14.usLcdMaxPixelClockPLL_Output) * 100;
1127                         if (p1pll->lcd_pll_out_max == 0)
1128                                 p1pll->lcd_pll_out_max = p1pll->pll_out_max;
1129                 } else {
1130                         p1pll->lcd_pll_out_min = p1pll->pll_out_min;
1131                         p1pll->lcd_pll_out_max = p1pll->pll_out_max;
1132                 }
1133
1134                 if (p1pll->pll_out_min == 0) {
1135                         if (ASIC_IS_AVIVO(rdev))
1136                                 p1pll->pll_out_min = 64800;
1137                         else
1138                                 p1pll->pll_out_min = 20000;
1139                 }
1140
1141                 p1pll->pll_in_min =
1142                     le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Input);
1143                 p1pll->pll_in_max =
1144                     le16_to_cpu(firmware_info->info.usMaxPixelClockPLL_Input);
1145
1146                 *p2pll = *p1pll;
1147
1148                 /* system clock */
1149                 spll->reference_freq =
1150                     le16_to_cpu(firmware_info->info.usReferenceClock);
1151                 spll->reference_div = 0;
1152
1153                 spll->pll_out_min =
1154                     le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Output);
1155                 spll->pll_out_max =
1156                     le32_to_cpu(firmware_info->info.ulMaxEngineClockPLL_Output);
1157
1158                 /* ??? */
1159                 if (spll->pll_out_min == 0) {
1160                         if (ASIC_IS_AVIVO(rdev))
1161                                 spll->pll_out_min = 64800;
1162                         else
1163                                 spll->pll_out_min = 20000;
1164                 }
1165
1166                 spll->pll_in_min =
1167                     le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Input);
1168                 spll->pll_in_max =
1169                     le16_to_cpu(firmware_info->info.usMaxEngineClockPLL_Input);
1170
1171                 /* memory clock */
1172                 mpll->reference_freq =
1173                     le16_to_cpu(firmware_info->info.usReferenceClock);
1174                 mpll->reference_div = 0;
1175
1176                 mpll->pll_out_min =
1177                     le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Output);
1178                 mpll->pll_out_max =
1179                     le32_to_cpu(firmware_info->info.ulMaxMemoryClockPLL_Output);
1180
1181                 /* ??? */
1182                 if (mpll->pll_out_min == 0) {
1183                         if (ASIC_IS_AVIVO(rdev))
1184                                 mpll->pll_out_min = 64800;
1185                         else
1186                                 mpll->pll_out_min = 20000;
1187                 }
1188
1189                 mpll->pll_in_min =
1190                     le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Input);
1191                 mpll->pll_in_max =
1192                     le16_to_cpu(firmware_info->info.usMaxMemoryClockPLL_Input);
1193
1194                 rdev->clock.default_sclk =
1195                     le32_to_cpu(firmware_info->info.ulDefaultEngineClock);
1196                 rdev->clock.default_mclk =
1197                     le32_to_cpu(firmware_info->info.ulDefaultMemoryClock);
1198
1199                 if (ASIC_IS_DCE4(rdev)) {
1200                         rdev->clock.default_dispclk =
1201                                 le32_to_cpu(firmware_info->info_21.ulDefaultDispEngineClkFreq);
1202                         if (rdev->clock.default_dispclk == 0)
1203                                 rdev->clock.default_dispclk = 60000; /* 600 Mhz */
1204                         rdev->clock.dp_extclk =
1205                                 le16_to_cpu(firmware_info->info_21.usUniphyDPModeExtClkFreq);
1206                 }
1207                 *dcpll = *p1pll;
1208
1209                 return true;
1210         }
1211
1212         return false;
1213 }
1214
1215 union igp_info {
1216         struct _ATOM_INTEGRATED_SYSTEM_INFO info;
1217         struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2;
1218 };
1219
1220 bool radeon_atombios_sideport_present(struct radeon_device *rdev)
1221 {
1222         struct radeon_mode_info *mode_info = &rdev->mode_info;
1223         int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
1224         union igp_info *igp_info;
1225         u8 frev, crev;
1226         u16 data_offset;
1227
1228         /* sideport is AMD only */
1229         if (rdev->family == CHIP_RS600)
1230                 return false;
1231
1232         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1233                                    &frev, &crev, &data_offset)) {
1234                 igp_info = (union igp_info *)(mode_info->atom_context->bios +
1235                                       data_offset);
1236                 switch (crev) {
1237                 case 1:
1238                         if (igp_info->info.ulBootUpMemoryClock)
1239                                 return true;
1240                         break;
1241                 case 2:
1242                         if (igp_info->info_2.ulBootUpSidePortClock)
1243                                 return true;
1244                         break;
1245                 default:
1246                         DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev);
1247                         break;
1248                 }
1249         }
1250         return false;
1251 }
1252
1253 bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder,
1254                                    struct radeon_encoder_int_tmds *tmds)
1255 {
1256         struct drm_device *dev = encoder->base.dev;
1257         struct radeon_device *rdev = dev->dev_private;
1258         struct radeon_mode_info *mode_info = &rdev->mode_info;
1259         int index = GetIndexIntoMasterTable(DATA, TMDS_Info);
1260         uint16_t data_offset;
1261         struct _ATOM_TMDS_INFO *tmds_info;
1262         uint8_t frev, crev;
1263         uint16_t maxfreq;
1264         int i;
1265
1266         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1267                                    &frev, &crev, &data_offset)) {
1268                 tmds_info =
1269                         (struct _ATOM_TMDS_INFO *)(mode_info->atom_context->bios +
1270                                                    data_offset);
1271
1272                 maxfreq = le16_to_cpu(tmds_info->usMaxFrequency);
1273                 for (i = 0; i < 4; i++) {
1274                         tmds->tmds_pll[i].freq =
1275                             le16_to_cpu(tmds_info->asMiscInfo[i].usFrequency);
1276                         tmds->tmds_pll[i].value =
1277                             tmds_info->asMiscInfo[i].ucPLL_ChargePump & 0x3f;
1278                         tmds->tmds_pll[i].value |=
1279                             (tmds_info->asMiscInfo[i].
1280                              ucPLL_VCO_Gain & 0x3f) << 6;
1281                         tmds->tmds_pll[i].value |=
1282                             (tmds_info->asMiscInfo[i].
1283                              ucPLL_DutyCycle & 0xf) << 12;
1284                         tmds->tmds_pll[i].value |=
1285                             (tmds_info->asMiscInfo[i].
1286                              ucPLL_VoltageSwing & 0xf) << 16;
1287
1288                         DRM_DEBUG_KMS("TMDS PLL From ATOMBIOS %u %x\n",
1289                                   tmds->tmds_pll[i].freq,
1290                                   tmds->tmds_pll[i].value);
1291
1292                         if (maxfreq == tmds->tmds_pll[i].freq) {
1293                                 tmds->tmds_pll[i].freq = 0xffffffff;
1294                                 break;
1295                         }
1296                 }
1297                 return true;
1298         }
1299         return false;
1300 }
1301
1302 bool radeon_atombios_get_ppll_ss_info(struct radeon_device *rdev,
1303                                       struct radeon_atom_ss *ss,
1304                                       int id)
1305 {
1306         struct radeon_mode_info *mode_info = &rdev->mode_info;
1307         int index = GetIndexIntoMasterTable(DATA, PPLL_SS_Info);
1308         uint16_t data_offset, size;
1309         struct _ATOM_SPREAD_SPECTRUM_INFO *ss_info;
1310         uint8_t frev, crev;
1311         int i, num_indices;
1312
1313         memset(ss, 0, sizeof(struct radeon_atom_ss));
1314         if (atom_parse_data_header(mode_info->atom_context, index, &size,
1315                                    &frev, &crev, &data_offset)) {
1316                 ss_info =
1317                         (struct _ATOM_SPREAD_SPECTRUM_INFO *)(mode_info->atom_context->bios + data_offset);
1318
1319                 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1320                         sizeof(ATOM_SPREAD_SPECTRUM_ASSIGNMENT);
1321
1322                 for (i = 0; i < num_indices; i++) {
1323                         if (ss_info->asSS_Info[i].ucSS_Id == id) {
1324                                 ss->percentage =
1325                                         le16_to_cpu(ss_info->asSS_Info[i].usSpreadSpectrumPercentage);
1326                                 ss->type = ss_info->asSS_Info[i].ucSpreadSpectrumType;
1327                                 ss->step = ss_info->asSS_Info[i].ucSS_Step;
1328                                 ss->delay = ss_info->asSS_Info[i].ucSS_Delay;
1329                                 ss->range = ss_info->asSS_Info[i].ucSS_Range;
1330                                 ss->refdiv = ss_info->asSS_Info[i].ucRecommendedRef_Div;
1331                                 return true;
1332                         }
1333                 }
1334         }
1335         return false;
1336 }
1337
1338 union asic_ss_info {
1339         struct _ATOM_ASIC_INTERNAL_SS_INFO info;
1340         struct _ATOM_ASIC_INTERNAL_SS_INFO_V2 info_2;
1341         struct _ATOM_ASIC_INTERNAL_SS_INFO_V3 info_3;
1342 };
1343
1344 bool radeon_atombios_get_asic_ss_info(struct radeon_device *rdev,
1345                                       struct radeon_atom_ss *ss,
1346                                       int id, u32 clock)
1347 {
1348         struct radeon_mode_info *mode_info = &rdev->mode_info;
1349         int index = GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info);
1350         uint16_t data_offset, size;
1351         union asic_ss_info *ss_info;
1352         uint8_t frev, crev;
1353         int i, num_indices;
1354
1355         memset(ss, 0, sizeof(struct radeon_atom_ss));
1356         if (atom_parse_data_header(mode_info->atom_context, index, &size,
1357                                    &frev, &crev, &data_offset)) {
1358
1359                 ss_info =
1360                         (union asic_ss_info *)(mode_info->atom_context->bios + data_offset);
1361
1362                 switch (frev) {
1363                 case 1:
1364                         num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1365                                 sizeof(ATOM_ASIC_SS_ASSIGNMENT);
1366
1367                         for (i = 0; i < num_indices; i++) {
1368                                 if ((ss_info->info.asSpreadSpectrum[i].ucClockIndication == id) &&
1369                                     (clock <= ss_info->info.asSpreadSpectrum[i].ulTargetClockRange)) {
1370                                         ss->percentage =
1371                                                 le16_to_cpu(ss_info->info.asSpreadSpectrum[i].usSpreadSpectrumPercentage);
1372                                         ss->type = ss_info->info.asSpreadSpectrum[i].ucSpreadSpectrumMode;
1373                                         ss->rate = le16_to_cpu(ss_info->info.asSpreadSpectrum[i].usSpreadRateInKhz);
1374                                         return true;
1375                                 }
1376                         }
1377                         break;
1378                 case 2:
1379                         num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1380                                 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2);
1381                         for (i = 0; i < num_indices; i++) {
1382                                 if ((ss_info->info_2.asSpreadSpectrum[i].ucClockIndication == id) &&
1383                                     (clock <= ss_info->info_2.asSpreadSpectrum[i].ulTargetClockRange)) {
1384                                         ss->percentage =
1385                                                 le16_to_cpu(ss_info->info_2.asSpreadSpectrum[i].usSpreadSpectrumPercentage);
1386                                         ss->type = ss_info->info_2.asSpreadSpectrum[i].ucSpreadSpectrumMode;
1387                                         ss->rate = le16_to_cpu(ss_info->info_2.asSpreadSpectrum[i].usSpreadRateIn10Hz);
1388                                         return true;
1389                                 }
1390                         }
1391                         break;
1392                 case 3:
1393                         num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1394                                 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3);
1395                         for (i = 0; i < num_indices; i++) {
1396                                 if ((ss_info->info_3.asSpreadSpectrum[i].ucClockIndication == id) &&
1397                                     (clock <= ss_info->info_3.asSpreadSpectrum[i].ulTargetClockRange)) {
1398                                         ss->percentage =
1399                                                 le16_to_cpu(ss_info->info_3.asSpreadSpectrum[i].usSpreadSpectrumPercentage);
1400                                         ss->type = ss_info->info_3.asSpreadSpectrum[i].ucSpreadSpectrumMode;
1401                                         ss->rate = le16_to_cpu(ss_info->info_3.asSpreadSpectrum[i].usSpreadRateIn10Hz);
1402                                         return true;
1403                                 }
1404                         }
1405                         break;
1406                 default:
1407                         DRM_ERROR("Unsupported ASIC_InternalSS_Info table: %d %d\n", frev, crev);
1408                         break;
1409                 }
1410
1411         }
1412         return false;
1413 }
1414
1415 union lvds_info {
1416         struct _ATOM_LVDS_INFO info;
1417         struct _ATOM_LVDS_INFO_V12 info_12;
1418 };
1419
1420 struct radeon_encoder_atom_dig *radeon_atombios_get_lvds_info(struct
1421                                                               radeon_encoder
1422                                                               *encoder)
1423 {
1424         struct drm_device *dev = encoder->base.dev;
1425         struct radeon_device *rdev = dev->dev_private;
1426         struct radeon_mode_info *mode_info = &rdev->mode_info;
1427         int index = GetIndexIntoMasterTable(DATA, LVDS_Info);
1428         uint16_t data_offset, misc;
1429         union lvds_info *lvds_info;
1430         uint8_t frev, crev;
1431         struct radeon_encoder_atom_dig *lvds = NULL;
1432         int encoder_enum = (encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
1433
1434         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1435                                    &frev, &crev, &data_offset)) {
1436                 lvds_info =
1437                         (union lvds_info *)(mode_info->atom_context->bios + data_offset);
1438                 lvds =
1439                     kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
1440
1441                 if (!lvds)
1442                         return NULL;
1443
1444                 lvds->native_mode.clock =
1445                     le16_to_cpu(lvds_info->info.sLCDTiming.usPixClk) * 10;
1446                 lvds->native_mode.hdisplay =
1447                     le16_to_cpu(lvds_info->info.sLCDTiming.usHActive);
1448                 lvds->native_mode.vdisplay =
1449                     le16_to_cpu(lvds_info->info.sLCDTiming.usVActive);
1450                 lvds->native_mode.htotal = lvds->native_mode.hdisplay +
1451                         le16_to_cpu(lvds_info->info.sLCDTiming.usHBlanking_Time);
1452                 lvds->native_mode.hsync_start = lvds->native_mode.hdisplay +
1453                         le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncOffset);
1454                 lvds->native_mode.hsync_end = lvds->native_mode.hsync_start +
1455                         le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncWidth);
1456                 lvds->native_mode.vtotal = lvds->native_mode.vdisplay +
1457                         le16_to_cpu(lvds_info->info.sLCDTiming.usVBlanking_Time);
1458                 lvds->native_mode.vsync_start = lvds->native_mode.vdisplay +
1459                         le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncOffset);
1460                 lvds->native_mode.vsync_end = lvds->native_mode.vsync_start +
1461                         le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncWidth);
1462                 lvds->panel_pwr_delay =
1463                     le16_to_cpu(lvds_info->info.usOffDelayInMs);
1464                 lvds->lcd_misc = lvds_info->info.ucLVDS_Misc;
1465
1466                 misc = le16_to_cpu(lvds_info->info.sLCDTiming.susModeMiscInfo.usAccess);
1467                 if (misc & ATOM_VSYNC_POLARITY)
1468                         lvds->native_mode.flags |= DRM_MODE_FLAG_NVSYNC;
1469                 if (misc & ATOM_HSYNC_POLARITY)
1470                         lvds->native_mode.flags |= DRM_MODE_FLAG_NHSYNC;
1471                 if (misc & ATOM_COMPOSITESYNC)
1472                         lvds->native_mode.flags |= DRM_MODE_FLAG_CSYNC;
1473                 if (misc & ATOM_INTERLACE)
1474                         lvds->native_mode.flags |= DRM_MODE_FLAG_INTERLACE;
1475                 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1476                         lvds->native_mode.flags |= DRM_MODE_FLAG_DBLSCAN;
1477
1478                 /* set crtc values */
1479                 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V);
1480
1481                 lvds->lcd_ss_id = lvds_info->info.ucSS_Id;
1482
1483                 encoder->native_mode = lvds->native_mode;
1484
1485                 if (encoder_enum == 2)
1486                         lvds->linkb = true;
1487                 else
1488                         lvds->linkb = false;
1489
1490         }
1491         return lvds;
1492 }
1493
1494 struct radeon_encoder_primary_dac *
1495 radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder)
1496 {
1497         struct drm_device *dev = encoder->base.dev;
1498         struct radeon_device *rdev = dev->dev_private;
1499         struct radeon_mode_info *mode_info = &rdev->mode_info;
1500         int index = GetIndexIntoMasterTable(DATA, CompassionateData);
1501         uint16_t data_offset;
1502         struct _COMPASSIONATE_DATA *dac_info;
1503         uint8_t frev, crev;
1504         uint8_t bg, dac;
1505         struct radeon_encoder_primary_dac *p_dac = NULL;
1506
1507         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1508                                    &frev, &crev, &data_offset)) {
1509                 dac_info = (struct _COMPASSIONATE_DATA *)
1510                         (mode_info->atom_context->bios + data_offset);
1511
1512                 p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac), GFP_KERNEL);
1513
1514                 if (!p_dac)
1515                         return NULL;
1516
1517                 bg = dac_info->ucDAC1_BG_Adjustment;
1518                 dac = dac_info->ucDAC1_DAC_Adjustment;
1519                 p_dac->ps2_pdac_adj = (bg << 8) | (dac);
1520
1521         }
1522         return p_dac;
1523 }
1524
1525 bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
1526                                 struct drm_display_mode *mode)
1527 {
1528         struct radeon_mode_info *mode_info = &rdev->mode_info;
1529         ATOM_ANALOG_TV_INFO *tv_info;
1530         ATOM_ANALOG_TV_INFO_V1_2 *tv_info_v1_2;
1531         ATOM_DTD_FORMAT *dtd_timings;
1532         int data_index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
1533         u8 frev, crev;
1534         u16 data_offset, misc;
1535
1536         if (!atom_parse_data_header(mode_info->atom_context, data_index, NULL,
1537                                     &frev, &crev, &data_offset))
1538                 return false;
1539
1540         switch (crev) {
1541         case 1:
1542                 tv_info = (ATOM_ANALOG_TV_INFO *)(mode_info->atom_context->bios + data_offset);
1543                 if (index >= MAX_SUPPORTED_TV_TIMING)
1544                         return false;
1545
1546                 mode->crtc_htotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Total);
1547                 mode->crtc_hdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Disp);
1548                 mode->crtc_hsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart);
1549                 mode->crtc_hsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart) +
1550                         le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncWidth);
1551
1552                 mode->crtc_vtotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Total);
1553                 mode->crtc_vdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Disp);
1554                 mode->crtc_vsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart);
1555                 mode->crtc_vsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart) +
1556                         le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncWidth);
1557
1558                 mode->flags = 0;
1559                 misc = le16_to_cpu(tv_info->aModeTimings[index].susModeMiscInfo.usAccess);
1560                 if (misc & ATOM_VSYNC_POLARITY)
1561                         mode->flags |= DRM_MODE_FLAG_NVSYNC;
1562                 if (misc & ATOM_HSYNC_POLARITY)
1563                         mode->flags |= DRM_MODE_FLAG_NHSYNC;
1564                 if (misc & ATOM_COMPOSITESYNC)
1565                         mode->flags |= DRM_MODE_FLAG_CSYNC;
1566                 if (misc & ATOM_INTERLACE)
1567                         mode->flags |= DRM_MODE_FLAG_INTERLACE;
1568                 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1569                         mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1570
1571                 mode->clock = le16_to_cpu(tv_info->aModeTimings[index].usPixelClock) * 10;
1572
1573                 if (index == 1) {
1574                         /* PAL timings appear to have wrong values for totals */
1575                         mode->crtc_htotal -= 1;
1576                         mode->crtc_vtotal -= 1;
1577                 }
1578                 break;
1579         case 2:
1580                 tv_info_v1_2 = (ATOM_ANALOG_TV_INFO_V1_2 *)(mode_info->atom_context->bios + data_offset);
1581                 if (index >= MAX_SUPPORTED_TV_TIMING_V1_2)
1582                         return false;
1583
1584                 dtd_timings = &tv_info_v1_2->aModeTimings[index];
1585                 mode->crtc_htotal = le16_to_cpu(dtd_timings->usHActive) +
1586                         le16_to_cpu(dtd_timings->usHBlanking_Time);
1587                 mode->crtc_hdisplay = le16_to_cpu(dtd_timings->usHActive);
1588                 mode->crtc_hsync_start = le16_to_cpu(dtd_timings->usHActive) +
1589                         le16_to_cpu(dtd_timings->usHSyncOffset);
1590                 mode->crtc_hsync_end = mode->crtc_hsync_start +
1591                         le16_to_cpu(dtd_timings->usHSyncWidth);
1592
1593                 mode->crtc_vtotal = le16_to_cpu(dtd_timings->usVActive) +
1594                         le16_to_cpu(dtd_timings->usVBlanking_Time);
1595                 mode->crtc_vdisplay = le16_to_cpu(dtd_timings->usVActive);
1596                 mode->crtc_vsync_start = le16_to_cpu(dtd_timings->usVActive) +
1597                         le16_to_cpu(dtd_timings->usVSyncOffset);
1598                 mode->crtc_vsync_end = mode->crtc_vsync_start +
1599                         le16_to_cpu(dtd_timings->usVSyncWidth);
1600
1601                 mode->flags = 0;
1602                 misc = le16_to_cpu(dtd_timings->susModeMiscInfo.usAccess);
1603                 if (misc & ATOM_VSYNC_POLARITY)
1604                         mode->flags |= DRM_MODE_FLAG_NVSYNC;
1605                 if (misc & ATOM_HSYNC_POLARITY)
1606                         mode->flags |= DRM_MODE_FLAG_NHSYNC;
1607                 if (misc & ATOM_COMPOSITESYNC)
1608                         mode->flags |= DRM_MODE_FLAG_CSYNC;
1609                 if (misc & ATOM_INTERLACE)
1610                         mode->flags |= DRM_MODE_FLAG_INTERLACE;
1611                 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1612                         mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1613
1614                 mode->clock = le16_to_cpu(dtd_timings->usPixClk) * 10;
1615                 break;
1616         }
1617         return true;
1618 }
1619
1620 enum radeon_tv_std
1621 radeon_atombios_get_tv_info(struct radeon_device *rdev)
1622 {
1623         struct radeon_mode_info *mode_info = &rdev->mode_info;
1624         int index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
1625         uint16_t data_offset;
1626         uint8_t frev, crev;
1627         struct _ATOM_ANALOG_TV_INFO *tv_info;
1628         enum radeon_tv_std tv_std = TV_STD_NTSC;
1629
1630         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1631                                    &frev, &crev, &data_offset)) {
1632
1633                 tv_info = (struct _ATOM_ANALOG_TV_INFO *)
1634                         (mode_info->atom_context->bios + data_offset);
1635
1636                 switch (tv_info->ucTV_BootUpDefaultStandard) {
1637                 case ATOM_TV_NTSC:
1638                         tv_std = TV_STD_NTSC;
1639                         DRM_DEBUG_KMS("Default TV standard: NTSC\n");
1640                         break;
1641                 case ATOM_TV_NTSCJ:
1642                         tv_std = TV_STD_NTSC_J;
1643                         DRM_DEBUG_KMS("Default TV standard: NTSC-J\n");
1644                         break;
1645                 case ATOM_TV_PAL:
1646                         tv_std = TV_STD_PAL;
1647                         DRM_DEBUG_KMS("Default TV standard: PAL\n");
1648                         break;
1649                 case ATOM_TV_PALM:
1650                         tv_std = TV_STD_PAL_M;
1651                         DRM_DEBUG_KMS("Default TV standard: PAL-M\n");
1652                         break;
1653                 case ATOM_TV_PALN:
1654                         tv_std = TV_STD_PAL_N;
1655                         DRM_DEBUG_KMS("Default TV standard: PAL-N\n");
1656                         break;
1657                 case ATOM_TV_PALCN:
1658                         tv_std = TV_STD_PAL_CN;
1659                         DRM_DEBUG_KMS("Default TV standard: PAL-CN\n");
1660                         break;
1661                 case ATOM_TV_PAL60:
1662                         tv_std = TV_STD_PAL_60;
1663                         DRM_DEBUG_KMS("Default TV standard: PAL-60\n");
1664                         break;
1665                 case ATOM_TV_SECAM:
1666                         tv_std = TV_STD_SECAM;
1667                         DRM_DEBUG_KMS("Default TV standard: SECAM\n");
1668                         break;
1669                 default:
1670                         tv_std = TV_STD_NTSC;
1671                         DRM_DEBUG_KMS("Unknown TV standard; defaulting to NTSC\n");
1672                         break;
1673                 }
1674         }
1675         return tv_std;
1676 }
1677
1678 struct radeon_encoder_tv_dac *
1679 radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder)
1680 {
1681         struct drm_device *dev = encoder->base.dev;
1682         struct radeon_device *rdev = dev->dev_private;
1683         struct radeon_mode_info *mode_info = &rdev->mode_info;
1684         int index = GetIndexIntoMasterTable(DATA, CompassionateData);
1685         uint16_t data_offset;
1686         struct _COMPASSIONATE_DATA *dac_info;
1687         uint8_t frev, crev;
1688         uint8_t bg, dac;
1689         struct radeon_encoder_tv_dac *tv_dac = NULL;
1690
1691         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1692                                    &frev, &crev, &data_offset)) {
1693
1694                 dac_info = (struct _COMPASSIONATE_DATA *)
1695                         (mode_info->atom_context->bios + data_offset);
1696
1697                 tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL);
1698
1699                 if (!tv_dac)
1700                         return NULL;
1701
1702                 bg = dac_info->ucDAC2_CRT2_BG_Adjustment;
1703                 dac = dac_info->ucDAC2_CRT2_DAC_Adjustment;
1704                 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
1705
1706                 bg = dac_info->ucDAC2_PAL_BG_Adjustment;
1707                 dac = dac_info->ucDAC2_PAL_DAC_Adjustment;
1708                 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
1709
1710                 bg = dac_info->ucDAC2_NTSC_BG_Adjustment;
1711                 dac = dac_info->ucDAC2_NTSC_DAC_Adjustment;
1712                 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
1713
1714                 tv_dac->tv_std = radeon_atombios_get_tv_info(rdev);
1715         }
1716         return tv_dac;
1717 }
1718
1719 static const char *thermal_controller_names[] = {
1720         "NONE",
1721         "lm63",
1722         "adm1032",
1723         "adm1030",
1724         "max6649",
1725         "lm64",
1726         "f75375",
1727         "asc7xxx",
1728 };
1729
1730 static const char *pp_lib_thermal_controller_names[] = {
1731         "NONE",
1732         "lm63",
1733         "adm1032",
1734         "adm1030",
1735         "max6649",
1736         "lm64",
1737         "f75375",
1738         "RV6xx",
1739         "RV770",
1740         "adt7473",
1741         "External GPIO",
1742         "Evergreen",
1743         "adt7473 with internal",
1744
1745 };
1746
1747 union power_info {
1748         struct _ATOM_POWERPLAY_INFO info;
1749         struct _ATOM_POWERPLAY_INFO_V2 info_2;
1750         struct _ATOM_POWERPLAY_INFO_V3 info_3;
1751         struct _ATOM_PPLIB_POWERPLAYTABLE info_4;
1752 };
1753
1754 void radeon_atombios_get_power_modes(struct radeon_device *rdev)
1755 {
1756         struct radeon_mode_info *mode_info = &rdev->mode_info;
1757         int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
1758         u16 data_offset;
1759         u8 frev, crev;
1760         u32 misc, misc2 = 0, sclk, mclk;
1761         union power_info *power_info;
1762         struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
1763         struct _ATOM_PPLIB_STATE *power_state;
1764         int num_modes = 0, i, j;
1765         int state_index = 0, mode_index = 0;
1766         struct radeon_i2c_bus_rec i2c_bus;
1767
1768         rdev->pm.default_power_state_index = -1;
1769
1770         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1771                                    &frev, &crev, &data_offset)) {
1772                 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
1773                 if (frev < 4) {
1774                         /* add the i2c bus for thermal/fan chip */
1775                         if (power_info->info.ucOverdriveThermalController > 0) {
1776                                 DRM_INFO("Possible %s thermal controller at 0x%02x\n",
1777                                          thermal_controller_names[power_info->info.ucOverdriveThermalController],
1778                                          power_info->info.ucOverdriveControllerAddress >> 1);
1779                                 i2c_bus = radeon_lookup_i2c_gpio(rdev, power_info->info.ucOverdriveI2cLine);
1780                                 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
1781                                 if (rdev->pm.i2c_bus) {
1782                                         struct i2c_board_info info = { };
1783                                         const char *name = thermal_controller_names[power_info->info.
1784                                                                                     ucOverdriveThermalController];
1785                                         info.addr = power_info->info.ucOverdriveControllerAddress >> 1;
1786                                         strlcpy(info.type, name, sizeof(info.type));
1787                                         i2c_new_device(&rdev->pm.i2c_bus->adapter, &info);
1788                                 }
1789                         }
1790                         num_modes = power_info->info.ucNumOfPowerModeEntries;
1791                         if (num_modes > ATOM_MAX_NUMBEROF_POWER_BLOCK)
1792                                 num_modes = ATOM_MAX_NUMBEROF_POWER_BLOCK;
1793                         /* last mode is usually default, array is low to high */
1794                         for (i = 0; i < num_modes; i++) {
1795                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
1796                                 switch (frev) {
1797                                 case 1:
1798                                         rdev->pm.power_state[state_index].num_clock_modes = 1;
1799                                         rdev->pm.power_state[state_index].clock_info[0].mclk =
1800                                                 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usMemoryClock);
1801                                         rdev->pm.power_state[state_index].clock_info[0].sclk =
1802                                                 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usEngineClock);
1803                                         /* skip invalid modes */
1804                                         if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
1805                                             (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
1806                                                 continue;
1807                                         rdev->pm.power_state[state_index].pcie_lanes =
1808                                                 power_info->info.asPowerPlayInfo[i].ucNumPciELanes;
1809                                         misc = le32_to_cpu(power_info->info.asPowerPlayInfo[i].ulMiscInfo);
1810                                         if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
1811                                             (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
1812                                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1813                                                         VOLTAGE_GPIO;
1814                                                 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
1815                                                         radeon_lookup_gpio(rdev,
1816                                                         power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex);
1817                                                 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
1818                                                         rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1819                                                                 true;
1820                                                 else
1821                                                         rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1822                                                                 false;
1823                                         } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
1824                                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1825                                                         VOLTAGE_VDDC;
1826                                                 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
1827                                                         power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex;
1828                                         }
1829                                         rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
1830                                         rdev->pm.power_state[state_index].misc = misc;
1831                                         /* order matters! */
1832                                         if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE)
1833                                                 rdev->pm.power_state[state_index].type =
1834                                                         POWER_STATE_TYPE_POWERSAVE;
1835                                         if (misc & ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE)
1836                                                 rdev->pm.power_state[state_index].type =
1837                                                         POWER_STATE_TYPE_BATTERY;
1838                                         if (misc & ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE)
1839                                                 rdev->pm.power_state[state_index].type =
1840                                                         POWER_STATE_TYPE_BATTERY;
1841                                         if (misc & ATOM_PM_MISCINFO_LOAD_BALANCE_EN)
1842                                                 rdev->pm.power_state[state_index].type =
1843                                                         POWER_STATE_TYPE_BALANCED;
1844                                         if (misc & ATOM_PM_MISCINFO_3D_ACCELERATION_EN) {
1845                                                 rdev->pm.power_state[state_index].type =
1846                                                         POWER_STATE_TYPE_PERFORMANCE;
1847                                                 rdev->pm.power_state[state_index].flags &=
1848                                                         ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
1849                                         }
1850                                         if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) {
1851                                                 rdev->pm.power_state[state_index].type =
1852                                                         POWER_STATE_TYPE_DEFAULT;
1853                                                 rdev->pm.default_power_state_index = state_index;
1854                                                 rdev->pm.power_state[state_index].default_clock_mode =
1855                                                         &rdev->pm.power_state[state_index].clock_info[0];
1856                                                 rdev->pm.power_state[state_index].flags &=
1857                                                         ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
1858                                         } else if (state_index == 0) {
1859                                                 rdev->pm.power_state[state_index].clock_info[0].flags |=
1860                                                         RADEON_PM_MODE_NO_DISPLAY;
1861                                         }
1862                                         state_index++;
1863                                         break;
1864                                 case 2:
1865                                         rdev->pm.power_state[state_index].num_clock_modes = 1;
1866                                         rdev->pm.power_state[state_index].clock_info[0].mclk =
1867                                                 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMemoryClock);
1868                                         rdev->pm.power_state[state_index].clock_info[0].sclk =
1869                                                 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulEngineClock);
1870                                         /* skip invalid modes */
1871                                         if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
1872                                             (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
1873                                                 continue;
1874                                         rdev->pm.power_state[state_index].pcie_lanes =
1875                                                 power_info->info_2.asPowerPlayInfo[i].ucNumPciELanes;
1876                                         misc = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo);
1877                                         misc2 = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo2);
1878                                         if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
1879                                             (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
1880                                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1881                                                         VOLTAGE_GPIO;
1882                                                 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
1883                                                         radeon_lookup_gpio(rdev,
1884                                                         power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex);
1885                                                 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
1886                                                         rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1887                                                                 true;
1888                                                 else
1889                                                         rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1890                                                                 false;
1891                                         } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
1892                                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1893                                                         VOLTAGE_VDDC;
1894                                                 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
1895                                                         power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex;
1896                                         }
1897                                         rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
1898                                         rdev->pm.power_state[state_index].misc = misc;
1899                                         rdev->pm.power_state[state_index].misc2 = misc2;
1900                                         /* order matters! */
1901                                         if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE)
1902                                                 rdev->pm.power_state[state_index].type =
1903                                                         POWER_STATE_TYPE_POWERSAVE;
1904                                         if (misc & ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE)
1905                                                 rdev->pm.power_state[state_index].type =
1906                                                         POWER_STATE_TYPE_BATTERY;
1907                                         if (misc & ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE)
1908                                                 rdev->pm.power_state[state_index].type =
1909                                                         POWER_STATE_TYPE_BATTERY;
1910                                         if (misc & ATOM_PM_MISCINFO_LOAD_BALANCE_EN)
1911                                                 rdev->pm.power_state[state_index].type =
1912                                                         POWER_STATE_TYPE_BALANCED;
1913                                         if (misc & ATOM_PM_MISCINFO_3D_ACCELERATION_EN) {
1914                                                 rdev->pm.power_state[state_index].type =
1915                                                         POWER_STATE_TYPE_PERFORMANCE;
1916                                                 rdev->pm.power_state[state_index].flags &=
1917                                                         ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
1918                                         }
1919                                         if (misc2 & ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE)
1920                                                 rdev->pm.power_state[state_index].type =
1921                                                         POWER_STATE_TYPE_BALANCED;
1922                                         if (misc2 & ATOM_PM_MISCINFO2_MULTI_DISPLAY_SUPPORT)
1923                                                 rdev->pm.power_state[state_index].flags &=
1924                                                         ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
1925                                         if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) {
1926                                                 rdev->pm.power_state[state_index].type =
1927                                                         POWER_STATE_TYPE_DEFAULT;
1928                                                 rdev->pm.default_power_state_index = state_index;
1929                                                 rdev->pm.power_state[state_index].default_clock_mode =
1930                                                         &rdev->pm.power_state[state_index].clock_info[0];
1931                                                 rdev->pm.power_state[state_index].flags &=
1932                                                         ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
1933                                         } else if (state_index == 0) {
1934                                                 rdev->pm.power_state[state_index].clock_info[0].flags |=
1935                                                         RADEON_PM_MODE_NO_DISPLAY;
1936                                         }
1937                                         state_index++;
1938                                         break;
1939                                 case 3:
1940                                         rdev->pm.power_state[state_index].num_clock_modes = 1;
1941                                         rdev->pm.power_state[state_index].clock_info[0].mclk =
1942                                                 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMemoryClock);
1943                                         rdev->pm.power_state[state_index].clock_info[0].sclk =
1944                                                 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulEngineClock);
1945                                         /* skip invalid modes */
1946                                         if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
1947                                             (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
1948                                                 continue;
1949                                         rdev->pm.power_state[state_index].pcie_lanes =
1950                                                 power_info->info_3.asPowerPlayInfo[i].ucNumPciELanes;
1951                                         misc = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo);
1952                                         misc2 = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo2);
1953                                         if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
1954                                             (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
1955                                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1956                                                         VOLTAGE_GPIO;
1957                                                 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
1958                                                         radeon_lookup_gpio(rdev,
1959                                                         power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex);
1960                                                 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
1961                                                         rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1962                                                                 true;
1963                                                 else
1964                                                         rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1965                                                                 false;
1966                                         } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
1967                                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1968                                                         VOLTAGE_VDDC;
1969                                                 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
1970                                                         power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex;
1971                                                 if (misc2 & ATOM_PM_MISCINFO2_VDDCI_DYNAMIC_VOLTAGE_EN) {
1972                                                         rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_enabled =
1973                                                                 true;
1974                                                         rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_id =
1975                                                         power_info->info_3.asPowerPlayInfo[i].ucVDDCI_VoltageDropIndex;
1976                                                 }
1977                                         }
1978                                         rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
1979                                         rdev->pm.power_state[state_index].misc = misc;
1980                                         rdev->pm.power_state[state_index].misc2 = misc2;
1981                                         /* order matters! */
1982                                         if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE)
1983                                                 rdev->pm.power_state[state_index].type =
1984                                                         POWER_STATE_TYPE_POWERSAVE;
1985                                         if (misc & ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE)
1986                                                 rdev->pm.power_state[state_index].type =
1987                                                         POWER_STATE_TYPE_BATTERY;
1988                                         if (misc & ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE)
1989                                                 rdev->pm.power_state[state_index].type =
1990                                                         POWER_STATE_TYPE_BATTERY;
1991                                         if (misc & ATOM_PM_MISCINFO_LOAD_BALANCE_EN)
1992                                                 rdev->pm.power_state[state_index].type =
1993                                                         POWER_STATE_TYPE_BALANCED;
1994                                         if (misc & ATOM_PM_MISCINFO_3D_ACCELERATION_EN) {
1995                                                 rdev->pm.power_state[state_index].type =
1996                                                         POWER_STATE_TYPE_PERFORMANCE;
1997                                                 rdev->pm.power_state[state_index].flags &=
1998                                                         ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
1999                                         }
2000                                         if (misc2 & ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE)
2001                                                 rdev->pm.power_state[state_index].type =
2002                                                         POWER_STATE_TYPE_BALANCED;
2003                                         if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) {
2004                                                 rdev->pm.power_state[state_index].type =
2005                                                         POWER_STATE_TYPE_DEFAULT;
2006                                                 rdev->pm.default_power_state_index = state_index;
2007                                                 rdev->pm.power_state[state_index].default_clock_mode =
2008                                                         &rdev->pm.power_state[state_index].clock_info[0];
2009                                         } else if (state_index == 0) {
2010                                                 rdev->pm.power_state[state_index].clock_info[0].flags |=
2011                                                         RADEON_PM_MODE_NO_DISPLAY;
2012                                         }
2013                                         state_index++;
2014                                         break;
2015                                 }
2016                         }
2017                         /* last mode is usually default */
2018                         if (rdev->pm.default_power_state_index == -1) {
2019                                 rdev->pm.power_state[state_index - 1].type =
2020                                         POWER_STATE_TYPE_DEFAULT;
2021                                 rdev->pm.default_power_state_index = state_index - 1;
2022                                 rdev->pm.power_state[state_index - 1].default_clock_mode =
2023                                         &rdev->pm.power_state[state_index - 1].clock_info[0];
2024                                 rdev->pm.power_state[state_index].flags &=
2025                                         ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2026                                 rdev->pm.power_state[state_index].misc = 0;
2027                                 rdev->pm.power_state[state_index].misc2 = 0;
2028                         }
2029                 } else {
2030                         int fw_index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
2031                         uint8_t fw_frev, fw_crev;
2032                         uint16_t fw_data_offset, vddc = 0;
2033                         union firmware_info *firmware_info;
2034                         ATOM_PPLIB_THERMALCONTROLLER *controller = &power_info->info_4.sThermalController;
2035
2036                         if (atom_parse_data_header(mode_info->atom_context, fw_index, NULL,
2037                                                    &fw_frev, &fw_crev, &fw_data_offset)) {
2038                                 firmware_info =
2039                                         (union firmware_info *)(mode_info->atom_context->bios +
2040                                                                 fw_data_offset);
2041                                 vddc = firmware_info->info_14.usBootUpVDDCVoltage;
2042                         }
2043
2044                         /* add the i2c bus for thermal/fan chip */
2045                         if (controller->ucType > 0) {
2046                                 if (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV6xx) {
2047                                         DRM_INFO("Internal thermal controller %s fan control\n",
2048                                                  (controller->ucFanParameters &
2049                                                   ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2050                                         rdev->pm.int_thermal_type = THERMAL_TYPE_RV6XX;
2051                                 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV770) {
2052                                         DRM_INFO("Internal thermal controller %s fan control\n",
2053                                                  (controller->ucFanParameters &
2054                                                   ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2055                                         rdev->pm.int_thermal_type = THERMAL_TYPE_RV770;
2056                                 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_EVERGREEN) {
2057                                         DRM_INFO("Internal thermal controller %s fan control\n",
2058                                                  (controller->ucFanParameters &
2059                                                   ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2060                                         rdev->pm.int_thermal_type = THERMAL_TYPE_EVERGREEN;
2061                                 } else if ((controller->ucType ==
2062                                             ATOM_PP_THERMALCONTROLLER_EXTERNAL_GPIO) ||
2063                                            (controller->ucType ==
2064                                             ATOM_PP_THERMALCONTROLLER_ADT7473_WITH_INTERNAL)) {
2065                                         DRM_INFO("Special thermal controller config\n");
2066                                 } else {
2067                                         DRM_INFO("Possible %s thermal controller at 0x%02x %s fan control\n",
2068                                                  pp_lib_thermal_controller_names[controller->ucType],
2069                                                  controller->ucI2cAddress >> 1,
2070                                                  (controller->ucFanParameters &
2071                                                   ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2072                                         i2c_bus = radeon_lookup_i2c_gpio(rdev, controller->ucI2cLine);
2073                                         rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
2074                                         if (rdev->pm.i2c_bus) {
2075                                                 struct i2c_board_info info = { };
2076                                                 const char *name = pp_lib_thermal_controller_names[controller->ucType];
2077                                                 info.addr = controller->ucI2cAddress >> 1;
2078                                                 strlcpy(info.type, name, sizeof(info.type));
2079                                                 i2c_new_device(&rdev->pm.i2c_bus->adapter, &info);
2080                                         }
2081
2082                                 }
2083                         }
2084                         /* first mode is usually default, followed by low to high */
2085                         for (i = 0; i < power_info->info_4.ucNumStates; i++) {
2086                                 mode_index = 0;
2087                                 power_state = (struct _ATOM_PPLIB_STATE *)
2088                                         (mode_info->atom_context->bios +
2089                                          data_offset +
2090                                          le16_to_cpu(power_info->info_4.usStateArrayOffset) +
2091                                          i * power_info->info_4.ucStateEntrySize);
2092                                 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
2093                                         (mode_info->atom_context->bios +
2094                                          data_offset +
2095                                          le16_to_cpu(power_info->info_4.usNonClockInfoArrayOffset) +
2096                                          (power_state->ucNonClockStateIndex *
2097                                           power_info->info_4.ucNonClockSize));
2098                                 for (j = 0; j < (power_info->info_4.ucStateEntrySize - 1); j++) {
2099                                         if (rdev->flags & RADEON_IS_IGP) {
2100                                                 struct _ATOM_PPLIB_RS780_CLOCK_INFO *clock_info =
2101                                                         (struct _ATOM_PPLIB_RS780_CLOCK_INFO *)
2102                                                         (mode_info->atom_context->bios +
2103                                                          data_offset +
2104                                                          le16_to_cpu(power_info->info_4.usClockInfoArrayOffset) +
2105                                                          (power_state->ucClockStateIndices[j] *
2106                                                           power_info->info_4.ucClockInfoSize));
2107                                                 sclk = le16_to_cpu(clock_info->usLowEngineClockLow);
2108                                                 sclk |= clock_info->ucLowEngineClockHigh << 16;
2109                                                 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2110                                                 /* skip invalid modes */
2111                                                 if (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0)
2112                                                         continue;
2113                                                 /* voltage works differently on IGPs */
2114                                                 mode_index++;
2115                                         } else if (ASIC_IS_DCE4(rdev)) {
2116                                                 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO *clock_info =
2117                                                         (struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO *)
2118                                                         (mode_info->atom_context->bios +
2119                                                          data_offset +
2120                                                          le16_to_cpu(power_info->info_4.usClockInfoArrayOffset) +
2121                                                          (power_state->ucClockStateIndices[j] *
2122                                                           power_info->info_4.ucClockInfoSize));
2123                                                 sclk = le16_to_cpu(clock_info->usEngineClockLow);
2124                                                 sclk |= clock_info->ucEngineClockHigh << 16;
2125                                                 mclk = le16_to_cpu(clock_info->usMemoryClockLow);
2126                                                 mclk |= clock_info->ucMemoryClockHigh << 16;
2127                                                 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2128                                                 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2129                                                 /* skip invalid modes */
2130                                                 if ((rdev->pm.power_state[state_index].clock_info[mode_index].mclk == 0) ||
2131                                                     (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0))
2132                                                         continue;
2133                                                 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2134                                                         VOLTAGE_SW;
2135                                                 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
2136                                                         clock_info->usVDDC;
2137                                                 /* XXX usVDDCI */
2138                                                 mode_index++;
2139                                         } else {
2140                                                 struct _ATOM_PPLIB_R600_CLOCK_INFO *clock_info =
2141                                                         (struct _ATOM_PPLIB_R600_CLOCK_INFO *)
2142                                                         (mode_info->atom_context->bios +
2143                                                          data_offset +
2144                                                          le16_to_cpu(power_info->info_4.usClockInfoArrayOffset) +
2145                                                          (power_state->ucClockStateIndices[j] *
2146                                                           power_info->info_4.ucClockInfoSize));
2147                                                 sclk = le16_to_cpu(clock_info->usEngineClockLow);
2148                                                 sclk |= clock_info->ucEngineClockHigh << 16;
2149                                                 mclk = le16_to_cpu(clock_info->usMemoryClockLow);
2150                                                 mclk |= clock_info->ucMemoryClockHigh << 16;
2151                                                 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2152                                                 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2153                                                 /* skip invalid modes */
2154                                                 if ((rdev->pm.power_state[state_index].clock_info[mode_index].mclk == 0) ||
2155                                                     (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0))
2156                                                         continue;
2157                                                 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2158                                                         VOLTAGE_SW;
2159                                                 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
2160                                                         clock_info->usVDDC;
2161                                                 mode_index++;
2162                                         }
2163                                 }
2164                                 rdev->pm.power_state[state_index].num_clock_modes = mode_index;
2165                                 if (mode_index) {
2166                                         misc = le32_to_cpu(non_clock_info->ulCapsAndSettings);
2167                                         misc2 = le16_to_cpu(non_clock_info->usClassification);
2168                                         rdev->pm.power_state[state_index].misc = misc;
2169                                         rdev->pm.power_state[state_index].misc2 = misc2;
2170                                         rdev->pm.power_state[state_index].pcie_lanes =
2171                                                 ((misc & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >>
2172                                                 ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1;
2173                                         switch (misc2 & ATOM_PPLIB_CLASSIFICATION_UI_MASK) {
2174                                         case ATOM_PPLIB_CLASSIFICATION_UI_BATTERY:
2175                                                 rdev->pm.power_state[state_index].type =
2176                                                         POWER_STATE_TYPE_BATTERY;
2177                                                 break;
2178                                         case ATOM_PPLIB_CLASSIFICATION_UI_BALANCED:
2179                                                 rdev->pm.power_state[state_index].type =
2180                                                         POWER_STATE_TYPE_BALANCED;
2181                                                 break;
2182                                         case ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE:
2183                                                 rdev->pm.power_state[state_index].type =
2184                                                         POWER_STATE_TYPE_PERFORMANCE;
2185                                                 break;
2186                                         case ATOM_PPLIB_CLASSIFICATION_UI_NONE:
2187                                                 if (misc2 & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE)
2188                                                         rdev->pm.power_state[state_index].type =
2189                                                                 POWER_STATE_TYPE_PERFORMANCE;
2190                                                 break;
2191                                         }
2192                                         rdev->pm.power_state[state_index].flags = 0;
2193                                         if (misc & ATOM_PPLIB_SINGLE_DISPLAY_ONLY)
2194                                                 rdev->pm.power_state[state_index].flags |=
2195                                                         RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2196                                         if (misc2 & ATOM_PPLIB_CLASSIFICATION_BOOT) {
2197                                                 rdev->pm.power_state[state_index].type =
2198                                                         POWER_STATE_TYPE_DEFAULT;
2199                                                 rdev->pm.default_power_state_index = state_index;
2200                                                 rdev->pm.power_state[state_index].default_clock_mode =
2201                                                         &rdev->pm.power_state[state_index].clock_info[mode_index - 1];
2202                                                 /* patch the table values with the default slck/mclk from firmware info */
2203                                                 for (j = 0; j < mode_index; j++) {
2204                                                         rdev->pm.power_state[state_index].clock_info[j].mclk =
2205                                                                 rdev->clock.default_mclk;
2206                                                         rdev->pm.power_state[state_index].clock_info[j].sclk =
2207                                                                 rdev->clock.default_sclk;
2208                                                         if (vddc)
2209                                                                 rdev->pm.power_state[state_index].clock_info[j].voltage.voltage =
2210                                                                         vddc;
2211                                                 }
2212                                         }
2213                                         state_index++;
2214                                 }
2215                         }
2216                         /* if multiple clock modes, mark the lowest as no display */
2217                         for (i = 0; i < state_index; i++) {
2218                                 if (rdev->pm.power_state[i].num_clock_modes > 1)
2219                                         rdev->pm.power_state[i].clock_info[0].flags |=
2220                                                 RADEON_PM_MODE_NO_DISPLAY;
2221                         }
2222                         /* first mode is usually default */
2223                         if (rdev->pm.default_power_state_index == -1) {
2224                                 rdev->pm.power_state[0].type =
2225                                         POWER_STATE_TYPE_DEFAULT;
2226                                 rdev->pm.default_power_state_index = 0;
2227                                 rdev->pm.power_state[0].default_clock_mode =
2228                                         &rdev->pm.power_state[0].clock_info[0];
2229                         }
2230                 }
2231         } else {
2232                 /* add the default mode */
2233                 rdev->pm.power_state[state_index].type =
2234                         POWER_STATE_TYPE_DEFAULT;
2235                 rdev->pm.power_state[state_index].num_clock_modes = 1;
2236                 rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk;
2237                 rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk;
2238                 rdev->pm.power_state[state_index].default_clock_mode =
2239                         &rdev->pm.power_state[state_index].clock_info[0];
2240                 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2241                 rdev->pm.power_state[state_index].pcie_lanes = 16;
2242                 rdev->pm.default_power_state_index = state_index;
2243                 rdev->pm.power_state[state_index].flags = 0;
2244                 state_index++;
2245         }
2246
2247         rdev->pm.num_power_states = state_index;
2248
2249         rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
2250         rdev->pm.current_clock_mode_index = 0;
2251         rdev->pm.current_vddc = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage;
2252 }
2253
2254 void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable)
2255 {
2256         DYNAMIC_CLOCK_GATING_PS_ALLOCATION args;
2257         int index = GetIndexIntoMasterTable(COMMAND, DynamicClockGating);
2258
2259         args.ucEnable = enable;
2260
2261         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2262 }
2263
2264 uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev)
2265 {
2266         GET_ENGINE_CLOCK_PS_ALLOCATION args;
2267         int index = GetIndexIntoMasterTable(COMMAND, GetEngineClock);
2268
2269         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2270         return args.ulReturnEngineClock;
2271 }
2272
2273 uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev)
2274 {
2275         GET_MEMORY_CLOCK_PS_ALLOCATION args;
2276         int index = GetIndexIntoMasterTable(COMMAND, GetMemoryClock);
2277
2278         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2279         return args.ulReturnMemoryClock;
2280 }
2281
2282 void radeon_atom_set_engine_clock(struct radeon_device *rdev,
2283                                   uint32_t eng_clock)
2284 {
2285         SET_ENGINE_CLOCK_PS_ALLOCATION args;
2286         int index = GetIndexIntoMasterTable(COMMAND, SetEngineClock);
2287
2288         args.ulTargetEngineClock = eng_clock;   /* 10 khz */
2289
2290         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2291 }
2292
2293 void radeon_atom_set_memory_clock(struct radeon_device *rdev,
2294                                   uint32_t mem_clock)
2295 {
2296         SET_MEMORY_CLOCK_PS_ALLOCATION args;
2297         int index = GetIndexIntoMasterTable(COMMAND, SetMemoryClock);
2298
2299         if (rdev->flags & RADEON_IS_IGP)
2300                 return;
2301
2302         args.ulTargetMemoryClock = mem_clock;   /* 10 khz */
2303
2304         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2305 }
2306
2307 union set_voltage {
2308         struct _SET_VOLTAGE_PS_ALLOCATION alloc;
2309         struct _SET_VOLTAGE_PARAMETERS v1;
2310         struct _SET_VOLTAGE_PARAMETERS_V2 v2;
2311 };
2312
2313 void radeon_atom_set_voltage(struct radeon_device *rdev, u16 level)
2314 {
2315         union set_voltage args;
2316         int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
2317         u8 frev, crev, volt_index = level;
2318
2319         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
2320                 return;
2321
2322         switch (crev) {
2323         case 1:
2324                 args.v1.ucVoltageType = SET_VOLTAGE_TYPE_ASIC_VDDC;
2325                 args.v1.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_ALL_SOURCE;
2326                 args.v1.ucVoltageIndex = volt_index;
2327                 break;
2328         case 2:
2329                 args.v2.ucVoltageType = SET_VOLTAGE_TYPE_ASIC_VDDC;
2330                 args.v2.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_SET_VOLTAGE;
2331                 args.v2.usVoltageLevel = cpu_to_le16(level);
2332                 break;
2333         default:
2334                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
2335                 return;
2336         }
2337
2338         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2339 }
2340
2341
2342
2343 void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev)
2344 {
2345         struct radeon_device *rdev = dev->dev_private;
2346         uint32_t bios_2_scratch, bios_6_scratch;
2347
2348         if (rdev->family >= CHIP_R600) {
2349                 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
2350                 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
2351         } else {
2352                 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
2353                 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
2354         }
2355
2356         /* let the bios control the backlight */
2357         bios_2_scratch &= ~ATOM_S2_VRI_BRIGHT_ENABLE;
2358
2359         /* tell the bios not to handle mode switching */
2360         bios_6_scratch |= (ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH | ATOM_S6_ACC_MODE);
2361
2362         if (rdev->family >= CHIP_R600) {
2363                 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
2364                 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
2365         } else {
2366                 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
2367                 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
2368         }
2369
2370 }
2371
2372 void radeon_save_bios_scratch_regs(struct radeon_device *rdev)
2373 {
2374         uint32_t scratch_reg;
2375         int i;
2376
2377         if (rdev->family >= CHIP_R600)
2378                 scratch_reg = R600_BIOS_0_SCRATCH;
2379         else
2380                 scratch_reg = RADEON_BIOS_0_SCRATCH;
2381
2382         for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
2383                 rdev->bios_scratch[i] = RREG32(scratch_reg + (i * 4));
2384 }
2385
2386 void radeon_restore_bios_scratch_regs(struct radeon_device *rdev)
2387 {
2388         uint32_t scratch_reg;
2389         int i;
2390
2391         if (rdev->family >= CHIP_R600)
2392                 scratch_reg = R600_BIOS_0_SCRATCH;
2393         else
2394                 scratch_reg = RADEON_BIOS_0_SCRATCH;
2395
2396         for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
2397                 WREG32(scratch_reg + (i * 4), rdev->bios_scratch[i]);
2398 }
2399
2400 void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock)
2401 {
2402         struct drm_device *dev = encoder->dev;
2403         struct radeon_device *rdev = dev->dev_private;
2404         uint32_t bios_6_scratch;
2405
2406         if (rdev->family >= CHIP_R600)
2407                 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
2408         else
2409                 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
2410
2411         if (lock)
2412                 bios_6_scratch |= ATOM_S6_CRITICAL_STATE;
2413         else
2414                 bios_6_scratch &= ~ATOM_S6_CRITICAL_STATE;
2415
2416         if (rdev->family >= CHIP_R600)
2417                 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
2418         else
2419                 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
2420 }
2421
2422 /* at some point we may want to break this out into individual functions */
2423 void
2424 radeon_atombios_connected_scratch_regs(struct drm_connector *connector,
2425                                        struct drm_encoder *encoder,
2426                                        bool connected)
2427 {
2428         struct drm_device *dev = connector->dev;
2429         struct radeon_device *rdev = dev->dev_private;
2430         struct radeon_connector *radeon_connector =
2431             to_radeon_connector(connector);
2432         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2433         uint32_t bios_0_scratch, bios_3_scratch, bios_6_scratch;
2434
2435         if (rdev->family >= CHIP_R600) {
2436                 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
2437                 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
2438                 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
2439         } else {
2440                 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
2441                 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
2442                 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
2443         }
2444
2445         if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) &&
2446             (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) {
2447                 if (connected) {
2448                         DRM_DEBUG_KMS("TV1 connected\n");
2449                         bios_3_scratch |= ATOM_S3_TV1_ACTIVE;
2450                         bios_6_scratch |= ATOM_S6_ACC_REQ_TV1;
2451                 } else {
2452                         DRM_DEBUG_KMS("TV1 disconnected\n");
2453                         bios_0_scratch &= ~ATOM_S0_TV1_MASK;
2454                         bios_3_scratch &= ~ATOM_S3_TV1_ACTIVE;
2455                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_TV1;
2456                 }
2457         }
2458         if ((radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) &&
2459             (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT)) {
2460                 if (connected) {
2461                         DRM_DEBUG_KMS("CV connected\n");
2462                         bios_3_scratch |= ATOM_S3_CV_ACTIVE;
2463                         bios_6_scratch |= ATOM_S6_ACC_REQ_CV;
2464                 } else {
2465                         DRM_DEBUG_KMS("CV disconnected\n");
2466                         bios_0_scratch &= ~ATOM_S0_CV_MASK;
2467                         bios_3_scratch &= ~ATOM_S3_CV_ACTIVE;
2468                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_CV;
2469                 }
2470         }
2471         if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) &&
2472             (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) {
2473                 if (connected) {
2474                         DRM_DEBUG_KMS("LCD1 connected\n");
2475                         bios_0_scratch |= ATOM_S0_LCD1;
2476                         bios_3_scratch |= ATOM_S3_LCD1_ACTIVE;
2477                         bios_6_scratch |= ATOM_S6_ACC_REQ_LCD1;
2478                 } else {
2479                         DRM_DEBUG_KMS("LCD1 disconnected\n");
2480                         bios_0_scratch &= ~ATOM_S0_LCD1;
2481                         bios_3_scratch &= ~ATOM_S3_LCD1_ACTIVE;
2482                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_LCD1;
2483                 }
2484         }
2485         if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) &&
2486             (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) {
2487                 if (connected) {
2488                         DRM_DEBUG_KMS("CRT1 connected\n");
2489                         bios_0_scratch |= ATOM_S0_CRT1_COLOR;
2490                         bios_3_scratch |= ATOM_S3_CRT1_ACTIVE;
2491                         bios_6_scratch |= ATOM_S6_ACC_REQ_CRT1;
2492                 } else {
2493                         DRM_DEBUG_KMS("CRT1 disconnected\n");
2494                         bios_0_scratch &= ~ATOM_S0_CRT1_MASK;
2495                         bios_3_scratch &= ~ATOM_S3_CRT1_ACTIVE;
2496                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT1;
2497                 }
2498         }
2499         if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) &&
2500             (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) {
2501                 if (connected) {
2502                         DRM_DEBUG_KMS("CRT2 connected\n");
2503                         bios_0_scratch |= ATOM_S0_CRT2_COLOR;
2504                         bios_3_scratch |= ATOM_S3_CRT2_ACTIVE;
2505                         bios_6_scratch |= ATOM_S6_ACC_REQ_CRT2;
2506                 } else {
2507                         DRM_DEBUG_KMS("CRT2 disconnected\n");
2508                         bios_0_scratch &= ~ATOM_S0_CRT2_MASK;
2509                         bios_3_scratch &= ~ATOM_S3_CRT2_ACTIVE;
2510                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT2;
2511                 }
2512         }
2513         if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) &&
2514             (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) {
2515                 if (connected) {
2516                         DRM_DEBUG_KMS("DFP1 connected\n");
2517                         bios_0_scratch |= ATOM_S0_DFP1;
2518                         bios_3_scratch |= ATOM_S3_DFP1_ACTIVE;
2519                         bios_6_scratch |= ATOM_S6_ACC_REQ_DFP1;
2520                 } else {
2521                         DRM_DEBUG_KMS("DFP1 disconnected\n");
2522                         bios_0_scratch &= ~ATOM_S0_DFP1;
2523                         bios_3_scratch &= ~ATOM_S3_DFP1_ACTIVE;
2524                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP1;
2525                 }
2526         }
2527         if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) &&
2528             (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) {
2529                 if (connected) {
2530                         DRM_DEBUG_KMS("DFP2 connected\n");
2531                         bios_0_scratch |= ATOM_S0_DFP2;
2532                         bios_3_scratch |= ATOM_S3_DFP2_ACTIVE;
2533                         bios_6_scratch |= ATOM_S6_ACC_REQ_DFP2;
2534                 } else {
2535                         DRM_DEBUG_KMS("DFP2 disconnected\n");
2536                         bios_0_scratch &= ~ATOM_S0_DFP2;
2537                         bios_3_scratch &= ~ATOM_S3_DFP2_ACTIVE;
2538                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP2;
2539                 }
2540         }
2541         if ((radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) &&
2542             (radeon_connector->devices & ATOM_DEVICE_DFP3_SUPPORT)) {
2543                 if (connected) {
2544                         DRM_DEBUG_KMS("DFP3 connected\n");
2545                         bios_0_scratch |= ATOM_S0_DFP3;
2546                         bios_3_scratch |= ATOM_S3_DFP3_ACTIVE;
2547                         bios_6_scratch |= ATOM_S6_ACC_REQ_DFP3;
2548                 } else {
2549                         DRM_DEBUG_KMS("DFP3 disconnected\n");
2550                         bios_0_scratch &= ~ATOM_S0_DFP3;
2551                         bios_3_scratch &= ~ATOM_S3_DFP3_ACTIVE;
2552                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP3;
2553                 }
2554         }
2555         if ((radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) &&
2556             (radeon_connector->devices & ATOM_DEVICE_DFP4_SUPPORT)) {
2557                 if (connected) {
2558                         DRM_DEBUG_KMS("DFP4 connected\n");
2559                         bios_0_scratch |= ATOM_S0_DFP4;
2560                         bios_3_scratch |= ATOM_S3_DFP4_ACTIVE;
2561                         bios_6_scratch |= ATOM_S6_ACC_REQ_DFP4;
2562                 } else {
2563                         DRM_DEBUG_KMS("DFP4 disconnected\n");
2564                         bios_0_scratch &= ~ATOM_S0_DFP4;
2565                         bios_3_scratch &= ~ATOM_S3_DFP4_ACTIVE;
2566                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP4;
2567                 }
2568         }
2569         if ((radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) &&
2570             (radeon_connector->devices & ATOM_DEVICE_DFP5_SUPPORT)) {
2571                 if (connected) {
2572                         DRM_DEBUG_KMS("DFP5 connected\n");
2573                         bios_0_scratch |= ATOM_S0_DFP5;
2574                         bios_3_scratch |= ATOM_S3_DFP5_ACTIVE;
2575                         bios_6_scratch |= ATOM_S6_ACC_REQ_DFP5;
2576                 } else {
2577                         DRM_DEBUG_KMS("DFP5 disconnected\n");
2578                         bios_0_scratch &= ~ATOM_S0_DFP5;
2579                         bios_3_scratch &= ~ATOM_S3_DFP5_ACTIVE;
2580                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP5;
2581                 }
2582         }
2583
2584         if (rdev->family >= CHIP_R600) {
2585                 WREG32(R600_BIOS_0_SCRATCH, bios_0_scratch);
2586                 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
2587                 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
2588         } else {
2589                 WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch);
2590                 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
2591                 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
2592         }
2593 }
2594
2595 void
2596 radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc)
2597 {
2598         struct drm_device *dev = encoder->dev;
2599         struct radeon_device *rdev = dev->dev_private;
2600         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2601         uint32_t bios_3_scratch;
2602
2603         if (rdev->family >= CHIP_R600)
2604                 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
2605         else
2606                 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
2607
2608         if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
2609                 bios_3_scratch &= ~ATOM_S3_TV1_CRTC_ACTIVE;
2610                 bios_3_scratch |= (crtc << 18);
2611         }
2612         if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
2613                 bios_3_scratch &= ~ATOM_S3_CV_CRTC_ACTIVE;
2614                 bios_3_scratch |= (crtc << 24);
2615         }
2616         if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2617                 bios_3_scratch &= ~ATOM_S3_CRT1_CRTC_ACTIVE;
2618                 bios_3_scratch |= (crtc << 16);
2619         }
2620         if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2621                 bios_3_scratch &= ~ATOM_S3_CRT2_CRTC_ACTIVE;
2622                 bios_3_scratch |= (crtc << 20);
2623         }
2624         if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
2625                 bios_3_scratch &= ~ATOM_S3_LCD1_CRTC_ACTIVE;
2626                 bios_3_scratch |= (crtc << 17);
2627         }
2628         if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
2629                 bios_3_scratch &= ~ATOM_S3_DFP1_CRTC_ACTIVE;
2630                 bios_3_scratch |= (crtc << 19);
2631         }
2632         if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
2633                 bios_3_scratch &= ~ATOM_S3_DFP2_CRTC_ACTIVE;
2634                 bios_3_scratch |= (crtc << 23);
2635         }
2636         if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
2637                 bios_3_scratch &= ~ATOM_S3_DFP3_CRTC_ACTIVE;
2638                 bios_3_scratch |= (crtc << 25);
2639         }
2640
2641         if (rdev->family >= CHIP_R600)
2642                 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
2643         else
2644                 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
2645 }
2646
2647 void
2648 radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on)
2649 {
2650         struct drm_device *dev = encoder->dev;
2651         struct radeon_device *rdev = dev->dev_private;
2652         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2653         uint32_t bios_2_scratch;
2654
2655         if (rdev->family >= CHIP_R600)
2656                 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
2657         else
2658                 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
2659
2660         if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
2661                 if (on)
2662                         bios_2_scratch &= ~ATOM_S2_TV1_DPMS_STATE;
2663                 else
2664                         bios_2_scratch |= ATOM_S2_TV1_DPMS_STATE;
2665         }
2666         if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
2667                 if (on)
2668                         bios_2_scratch &= ~ATOM_S2_CV_DPMS_STATE;
2669                 else
2670                         bios_2_scratch |= ATOM_S2_CV_DPMS_STATE;
2671         }
2672         if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2673                 if (on)
2674                         bios_2_scratch &= ~ATOM_S2_CRT1_DPMS_STATE;
2675                 else
2676                         bios_2_scratch |= ATOM_S2_CRT1_DPMS_STATE;
2677         }
2678         if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2679                 if (on)
2680                         bios_2_scratch &= ~ATOM_S2_CRT2_DPMS_STATE;
2681                 else
2682                         bios_2_scratch |= ATOM_S2_CRT2_DPMS_STATE;
2683         }
2684         if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
2685                 if (on)
2686                         bios_2_scratch &= ~ATOM_S2_LCD1_DPMS_STATE;
2687                 else
2688                         bios_2_scratch |= ATOM_S2_LCD1_DPMS_STATE;
2689         }
2690         if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
2691                 if (on)
2692                         bios_2_scratch &= ~ATOM_S2_DFP1_DPMS_STATE;
2693                 else
2694                         bios_2_scratch |= ATOM_S2_DFP1_DPMS_STATE;
2695         }
2696         if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
2697                 if (on)
2698                         bios_2_scratch &= ~ATOM_S2_DFP2_DPMS_STATE;
2699                 else
2700                         bios_2_scratch |= ATOM_S2_DFP2_DPMS_STATE;
2701         }
2702         if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
2703                 if (on)
2704                         bios_2_scratch &= ~ATOM_S2_DFP3_DPMS_STATE;
2705                 else
2706                         bios_2_scratch |= ATOM_S2_DFP3_DPMS_STATE;
2707         }
2708         if (radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) {
2709                 if (on)
2710                         bios_2_scratch &= ~ATOM_S2_DFP4_DPMS_STATE;
2711                 else
2712                         bios_2_scratch |= ATOM_S2_DFP4_DPMS_STATE;
2713         }
2714         if (radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) {
2715                 if (on)
2716                         bios_2_scratch &= ~ATOM_S2_DFP5_DPMS_STATE;
2717                 else
2718                         bios_2_scratch |= ATOM_S2_DFP5_DPMS_STATE;
2719         }
2720
2721         if (rdev->family >= CHIP_R600)
2722                 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
2723         else
2724                 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
2725 }