drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/cpufreq.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include "drmP.h"
  36 #include "intel_drv.h"
  37 #include "i915_drm.h"
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include "drm_dp_helper.h"
  41 #include "drm_crtc_helper.h"
  42 #include <linux/dma_remapping.h>
  43
  44 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
  45
  46 bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
  47 static void intel_update_watermarks(struct drm_device *dev);
  48 static void intel_increase_pllclock(struct drm_crtc *crtc);
  49 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  50
  51 typedef struct {
  52         /* given values */
  53         int n;
  54         int m1, m2;
  55         int p1, p2;
  56         /* derived values */
  57         int     dot;
  58         int     vco;
  59         int     m;
  60         int     p;
  61 } intel_clock_t;
  62
  63 typedef struct {
  64         int     min, max;
  65 } intel_range_t;
  66
  67 typedef struct {
  68         int     dot_limit;
  69         int     p2_slow, p2_fast;
  70 } intel_p2_t;
  71
  72 #define INTEL_P2_NUM                  2
  73 typedef struct intel_limit intel_limit_t;
  74 struct intel_limit {
  75         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  76         intel_p2_t          p2;
  77         bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
  78                         int, int, intel_clock_t *);
  79 };
  80
  81 /* FDI */
  82 #define IRONLAKE_FDI_FREQ               2700000 /* in kHz for mode->clock */
  83
  84 static bool
  85 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  86                     int target, int refclk, intel_clock_t *best_clock);
  87 static bool
  88 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  89                         int target, int refclk, intel_clock_t *best_clock);
  90
  91 static bool
  92 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
  93                       int target, int refclk, intel_clock_t *best_clock);
  94 static bool
  95 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
  96                            int target, int refclk, intel_clock_t *best_clock);
  97
  98 static inline u32 /* units of 100MHz */
  99 intel_fdi_link_freq(struct drm_device *dev)
 100 {
 101         if (IS_GEN5(dev)) {
 102                 struct drm_i915_private *dev_priv = dev->dev_private;
 103                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
 104         } else
 105                 return 27;
 106 }
 107
 108 static const intel_limit_t intel_limits_i8xx_dvo = {
 109         .dot = { .min = 25000, .max = 350000 },
 110         .vco = { .min = 930000, .max = 1400000 },
 111         .n = { .min = 3, .max = 16 },
 112         .m = { .min = 96, .max = 140 },
 113         .m1 = { .min = 18, .max = 26 },
 114         .m2 = { .min = 6, .max = 16 },
 115         .p = { .min = 4, .max = 128 },
 116         .p1 = { .min = 2, .max = 33 },
 117         .p2 = { .dot_limit = 165000,
 118                 .p2_slow = 4, .p2_fast = 2 },
 119         .find_pll = intel_find_best_PLL,
 120 };
 121
 122 static const intel_limit_t intel_limits_i8xx_lvds = {
 123         .dot = { .min = 25000, .max = 350000 },
 124         .vco = { .min = 930000, .max = 1400000 },
 125         .n = { .min = 3, .max = 16 },
 126         .m = { .min = 96, .max = 140 },
 127         .m1 = { .min = 18, .max = 26 },
 128         .m2 = { .min = 6, .max = 16 },
 129         .p = { .min = 4, .max = 128 },
 130         .p1 = { .min = 1, .max = 6 },
 131         .p2 = { .dot_limit = 165000,
 132                 .p2_slow = 14, .p2_fast = 7 },
 133         .find_pll = intel_find_best_PLL,
 134 };
 135
 136 static const intel_limit_t intel_limits_i9xx_sdvo = {
 137         .dot = { .min = 20000, .max = 400000 },
 138         .vco = { .min = 1400000, .max = 2800000 },
 139         .n = { .min = 1, .max = 6 },
 140         .m = { .min = 70, .max = 120 },
 141         .m1 = { .min = 10, .max = 22 },
 142         .m2 = { .min = 5, .max = 9 },
 143         .p = { .min = 5, .max = 80 },
 144         .p1 = { .min = 1, .max = 8 },
 145         .p2 = { .dot_limit = 200000,
 146                 .p2_slow = 10, .p2_fast = 5 },
 147         .find_pll = intel_find_best_PLL,
 148 };
 149
 150 static const intel_limit_t intel_limits_i9xx_lvds = {
 151         .dot = { .min = 20000, .max = 400000 },
 152         .vco = { .min = 1400000, .max = 2800000 },
 153         .n = { .min = 1, .max = 6 },
 154         .m = { .min = 70, .max = 120 },
 155         .m1 = { .min = 10, .max = 22 },
 156         .m2 = { .min = 5, .max = 9 },
 157         .p = { .min = 7, .max = 98 },
 158         .p1 = { .min = 1, .max = 8 },
 159         .p2 = { .dot_limit = 112000,
 160                 .p2_slow = 14, .p2_fast = 7 },
 161         .find_pll = intel_find_best_PLL,
 162 };
 163
 164
 165 static const intel_limit_t intel_limits_g4x_sdvo = {
 166         .dot = { .min = 25000, .max = 270000 },
 167         .vco = { .min = 1750000, .max = 3500000},
 168         .n = { .min = 1, .max = 4 },
 169         .m = { .min = 104, .max = 138 },
 170         .m1 = { .min = 17, .max = 23 },
 171         .m2 = { .min = 5, .max = 11 },
 172         .p = { .min = 10, .max = 30 },
 173         .p1 = { .min = 1, .max = 3},
 174         .p2 = { .dot_limit = 270000,
 175                 .p2_slow = 10,
 176                 .p2_fast = 10
 177         },
 178         .find_pll = intel_g4x_find_best_PLL,
 179 };
 180
 181 static const intel_limit_t intel_limits_g4x_hdmi = {
 182         .dot = { .min = 22000, .max = 400000 },
 183         .vco = { .min = 1750000, .max = 3500000},
 184         .n = { .min = 1, .max = 4 },
 185         .m = { .min = 104, .max = 138 },
 186         .m1 = { .min = 16, .max = 23 },
 187         .m2 = { .min = 5, .max = 11 },
 188         .p = { .min = 5, .max = 80 },
 189         .p1 = { .min = 1, .max = 8},
 190         .p2 = { .dot_limit = 165000,
 191                 .p2_slow = 10, .p2_fast = 5 },
 192         .find_pll = intel_g4x_find_best_PLL,
 193 };
 194
 195 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 196         .dot = { .min = 20000, .max = 115000 },
 197         .vco = { .min = 1750000, .max = 3500000 },
 198         .n = { .min = 1, .max = 3 },
 199         .m = { .min = 104, .max = 138 },
 200         .m1 = { .min = 17, .max = 23 },
 201         .m2 = { .min = 5, .max = 11 },
 202         .p = { .min = 28, .max = 112 },
 203         .p1 = { .min = 2, .max = 8 },
 204         .p2 = { .dot_limit = 0,
 205                 .p2_slow = 14, .p2_fast = 14
 206         },
 207         .find_pll = intel_g4x_find_best_PLL,
 208 };
 209
 210 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 211         .dot = { .min = 80000, .max = 224000 },
 212         .vco = { .min = 1750000, .max = 3500000 },
 213         .n = { .min = 1, .max = 3 },
 214         .m = { .min = 104, .max = 138 },
 215         .m1 = { .min = 17, .max = 23 },
 216         .m2 = { .min = 5, .max = 11 },
 217         .p = { .min = 14, .max = 42 },
 218         .p1 = { .min = 2, .max = 6 },
 219         .p2 = { .dot_limit = 0,
 220                 .p2_slow = 7, .p2_fast = 7
 221         },
 222         .find_pll = intel_g4x_find_best_PLL,
 223 };
 224
 225 static const intel_limit_t intel_limits_g4x_display_port = {
 226         .dot = { .min = 161670, .max = 227000 },
 227         .vco = { .min = 1750000, .max = 3500000},
 228         .n = { .min = 1, .max = 2 },
 229         .m = { .min = 97, .max = 108 },
 230         .m1 = { .min = 0x10, .max = 0x12 },
 231         .m2 = { .min = 0x05, .max = 0x06 },
 232         .p = { .min = 10, .max = 20 },
 233         .p1 = { .min = 1, .max = 2},
 234         .p2 = { .dot_limit = 0,
 235                 .p2_slow = 10, .p2_fast = 10 },
 236         .find_pll = intel_find_pll_g4x_dp,
 237 };
 238
 239 static const intel_limit_t intel_limits_pineview_sdvo = {
 240         .dot = { .min = 20000, .max = 400000},
 241         .vco = { .min = 1700000, .max = 3500000 },
 242         /* Pineview's Ncounter is a ring counter */
 243         .n = { .min = 3, .max = 6 },
 244         .m = { .min = 2, .max = 256 },
 245         /* Pineview only has one combined m divider, which we treat as m2. */
 246         .m1 = { .min = 0, .max = 0 },
 247         .m2 = { .min = 0, .max = 254 },
 248         .p = { .min = 5, .max = 80 },
 249         .p1 = { .min = 1, .max = 8 },
 250         .p2 = { .dot_limit = 200000,
 251                 .p2_slow = 10, .p2_fast = 5 },
 252         .find_pll = intel_find_best_PLL,
 253 };
 254
 255 static const intel_limit_t intel_limits_pineview_lvds = {
 256         .dot = { .min = 20000, .max = 400000 },
 257         .vco = { .min = 1700000, .max = 3500000 },
 258         .n = { .min = 3, .max = 6 },
 259         .m = { .min = 2, .max = 256 },
 260         .m1 = { .min = 0, .max = 0 },
 261         .m2 = { .min = 0, .max = 254 },
 262         .p = { .min = 7, .max = 112 },
 263         .p1 = { .min = 1, .max = 8 },
 264         .p2 = { .dot_limit = 112000,
 265                 .p2_slow = 14, .p2_fast = 14 },
 266         .find_pll = intel_find_best_PLL,
 267 };
 268
 269 /* Ironlake / Sandybridge
 270  *
 271  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 272  * the range value for them is (actual_value - 2).
 273  */
 274 static const intel_limit_t intel_limits_ironlake_dac = {
 275         .dot = { .min = 25000, .max = 350000 },
 276         .vco = { .min = 1760000, .max = 3510000 },
 277         .n = { .min = 1, .max = 5 },
 278         .m = { .min = 79, .max = 127 },
 279         .m1 = { .min = 12, .max = 22 },
 280         .m2 = { .min = 5, .max = 9 },
 281         .p = { .min = 5, .max = 80 },
 282         .p1 = { .min = 1, .max = 8 },
 283         .p2 = { .dot_limit = 225000,
 284                 .p2_slow = 10, .p2_fast = 5 },
 285         .find_pll = intel_g4x_find_best_PLL,
 286 };
 287
 288 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 289         .dot = { .min = 25000, .max = 350000 },
 290         .vco = { .min = 1760000, .max = 3510000 },
 291         .n = { .min = 1, .max = 3 },
 292         .m = { .min = 79, .max = 118 },
 293         .m1 = { .min = 12, .max = 22 },
 294         .m2 = { .min = 5, .max = 9 },
 295         .p = { .min = 28, .max = 112 },
 296         .p1 = { .min = 2, .max = 8 },
 297         .p2 = { .dot_limit = 225000,
 298                 .p2_slow = 14, .p2_fast = 14 },
 299         .find_pll = intel_g4x_find_best_PLL,
 300 };
 301
 302 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 303         .dot = { .min = 25000, .max = 350000 },
 304         .vco = { .min = 1760000, .max = 3510000 },
 305         .n = { .min = 1, .max = 3 },
 306         .m = { .min = 79, .max = 127 },
 307         .m1 = { .min = 12, .max = 22 },
 308         .m2 = { .min = 5, .max = 9 },
 309         .p = { .min = 14, .max = 56 },
 310         .p1 = { .min = 2, .max = 8 },
 311         .p2 = { .dot_limit = 225000,
 312                 .p2_slow = 7, .p2_fast = 7 },
 313         .find_pll = intel_g4x_find_best_PLL,
 314 };
 315
 316 /* LVDS 100mhz refclk limits. */
 317 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 318         .dot = { .min = 25000, .max = 350000 },
 319         .vco = { .min = 1760000, .max = 3510000 },
 320         .n = { .min = 1, .max = 2 },
 321         .m = { .min = 79, .max = 126 },
 322         .m1 = { .min = 12, .max = 22 },
 323         .m2 = { .min = 5, .max = 9 },
 324         .p = { .min = 28, .max = 112 },
 325         .p1 = { .min = 2, .max = 8 },
 326         .p2 = { .dot_limit = 225000,
 327                 .p2_slow = 14, .p2_fast = 14 },
 328         .find_pll = intel_g4x_find_best_PLL,
 329 };
 330
 331 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 332         .dot = { .min = 25000, .max = 350000 },
 333         .vco = { .min = 1760000, .max = 3510000 },
 334         .n = { .min = 1, .max = 3 },
 335         .m = { .min = 79, .max = 126 },
 336         .m1 = { .min = 12, .max = 22 },
 337         .m2 = { .min = 5, .max = 9 },
 338         .p = { .min = 14, .max = 42 },
 339         .p1 = { .min = 2, .max = 6 },
 340         .p2 = { .dot_limit = 225000,
 341                 .p2_slow = 7, .p2_fast = 7 },
 342         .find_pll = intel_g4x_find_best_PLL,
 343 };
 344
 345 static const intel_limit_t intel_limits_ironlake_display_port = {
 346         .dot = { .min = 25000, .max = 350000 },
 347         .vco = { .min = 1760000, .max = 3510000},
 348         .n = { .min = 1, .max = 2 },
 349         .m = { .min = 81, .max = 90 },
 350         .m1 = { .min = 12, .max = 22 },
 351         .m2 = { .min = 5, .max = 9 },
 352         .p = { .min = 10, .max = 20 },
 353         .p1 = { .min = 1, .max = 2},
 354         .p2 = { .dot_limit = 0,
 355                 .p2_slow = 10, .p2_fast = 10 },
 356         .find_pll = intel_find_pll_ironlake_dp,
 357 };
 358
 359 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
 360                                                 int refclk)
 361 {
 362         struct drm_device *dev = crtc->dev;
 363         struct drm_i915_private *dev_priv = dev->dev_private;
 364         const intel_limit_t *limit;
 365
 366         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 367                 if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
 368                     LVDS_CLKB_POWER_UP) {
 369                         /* LVDS dual channel */
 370                         if (refclk == 100000)
 371                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 372                         else
 373                                 limit = &intel_limits_ironlake_dual_lvds;
 374                 } else {
 375                         if (refclk == 100000)
 376                                 limit = &intel_limits_ironlake_single_lvds_100m;
 377                         else
 378                                 limit = &intel_limits_ironlake_single_lvds;
 379                 }
 380         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
 381                         HAS_eDP)
 382                 limit = &intel_limits_ironlake_display_port;
 383         else
 384                 limit = &intel_limits_ironlake_dac;
 385
 386         return limit;
 387 }
 388
 389 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 390 {
 391         struct drm_device *dev = crtc->dev;
 392         struct drm_i915_private *dev_priv = dev->dev_private;
 393         const intel_limit_t *limit;
 394
 395         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 396                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 397                     LVDS_CLKB_POWER_UP)
 398                         /* LVDS with dual channel */
 399                         limit = &intel_limits_g4x_dual_channel_lvds;
 400                 else
 401                         /* LVDS with dual channel */
 402                         limit = &intel_limits_g4x_single_channel_lvds;
 403         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 404                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 405                 limit = &intel_limits_g4x_hdmi;
 406         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 407                 limit = &intel_limits_g4x_sdvo;
 408         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
 409                 limit = &intel_limits_g4x_display_port;
 410         } else /* The option is for other outputs */
 411                 limit = &intel_limits_i9xx_sdvo;
 412
 413         return limit;
 414 }
 415
 416 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
 417 {
 418         struct drm_device *dev = crtc->dev;
 419         const intel_limit_t *limit;
 420
 421         if (HAS_PCH_SPLIT(dev))
 422                 limit = intel_ironlake_limit(crtc, refclk);
 423         else if (IS_G4X(dev)) {
 424                 limit = intel_g4x_limit(crtc);
 425         } else if (IS_PINEVIEW(dev)) {
 426                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 427                         limit = &intel_limits_pineview_lvds;
 428                 else
 429                         limit = &intel_limits_pineview_sdvo;
 430         } else if (!IS_GEN2(dev)) {
 431                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 432                         limit = &intel_limits_i9xx_lvds;
 433                 else
 434                         limit = &intel_limits_i9xx_sdvo;
 435         } else {
 436                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 437                         limit = &intel_limits_i8xx_lvds;
 438                 else
 439                         limit = &intel_limits_i8xx_dvo;
 440         }
 441         return limit;
 442 }
 443
 444 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 445 static void pineview_clock(int refclk, intel_clock_t *clock)
 446 {
 447         clock->m = clock->m2 + 2;
 448         clock->p = clock->p1 * clock->p2;
 449         clock->vco = refclk * clock->m / clock->n;
 450         clock->dot = clock->vco / clock->p;
 451 }
 452
 453 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
 454 {
 455         if (IS_PINEVIEW(dev)) {
 456                 pineview_clock(refclk, clock);
 457                 return;
 458         }
 459         clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
 460         clock->p = clock->p1 * clock->p2;
 461         clock->vco = refclk * clock->m / (clock->n + 2);
 462         clock->dot = clock->vco / clock->p;
 463 }
 464
 465 /**
 466  * Returns whether any output on the specified pipe is of the specified type
 467  */
 468 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
 469 {
 470         struct drm_device *dev = crtc->dev;
 471         struct drm_mode_config *mode_config = &dev->mode_config;
 472         struct intel_encoder *encoder;
 473
 474         list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
 475                 if (encoder->base.crtc == crtc && encoder->type == type)
 476                         return true;
 477
 478         return false;
 479 }
 480
 481 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 482 /**
 483  * Returns whether the given set of divisors are valid for a given refclk with
 484  * the given connectors.
 485  */
 486
 487 static bool intel_PLL_is_valid(struct drm_device *dev,
 488                                const intel_limit_t *limit,
 489                                const intel_clock_t *clock)
 490 {
 491         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 492                 INTELPllInvalid("p1 out of range\n");
 493         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
 494                 INTELPllInvalid("p out of range\n");
 495         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 496                 INTELPllInvalid("m2 out of range\n");
 497         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 498                 INTELPllInvalid("m1 out of range\n");
 499         if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
 500                 INTELPllInvalid("m1 <= m2\n");
 501         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
 502                 INTELPllInvalid("m out of range\n");
 503         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 504                 INTELPllInvalid("n out of range\n");
 505         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 506                 INTELPllInvalid("vco out of range\n");
 507         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 508          * connector, etc., rather than just a single range.
 509          */
 510         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 511                 INTELPllInvalid("dot out of range\n");
 512
 513         return true;
 514 }
 515
 516 static bool
 517 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 518                     int target, int refclk, intel_clock_t *best_clock)
 519
 520 {
 521         struct drm_device *dev = crtc->dev;
 522         struct drm_i915_private *dev_priv = dev->dev_private;
 523         intel_clock_t clock;
 524         int err = target;
 525
 526         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
 527             (I915_READ(LVDS)) != 0) {
 528                 /*
 529                  * For LVDS, if the panel is on, just rely on its current
 530                  * settings for dual-channel.  We haven't figured out how to
 531                  * reliably set up different single/dual channel state, if we
 532                  * even can.
 533                  */
 534                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 535                     LVDS_CLKB_POWER_UP)
 536                         clock.p2 = limit->p2.p2_fast;
 537                 else
 538                         clock.p2 = limit->p2.p2_slow;
 539         } else {
 540                 if (target < limit->p2.dot_limit)
 541                         clock.p2 = limit->p2.p2_slow;
 542                 else
 543                         clock.p2 = limit->p2.p2_fast;
 544         }
 545
 546         memset(best_clock, 0, sizeof(*best_clock));
 547
 548         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 549              clock.m1++) {
 550                 for (clock.m2 = limit->m2.min;
 551                      clock.m2 <= limit->m2.max; clock.m2++) {
 552                         /* m1 is always 0 in Pineview */
 553                         if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
 554                                 break;
 555                         for (clock.n = limit->n.min;
 556                              clock.n <= limit->n.max; clock.n++) {
 557                                 for (clock.p1 = limit->p1.min;
 558                                         clock.p1 <= limit->p1.max; clock.p1++) {
 559                                         int this_err;
 560
 561                                         intel_clock(dev, refclk, &clock);
 562                                         if (!intel_PLL_is_valid(dev, limit,
 563                                                                 &clock))
 564                                                 continue;
 565
 566                                         this_err = abs(clock.dot - target);
 567                                         if (this_err < err) {
 568                                                 *best_clock = clock;
 569                                                 err = this_err;
 570                                         }
 571                                 }
 572                         }
 573                 }
 574         }
 575
 576         return (err != target);
 577 }
 578
 579 static bool
 580 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 581                         int target, int refclk, intel_clock_t *best_clock)
 582 {
 583         struct drm_device *dev = crtc->dev;
 584         struct drm_i915_private *dev_priv = dev->dev_private;
 585         intel_clock_t clock;
 586         int max_n;
 587         bool found;
 588         /* approximately equals target * 0.00585 */
 589         int err_most = (target >> 8) + (target >> 9);
 590         found = false;
 591
 592         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 593                 int lvds_reg;
 594
 595                 if (HAS_PCH_SPLIT(dev))
 596                         lvds_reg = PCH_LVDS;
 597                 else
 598                         lvds_reg = LVDS;
 599                 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
 600                     LVDS_CLKB_POWER_UP)
 601                         clock.p2 = limit->p2.p2_fast;
 602                 else
 603                         clock.p2 = limit->p2.p2_slow;
 604         } else {
 605                 if (target < limit->p2.dot_limit)
 606                         clock.p2 = limit->p2.p2_slow;
 607                 else
 608                         clock.p2 = limit->p2.p2_fast;
 609         }
 610
 611         memset(best_clock, 0, sizeof(*best_clock));
 612         max_n = limit->n.max;
 613         /* based on hardware requirement, prefer smaller n to precision */
 614         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 615                 /* based on hardware requirement, prefere larger m1,m2 */
 616                 for (clock.m1 = limit->m1.max;
 617                      clock.m1 >= limit->m1.min; clock.m1--) {
 618                         for (clock.m2 = limit->m2.max;
 619                              clock.m2 >= limit->m2.min; clock.m2--) {
 620                                 for (clock.p1 = limit->p1.max;
 621                                      clock.p1 >= limit->p1.min; clock.p1--) {
 622                                         int this_err;
 623
 624                                         intel_clock(dev, refclk, &clock);
 625                                         if (!intel_PLL_is_valid(dev, limit,
 626                                                                 &clock))
 627                                                 continue;
 628
 629                                         this_err = abs(clock.dot - target);
 630                                         if (this_err < err_most) {
 631                                                 *best_clock = clock;
 632                                                 err_most = this_err;
 633                                                 max_n = clock.n;
 634                                                 found = true;
 635                                         }
 636                                 }
 637                         }
 638                 }
 639         }
 640         return found;
 641 }
 642
 643 static bool
 644 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 645                            int target, int refclk, intel_clock_t *best_clock)
 646 {
 647         struct drm_device *dev = crtc->dev;
 648         intel_clock_t clock;
 649
 650         if (target < 200000) {
 651                 clock.n = 1;
 652                 clock.p1 = 2;
 653                 clock.p2 = 10;
 654                 clock.m1 = 12;
 655                 clock.m2 = 9;
 656         } else {
 657                 clock.n = 2;
 658                 clock.p1 = 1;
 659                 clock.p2 = 10;
 660                 clock.m1 = 14;
 661                 clock.m2 = 8;
 662         }
 663         intel_clock(dev, refclk, &clock);
 664         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 665         return true;
 666 }
 667
 668 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
 669 static bool
 670 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 671                       int target, int refclk, intel_clock_t *best_clock)
 672 {
 673         intel_clock_t clock;
 674         if (target < 200000) {
 675                 clock.p1 = 2;
 676                 clock.p2 = 10;
 677                 clock.n = 2;
 678                 clock.m1 = 23;
 679                 clock.m2 = 8;
 680         } else {
 681                 clock.p1 = 1;
 682                 clock.p2 = 10;
 683                 clock.n = 1;
 684                 clock.m1 = 14;
 685                 clock.m2 = 2;
 686         }
 687         clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
 688         clock.p = (clock.p1 * clock.p2);
 689         clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
 690         clock.vco = 0;
 691         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 692         return true;
 693 }
 694
 695 /**
 696  * intel_wait_for_vblank - wait for vblank on a given pipe
 697  * @dev: drm device
 698  * @pipe: pipe to wait for
 699  *
 700  * Wait for vblank to occur on a given pipe.  Needed for various bits of
 701  * mode setting code.
 702  */
 703 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
 704 {
 705         struct drm_i915_private *dev_priv = dev->dev_private;
 706         int pipestat_reg = PIPESTAT(pipe);
 707
 708         /* Clear existing vblank status. Note this will clear any other
 709          * sticky status fields as well.
 710          *
 711          * This races with i915_driver_irq_handler() with the result
 712          * that either function could miss a vblank event.  Here it is not
 713          * fatal, as we will either wait upon the next vblank interrupt or
 714          * timeout.  Generally speaking intel_wait_for_vblank() is only
 715          * called during modeset at which time the GPU should be idle and
 716          * should *not* be performing page flips and thus not waiting on
 717          * vblanks...
 718          * Currently, the result of us stealing a vblank from the irq
 719          * handler is that a single frame will be skipped during swapbuffers.
 720          */
 721         I915_WRITE(pipestat_reg,
 722                    I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
 723
 724         /* Wait for vblank interrupt bit to set */
 725         if (wait_for(I915_READ(pipestat_reg) &
 726                      PIPE_VBLANK_INTERRUPT_STATUS,
 727                      50))
 728                 DRM_DEBUG_KMS("vblank wait timed out\n");
 729 }
 730
 731 /*
 732  * intel_wait_for_pipe_off - wait for pipe to turn off
 733  * @dev: drm device
 734  * @pipe: pipe to wait for
 735  *
 736  * After disabling a pipe, we can't wait for vblank in the usual way,
 737  * spinning on the vblank interrupt status bit, since we won't actually
 738  * see an interrupt when the pipe is disabled.
 739  *
 740  * On Gen4 and above:
 741  *   wait for the pipe register state bit to turn off
 742  *
 743  * Otherwise:
 744  *   wait for the display line value to settle (it usually
 745  *   ends up stopping at the start of the next frame).
 746  *
 747  */
 748 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
 749 {
 750         struct drm_i915_private *dev_priv = dev->dev_private;
 751
 752         if (INTEL_INFO(dev)->gen >= 4) {
 753                 int reg = PIPECONF(pipe);
 754
 755                 /* Wait for the Pipe State to go off */
 756                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
 757                              100))
 758                         DRM_DEBUG_KMS("pipe_off wait timed out\n");
 759         } else {
 760                 u32 last_line;
 761                 int reg = PIPEDSL(pipe);
 762                 unsigned long timeout = jiffies + msecs_to_jiffies(100);
 763
 764                 /* Wait for the display line to settle */
 765                 do {
 766                         last_line = I915_READ(reg) & DSL_LINEMASK;
 767                         mdelay(5);
 768                 } while (((I915_READ(reg) & DSL_LINEMASK) != last_line) &&
 769                          time_after(timeout, jiffies));
 770                 if (time_after(jiffies, timeout))
 771                         DRM_DEBUG_KMS("pipe_off wait timed out\n");
 772         }
 773 }
 774
 775 static const char *state_string(bool enabled)
 776 {
 777         return enabled ? "on" : "off";
 778 }
 779
 780 /* Only for pre-ILK configs */
 781 static void assert_pll(struct drm_i915_private *dev_priv,
 782                        enum pipe pipe, bool state)
 783 {
 784         int reg;
 785         u32 val;
 786         bool cur_state;
 787
 788         reg = DPLL(pipe);
 789         val = I915_READ(reg);
 790         cur_state = !!(val & DPLL_VCO_ENABLE);
 791         WARN(cur_state != state,
 792              "PLL state assertion failure (expected %s, current %s)\n",
 793              state_string(state), state_string(cur_state));
 794 }
 795 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
 796 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
 797
 798 /* For ILK+ */
 799 static void assert_pch_pll(struct drm_i915_private *dev_priv,
 800                            enum pipe pipe, bool state)
 801 {
 802         int reg;
 803         u32 val;
 804         bool cur_state;
 805
 806         if (HAS_PCH_CPT(dev_priv->dev)) {
 807                 u32 pch_dpll;
 808
 809                 pch_dpll = I915_READ(PCH_DPLL_SEL);
 810
 811                 /* Make sure the selected PLL is enabled to the transcoder */
 812                 WARN(!((pch_dpll >> (4 * pipe)) & 8),
 813                      "transcoder %d PLL not enabled\n", pipe);
 814
 815                 /* Convert the transcoder pipe number to a pll pipe number */
 816                 pipe = (pch_dpll >> (4 * pipe)) & 1;
 817         }
 818
 819         reg = PCH_DPLL(pipe);
 820         val = I915_READ(reg);
 821         cur_state = !!(val & DPLL_VCO_ENABLE);
 822         WARN(cur_state != state,
 823              "PCH PLL state assertion failure (expected %s, current %s)\n",
 824              state_string(state), state_string(cur_state));
 825 }
 826 #define assert_pch_pll_enabled(d, p) assert_pch_pll(d, p, true)
 827 #define assert_pch_pll_disabled(d, p) assert_pch_pll(d, p, false)
 828
 829 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
 830                           enum pipe pipe, bool state)
 831 {
 832         int reg;
 833         u32 val;
 834         bool cur_state;
 835
 836         reg = FDI_TX_CTL(pipe);
 837         val = I915_READ(reg);
 838         cur_state = !!(val & FDI_TX_ENABLE);
 839         WARN(cur_state != state,
 840              "FDI TX state assertion failure (expected %s, current %s)\n",
 841              state_string(state), state_string(cur_state));
 842 }
 843 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
 844 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
 845
 846 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
 847                           enum pipe pipe, bool state)
 848 {
 849         int reg;
 850         u32 val;
 851         bool cur_state;
 852
 853         reg = FDI_RX_CTL(pipe);
 854         val = I915_READ(reg);
 855         cur_state = !!(val & FDI_RX_ENABLE);
 856         WARN(cur_state != state,
 857              "FDI RX state assertion failure (expected %s, current %s)\n",
 858              state_string(state), state_string(cur_state));
 859 }
 860 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
 861 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
 862
 863 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
 864                                       enum pipe pipe)
 865 {
 866         int reg;
 867         u32 val;
 868
 869         /* ILK FDI PLL is always enabled */
 870         if (dev_priv->info->gen == 5)
 871                 return;
 872
 873         reg = FDI_TX_CTL(pipe);
 874         val = I915_READ(reg);
 875         WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
 876 }
 877
 878 static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
 879                                       enum pipe pipe)
 880 {
 881         int reg;
 882         u32 val;
 883
 884         reg = FDI_RX_CTL(pipe);
 885         val = I915_READ(reg);
 886         WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
 887 }
 888
 889 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
 890                                   enum pipe pipe)
 891 {
 892         int pp_reg, lvds_reg;
 893         u32 val;
 894         enum pipe panel_pipe = PIPE_A;
 895         bool locked = true;
 896
 897         if (HAS_PCH_SPLIT(dev_priv->dev)) {
 898                 pp_reg = PCH_PP_CONTROL;
 899                 lvds_reg = PCH_LVDS;
 900         } else {
 901                 pp_reg = PP_CONTROL;
 902                 lvds_reg = LVDS;
 903         }
 904
 905         val = I915_READ(pp_reg);
 906         if (!(val & PANEL_POWER_ON) ||
 907             ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
 908                 locked = false;
 909
 910         if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
 911                 panel_pipe = PIPE_B;
 912
 913         WARN(panel_pipe == pipe && locked,
 914              "panel assertion failure, pipe %c regs locked\n",
 915              pipe_name(pipe));
 916 }
 917
 918 static void assert_pipe(struct drm_i915_private *dev_priv,
 919                         enum pipe pipe, bool state)
 920 {
 921         int reg;
 922         u32 val;
 923         bool cur_state;
 924
 925         reg = PIPECONF(pipe);
 926         val = I915_READ(reg);
 927         cur_state = !!(val & PIPECONF_ENABLE);
 928         WARN(cur_state != state,
 929              "pipe %c assertion failure (expected %s, current %s)\n",
 930              pipe_name(pipe), state_string(state), state_string(cur_state));
 931 }
 932 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
 933 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
 934
 935 static void assert_plane_enabled(struct drm_i915_private *dev_priv,
 936                                  enum plane plane)
 937 {
 938         int reg;
 939         u32 val;
 940
 941         reg = DSPCNTR(plane);
 942         val = I915_READ(reg);
 943         WARN(!(val & DISPLAY_PLANE_ENABLE),
 944              "plane %c assertion failure, should be active but is disabled\n",
 945              plane_name(plane));
 946 }
 947
 948 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
 949                                    enum pipe pipe)
 950 {
 951         int reg, i;
 952         u32 val;
 953         int cur_pipe;
 954
 955         /* Planes are fixed to pipes on ILK+ */
 956         if (HAS_PCH_SPLIT(dev_priv->dev))
 957                 return;
 958
 959         /* Need to check both planes against the pipe */
 960         for (i = 0; i < 2; i++) {
 961                 reg = DSPCNTR(i);
 962                 val = I915_READ(reg);
 963                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
 964                         DISPPLANE_SEL_PIPE_SHIFT;
 965                 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
 966                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
 967                      plane_name(i), pipe_name(pipe));
 968         }
 969 }
 970
 971 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
 972 {
 973         u32 val;
 974         bool enabled;
 975
 976         val = I915_READ(PCH_DREF_CONTROL);
 977         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
 978                             DREF_SUPERSPREAD_SOURCE_MASK));
 979         WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
 980 }
 981
 982 static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
 983                                        enum pipe pipe)
 984 {
 985         int reg;
 986         u32 val;
 987         bool enabled;
 988
 989         reg = TRANSCONF(pipe);
 990         val = I915_READ(reg);
 991         enabled = !!(val & TRANS_ENABLE);
 992         WARN(enabled,
 993              "transcoder assertion failed, should be off on pipe %c but is still active\n",
 994              pipe_name(pipe));
 995 }
 996
 997 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
 998                             enum pipe pipe, u32 port_sel, u32 val)
 999 {
1000         if ((val & DP_PORT_EN) == 0)
1001                 return false;
1002
1003         if (HAS_PCH_CPT(dev_priv->dev)) {
1004                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1005                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1006                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1007                         return false;
1008         } else {
1009                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1010                         return false;
1011         }
1012         return true;
1013 }
1014
1015 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1016                               enum pipe pipe, u32 val)
1017 {
1018         if ((val & PORT_ENABLE) == 0)
1019                 return false;
1020
1021         if (HAS_PCH_CPT(dev_priv->dev)) {
1022                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1023                         return false;
1024         } else {
1025                 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1026                         return false;
1027         }
1028         return true;
1029 }
1030
1031 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1032                               enum pipe pipe, u32 val)
1033 {
1034         if ((val & LVDS_PORT_EN) == 0)
1035                 return false;
1036
1037         if (HAS_PCH_CPT(dev_priv->dev)) {
1038                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1039                         return false;
1040         } else {
1041                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1042                         return false;
1043         }
1044         return true;
1045 }
1046
1047 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1048                               enum pipe pipe, u32 val)
1049 {
1050         if ((val & ADPA_DAC_ENABLE) == 0)
1051                 return false;
1052         if (HAS_PCH_CPT(dev_priv->dev)) {
1053                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1054                         return false;
1055         } else {
1056                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1057                         return false;
1058         }
1059         return true;
1060 }
1061
1062 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1063                                    enum pipe pipe, int reg, u32 port_sel)
1064 {
1065         u32 val = I915_READ(reg);
1066         WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1067              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1068              reg, pipe_name(pipe));
1069 }
1070
1071 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1072                                      enum pipe pipe, int reg)
1073 {
1074         u32 val = I915_READ(reg);
1075         WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1076              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1077              reg, pipe_name(pipe));
1078 }
1079
1080 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1081                                       enum pipe pipe)
1082 {
1083         int reg;
1084         u32 val;
1085
1086         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1087         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1088         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1089
1090         reg = PCH_ADPA;
1091         val = I915_READ(reg);
1092         WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1093              "PCH VGA enabled on transcoder %c, should be disabled\n",
1094              pipe_name(pipe));
1095
1096         reg = PCH_LVDS;
1097         val = I915_READ(reg);
1098         WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1099              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1100              pipe_name(pipe));
1101
1102         assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1103         assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1104         assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1105 }
1106
1107 /**
1108  * intel_enable_pll - enable a PLL
1109  * @dev_priv: i915 private structure
1110  * @pipe: pipe PLL to enable
1111  *
1112  * Enable @pipe's PLL so we can start pumping pixels from a plane.  Check to
1113  * make sure the PLL reg is writable first though, since the panel write
1114  * protect mechanism may be enabled.
1115  *
1116  * Note!  This is for pre-ILK only.
1117  */
1118 static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1119 {
1120         int reg;
1121         u32 val;
1122
1123         /* No really, not for ILK+ */
1124         BUG_ON(dev_priv->info->gen >= 5);
1125
1126         /* PLL is protected by panel, make sure we can write it */
1127         if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1128                 assert_panel_unlocked(dev_priv, pipe);
1129
1130         reg = DPLL(pipe);
1131         val = I915_READ(reg);
1132         val |= DPLL_VCO_ENABLE;
1133
1134         /* We do this three times for luck */
1135         I915_WRITE(reg, val);
1136         POSTING_READ(reg);
1137         udelay(150); /* wait for warmup */
1138         I915_WRITE(reg, val);
1139         POSTING_READ(reg);
1140         udelay(150); /* wait for warmup */
1141         I915_WRITE(reg, val);
1142         POSTING_READ(reg);
1143         udelay(150); /* wait for warmup */
1144 }
1145
1146 /**
1147  * intel_disable_pll - disable a PLL
1148  * @dev_priv: i915 private structure
1149  * @pipe: pipe PLL to disable
1150  *
1151  * Disable the PLL for @pipe, making sure the pipe is off first.
1152  *
1153  * Note!  This is for pre-ILK only.
1154  */
1155 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1156 {
1157         int reg;
1158         u32 val;
1159
1160         /* Don't disable pipe A or pipe A PLLs if needed */
1161         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1162                 return;
1163
1164         /* Make sure the pipe isn't still relying on us */
1165         assert_pipe_disabled(dev_priv, pipe);
1166
1167         reg = DPLL(pipe);
1168         val = I915_READ(reg);
1169         val &= ~DPLL_VCO_ENABLE;
1170         I915_WRITE(reg, val);
1171         POSTING_READ(reg);
1172 }
1173
1174 /**
1175  * intel_enable_pch_pll - enable PCH PLL
1176  * @dev_priv: i915 private structure
1177  * @pipe: pipe PLL to enable
1178  *
1179  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1180  * drives the transcoder clock.
1181  */
1182 static void intel_enable_pch_pll(struct drm_i915_private *dev_priv,
1183                                  enum pipe pipe)
1184 {
1185         int reg;
1186         u32 val;
1187
1188         if (pipe > 1)
1189                 return;
1190
1191         /* PCH only available on ILK+ */
1192         BUG_ON(dev_priv->info->gen < 5);
1193
1194         /* PCH refclock must be enabled first */
1195         assert_pch_refclk_enabled(dev_priv);
1196
1197         reg = PCH_DPLL(pipe);
1198         val = I915_READ(reg);
1199         val |= DPLL_VCO_ENABLE;
1200         I915_WRITE(reg, val);
1201         POSTING_READ(reg);
1202         udelay(200);
1203 }
1204
1205 static void intel_disable_pch_pll(struct drm_i915_private *dev_priv,
1206                                   enum pipe pipe)
1207 {
1208         int reg;
1209         u32 val;
1210
1211         if (pipe > 1)
1212                 return;
1213
1214         /* PCH only available on ILK+ */
1215         BUG_ON(dev_priv->info->gen < 5);
1216
1217         /* Make sure transcoder isn't still depending on us */
1218         assert_transcoder_disabled(dev_priv, pipe);
1219
1220         reg = PCH_DPLL(pipe);
1221         val = I915_READ(reg);
1222         val &= ~DPLL_VCO_ENABLE;
1223         I915_WRITE(reg, val);
1224         POSTING_READ(reg);
1225         udelay(200);
1226 }
1227
1228 static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
1229                                     enum pipe pipe)
1230 {
1231         int reg;
1232         u32 val;
1233
1234         /* PCH only available on ILK+ */
1235         BUG_ON(dev_priv->info->gen < 5);
1236
1237         /* Make sure PCH DPLL is enabled */
1238         assert_pch_pll_enabled(dev_priv, pipe);
1239
1240         /* FDI must be feeding us bits for PCH ports */
1241         assert_fdi_tx_enabled(dev_priv, pipe);
1242         assert_fdi_rx_enabled(dev_priv, pipe);
1243
1244         reg = TRANSCONF(pipe);
1245         val = I915_READ(reg);
1246
1247         if (HAS_PCH_IBX(dev_priv->dev)) {
1248                 /*
1249                  * make the BPC in transcoder be consistent with
1250                  * that in pipeconf reg.
1251                  */
1252                 val &= ~PIPE_BPC_MASK;
1253                 val |= I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK;
1254         }
1255         I915_WRITE(reg, val | TRANS_ENABLE);
1256         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1257                 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1258 }
1259
1260 static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
1261                                      enum pipe pipe)
1262 {
1263         int reg;
1264         u32 val;
1265
1266         /* FDI relies on the transcoder */
1267         assert_fdi_tx_disabled(dev_priv, pipe);
1268         assert_fdi_rx_disabled(dev_priv, pipe);
1269
1270         /* Ports must be off as well */
1271         assert_pch_ports_disabled(dev_priv, pipe);
1272
1273         reg = TRANSCONF(pipe);
1274         val = I915_READ(reg);
1275         val &= ~TRANS_ENABLE;
1276         I915_WRITE(reg, val);
1277         /* wait for PCH transcoder off, transcoder state */
1278         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1279                 DRM_ERROR("failed to disable transcoder %d\n", pipe);
1280 }
1281
1282 /**
1283  * intel_enable_pipe - enable a pipe, asserting requirements
1284  * @dev_priv: i915 private structure
1285  * @pipe: pipe to enable
1286  * @pch_port: on ILK+, is this pipe driving a PCH port or not
1287  *
1288  * Enable @pipe, making sure that various hardware specific requirements
1289  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1290  *
1291  * @pipe should be %PIPE_A or %PIPE_B.
1292  *
1293  * Will wait until the pipe is actually running (i.e. first vblank) before
1294  * returning.
1295  */
1296 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1297                               bool pch_port)
1298 {
1299         int reg;
1300         u32 val;
1301
1302         /*
1303          * A pipe without a PLL won't actually be able to drive bits from
1304          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1305          * need the check.
1306          */
1307         if (!HAS_PCH_SPLIT(dev_priv->dev))
1308                 assert_pll_enabled(dev_priv, pipe);
1309         else {
1310                 if (pch_port) {
1311                         /* if driving the PCH, we need FDI enabled */
1312                         assert_fdi_rx_pll_enabled(dev_priv, pipe);
1313                         assert_fdi_tx_pll_enabled(dev_priv, pipe);
1314                 }
1315                 /* FIXME: assert CPU port conditions for SNB+ */
1316         }
1317
1318         reg = PIPECONF(pipe);
1319         val = I915_READ(reg);
1320         if (val & PIPECONF_ENABLE)
1321                 return;
1322
1323         I915_WRITE(reg, val | PIPECONF_ENABLE);
1324         intel_wait_for_vblank(dev_priv->dev, pipe);
1325 }
1326
1327 /**
1328  * intel_disable_pipe - disable a pipe, asserting requirements
1329  * @dev_priv: i915 private structure
1330  * @pipe: pipe to disable
1331  *
1332  * Disable @pipe, making sure that various hardware specific requirements
1333  * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1334  *
1335  * @pipe should be %PIPE_A or %PIPE_B.
1336  *
1337  * Will wait until the pipe has shut down before returning.
1338  */
1339 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1340                                enum pipe pipe)
1341 {
1342         int reg;
1343         u32 val;
1344
1345         /*
1346          * Make sure planes won't keep trying to pump pixels to us,
1347          * or we might hang the display.
1348          */
1349         assert_planes_disabled(dev_priv, pipe);
1350
1351         /* Don't disable pipe A or pipe A PLLs if needed */
1352         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1353                 return;
1354
1355         reg = PIPECONF(pipe);
1356         val = I915_READ(reg);
1357         if ((val & PIPECONF_ENABLE) == 0)
1358                 return;
1359
1360         I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1361         intel_wait_for_pipe_off(dev_priv->dev, pipe);
1362 }
1363
1364 /*
1365  * Plane regs are double buffered, going from enabled->disabled needs a
1366  * trigger in order to latch.  The display address reg provides this.
1367  */
1368 static void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1369                                       enum plane plane)
1370 {
1371         I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1372         I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1373 }
1374
1375 /**
1376  * intel_enable_plane - enable a display plane on a given pipe
1377  * @dev_priv: i915 private structure
1378  * @plane: plane to enable
1379  * @pipe: pipe being fed
1380  *
1381  * Enable @plane on @pipe, making sure that @pipe is running first.
1382  */
1383 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1384                                enum plane plane, enum pipe pipe)
1385 {
1386         int reg;
1387         u32 val;
1388
1389         /* If the pipe isn't enabled, we can't pump pixels and may hang */
1390         assert_pipe_enabled(dev_priv, pipe);
1391
1392         reg = DSPCNTR(plane);
1393         val = I915_READ(reg);
1394         if (val & DISPLAY_PLANE_ENABLE)
1395                 return;
1396
1397         I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1398         intel_flush_display_plane(dev_priv, plane);
1399         intel_wait_for_vblank(dev_priv->dev, pipe);
1400 }
1401
1402 /**
1403  * intel_disable_plane - disable a display plane
1404  * @dev_priv: i915 private structure
1405  * @plane: plane to disable
1406  * @pipe: pipe consuming the data
1407  *
1408  * Disable @plane; should be an independent operation.
1409  */
1410 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1411                                 enum plane plane, enum pipe pipe)
1412 {
1413         int reg;
1414         u32 val;
1415
1416         reg = DSPCNTR(plane);
1417         val = I915_READ(reg);
1418         if ((val & DISPLAY_PLANE_ENABLE) == 0)
1419                 return;
1420
1421         I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1422         intel_flush_display_plane(dev_priv, plane);
1423         intel_wait_for_vblank(dev_priv->dev, pipe);
1424 }
1425
1426 static void disable_pch_dp(struct drm_i915_private *dev_priv,
1427                            enum pipe pipe, int reg, u32 port_sel)
1428 {
1429         u32 val = I915_READ(reg);
1430         if (dp_pipe_enabled(dev_priv, pipe, port_sel, val)) {
1431                 DRM_DEBUG_KMS("Disabling pch dp %x on pipe %d\n", reg, pipe);
1432                 I915_WRITE(reg, val & ~DP_PORT_EN);
1433         }
1434 }
1435
1436 static void disable_pch_hdmi(struct drm_i915_private *dev_priv,
1437                              enum pipe pipe, int reg)
1438 {
1439         u32 val = I915_READ(reg);
1440         if (hdmi_pipe_enabled(dev_priv, pipe, val)) {
1441                 DRM_DEBUG_KMS("Disabling pch HDMI %x on pipe %d\n",
1442                               reg, pipe);
1443                 I915_WRITE(reg, val & ~PORT_ENABLE);
1444         }
1445 }
1446
1447 /* Disable any ports connected to this transcoder */
1448 static void intel_disable_pch_ports(struct drm_i915_private *dev_priv,
1449                                     enum pipe pipe)
1450 {
1451         u32 reg, val;
1452
1453         val = I915_READ(PCH_PP_CONTROL);
1454         I915_WRITE(PCH_PP_CONTROL, val | PANEL_UNLOCK_REGS);
1455
1456         disable_pch_dp(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1457         disable_pch_dp(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1458         disable_pch_dp(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1459
1460         reg = PCH_ADPA;
1461         val = I915_READ(reg);
1462         if (adpa_pipe_enabled(dev_priv, pipe, val))
1463                 I915_WRITE(reg, val & ~ADPA_DAC_ENABLE);
1464
1465         reg = PCH_LVDS;
1466         val = I915_READ(reg);
1467         if (lvds_pipe_enabled(dev_priv, pipe, val)) {
1468                 DRM_DEBUG_KMS("disable lvds on pipe %d val 0x%08x\n", pipe, val);
1469                 I915_WRITE(reg, val & ~LVDS_PORT_EN);
1470                 POSTING_READ(reg);
1471                 udelay(100);
1472         }
1473
1474         disable_pch_hdmi(dev_priv, pipe, HDMIB);
1475         disable_pch_hdmi(dev_priv, pipe, HDMIC);
1476         disable_pch_hdmi(dev_priv, pipe, HDMID);
1477 }
1478
1479 static void i8xx_disable_fbc(struct drm_device *dev)
1480 {
1481         struct drm_i915_private *dev_priv = dev->dev_private;
1482         u32 fbc_ctl;
1483
1484         /* Disable compression */
1485         fbc_ctl = I915_READ(FBC_CONTROL);
1486         if ((fbc_ctl & FBC_CTL_EN) == 0)
1487                 return;
1488
1489         fbc_ctl &= ~FBC_CTL_EN;
1490         I915_WRITE(FBC_CONTROL, fbc_ctl);
1491
1492         /* Wait for compressing bit to clear */
1493         if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
1494                 DRM_DEBUG_KMS("FBC idle timed out\n");
1495                 return;
1496         }
1497
1498         DRM_DEBUG_KMS("disabled FBC\n");
1499 }
1500
1501 static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1502 {
1503         struct drm_device *dev = crtc->dev;
1504         struct drm_i915_private *dev_priv = dev->dev_private;
1505         struct drm_framebuffer *fb = crtc->fb;
1506         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1507         struct drm_i915_gem_object *obj = intel_fb->obj;
1508         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1509         int cfb_pitch;
1510         int plane, i;
1511         u32 fbc_ctl, fbc_ctl2;
1512
1513         cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
1514         if (fb->pitch < cfb_pitch)
1515                 cfb_pitch = fb->pitch;
1516
1517         /* FBC_CTL wants 64B units */
1518         cfb_pitch = (cfb_pitch / 64) - 1;
1519         plane = intel_crtc->plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
1520
1521         /* Clear old tags */
1522         for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
1523                 I915_WRITE(FBC_TAG + (i * 4), 0);
1524
1525         /* Set it up... */
1526         fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
1527         fbc_ctl2 |= plane;
1528         I915_WRITE(FBC_CONTROL2, fbc_ctl2);
1529         I915_WRITE(FBC_FENCE_OFF, crtc->y);
1530
1531         /* enable it... */
1532         fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
1533         if (IS_I945GM(dev))
1534                 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
1535         fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
1536         fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
1537         fbc_ctl |= obj->fence_reg;
1538         I915_WRITE(FBC_CONTROL, fbc_ctl);
1539
1540         DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %d, ",
1541                       cfb_pitch, crtc->y, intel_crtc->plane);
1542 }
1543
1544 static bool i8xx_fbc_enabled(struct drm_device *dev)
1545 {
1546         struct drm_i915_private *dev_priv = dev->dev_private;
1547
1548         return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
1549 }
1550
1551 static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1552 {
1553         struct drm_device *dev = crtc->dev;
1554         struct drm_i915_private *dev_priv = dev->dev_private;
1555         struct drm_framebuffer *fb = crtc->fb;
1556         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1557         struct drm_i915_gem_object *obj = intel_fb->obj;
1558         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1559         int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
1560         unsigned long stall_watermark = 200;
1561         u32 dpfc_ctl;
1562
1563         dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
1564         dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg;
1565         I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
1566
1567         I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1568                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1569                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1570         I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
1571
1572         /* enable it... */
1573         I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
1574
1575         DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1576 }
1577
1578 static void g4x_disable_fbc(struct drm_device *dev)
1579 {
1580         struct drm_i915_private *dev_priv = dev->dev_private;
1581         u32 dpfc_ctl;
1582
1583         /* Disable compression */
1584         dpfc_ctl = I915_READ(DPFC_CONTROL);
1585         if (dpfc_ctl & DPFC_CTL_EN) {
1586                 dpfc_ctl &= ~DPFC_CTL_EN;
1587                 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1588
1589                 DRM_DEBUG_KMS("disabled FBC\n");
1590         }
1591 }
1592
1593 static bool g4x_fbc_enabled(struct drm_device *dev)
1594 {
1595         struct drm_i915_private *dev_priv = dev->dev_private;
1596
1597         return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
1598 }
1599
1600 static void sandybridge_blit_fbc_update(struct drm_device *dev)
1601 {
1602         struct drm_i915_private *dev_priv = dev->dev_private;
1603         u32 blt_ecoskpd;
1604
1605         /* Make sure blitter notifies FBC of writes */
1606         gen6_gt_force_wake_get(dev_priv);
1607         blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
1608         blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
1609                 GEN6_BLITTER_LOCK_SHIFT;
1610         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1611         blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
1612         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1613         blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
1614                          GEN6_BLITTER_LOCK_SHIFT);
1615         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1616         POSTING_READ(GEN6_BLITTER_ECOSKPD);
1617         gen6_gt_force_wake_put(dev_priv);
1618 }
1619
1620 static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1621 {
1622         struct drm_device *dev = crtc->dev;
1623         struct drm_i915_private *dev_priv = dev->dev_private;
1624         struct drm_framebuffer *fb = crtc->fb;
1625         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1626         struct drm_i915_gem_object *obj = intel_fb->obj;
1627         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1628         int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
1629         unsigned long stall_watermark = 200;
1630         u32 dpfc_ctl;
1631
1632         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1633         dpfc_ctl &= DPFC_RESERVED;
1634         dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
1635         /* Set persistent mode for front-buffer rendering, ala X. */
1636         dpfc_ctl |= DPFC_CTL_PERSISTENT_MODE;
1637         dpfc_ctl |= (DPFC_CTL_FENCE_EN | obj->fence_reg);
1638         I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
1639
1640         I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1641                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1642                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1643         I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
1644         I915_WRITE(ILK_FBC_RT_BASE, obj->gtt_offset | ILK_FBC_RT_VALID);
1645         /* enable it... */
1646         I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
1647
1648         if (IS_GEN6(dev)) {
1649                 I915_WRITE(SNB_DPFC_CTL_SA,
1650                            SNB_CPU_FENCE_ENABLE | obj->fence_reg);
1651                 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
1652                 sandybridge_blit_fbc_update(dev);
1653         }
1654
1655         DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1656 }
1657
1658 static void ironlake_disable_fbc(struct drm_device *dev)
1659 {
1660         struct drm_i915_private *dev_priv = dev->dev_private;
1661         u32 dpfc_ctl;
1662
1663         /* Disable compression */
1664         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1665         if (dpfc_ctl & DPFC_CTL_EN) {
1666                 dpfc_ctl &= ~DPFC_CTL_EN;
1667                 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
1668
1669                 DRM_DEBUG_KMS("disabled FBC\n");
1670         }
1671 }
1672
1673 static bool ironlake_fbc_enabled(struct drm_device *dev)
1674 {
1675         struct drm_i915_private *dev_priv = dev->dev_private;
1676
1677         return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
1678 }
1679
1680 bool intel_fbc_enabled(struct drm_device *dev)
1681 {
1682         struct drm_i915_private *dev_priv = dev->dev_private;
1683
1684         if (!dev_priv->display.fbc_enabled)
1685                 return false;
1686
1687         return dev_priv->display.fbc_enabled(dev);
1688 }
1689
1690 static void intel_fbc_work_fn(struct work_struct *__work)
1691 {
1692         struct intel_fbc_work *work =
1693                 container_of(to_delayed_work(__work),
1694                              struct intel_fbc_work, work);
1695         struct drm_device *dev = work->crtc->dev;
1696         struct drm_i915_private *dev_priv = dev->dev_private;
1697
1698         mutex_lock(&dev->struct_mutex);
1699         if (work == dev_priv->fbc_work) {
1700                 /* Double check that we haven't switched fb without cancelling
1701                  * the prior work.
1702                  */
1703                 if (work->crtc->fb == work->fb) {
1704                         dev_priv->display.enable_fbc(work->crtc,
1705                                                      work->interval);
1706
1707                         dev_priv->cfb_plane = to_intel_crtc(work->crtc)->plane;
1708                         dev_priv->cfb_fb = work->crtc->fb->base.id;
1709                         dev_priv->cfb_y = work->crtc->y;
1710                 }
1711
1712                 dev_priv->fbc_work = NULL;
1713         }
1714         mutex_unlock(&dev->struct_mutex);
1715
1716         kfree(work);
1717 }
1718
1719 static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv)
1720 {
1721         if (dev_priv->fbc_work == NULL)
1722                 return;
1723
1724         DRM_DEBUG_KMS("cancelling pending FBC enable\n");
1725
1726         /* Synchronisation is provided by struct_mutex and checking of
1727          * dev_priv->fbc_work, so we can perform the cancellation
1728          * entirely asynchronously.
1729          */
1730         if (cancel_delayed_work(&dev_priv->fbc_work->work))
1731                 /* tasklet was killed before being run, clean up */
1732                 kfree(dev_priv->fbc_work);
1733
1734         /* Mark the work as no longer wanted so that if it does
1735          * wake-up (because the work was already running and waiting
1736          * for our mutex), it will discover that is no longer
1737          * necessary to run.
1738          */
1739         dev_priv->fbc_work = NULL;
1740 }
1741
1742 static void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1743 {
1744         struct intel_fbc_work *work;
1745         struct drm_device *dev = crtc->dev;
1746         struct drm_i915_private *dev_priv = dev->dev_private;
1747
1748         if (!dev_priv->display.enable_fbc)
1749                 return;
1750
1751         intel_cancel_fbc_work(dev_priv);
1752
1753         work = kzalloc(sizeof *work, GFP_KERNEL);
1754         if (work == NULL) {
1755                 dev_priv->display.enable_fbc(crtc, interval);
1756                 return;
1757         }
1758
1759         work->crtc = crtc;
1760         work->fb = crtc->fb;
1761         work->interval = interval;
1762         INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn);
1763
1764         dev_priv->fbc_work = work;
1765
1766         DRM_DEBUG_KMS("scheduling delayed FBC enable\n");
1767
1768         /* Delay the actual enabling to let pageflipping cease and the
1769          * display to settle before starting the compression. Note that
1770          * this delay also serves a second purpose: it allows for a
1771          * vblank to pass after disabling the FBC before we attempt
1772          * to modify the control registers.
1773          *
1774          * A more complicated solution would involve tracking vblanks
1775          * following the termination of the page-flipping sequence
1776          * and indeed performing the enable as a co-routine and not
1777          * waiting synchronously upon the vblank.
1778          */
1779         schedule_delayed_work(&work->work, msecs_to_jiffies(50));
1780 }
1781
1782 void intel_disable_fbc(struct drm_device *dev)
1783 {
1784         struct drm_i915_private *dev_priv = dev->dev_private;
1785
1786         intel_cancel_fbc_work(dev_priv);
1787
1788         if (!dev_priv->display.disable_fbc)
1789                 return;
1790
1791         dev_priv->display.disable_fbc(dev);
1792         dev_priv->cfb_plane = -1;
1793 }
1794
1795 /**
1796  * intel_update_fbc - enable/disable FBC as needed
1797  * @dev: the drm_device
1798  *
1799  * Set up the framebuffer compression hardware at mode set time.  We
1800  * enable it if possible:
1801  *   - plane A only (on pre-965)
1802  *   - no pixel mulitply/line duplication
1803  *   - no alpha buffer discard
1804  *   - no dual wide
1805  *   - framebuffer <= 2048 in width, 1536 in height
1806  *
1807  * We can't assume that any compression will take place (worst case),
1808  * so the compressed buffer has to be the same size as the uncompressed
1809  * one.  It also must reside (along with the line length buffer) in
1810  * stolen memory.
1811  *
1812  * We need to enable/disable FBC on a global basis.
1813  */
1814 static void intel_update_fbc(struct drm_device *dev)
1815 {
1816         struct drm_i915_private *dev_priv = dev->dev_private;
1817         struct drm_crtc *crtc = NULL, *tmp_crtc;
1818         struct intel_crtc *intel_crtc;
1819         struct drm_framebuffer *fb;
1820         struct intel_framebuffer *intel_fb;
1821         struct drm_i915_gem_object *obj;
1822         int enable_fbc;
1823
1824         DRM_DEBUG_KMS("\n");
1825
1826         if (!i915_powersave)
1827                 return;
1828
1829         if (!I915_HAS_FBC(dev))
1830                 return;
1831
1832         /*
1833          * If FBC is already on, we just have to verify that we can
1834          * keep it that way...
1835          * Need to disable if:
1836          *   - more than one pipe is active
1837          *   - changing FBC params (stride, fence, mode)
1838          *   - new fb is too large to fit in compressed buffer
1839          *   - going to an unsupported config (interlace, pixel multiply, etc.)
1840          */
1841         list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
1842                 if (tmp_crtc->enabled && tmp_crtc->fb) {
1843                         if (crtc) {
1844                                 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
1845                                 dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
1846                                 goto out_disable;
1847                         }
1848                         crtc = tmp_crtc;
1849                 }
1850         }
1851
1852         if (!crtc || crtc->fb == NULL) {
1853                 DRM_DEBUG_KMS("no output, disabling\n");
1854                 dev_priv->no_fbc_reason = FBC_NO_OUTPUT;
1855                 goto out_disable;
1856         }
1857
1858         intel_crtc = to_intel_crtc(crtc);
1859         fb = crtc->fb;
1860         intel_fb = to_intel_framebuffer(fb);
1861         obj = intel_fb->obj;
1862
1863         enable_fbc = i915_enable_fbc;
1864         if (enable_fbc < 0) {
1865                 DRM_DEBUG_KMS("fbc set to per-chip default\n");
1866                 enable_fbc = 1;
1867                 if (INTEL_INFO(dev)->gen <= 6)
1868                         enable_fbc = 0;
1869         }
1870         if (!enable_fbc) {
1871                 DRM_DEBUG_KMS("fbc disabled per module param\n");
1872                 dev_priv->no_fbc_reason = FBC_MODULE_PARAM;
1873                 goto out_disable;
1874         }
1875         if (intel_fb->obj->base.size > dev_priv->cfb_size) {
1876                 DRM_DEBUG_KMS("framebuffer too large, disabling "
1877                               "compression\n");
1878                 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
1879                 goto out_disable;
1880         }
1881         if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) ||
1882             (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) {
1883                 DRM_DEBUG_KMS("mode incompatible with compression, "
1884                               "disabling\n");
1885                 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
1886                 goto out_disable;
1887         }
1888         if ((crtc->mode.hdisplay > 2048) ||
1889             (crtc->mode.vdisplay > 1536)) {
1890                 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
1891                 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
1892                 goto out_disable;
1893         }
1894         if ((IS_I915GM(dev) || IS_I945GM(dev)) && intel_crtc->plane != 0) {
1895                 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
1896                 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
1897                 goto out_disable;
1898         }
1899
1900         /* The use of a CPU fence is mandatory in order to detect writes
1901          * by the CPU to the scanout and trigger updates to the FBC.
1902          */
1903         if (obj->tiling_mode != I915_TILING_X ||
1904             obj->fence_reg == I915_FENCE_REG_NONE) {
1905                 DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
1906                 dev_priv->no_fbc_reason = FBC_NOT_TILED;
1907                 goto out_disable;
1908         }
1909
1910         /* If the kernel debugger is active, always disable compression */
1911         if (in_dbg_master())
1912                 goto out_disable;
1913
1914         /* If the scanout has not changed, don't modify the FBC settings.
1915          * Note that we make the fundamental assumption that the fb->obj
1916          * cannot be unpinned (and have its GTT offset and fence revoked)
1917          * without first being decoupled from the scanout and FBC disabled.
1918          */
1919         if (dev_priv->cfb_plane == intel_crtc->plane &&
1920             dev_priv->cfb_fb == fb->base.id &&
1921             dev_priv->cfb_y == crtc->y)
1922                 return;
1923
1924         if (intel_fbc_enabled(dev)) {
1925                 /* We update FBC along two paths, after changing fb/crtc
1926                  * configuration (modeswitching) and after page-flipping
1927                  * finishes. For the latter, we know that not only did
1928                  * we disable the FBC at the start of the page-flip
1929                  * sequence, but also more than one vblank has passed.
1930                  *
1931                  * For the former case of modeswitching, it is possible
1932                  * to switch between two FBC valid configurations
1933                  * instantaneously so we do need to disable the FBC
1934                  * before we can modify its control registers. We also
1935                  * have to wait for the next vblank for that to take
1936                  * effect. However, since we delay enabling FBC we can
1937                  * assume that a vblank has passed since disabling and
1938                  * that we can safely alter the registers in the deferred
1939                  * callback.
1940                  *
1941                  * In the scenario that we go from a valid to invalid
1942                  * and then back to valid FBC configuration we have
1943                  * no strict enforcement that a vblank occurred since
1944                  * disabling the FBC. However, along all current pipe
1945                  * disabling paths we do need to wait for a vblank at
1946                  * some point. And we wait before enabling FBC anyway.
1947                  */
1948                 DRM_DEBUG_KMS("disabling active FBC for update\n");
1949                 intel_disable_fbc(dev);
1950         }
1951
1952         intel_enable_fbc(crtc, 500);
1953         return;
1954
1955 out_disable:
1956         /* Multiple disables should be harmless */
1957         if (intel_fbc_enabled(dev)) {
1958                 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
1959                 intel_disable_fbc(dev);
1960         }
1961 }
1962
1963 int
1964 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1965                            struct drm_i915_gem_object *obj,
1966                            struct intel_ring_buffer *pipelined)
1967 {
1968         struct drm_i915_private *dev_priv = dev->dev_private;
1969         u32 alignment;
1970         int ret;
1971
1972         switch (obj->tiling_mode) {
1973         case I915_TILING_NONE:
1974                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1975                         alignment = 128 * 1024;
1976                 else if (INTEL_INFO(dev)->gen >= 4)
1977                         alignment = 4 * 1024;
1978                 else
1979                         alignment = 64 * 1024;
1980                 break;
1981         case I915_TILING_X:
1982                 /* pin() will align the object as required by fence */
1983                 alignment = 0;
1984                 break;
1985         case I915_TILING_Y:
1986                 /* FIXME: Is this true? */
1987                 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1988                 return -EINVAL;
1989         default:
1990                 BUG();
1991         }
1992
1993         dev_priv->mm.interruptible = false;
1994         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1995         if (ret)
1996                 goto err_interruptible;
1997
1998         /* Install a fence for tiled scan-out. Pre-i965 always needs a
1999          * fence, whereas 965+ only requires a fence if using
2000          * framebuffer compression.  For simplicity, we always install
2001          * a fence as the cost is not that onerous.
2002          */
2003         if (obj->tiling_mode != I915_TILING_NONE) {
2004                 ret = i915_gem_object_get_fence(obj, pipelined);
2005                 if (ret)
2006                         goto err_unpin;
2007         }
2008
2009         dev_priv->mm.interruptible = true;
2010         return 0;
2011
2012 err_unpin:
2013         i915_gem_object_unpin(obj);
2014 err_interruptible:
2015         dev_priv->mm.interruptible = true;
2016         return ret;
2017 }
2018
2019 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2020                              int x, int y)
2021 {
2022         struct drm_device *dev = crtc->dev;
2023         struct drm_i915_private *dev_priv = dev->dev_private;
2024         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2025         struct intel_framebuffer *intel_fb;
2026         struct drm_i915_gem_object *obj;
2027         int plane = intel_crtc->plane;
2028         unsigned long Start, Offset;
2029         u32 dspcntr;
2030         u32 reg;
2031
2032         switch (plane) {
2033         case 0:
2034         case 1:
2035                 break;
2036         default:
2037                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2038                 return -EINVAL;
2039         }
2040
2041         intel_fb = to_intel_framebuffer(fb);
2042         obj = intel_fb->obj;
2043
2044         reg = DSPCNTR(plane);
2045         dspcntr = I915_READ(reg);
2046         /* Mask out pixel format bits in case we change it */
2047         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2048         switch (fb->bits_per_pixel) {
2049         case 8:
2050                 dspcntr |= DISPPLANE_8BPP;
2051                 break;
2052         case 16:
2053                 if (fb->depth == 15)
2054                         dspcntr |= DISPPLANE_15_16BPP;
2055                 else
2056                         dspcntr |= DISPPLANE_16BPP;
2057                 break;
2058         case 24:
2059         case 32:
2060                 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2061                 break;
2062         default:
2063                 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
2064                 return -EINVAL;
2065         }
2066         if (INTEL_INFO(dev)->gen >= 4) {
2067                 if (obj->tiling_mode != I915_TILING_NONE)
2068                         dspcntr |= DISPPLANE_TILED;
2069                 else
2070                         dspcntr &= ~DISPPLANE_TILED;
2071         }
2072
2073         I915_WRITE(reg, dspcntr);
2074
2075         Start = obj->gtt_offset;
2076         Offset = y * fb->pitch + x * (fb->bits_per_pixel / 8);
2077
2078         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2079                       Start, Offset, x, y, fb->pitch);
2080         I915_WRITE(DSPSTRIDE(plane), fb->pitch);
2081         if (INTEL_INFO(dev)->gen >= 4) {
2082                 I915_WRITE(DSPSURF(plane), Start);
2083                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2084                 I915_WRITE(DSPADDR(plane), Offset);
2085         } else
2086                 I915_WRITE(DSPADDR(plane), Start + Offset);
2087         POSTING_READ(reg);
2088
2089         return 0;
2090 }
2091
2092 static int ironlake_update_plane(struct drm_crtc *crtc,
2093                                  struct drm_framebuffer *fb, int x, int y)
2094 {
2095         struct drm_device *dev = crtc->dev;
2096         struct drm_i915_private *dev_priv = dev->dev_private;
2097         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2098         struct intel_framebuffer *intel_fb;
2099         struct drm_i915_gem_object *obj;
2100         int plane = intel_crtc->plane;
2101         unsigned long Start, Offset;
2102         u32 dspcntr;
2103         u32 reg;
2104
2105         switch (plane) {
2106         case 0:
2107         case 1:
2108         case 2:
2109                 break;
2110         default:
2111                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2112                 return -EINVAL;
2113         }
2114
2115         intel_fb = to_intel_framebuffer(fb);
2116         obj = intel_fb->obj;
2117
2118         reg = DSPCNTR(plane);
2119         dspcntr = I915_READ(reg);
2120         /* Mask out pixel format bits in case we change it */
2121         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2122         switch (fb->bits_per_pixel) {
2123         case 8:
2124                 dspcntr |= DISPPLANE_8BPP;
2125                 break;
2126         case 16:
2127                 if (fb->depth != 16)
2128                         return -EINVAL;
2129
2130                 dspcntr |= DISPPLANE_16BPP;
2131                 break;
2132         case 24:
2133         case 32:
2134                 if (fb->depth == 24)
2135                         dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2136                 else if (fb->depth == 30)
2137                         dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
2138                 else
2139                         return -EINVAL;
2140                 break;
2141         default:
2142                 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
2143                 return -EINVAL;
2144         }
2145
2146         if (obj->tiling_mode != I915_TILING_NONE)
2147                 dspcntr |= DISPPLANE_TILED;
2148         else
2149                 dspcntr &= ~DISPPLANE_TILED;
2150
2151         /* must disable */
2152         dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2153
2154         I915_WRITE(reg, dspcntr);
2155
2156         Start = obj->gtt_offset;
2157         Offset = y * fb->pitch + x * (fb->bits_per_pixel / 8);
2158
2159         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2160                       Start, Offset, x, y, fb->pitch);
2161         I915_WRITE(DSPSTRIDE(plane), fb->pitch);
2162         I915_WRITE(DSPSURF(plane), Start);
2163         I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2164         I915_WRITE(DSPADDR(plane), Offset);
2165         POSTING_READ(reg);
2166
2167         return 0;
2168 }
2169
2170 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2171 static int
2172 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2173                            int x, int y, enum mode_set_atomic state)
2174 {
2175         struct drm_device *dev = crtc->dev;
2176         struct drm_i915_private *dev_priv = dev->dev_private;
2177         int ret;
2178
2179         ret = dev_priv->display.update_plane(crtc, fb, x, y);
2180         if (ret)
2181                 return ret;
2182
2183         intel_update_fbc(dev);
2184         intel_increase_pllclock(crtc);
2185
2186         return 0;
2187 }
2188
2189 static int
2190 intel_finish_fb(struct drm_framebuffer *old_fb)
2191 {
2192         struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2193         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2194         bool was_interruptible = dev_priv->mm.interruptible;
2195         int ret;
2196
2197         wait_event(dev_priv->pending_flip_queue,
2198                    atomic_read(&dev_priv->mm.wedged) ||
2199                    atomic_read(&obj->pending_flip) == 0);
2200
2201         /* Big Hammer, we also need to ensure that any pending
2202          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2203          * current scanout is retired before unpinning the old
2204          * framebuffer.
2205          *
2206          * This should only fail upon a hung GPU, in which case we
2207          * can safely continue.
2208          */
2209         dev_priv->mm.interruptible = false;
2210         ret = i915_gem_object_finish_gpu(obj);
2211         dev_priv->mm.interruptible = was_interruptible;
2212
2213         return ret;
2214 }
2215
2216 static int
2217 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2218                     struct drm_framebuffer *old_fb)
2219 {
2220         struct drm_device *dev = crtc->dev;
2221         struct drm_i915_master_private *master_priv;
2222         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2223         int ret;
2224
2225         /* no fb bound */
2226         if (!crtc->fb) {
2227                 DRM_ERROR("No FB bound\n");
2228                 return 0;
2229         }
2230
2231         switch (intel_crtc->plane) {
2232         case 0:
2233         case 1:
2234                 break;
2235         case 2:
2236                 if (IS_IVYBRIDGE(dev))
2237                         break;
2238                 /* fall through otherwise */
2239         default:
2240                 DRM_ERROR("no plane for crtc\n");
2241                 return -EINVAL;
2242         }
2243
2244         mutex_lock(&dev->struct_mutex);
2245         ret = intel_pin_and_fence_fb_obj(dev,
2246                                          to_intel_framebuffer(crtc->fb)->obj,
2247                                          NULL);
2248         if (ret != 0) {
2249                 mutex_unlock(&dev->struct_mutex);
2250                 DRM_ERROR("pin & fence failed\n");
2251                 return ret;
2252         }
2253
2254         if (old_fb)
2255                 intel_finish_fb(old_fb);
2256
2257         ret = intel_pipe_set_base_atomic(crtc, crtc->fb, x, y,
2258                                          LEAVE_ATOMIC_MODE_SET);
2259         if (ret) {
2260                 i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
2261                 mutex_unlock(&dev->struct_mutex);
2262                 DRM_ERROR("failed to update base address\n");
2263                 return ret;
2264         }
2265
2266         if (old_fb) {
2267                 intel_wait_for_vblank(dev, intel_crtc->pipe);
2268                 i915_gem_object_unpin(to_intel_framebuffer(old_fb)->obj);
2269         }
2270
2271         mutex_unlock(&dev->struct_mutex);
2272
2273         if (!dev->primary->master)
2274                 return 0;
2275
2276         master_priv = dev->primary->master->driver_priv;
2277         if (!master_priv->sarea_priv)
2278                 return 0;
2279
2280         if (intel_crtc->pipe) {
2281                 master_priv->sarea_priv->pipeB_x = x;
2282                 master_priv->sarea_priv->pipeB_y = y;
2283         } else {
2284                 master_priv->sarea_priv->pipeA_x = x;
2285                 master_priv->sarea_priv->pipeA_y = y;
2286         }
2287
2288         return 0;
2289 }
2290
2291 static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
2292 {
2293         struct drm_device *dev = crtc->dev;
2294         struct drm_i915_private *dev_priv = dev->dev_private;
2295         u32 dpa_ctl;
2296
2297         DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
2298         dpa_ctl = I915_READ(DP_A);
2299         dpa_ctl &= ~DP_PLL_FREQ_MASK;
2300
2301         if (clock < 200000) {
2302                 u32 temp;
2303                 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2304                 /* workaround for 160Mhz:
2305                    1) program 0x4600c bits 15:0 = 0x8124
2306                    2) program 0x46010 bit 0 = 1
2307                    3) program 0x46034 bit 24 = 1
2308                    4) program 0x64000 bit 14 = 1
2309                    */
2310                 temp = I915_READ(0x4600c);
2311                 temp &= 0xffff0000;
2312                 I915_WRITE(0x4600c, temp | 0x8124);
2313
2314                 temp = I915_READ(0x46010);
2315                 I915_WRITE(0x46010, temp | 1);
2316
2317                 temp = I915_READ(0x46034);
2318                 I915_WRITE(0x46034, temp | (1 << 24));
2319         } else {
2320                 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2321         }
2322         I915_WRITE(DP_A, dpa_ctl);
2323
2324         POSTING_READ(DP_A);
2325         udelay(500);
2326 }
2327
2328 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2329 {
2330         struct drm_device *dev = crtc->dev;
2331         struct drm_i915_private *dev_priv = dev->dev_private;
2332         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2333         int pipe = intel_crtc->pipe;
2334         u32 reg, temp;
2335
2336         /* enable normal train */
2337         reg = FDI_TX_CTL(pipe);
2338         temp = I915_READ(reg);
2339         if (IS_IVYBRIDGE(dev)) {
2340                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2341                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2342         } else {
2343                 temp &= ~FDI_LINK_TRAIN_NONE;
2344                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2345         }
2346         I915_WRITE(reg, temp);
2347
2348         reg = FDI_RX_CTL(pipe);
2349         temp = I915_READ(reg);
2350         if (HAS_PCH_CPT(dev)) {
2351                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2352                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2353         } else {
2354                 temp &= ~FDI_LINK_TRAIN_NONE;
2355                 temp |= FDI_LINK_TRAIN_NONE;
2356         }
2357         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2358
2359         /* wait one idle pattern time */
2360         POSTING_READ(reg);
2361         udelay(1000);
2362
2363         /* IVB wants error correction enabled */
2364         if (IS_IVYBRIDGE(dev))
2365                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2366                            FDI_FE_ERRC_ENABLE);
2367 }
2368
2369 static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
2370 {
2371         struct drm_i915_private *dev_priv = dev->dev_private;
2372         u32 flags = I915_READ(SOUTH_CHICKEN1);
2373
2374         flags |= FDI_PHASE_SYNC_OVR(pipe);
2375         I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
2376         flags |= FDI_PHASE_SYNC_EN(pipe);
2377         I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
2378         POSTING_READ(SOUTH_CHICKEN1);
2379 }
2380
2381 /* The FDI link training functions for ILK/Ibexpeak. */
2382 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2383 {
2384         struct drm_device *dev = crtc->dev;
2385         struct drm_i915_private *dev_priv = dev->dev_private;
2386         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2387         int pipe = intel_crtc->pipe;
2388         int plane = intel_crtc->plane;
2389         u32 reg, temp, tries;
2390
2391         /* FDI needs bits from pipe & plane first */
2392         assert_pipe_enabled(dev_priv, pipe);
2393         assert_plane_enabled(dev_priv, plane);
2394
2395         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2396            for train result */
2397         reg = FDI_RX_IMR(pipe);
2398         temp = I915_READ(reg);
2399         temp &= ~FDI_RX_SYMBOL_LOCK;
2400         temp &= ~FDI_RX_BIT_LOCK;
2401         I915_WRITE(reg, temp);
2402         I915_READ(reg);
2403         udelay(150);
2404
2405         /* enable CPU FDI TX and PCH FDI RX */
2406         reg = FDI_TX_CTL(pipe);
2407         temp = I915_READ(reg);
2408         temp &= ~(7 << 19);
2409         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2410         temp &= ~FDI_LINK_TRAIN_NONE;
2411         temp |= FDI_LINK_TRAIN_PATTERN_1;
2412         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2413
2414         reg = FDI_RX_CTL(pipe);
2415         temp = I915_READ(reg);
2416         temp &= ~FDI_LINK_TRAIN_NONE;
2417         temp |= FDI_LINK_TRAIN_PATTERN_1;
2418         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2419
2420         POSTING_READ(reg);
2421         udelay(150);
2422
2423         /* Ironlake workaround, enable clock pointer after FDI enable*/
2424         if (HAS_PCH_IBX(dev)) {
2425                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2426                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2427                            FDI_RX_PHASE_SYNC_POINTER_EN);
2428         }
2429
2430         reg = FDI_RX_IIR(pipe);
2431         for (tries = 0; tries < 5; tries++) {
2432                 temp = I915_READ(reg);
2433                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2434
2435                 if ((temp & FDI_RX_BIT_LOCK)) {
2436                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2437                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2438                         break;
2439                 }
2440         }
2441         if (tries == 5)
2442                 DRM_ERROR("FDI train 1 fail!\n");
2443
2444         /* Train 2 */
2445         reg = FDI_TX_CTL(pipe);
2446         temp = I915_READ(reg);
2447         temp &= ~FDI_LINK_TRAIN_NONE;
2448         temp |= FDI_LINK_TRAIN_PATTERN_2;
2449         I915_WRITE(reg, temp);
2450
2451         reg = FDI_RX_CTL(pipe);
2452         temp = I915_READ(reg);
2453         temp &= ~FDI_LINK_TRAIN_NONE;
2454         temp |= FDI_LINK_TRAIN_PATTERN_2;
2455         I915_WRITE(reg, temp);
2456
2457         POSTING_READ(reg);
2458         udelay(150);
2459
2460         reg = FDI_RX_IIR(pipe);
2461         for (tries = 0; tries < 5; tries++) {
2462                 temp = I915_READ(reg);
2463                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2464
2465                 if (temp & FDI_RX_SYMBOL_LOCK) {
2466                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2467                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2468                         break;
2469                 }
2470         }
2471         if (tries == 5)
2472                 DRM_ERROR("FDI train 2 fail!\n");
2473
2474         DRM_DEBUG_KMS("FDI train done\n");
2475
2476 }
2477
2478 static const int snb_b_fdi_train_param[] = {
2479         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2480         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2481         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2482         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2483 };
2484
2485 /* The FDI link training functions for SNB/Cougarpoint. */
2486 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2487 {
2488         struct drm_device *dev = crtc->dev;
2489         struct drm_i915_private *dev_priv = dev->dev_private;
2490         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2491         int pipe = intel_crtc->pipe;
2492         u32 reg, temp, i;
2493
2494         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2495            for train result */
2496         reg = FDI_RX_IMR(pipe);
2497         temp = I915_READ(reg);
2498         temp &= ~FDI_RX_SYMBOL_LOCK;
2499         temp &= ~FDI_RX_BIT_LOCK;
2500         I915_WRITE(reg, temp);
2501
2502         POSTING_READ(reg);
2503         udelay(150);
2504
2505         /* enable CPU FDI TX and PCH FDI RX */
2506         reg = FDI_TX_CTL(pipe);
2507         temp = I915_READ(reg);
2508         temp &= ~(7 << 19);
2509         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2510         temp &= ~FDI_LINK_TRAIN_NONE;
2511         temp |= FDI_LINK_TRAIN_PATTERN_1;
2512         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2513         /* SNB-B */
2514         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2515         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2516
2517         reg = FDI_RX_CTL(pipe);
2518         temp = I915_READ(reg);
2519         if (HAS_PCH_CPT(dev)) {
2520                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2521                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2522         } else {
2523                 temp &= ~FDI_LINK_TRAIN_NONE;
2524                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2525         }
2526         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2527
2528         POSTING_READ(reg);
2529         udelay(150);
2530
2531         if (HAS_PCH_CPT(dev))
2532                 cpt_phase_pointer_enable(dev, pipe);
2533
2534         for (i = 0; i < 4; i++) {
2535                 reg = FDI_TX_CTL(pipe);
2536                 temp = I915_READ(reg);
2537                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2538                 temp |= snb_b_fdi_train_param[i];
2539                 I915_WRITE(reg, temp);
2540
2541                 POSTING_READ(reg);
2542                 udelay(500);
2543
2544                 reg = FDI_RX_IIR(pipe);
2545                 temp = I915_READ(reg);
2546                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2547
2548                 if (temp & FDI_RX_BIT_LOCK) {
2549                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2550                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2551                         break;
2552                 }
2553         }
2554         if (i == 4)
2555                 DRM_ERROR("FDI train 1 fail!\n");
2556
2557         /* Train 2 */
2558         reg = FDI_TX_CTL(pipe);
2559         temp = I915_READ(reg);
2560         temp &= ~FDI_LINK_TRAIN_NONE;
2561         temp |= FDI_LINK_TRAIN_PATTERN_2;
2562         if (IS_GEN6(dev)) {
2563                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2564                 /* SNB-B */
2565                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2566         }
2567         I915_WRITE(reg, temp);
2568
2569         reg = FDI_RX_CTL(pipe);
2570         temp = I915_READ(reg);
2571         if (HAS_PCH_CPT(dev)) {
2572                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2573                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2574         } else {
2575                 temp &= ~FDI_LINK_TRAIN_NONE;
2576                 temp |= FDI_LINK_TRAIN_PATTERN_2;
2577         }
2578         I915_WRITE(reg, temp);
2579
2580         POSTING_READ(reg);
2581         udelay(150);
2582
2583         for (i = 0; i < 4; i++) {
2584                 reg = FDI_TX_CTL(pipe);
2585                 temp = I915_READ(reg);
2586                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2587                 temp |= snb_b_fdi_train_param[i];
2588                 I915_WRITE(reg, temp);
2589
2590                 POSTING_READ(reg);
2591                 udelay(500);
2592
2593                 reg = FDI_RX_IIR(pipe);
2594                 temp = I915_READ(reg);
2595                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2596
2597                 if (temp & FDI_RX_SYMBOL_LOCK) {
2598                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2599                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2600                         break;
2601                 }
2602         }
2603         if (i == 4)
2604                 DRM_ERROR("FDI train 2 fail!\n");
2605
2606         DRM_DEBUG_KMS("FDI train done.\n");
2607 }
2608
2609 /* Manual link training for Ivy Bridge A0 parts */
2610 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2611 {
2612         struct drm_device *dev = crtc->dev;
2613         struct drm_i915_private *dev_priv = dev->dev_private;
2614         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2615         int pipe = intel_crtc->pipe;
2616         u32 reg, temp, i;
2617
2618         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2619            for train result */
2620         reg = FDI_RX_IMR(pipe);
2621         temp = I915_READ(reg);
2622         temp &= ~FDI_RX_SYMBOL_LOCK;
2623         temp &= ~FDI_RX_BIT_LOCK;
2624         I915_WRITE(reg, temp);
2625
2626         POSTING_READ(reg);
2627         udelay(150);
2628
2629         /* enable CPU FDI TX and PCH FDI RX */
2630         reg = FDI_TX_CTL(pipe);
2631         temp = I915_READ(reg);
2632         temp &= ~(7 << 19);
2633         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2634         temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2635         temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2636         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2637         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2638         temp |= FDI_COMPOSITE_SYNC;
2639         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2640
2641         reg = FDI_RX_CTL(pipe);
2642         temp = I915_READ(reg);
2643         temp &= ~FDI_LINK_TRAIN_AUTO;
2644         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2645         temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2646         temp |= FDI_COMPOSITE_SYNC;
2647         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2648
2649         POSTING_READ(reg);
2650         udelay(150);
2651
2652         if (HAS_PCH_CPT(dev))
2653                 cpt_phase_pointer_enable(dev, pipe);
2654
2655         for (i = 0; i < 4; i++) {
2656                 reg = FDI_TX_CTL(pipe);
2657                 temp = I915_READ(reg);
2658                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2659                 temp |= snb_b_fdi_train_param[i];
2660                 I915_WRITE(reg, temp);
2661
2662                 POSTING_READ(reg);
2663                 udelay(500);
2664
2665                 reg = FDI_RX_IIR(pipe);
2666                 temp = I915_READ(reg);
2667                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2668
2669                 if (temp & FDI_RX_BIT_LOCK ||
2670                     (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2671                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2672                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2673                         break;
2674                 }
2675         }
2676         if (i == 4)
2677                 DRM_ERROR("FDI train 1 fail!\n");
2678
2679         /* Train 2 */
2680         reg = FDI_TX_CTL(pipe);
2681         temp = I915_READ(reg);
2682         temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2683         temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2684         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2685         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2686         I915_WRITE(reg, temp);
2687
2688         reg = FDI_RX_CTL(pipe);
2689         temp = I915_READ(reg);
2690         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2691         temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2692         I915_WRITE(reg, temp);
2693
2694         POSTING_READ(reg);
2695         udelay(150);
2696
2697         for (i = 0; i < 4; i++) {
2698                 reg = FDI_TX_CTL(pipe);
2699                 temp = I915_READ(reg);
2700                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2701                 temp |= snb_b_fdi_train_param[i];
2702                 I915_WRITE(reg, temp);
2703
2704                 POSTING_READ(reg);
2705                 udelay(500);
2706
2707                 reg = FDI_RX_IIR(pipe);
2708                 temp = I915_READ(reg);
2709                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2710
2711                 if (temp & FDI_RX_SYMBOL_LOCK) {
2712                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2713                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2714                         break;
2715                 }
2716         }
2717         if (i == 4)
2718                 DRM_ERROR("FDI train 2 fail!\n");
2719
2720         DRM_DEBUG_KMS("FDI train done.\n");
2721 }
2722
2723 static void ironlake_fdi_pll_enable(struct drm_crtc *crtc)
2724 {
2725         struct drm_device *dev = crtc->dev;
2726         struct drm_i915_private *dev_priv = dev->dev_private;
2727         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2728         int pipe = intel_crtc->pipe;
2729         u32 reg, temp;
2730
2731         /* Write the TU size bits so error detection works */
2732         I915_WRITE(FDI_RX_TUSIZE1(pipe),
2733                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
2734
2735         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2736         reg = FDI_RX_CTL(pipe);
2737         temp = I915_READ(reg);
2738         temp &= ~((0x7 << 19) | (0x7 << 16));
2739         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2740         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2741         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2742
2743         POSTING_READ(reg);
2744         udelay(200);
2745
2746         /* Switch from Rawclk to PCDclk */
2747         temp = I915_READ(reg);
2748         I915_WRITE(reg, temp | FDI_PCDCLK);
2749
2750         POSTING_READ(reg);
2751         udelay(200);
2752
2753         /* Enable CPU FDI TX PLL, always on for Ironlake */
2754         reg = FDI_TX_CTL(pipe);
2755         temp = I915_READ(reg);
2756         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2757                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2758
2759                 POSTING_READ(reg);
2760                 udelay(100);
2761         }
2762 }
2763
2764 static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
2765 {
2766         struct drm_i915_private *dev_priv = dev->dev_private;
2767         u32 flags = I915_READ(SOUTH_CHICKEN1);
2768
2769         flags &= ~(FDI_PHASE_SYNC_EN(pipe));
2770         I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
2771         flags &= ~(FDI_PHASE_SYNC_OVR(pipe));
2772         I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
2773         POSTING_READ(SOUTH_CHICKEN1);
2774 }
2775 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2776 {
2777         struct drm_device *dev = crtc->dev;
2778         struct drm_i915_private *dev_priv = dev->dev_private;
2779         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2780         int pipe = intel_crtc->pipe;
2781         u32 reg, temp;
2782
2783         /* disable CPU FDI tx and PCH FDI rx */
2784         reg = FDI_TX_CTL(pipe);
2785         temp = I915_READ(reg);
2786         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2787         POSTING_READ(reg);
2788
2789         reg = FDI_RX_CTL(pipe);
2790         temp = I915_READ(reg);
2791         temp &= ~(0x7 << 16);
2792         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2793         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2794
2795         POSTING_READ(reg);
2796         udelay(100);
2797
2798         /* Ironlake workaround, disable clock pointer after downing FDI */
2799         if (HAS_PCH_IBX(dev)) {
2800                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2801                 I915_WRITE(FDI_RX_CHICKEN(pipe),
2802                            I915_READ(FDI_RX_CHICKEN(pipe) &
2803                                      ~FDI_RX_PHASE_SYNC_POINTER_EN));
2804         } else if (HAS_PCH_CPT(dev)) {
2805                 cpt_phase_pointer_disable(dev, pipe);
2806         }
2807
2808         /* still set train pattern 1 */
2809         reg = FDI_TX_CTL(pipe);
2810         temp = I915_READ(reg);
2811         temp &= ~FDI_LINK_TRAIN_NONE;
2812         temp |= FDI_LINK_TRAIN_PATTERN_1;
2813         I915_WRITE(reg, temp);
2814
2815         reg = FDI_RX_CTL(pipe);
2816         temp = I915_READ(reg);
2817         if (HAS_PCH_CPT(dev)) {
2818                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2819                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2820         } else {
2821                 temp &= ~FDI_LINK_TRAIN_NONE;
2822                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2823         }
2824         /* BPC in FDI rx is consistent with that in PIPECONF */
2825         temp &= ~(0x07 << 16);
2826         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2827         I915_WRITE(reg, temp);
2828
2829         POSTING_READ(reg);
2830         udelay(100);
2831 }
2832
2833 /*
2834  * When we disable a pipe, we need to clear any pending scanline wait events
2835  * to avoid hanging the ring, which we assume we are waiting on.
2836  */
2837 static void intel_clear_scanline_wait(struct drm_device *dev)
2838 {
2839         struct drm_i915_private *dev_priv = dev->dev_private;
2840         struct intel_ring_buffer *ring;
2841         u32 tmp;
2842
2843         if (IS_GEN2(dev))
2844                 /* Can't break the hang on i8xx */
2845                 return;
2846
2847         ring = LP_RING(dev_priv);
2848         tmp = I915_READ_CTL(ring);
2849         if (tmp & RING_WAIT)
2850                 I915_WRITE_CTL(ring, tmp);
2851 }
2852
2853 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2854 {
2855         struct drm_device *dev = crtc->dev;
2856         struct drm_i915_private *dev_priv = dev->dev_private;
2857         unsigned long flags;
2858         bool pending;
2859
2860         if (atomic_read(&dev_priv->mm.wedged))
2861                 return false;
2862
2863         spin_lock_irqsave(&dev->event_lock, flags);
2864         pending = to_intel_crtc(crtc)->unpin_work != NULL;
2865         spin_unlock_irqrestore(&dev->event_lock, flags);
2866
2867         return pending;
2868 }
2869
2870 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2871 {
2872         struct drm_device *dev = crtc->dev;
2873         struct drm_i915_private *dev_priv = dev->dev_private;
2874
2875         if (crtc->fb == NULL)
2876                 return;
2877
2878         wait_event(dev_priv->pending_flip_queue,
2879                    !intel_crtc_has_pending_flip(crtc));
2880
2881         mutex_lock(&dev->struct_mutex);
2882         intel_finish_fb(crtc->fb);
2883         mutex_unlock(&dev->struct_mutex);
2884 }
2885
2886 static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
2887 {
2888         struct drm_device *dev = crtc->dev;
2889         struct drm_mode_config *mode_config = &dev->mode_config;
2890         struct intel_encoder *encoder;
2891
2892         /*
2893          * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2894          * must be driven by its own crtc; no sharing is possible.
2895          */
2896         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
2897                 if (encoder->base.crtc != crtc)
2898                         continue;
2899
2900                 switch (encoder->type) {
2901                 case INTEL_OUTPUT_EDP:
2902                         if (!intel_encoder_is_pch_edp(&encoder->base))
2903                                 return false;
2904                         continue;
2905                 }
2906         }
2907
2908         return true;
2909 }
2910
2911 /*
2912  * Enable PCH resources required for PCH ports:
2913  *   - PCH PLLs
2914  *   - FDI training & RX/TX
2915  *   - update transcoder timings
2916  *   - DP transcoding bits
2917  *   - transcoder
2918  */
2919 static void ironlake_pch_enable(struct drm_crtc *crtc)
2920 {
2921         struct drm_device *dev = crtc->dev;
2922         struct drm_i915_private *dev_priv = dev->dev_private;
2923         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2924         int pipe = intel_crtc->pipe;
2925         u32 reg, temp, transc_sel;
2926
2927         /* For PCH output, training FDI link */
2928         dev_priv->display.fdi_link_train(crtc);
2929
2930         intel_enable_pch_pll(dev_priv, pipe);
2931
2932         if (HAS_PCH_CPT(dev)) {
2933                 transc_sel = intel_crtc->use_pll_a ? TRANSC_DPLLA_SEL :
2934                         TRANSC_DPLLB_SEL;
2935
2936                 /* Be sure PCH DPLL SEL is set */
2937                 temp = I915_READ(PCH_DPLL_SEL);
2938                 if (pipe == 0) {
2939                         temp &= ~(TRANSA_DPLLB_SEL);
2940                         temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
2941                 } else if (pipe == 1) {
2942                         temp &= ~(TRANSB_DPLLB_SEL);
2943                         temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2944                 } else if (pipe == 2) {
2945                         temp &= ~(TRANSC_DPLLB_SEL);
2946                         temp |= (TRANSC_DPLL_ENABLE | transc_sel);
2947                 }
2948                 I915_WRITE(PCH_DPLL_SEL, temp);
2949         }
2950
2951         /* set transcoder timing, panel must allow it */
2952         assert_panel_unlocked(dev_priv, pipe);
2953         I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
2954         I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
2955         I915_WRITE(TRANS_HSYNC(pipe),  I915_READ(HSYNC(pipe)));
2956
2957         I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
2958         I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
2959         I915_WRITE(TRANS_VSYNC(pipe),  I915_READ(VSYNC(pipe)));
2960
2961         intel_fdi_normal_train(crtc);
2962
2963         /* For PCH DP, enable TRANS_DP_CTL */
2964         if (HAS_PCH_CPT(dev) &&
2965             (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
2966              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2967                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
2968                 reg = TRANS_DP_CTL(pipe);
2969                 temp = I915_READ(reg);
2970                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
2971                           TRANS_DP_SYNC_MASK |
2972                           TRANS_DP_BPC_MASK);
2973                 temp |= (TRANS_DP_OUTPUT_ENABLE |
2974                          TRANS_DP_ENH_FRAMING);
2975                 temp |= bpc << 9; /* same format but at 11:9 */
2976
2977                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
2978                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
2979                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
2980                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
2981
2982                 switch (intel_trans_dp_port_sel(crtc)) {
2983                 case PCH_DP_B:
2984                         temp |= TRANS_DP_PORT_SEL_B;
2985                         break;
2986                 case PCH_DP_C:
2987                         temp |= TRANS_DP_PORT_SEL_C;
2988                         break;
2989                 case PCH_DP_D:
2990                         temp |= TRANS_DP_PORT_SEL_D;
2991                         break;
2992                 default:
2993                         DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
2994                         temp |= TRANS_DP_PORT_SEL_B;
2995                         break;
2996                 }
2997
2998                 I915_WRITE(reg, temp);
2999         }
3000
3001         intel_enable_transcoder(dev_priv, pipe);
3002 }
3003
3004 void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
3005 {
3006         struct drm_i915_private *dev_priv = dev->dev_private;
3007         int dslreg = PIPEDSL(pipe), tc2reg = TRANS_CHICKEN2(pipe);
3008         u32 temp;
3009
3010         temp = I915_READ(dslreg);
3011         udelay(500);
3012         if (wait_for(I915_READ(dslreg) != temp, 5)) {
3013                 /* Without this, mode sets may fail silently on FDI */
3014                 I915_WRITE(tc2reg, TRANS_AUTOTRAIN_GEN_STALL_DIS);
3015                 udelay(250);
3016                 I915_WRITE(tc2reg, 0);
3017                 if (wait_for(I915_READ(dslreg) != temp, 5))
3018                         DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
3019         }
3020 }
3021
3022 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3023 {
3024         struct drm_device *dev = crtc->dev;
3025         struct drm_i915_private *dev_priv = dev->dev_private;
3026         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3027         int pipe = intel_crtc->pipe;
3028         int plane = intel_crtc->plane;
3029         u32 temp;
3030         bool is_pch_port;
3031
3032         if (intel_crtc->active)
3033                 return;
3034
3035         intel_crtc->active = true;
3036         intel_update_watermarks(dev);
3037
3038         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3039                 temp = I915_READ(PCH_LVDS);
3040                 if ((temp & LVDS_PORT_EN) == 0)
3041                         I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3042         }
3043
3044         is_pch_port = intel_crtc_driving_pch(crtc);
3045
3046         if (is_pch_port)
3047                 ironlake_fdi_pll_enable(crtc);
3048         else
3049                 ironlake_fdi_disable(crtc);
3050
3051         /* Enable panel fitting for LVDS */
3052         if (dev_priv->pch_pf_size &&
3053             (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
3054                 /* Force use of hard-coded filter coefficients
3055                  * as some pre-programmed values are broken,
3056                  * e.g. x201.
3057                  */
3058                 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3059                 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3060                 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3061         }
3062
3063         /*
3064          * On ILK+ LUT must be loaded before the pipe is running but with
3065          * clocks enabled
3066          */
3067         intel_crtc_load_lut(crtc);
3068
3069         intel_enable_pipe(dev_priv, pipe, is_pch_port);
3070         intel_enable_plane(dev_priv, plane, pipe);
3071
3072         if (is_pch_port)
3073                 ironlake_pch_enable(crtc);
3074
3075         mutex_lock(&dev->struct_mutex);
3076         intel_update_fbc(dev);
3077         mutex_unlock(&dev->struct_mutex);
3078
3079         intel_crtc_update_cursor(crtc, true);
3080 }
3081
3082 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3083 {
3084         struct drm_device *dev = crtc->dev;
3085         struct drm_i915_private *dev_priv = dev->dev_private;
3086         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3087         int pipe = intel_crtc->pipe;
3088         int plane = intel_crtc->plane;
3089         u32 reg, temp;
3090
3091         if (!intel_crtc->active)
3092                 return;
3093
3094         intel_crtc_wait_for_pending_flips(crtc);
3095         drm_vblank_off(dev, pipe);
3096         intel_crtc_update_cursor(crtc, false);
3097
3098         intel_disable_plane(dev_priv, plane, pipe);
3099
3100         if (dev_priv->cfb_plane == plane)
3101                 intel_disable_fbc(dev);
3102
3103         intel_disable_pipe(dev_priv, pipe);
3104
3105         /* Disable PF */
3106         I915_WRITE(PF_CTL(pipe), 0);
3107         I915_WRITE(PF_WIN_SZ(pipe), 0);
3108
3109         ironlake_fdi_disable(crtc);
3110
3111         /* This is a horrible layering violation; we should be doing this in
3112          * the connector/encoder ->prepare instead, but we don't always have
3113          * enough information there about the config to know whether it will
3114          * actually be necessary or just cause undesired flicker.
3115          */
3116         intel_disable_pch_ports(dev_priv, pipe);
3117
3118         intel_disable_transcoder(dev_priv, pipe);
3119
3120         if (HAS_PCH_CPT(dev)) {
3121                 /* disable TRANS_DP_CTL */
3122                 reg = TRANS_DP_CTL(pipe);
3123                 temp = I915_READ(reg);
3124                 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
3125                 temp |= TRANS_DP_PORT_SEL_NONE;
3126                 I915_WRITE(reg, temp);
3127
3128                 /* disable DPLL_SEL */
3129                 temp = I915_READ(PCH_DPLL_SEL);
3130                 switch (pipe) {
3131                 case 0:
3132                         temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
3133                         break;
3134                 case 1:
3135                         temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3136                         break;
3137                 case 2:
3138                         /* C shares PLL A or B */
3139                         temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
3140                         break;
3141                 default:
3142                         BUG(); /* wtf */
3143                 }
3144                 I915_WRITE(PCH_DPLL_SEL, temp);
3145         }
3146
3147         /* disable PCH DPLL */
3148         if (!intel_crtc->no_pll)
3149                 intel_disable_pch_pll(dev_priv, pipe);
3150
3151         /* Switch from PCDclk to Rawclk */
3152         reg = FDI_RX_CTL(pipe);
3153         temp = I915_READ(reg);
3154         I915_WRITE(reg, temp & ~FDI_PCDCLK);
3155
3156         /* Disable CPU FDI TX PLL */
3157         reg = FDI_TX_CTL(pipe);
3158         temp = I915_READ(reg);
3159         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3160
3161         POSTING_READ(reg);
3162         udelay(100);
3163
3164         reg = FDI_RX_CTL(pipe);
3165         temp = I915_READ(reg);
3166         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3167
3168         /* Wait for the clocks to turn off. */
3169         POSTING_READ(reg);
3170         udelay(100);
3171
3172         intel_crtc->active = false;
3173         intel_update_watermarks(dev);
3174
3175         mutex_lock(&dev->struct_mutex);
3176         intel_update_fbc(dev);
3177         intel_clear_scanline_wait(dev);
3178         mutex_unlock(&dev->struct_mutex);
3179 }
3180
3181 static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
3182 {
3183         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3184         int pipe = intel_crtc->pipe;
3185         int plane = intel_crtc->plane;
3186
3187         /* XXX: When our outputs are all unaware of DPMS modes other than off
3188          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3189          */
3190         switch (mode) {
3191         case DRM_MODE_DPMS_ON:
3192         case DRM_MODE_DPMS_STANDBY:
3193         case DRM_MODE_DPMS_SUSPEND:
3194                 DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane);
3195                 ironlake_crtc_enable(crtc);
3196                 break;
3197
3198         case DRM_MODE_DPMS_OFF:
3199                 DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane);
3200                 ironlake_crtc_disable(crtc);
3201                 break;
3202         }
3203 }
3204
3205 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3206 {
3207         if (!enable && intel_crtc->overlay) {
3208                 struct drm_device *dev = intel_crtc->base.dev;
3209                 struct drm_i915_private *dev_priv = dev->dev_private;
3210
3211                 mutex_lock(&dev->struct_mutex);
3212                 dev_priv->mm.interruptible = false;
3213                 (void) intel_overlay_switch_off(intel_crtc->overlay);
3214                 dev_priv->mm.interruptible = true;
3215                 mutex_unlock(&dev->struct_mutex);
3216         }
3217
3218         /* Let userspace switch the overlay on again. In most cases userspace
3219          * has to recompute where to put it anyway.
3220          */
3221 }
3222
3223 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3224 {
3225         struct drm_device *dev = crtc->dev;
3226         struct drm_i915_private *dev_priv = dev->dev_private;
3227         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3228         int pipe = intel_crtc->pipe;
3229         int plane = intel_crtc->plane;
3230
3231         if (intel_crtc->active)
3232                 return;
3233
3234         intel_crtc->active = true;
3235         intel_update_watermarks(dev);
3236
3237         intel_enable_pll(dev_priv, pipe);
3238         intel_enable_pipe(dev_priv, pipe, false);
3239         intel_enable_plane(dev_priv, plane, pipe);
3240
3241         intel_crtc_load_lut(crtc);
3242         intel_update_fbc(dev);
3243
3244         /* Give the overlay scaler a chance to enable if it's on this pipe */
3245         intel_crtc_dpms_overlay(intel_crtc, true);
3246         intel_crtc_update_cursor(crtc, true);
3247 }
3248
3249 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3250 {
3251         struct drm_device *dev = crtc->dev;
3252         struct drm_i915_private *dev_priv = dev->dev_private;
3253         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3254         int pipe = intel_crtc->pipe;
3255         int plane = intel_crtc->plane;
3256
3257         if (!intel_crtc->active)
3258                 return;
3259
3260         /* Give the overlay scaler a chance to disable if it's on this pipe */
3261         intel_crtc_wait_for_pending_flips(crtc);
3262         drm_vblank_off(dev, pipe);
3263         intel_crtc_dpms_overlay(intel_crtc, false);
3264         intel_crtc_update_cursor(crtc, false);
3265
3266         if (dev_priv->cfb_plane == plane)
3267                 intel_disable_fbc(dev);
3268
3269         intel_disable_plane(dev_priv, plane, pipe);
3270         intel_disable_pipe(dev_priv, pipe);
3271         intel_disable_pll(dev_priv, pipe);
3272
3273         intel_crtc->active = false;
3274         intel_update_fbc(dev);
3275         intel_update_watermarks(dev);
3276         intel_clear_scanline_wait(dev);
3277 }
3278
3279 static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
3280 {
3281         /* XXX: When our outputs are all unaware of DPMS modes other than off
3282          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3283          */
3284         switch (mode) {
3285         case DRM_MODE_DPMS_ON:
3286         case DRM_MODE_DPMS_STANDBY:
3287         case DRM_MODE_DPMS_SUSPEND:
3288                 i9xx_crtc_enable(crtc);
3289                 break;
3290         case DRM_MODE_DPMS_OFF:
3291                 i9xx_crtc_disable(crtc);
3292                 break;
3293         }
3294 }
3295
3296 /**
3297  * Sets the power management mode of the pipe and plane.
3298  */
3299 static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
3300 {
3301         struct drm_device *dev = crtc->dev;
3302         struct drm_i915_private *dev_priv = dev->dev_private;
3303         struct drm_i915_master_private *master_priv;
3304         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3305         int pipe = intel_crtc->pipe;
3306         bool enabled;
3307
3308         if (intel_crtc->dpms_mode == mode)
3309                 return;
3310
3311         intel_crtc->dpms_mode = mode;
3312
3313         dev_priv->display.dpms(crtc, mode);
3314
3315         if (!dev->primary->master)
3316                 return;
3317
3318         master_priv = dev->primary->master->driver_priv;
3319         if (!master_priv->sarea_priv)
3320                 return;
3321
3322         enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
3323
3324         switch (pipe) {
3325         case 0:
3326                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3327                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3328                 break;
3329         case 1:
3330                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3331                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3332                 break;
3333         default:
3334                 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3335                 break;
3336         }
3337 }
3338
3339 static void intel_crtc_disable(struct drm_crtc *crtc)
3340 {
3341         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
3342         struct drm_device *dev = crtc->dev;
3343
3344         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
3345
3346         if (crtc->fb) {
3347                 mutex_lock(&dev->struct_mutex);
3348                 i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
3349                 mutex_unlock(&dev->struct_mutex);
3350         }
3351 }
3352
3353 /* Prepare for a mode set.
3354  *
3355  * Note we could be a lot smarter here.  We need to figure out which outputs
3356  * will be enabled, which disabled (in short, how the config will changes)
3357  * and perform the minimum necessary steps to accomplish that, e.g. updating
3358  * watermarks, FBC configuration, making sure PLLs are programmed correctly,
3359  * panel fitting is in the proper state, etc.
3360  */
3361 static void i9xx_crtc_prepare(struct drm_crtc *crtc)
3362 {
3363         i9xx_crtc_disable(crtc);
3364 }
3365
3366 static void i9xx_crtc_commit(struct drm_crtc *crtc)
3367 {
3368         i9xx_crtc_enable(crtc);
3369 }
3370
3371 static void ironlake_crtc_prepare(struct drm_crtc *crtc)
3372 {
3373         ironlake_crtc_disable(crtc);
3374 }
3375
3376 static void ironlake_crtc_commit(struct drm_crtc *crtc)
3377 {
3378         ironlake_crtc_enable(crtc);
3379 }
3380
3381 void intel_encoder_prepare(struct drm_encoder *encoder)
3382 {
3383         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3384         /* lvds has its own version of prepare see intel_lvds_prepare */
3385         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
3386 }
3387
3388 void intel_encoder_commit(struct drm_encoder *encoder)
3389 {
3390         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3391         struct drm_device *dev = encoder->dev;
3392         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3393         struct intel_crtc *intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
3394
3395         /* lvds has its own version of commit see intel_lvds_commit */
3396         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
3397
3398         if (HAS_PCH_CPT(dev))
3399                 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
3400 }
3401
3402 void intel_encoder_destroy(struct drm_encoder *encoder)
3403 {
3404         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3405
3406         drm_encoder_cleanup(encoder);
3407         kfree(intel_encoder);
3408 }
3409
3410 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
3411                                   struct drm_display_mode *mode,
3412                                   struct drm_display_mode *adjusted_mode)
3413 {
3414         struct drm_device *dev = crtc->dev;
3415
3416         if (HAS_PCH_SPLIT(dev)) {
3417                 /* FDI link clock is fixed at 2.7G */
3418                 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3419                         return false;
3420         }
3421
3422         /* XXX some encoders set the crtcinfo, others don't.
3423          * Obviously we need some form of conflict resolution here...
3424          */
3425         if (adjusted_mode->crtc_htotal == 0)
3426                 drm_mode_set_crtcinfo(adjusted_mode, 0);
3427
3428         return true;
3429 }
3430
3431 static int i945_get_display_clock_speed(struct drm_device *dev)
3432 {
3433         return 400000;
3434 }
3435
3436 static int i915_get_display_clock_speed(struct drm_device *dev)
3437 {
3438         return 333000;
3439 }
3440
3441 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3442 {
3443         return 200000;
3444 }
3445
3446 static int i915gm_get_display_clock_speed(struct drm_device *dev)
3447 {
3448         u16 gcfgc = 0;
3449
3450         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3451
3452         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
3453                 return 133000;
3454         else {
3455                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3456                 case GC_DISPLAY_CLOCK_333_MHZ:
3457                         return 333000;
3458                 default:
3459                 case GC_DISPLAY_CLOCK_190_200_MHZ:
3460                         return 190000;
3461                 }
3462         }
3463 }
3464
3465 static int i865_get_display_clock_speed(struct drm_device *dev)
3466 {
3467         return 266000;
3468 }
3469
3470 static int i855_get_display_clock_speed(struct drm_device *dev)
3471 {
3472         u16 hpllcc = 0;
3473         /* Assume that the hardware is in the high speed state.  This
3474          * should be the default.
3475          */
3476         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3477         case GC_CLOCK_133_200:
3478         case GC_CLOCK_100_200:
3479                 return 200000;
3480         case GC_CLOCK_166_250:
3481                 return 250000;
3482         case GC_CLOCK_100_133:
3483                 return 133000;
3484         }
3485
3486         /* Shouldn't happen */
3487         return 0;
3488 }
3489
3490 static int i830_get_display_clock_speed(struct drm_device *dev)
3491 {
3492         return 133000;
3493 }
3494
3495 struct fdi_m_n {
3496         u32        tu;
3497         u32        gmch_m;
3498         u32        gmch_n;
3499         u32        link_m;
3500         u32        link_n;
3501 };
3502
3503 static void
3504 fdi_reduce_ratio(u32 *num, u32 *den)
3505 {
3506         while (*num > 0xffffff || *den > 0xffffff) {
3507                 *num >>= 1;
3508                 *den >>= 1;
3509         }
3510 }
3511
3512 static void
3513 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
3514                      int link_clock, struct fdi_m_n *m_n)
3515 {
3516         m_n->tu = 64; /* default size */
3517
3518         /* BUG_ON(pixel_clock > INT_MAX / 36); */
3519         m_n->gmch_m = bits_per_pixel * pixel_clock;
3520         m_n->gmch_n = link_clock * nlanes * 8;
3521         fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
3522
3523         m_n->link_m = pixel_clock;
3524         m_n->link_n = link_clock;
3525         fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
3526 }
3527
3528
3529 struct intel_watermark_params {
3530         unsigned long fifo_size;
3531         unsigned long max_wm;
3532         unsigned long default_wm;
3533         unsigned long guard_size;
3534         unsigned long cacheline_size;
3535 };
3536
3537 /* Pineview has different values for various configs */
3538 static const struct intel_watermark_params pineview_display_wm = {
3539         PINEVIEW_DISPLAY_FIFO,
3540         PINEVIEW_MAX_WM,
3541         PINEVIEW_DFT_WM,
3542         PINEVIEW_GUARD_WM,
3543         PINEVIEW_FIFO_LINE_SIZE
3544 };
3545 static const struct intel_watermark_params pineview_display_hplloff_wm = {
3546         PINEVIEW_DISPLAY_FIFO,
3547         PINEVIEW_MAX_WM,
3548         PINEVIEW_DFT_HPLLOFF_WM,
3549         PINEVIEW_GUARD_WM,
3550         PINEVIEW_FIFO_LINE_SIZE
3551 };
3552 static const struct intel_watermark_params pineview_cursor_wm = {
3553         PINEVIEW_CURSOR_FIFO,
3554         PINEVIEW_CURSOR_MAX_WM,
3555         PINEVIEW_CURSOR_DFT_WM,
3556         PINEVIEW_CURSOR_GUARD_WM,
3557         PINEVIEW_FIFO_LINE_SIZE,
3558 };
3559 static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
3560         PINEVIEW_CURSOR_FIFO,
3561         PINEVIEW_CURSOR_MAX_WM,
3562         PINEVIEW_CURSOR_DFT_WM,
3563         PINEVIEW_CURSOR_GUARD_WM,
3564         PINEVIEW_FIFO_LINE_SIZE
3565 };
3566 static const struct intel_watermark_params g4x_wm_info = {
3567         G4X_FIFO_SIZE,
3568         G4X_MAX_WM,
3569         G4X_MAX_WM,
3570         2,
3571         G4X_FIFO_LINE_SIZE,
3572 };
3573 static const struct intel_watermark_params g4x_cursor_wm_info = {
3574         I965_CURSOR_FIFO,
3575         I965_CURSOR_MAX_WM,
3576         I965_CURSOR_DFT_WM,
3577         2,
3578         G4X_FIFO_LINE_SIZE,
3579 };
3580 static const struct intel_watermark_params i965_cursor_wm_info = {
3581         I965_CURSOR_FIFO,
3582         I965_CURSOR_MAX_WM,
3583         I965_CURSOR_DFT_WM,
3584         2,
3585         I915_FIFO_LINE_SIZE,
3586 };
3587 static const struct intel_watermark_params i945_wm_info = {
3588         I945_FIFO_SIZE,
3589         I915_MAX_WM,
3590         1,
3591         2,
3592         I915_FIFO_LINE_SIZE
3593 };
3594 static const struct intel_watermark_params i915_wm_info = {
3595         I915_FIFO_SIZE,
3596         I915_MAX_WM,
3597         1,
3598         2,
3599         I915_FIFO_LINE_SIZE
3600 };
3601 static const struct intel_watermark_params i855_wm_info = {
3602         I855GM_FIFO_SIZE,
3603         I915_MAX_WM,
3604         1,
3605         2,
3606         I830_FIFO_LINE_SIZE
3607 };
3608 static const struct intel_watermark_params i830_wm_info = {
3609         I830_FIFO_SIZE,
3610         I915_MAX_WM,
3611         1,
3612         2,
3613         I830_FIFO_LINE_SIZE
3614 };
3615
3616 static const struct intel_watermark_params ironlake_display_wm_info = {
3617         ILK_DISPLAY_FIFO,
3618         ILK_DISPLAY_MAXWM,
3619         ILK_DISPLAY_DFTWM,
3620         2,
3621         ILK_FIFO_LINE_SIZE
3622 };
3623 static const struct intel_watermark_params ironlake_cursor_wm_info = {
3624         ILK_CURSOR_FIFO,
3625         ILK_CURSOR_MAXWM,
3626         ILK_CURSOR_DFTWM,
3627         2,
3628         ILK_FIFO_LINE_SIZE
3629 };
3630 static const struct intel_watermark_params ironlake_display_srwm_info = {
3631         ILK_DISPLAY_SR_FIFO,
3632         ILK_DISPLAY_MAX_SRWM,
3633         ILK_DISPLAY_DFT_SRWM,
3634         2,
3635         ILK_FIFO_LINE_SIZE
3636 };
3637 static const struct intel_watermark_params ironlake_cursor_srwm_info = {
3638         ILK_CURSOR_SR_FIFO,
3639         ILK_CURSOR_MAX_SRWM,
3640         ILK_CURSOR_DFT_SRWM,
3641         2,
3642         ILK_FIFO_LINE_SIZE
3643 };
3644
3645 static const struct intel_watermark_params sandybridge_display_wm_info = {
3646         SNB_DISPLAY_FIFO,
3647         SNB_DISPLAY_MAXWM,
3648         SNB_DISPLAY_DFTWM,
3649         2,
3650         SNB_FIFO_LINE_SIZE
3651 };
3652 static const struct intel_watermark_params sandybridge_cursor_wm_info = {
3653         SNB_CURSOR_FIFO,
3654         SNB_CURSOR_MAXWM,
3655         SNB_CURSOR_DFTWM,
3656         2,
3657         SNB_FIFO_LINE_SIZE
3658 };
3659 static const struct intel_watermark_params sandybridge_display_srwm_info = {
3660         SNB_DISPLAY_SR_FIFO,
3661         SNB_DISPLAY_MAX_SRWM,
3662         SNB_DISPLAY_DFT_SRWM,
3663         2,
3664         SNB_FIFO_LINE_SIZE
3665 };
3666 static const struct intel_watermark_params sandybridge_cursor_srwm_info = {
3667         SNB_CURSOR_SR_FIFO,
3668         SNB_CURSOR_MAX_SRWM,
3669         SNB_CURSOR_DFT_SRWM,
3670         2,
3671         SNB_FIFO_LINE_SIZE
3672 };
3673
3674
3675 /**
3676  * intel_calculate_wm - calculate watermark level
3677  * @clock_in_khz: pixel clock
3678  * @wm: chip FIFO params
3679  * @pixel_size: display pixel size
3680  * @latency_ns: memory latency for the platform
3681  *
3682  * Calculate the watermark level (the level at which the display plane will
3683  * start fetching from memory again).  Each chip has a different display
3684  * FIFO size and allocation, so the caller needs to figure that out and pass
3685  * in the correct intel_watermark_params structure.
3686  *
3687  * As the pixel clock runs, the FIFO will be drained at a rate that depends
3688  * on the pixel size.  When it reaches the watermark level, it'll start
3689  * fetching FIFO line sized based chunks from memory until the FIFO fills
3690  * past the watermark point.  If the FIFO drains completely, a FIFO underrun
3691  * will occur, and a display engine hang could result.
3692  */
3693 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
3694                                         const struct intel_watermark_params *wm,
3695                                         int fifo_size,
3696                                         int pixel_size,
3697                                         unsigned long latency_ns)
3698 {
3699         long entries_required, wm_size;
3700
3701         /*
3702          * Note: we need to make sure we don't overflow for various clock &
3703          * latency values.
3704          * clocks go from a few thousand to several hundred thousand.
3705          * latency is usually a few thousand
3706          */
3707         entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
3708                 1000;
3709         entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
3710
3711         DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
3712
3713         wm_size = fifo_size - (entries_required + wm->guard_size);
3714
3715         DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
3716
3717         /* Don't promote wm_size to unsigned... */
3718         if (wm_size > (long)wm->max_wm)
3719                 wm_size = wm->max_wm;
3720         if (wm_size <= 0)
3721                 wm_size = wm->default_wm;
3722         return wm_size;
3723 }
3724
3725 struct cxsr_latency {
3726         int is_desktop;
3727         int is_ddr3;
3728         unsigned long fsb_freq;
3729         unsigned long mem_freq;
3730         unsigned long display_sr;
3731         unsigned long display_hpll_disable;
3732         unsigned long cursor_sr;
3733         unsigned long cursor_hpll_disable;
3734 };
3735
3736 static const struct cxsr_latency cxsr_latency_table[] = {
3737         {1, 0, 800, 400, 3382, 33382, 3983, 33983},    /* DDR2-400 SC */
3738         {1, 0, 800, 667, 3354, 33354, 3807, 33807},    /* DDR2-667 SC */
3739         {1, 0, 800, 800, 3347, 33347, 3763, 33763},    /* DDR2-800 SC */
3740         {1, 1, 800, 667, 6420, 36420, 6873, 36873},    /* DDR3-667 SC */
3741         {1, 1, 800, 800, 5902, 35902, 6318, 36318},    /* DDR3-800 SC */
3742
3743         {1, 0, 667, 400, 3400, 33400, 4021, 34021},    /* DDR2-400 SC */
3744         {1, 0, 667, 667, 3372, 33372, 3845, 33845},    /* DDR2-667 SC */
3745         {1, 0, 667, 800, 3386, 33386, 3822, 33822},    /* DDR2-800 SC */
3746         {1, 1, 667, 667, 6438, 36438, 6911, 36911},    /* DDR3-667 SC */
3747         {1, 1, 667, 800, 5941, 35941, 6377, 36377},    /* DDR3-800 SC */
3748
3749         {1, 0, 400, 400, 3472, 33472, 4173, 34173},    /* DDR2-400 SC */
3750         {1, 0, 400, 667, 3443, 33443, 3996, 33996},    /* DDR2-667 SC */
3751         {1, 0, 400, 800, 3430, 33430, 3946, 33946},    /* DDR2-800 SC */
3752         {1, 1, 400, 667, 6509, 36509, 7062, 37062},    /* DDR3-667 SC */
3753         {1, 1, 400, 800, 5985, 35985, 6501, 36501},    /* DDR3-800 SC */
3754
3755         {0, 0, 800, 400, 3438, 33438, 4065, 34065},    /* DDR2-400 SC */
3756         {0, 0, 800, 667, 3410, 33410, 3889, 33889},    /* DDR2-667 SC */
3757         {0, 0, 800, 800, 3403, 33403, 3845, 33845},    /* DDR2-800 SC */
3758         {0, 1, 800, 667, 6476, 36476, 6955, 36955},    /* DDR3-667 SC */
3759         {0, 1, 800, 800, 5958, 35958, 6400, 36400},    /* DDR3-800 SC */
3760
3761         {0, 0, 667, 400, 3456, 33456, 4103, 34106},    /* DDR2-400 SC */
3762         {0, 0, 667, 667, 3428, 33428, 3927, 33927},    /* DDR2-667 SC */
3763         {0, 0, 667, 800, 3443, 33443, 3905, 33905},    /* DDR2-800 SC */
3764         {0, 1, 667, 667, 6494, 36494, 6993, 36993},    /* DDR3-667 SC */
3765         {0, 1, 667, 800, 5998, 35998, 6460, 36460},    /* DDR3-800 SC */
3766
3767         {0, 0, 400, 400, 3528, 33528, 4255, 34255},    /* DDR2-400 SC */
3768         {0, 0, 400, 667, 3500, 33500, 4079, 34079},    /* DDR2-667 SC */
3769         {0, 0, 400, 800, 3487, 33487, 4029, 34029},    /* DDR2-800 SC */
3770         {0, 1, 400, 667, 6566, 36566, 7145, 37145},    /* DDR3-667 SC */
3771         {0, 1, 400, 800, 6042, 36042, 6584, 36584},    /* DDR3-800 SC */
3772 };
3773
3774 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
3775                                                          int is_ddr3,
3776                                                          int fsb,
3777                                                          int mem)
3778 {
3779         const struct cxsr_latency *latency;
3780         int i;
3781
3782         if (fsb == 0 || mem == 0)
3783                 return NULL;
3784
3785         for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
3786                 latency = &cxsr_latency_table[i];
3787                 if (is_desktop == latency->is_desktop &&
3788                     is_ddr3 == latency->is_ddr3 &&
3789                     fsb == latency->fsb_freq && mem == latency->mem_freq)
3790                         return latency;
3791         }
3792
3793         DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3794
3795         return NULL;
3796 }
3797
3798 static void pineview_disable_cxsr(struct drm_device *dev)
3799 {
3800         struct drm_i915_private *dev_priv = dev->dev_private;
3801
3802         /* deactivate cxsr */
3803         I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
3804 }
3805
3806 /*
3807  * Latency for FIFO fetches is dependent on several factors:
3808  *   - memory configuration (speed, channels)
3809  *   - chipset
3810  *   - current MCH state
3811  * It can be fairly high in some situations, so here we assume a fairly
3812  * pessimal value.  It's a tradeoff between extra memory fetches (if we
3813  * set this value too high, the FIFO will fetch frequently to stay full)
3814  * and power consumption (set it too low to save power and we might see
3815  * FIFO underruns and display "flicker").
3816  *
3817  * A value of 5us seems to be a good balance; safe for very low end
3818  * platforms but not overly aggressive on lower latency configs.
3819  */
3820 static const int latency_ns = 5000;
3821
3822 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
3823 {
3824         struct drm_i915_private *dev_priv = dev->dev_private;
3825         uint32_t dsparb = I915_READ(DSPARB);
3826         int size;
3827
3828         size = dsparb & 0x7f;
3829         if (plane)
3830                 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
3831
3832         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3833                       plane ? "B" : "A", size);
3834
3835         return size;
3836 }
3837
3838 static int i85x_get_fifo_size(struct drm_device *dev, int plane)
3839 {
3840         struct drm_i915_private *dev_priv = dev->dev_private;
3841         uint32_t dsparb = I915_READ(DSPARB);
3842         int size;
3843
3844         size = dsparb & 0x1ff;
3845         if (plane)
3846                 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
3847         size >>= 1; /* Convert to cachelines */
3848
3849         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3850                       plane ? "B" : "A", size);
3851
3852         return size;
3853 }
3854
3855 static int i845_get_fifo_size(struct drm_device *dev, int plane)
3856 {
3857         struct drm_i915_private *dev_priv = dev->dev_private;
3858         uint32_t dsparb = I915_READ(DSPARB);
3859         int size;
3860
3861         size = dsparb & 0x7f;
3862         size >>= 2; /* Convert to cachelines */
3863
3864         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3865                       plane ? "B" : "A",
3866                       size);
3867
3868         return size;
3869 }
3870
3871 static int i830_get_fifo_size(struct drm_device *dev, int plane)
3872 {
3873         struct drm_i915_private *dev_priv = dev->dev_private;
3874         uint32_t dsparb = I915_READ(DSPARB);
3875         int size;
3876
3877         size = dsparb & 0x7f;
3878         size >>= 1; /* Convert to cachelines */
3879
3880         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3881                       plane ? "B" : "A", size);
3882
3883         return size;
3884 }
3885
3886 static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
3887 {
3888         struct drm_crtc *crtc, *enabled = NULL;
3889
3890         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3891                 if (crtc->enabled && crtc->fb) {
3892                         if (enabled)
3893                                 return NULL;
3894                         enabled = crtc;
3895                 }
3896         }
3897
3898         return enabled;
3899 }
3900
3901 static void pineview_update_wm(struct drm_device *dev)
3902 {
3903         struct drm_i915_private *dev_priv = dev->dev_private;
3904         struct drm_crtc *crtc;
3905         const struct cxsr_latency *latency;
3906         u32 reg;
3907         unsigned long wm;
3908
3909         latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
3910                                          dev_priv->fsb_freq, dev_priv->mem_freq);
3911         if (!latency) {
3912                 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3913                 pineview_disable_cxsr(dev);
3914                 return;
3915         }
3916
3917         crtc = single_enabled_crtc(dev);
3918         if (crtc) {
3919                 int clock = crtc->mode.clock;
3920                 int pixel_size = crtc->fb->bits_per_pixel / 8;
3921
3922                 /* Display SR */
3923                 wm = intel_calculate_wm(clock, &pineview_display_wm,
3924                                         pineview_display_wm.fifo_size,
3925                                         pixel_size, latency->display_sr);
3926                 reg = I915_READ(DSPFW1);
3927                 reg &= ~DSPFW_SR_MASK;
3928                 reg |= wm << DSPFW_SR_SHIFT;
3929                 I915_WRITE(DSPFW1, reg);
3930                 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
3931
3932                 /* cursor SR */
3933                 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
3934                                         pineview_display_wm.fifo_size,
3935                                         pixel_size, latency->cursor_sr);
3936                 reg = I915_READ(DSPFW3);
3937                 reg &= ~DSPFW_CURSOR_SR_MASK;
3938                 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
3939                 I915_WRITE(DSPFW3, reg);
3940
3941                 /* Display HPLL off SR */
3942                 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
3943                                         pineview_display_hplloff_wm.fifo_size,
3944                                         pixel_size, latency->display_hpll_disable);
3945                 reg = I915_READ(DSPFW3);
3946                 reg &= ~DSPFW_HPLL_SR_MASK;
3947                 reg |= wm & DSPFW_HPLL_SR_MASK;
3948                 I915_WRITE(DSPFW3, reg);
3949
3950                 /* cursor HPLL off SR */
3951                 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
3952                                         pineview_display_hplloff_wm.fifo_size,
3953                                         pixel_size, latency->cursor_hpll_disable);
3954                 reg = I915_READ(DSPFW3);
3955                 reg &= ~DSPFW_HPLL_CURSOR_MASK;
3956                 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
3957                 I915_WRITE(DSPFW3, reg);
3958                 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
3959
3960                 /* activate cxsr */
3961                 I915_WRITE(DSPFW3,
3962                            I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
3963                 DRM_DEBUG_KMS("Self-refresh is enabled\n");
3964         } else {
3965                 pineview_disable_cxsr(dev);
3966                 DRM_DEBUG_KMS("Self-refresh is disabled\n");
3967         }
3968 }
3969
3970 static bool g4x_compute_wm0(struct drm_device *dev,
3971                             int plane,
3972                             const struct intel_watermark_params *display,
3973                             int display_latency_ns,
3974                             const struct intel_watermark_params *cursor,
3975                             int cursor_latency_ns,
3976                             int *plane_wm,
3977                             int *cursor_wm)
3978 {
3979         struct drm_crtc *crtc;
3980         int htotal, hdisplay, clock, pixel_size;
3981         int line_time_us, line_count;
3982         int entries, tlb_miss;
3983
3984         crtc = intel_get_crtc_for_plane(dev, plane);
3985         if (crtc->fb == NULL || !crtc->enabled) {
3986                 *cursor_wm = cursor->guard_size;
3987                 *plane_wm = display->guard_size;
3988                 return false;
3989         }
3990
3991         htotal = crtc->mode.htotal;
3992         hdisplay = crtc->mode.hdisplay;
3993         clock = crtc->mode.clock;
3994         pixel_size = crtc->fb->bits_per_pixel / 8;
3995
3996         /* Use the small buffer method to calculate plane watermark */
3997         entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
3998         tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
3999         if (tlb_miss > 0)
4000                 entries += tlb_miss;
4001         entries = DIV_ROUND_UP(entries, display->cacheline_size);
4002         *plane_wm = entries + display->guard_size;
4003         if (*plane_wm > (int)display->max_wm)
4004                 *plane_wm = display->max_wm;
4005
4006         /* Use the large buffer method to calculate cursor watermark */
4007         line_time_us = ((htotal * 1000) / clock);
4008         line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
4009         entries = line_count * 64 * pixel_size;
4010         tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
4011         if (tlb_miss > 0)
4012                 entries += tlb_miss;
4013         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
4014         *cursor_wm = entries + cursor->guard_size;
4015         if (*cursor_wm > (int)cursor->max_wm)
4016                 *cursor_wm = (int)cursor->max_wm;
4017
4018         return true;
4019 }
4020
4021 /*
4022  * Check the wm result.
4023  *
4024  * If any calculated watermark values is larger than the maximum value that
4025  * can be programmed into the associated watermark register, that watermark
4026  * must be disabled.
4027  */
4028 static bool g4x_check_srwm(struct drm_device *dev,
4029                            int display_wm, int cursor_wm,
4030                            const struct intel_watermark_params *display,
4031                            const struct intel_watermark_params *cursor)
4032 {
4033         DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
4034                       display_wm, cursor_wm);
4035
4036         if (display_wm > display->max_wm) {
4037                 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
4038                               display_wm, display->max_wm);
4039                 return false;
4040         }
4041
4042         if (cursor_wm > cursor->max_wm) {
4043                 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
4044                               cursor_wm, cursor->max_wm);
4045                 return false;
4046         }
4047
4048         if (!(display_wm || cursor_wm)) {
4049                 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
4050                 return false;
4051         }
4052
4053         return true;
4054 }
4055
4056 static bool g4x_compute_srwm(struct drm_device *dev,
4057                              int plane,
4058                              int latency_ns,
4059                              const struct intel_watermark_params *display,
4060                              const struct intel_watermark_params *cursor,
4061                              int *display_wm, int *cursor_wm)
4062 {
4063         struct drm_crtc *crtc;
4064         int hdisplay, htotal, pixel_size, clock;
4065         unsigned long line_time_us;
4066         int line_count, line_size;
4067         int small, large;
4068         int entries;
4069
4070         if (!latency_ns) {
4071                 *display_wm = *cursor_wm = 0;
4072                 return false;
4073         }
4074
4075         crtc = intel_get_crtc_for_plane(dev, plane);
4076         hdisplay = crtc->mode.hdisplay;
4077         htotal = crtc->mode.htotal;
4078         clock = crtc->mode.clock;
4079         pixel_size = crtc->fb->bits_per_pixel / 8;
4080
4081         line_time_us = (htotal * 1000) / clock;
4082         line_count = (latency_ns / line_time_us + 1000) / 1000;
4083         line_size = hdisplay * pixel_size;
4084
4085         /* Use the minimum of the small and large buffer method for primary */
4086         small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
4087         large = line_count * line_size;
4088
4089         entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
4090         *display_wm = entries + display->guard_size;
4091
4092         /* calculate the self-refresh watermark for display cursor */
4093         entries = line_count * pixel_size * 64;
4094         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
4095         *cursor_wm = entries + cursor->guard_size;
4096
4097         return g4x_check_srwm(dev,
4098                               *display_wm, *cursor_wm,
4099                               display, cursor);
4100 }
4101
4102 #define single_plane_enabled(mask) is_power_of_2(mask)
4103
4104 static void g4x_update_wm(struct drm_device *dev)
4105 {
4106         static const int sr_latency_ns = 12000;
4107         struct drm_i915_private *dev_priv = dev->dev_private;
4108         int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
4109         int plane_sr, cursor_sr;
4110         unsigned int enabled = 0;
4111
4112         if (g4x_compute_wm0(dev, 0,
4113                             &g4x_wm_info, latency_ns,
4114                             &g4x_cursor_wm_info, latency_ns,
4115                             &planea_wm, &cursora_wm))
4116                 enabled |= 1;
4117
4118         if (g4x_compute_wm0(dev, 1,
4119                             &g4x_wm_info, latency_ns,
4120                             &g4x_cursor_wm_info, latency_ns,
4121                             &planeb_wm, &cursorb_wm))
4122                 enabled |= 2;
4123
4124         plane_sr = cursor_sr = 0;
4125         if (single_plane_enabled(enabled) &&
4126             g4x_compute_srwm(dev, ffs(enabled) - 1,
4127                              sr_latency_ns,
4128                              &g4x_wm_info,
4129                              &g4x_cursor_wm_info,
4130                              &plane_sr, &cursor_sr))
4131                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
4132         else
4133                 I915_WRITE(FW_BLC_SELF,
4134                            I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
4135
4136         DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
4137                       planea_wm, cursora_wm,
4138                       planeb_wm, cursorb_wm,
4139                       plane_sr, cursor_sr);
4140
4141         I915_WRITE(DSPFW1,
4142                    (plane_sr << DSPFW_SR_SHIFT) |
4143                    (cursorb_wm << DSPFW_CURSORB_SHIFT) |
4144                    (planeb_wm << DSPFW_PLANEB_SHIFT) |
4145                    planea_wm);
4146         I915_WRITE(DSPFW2,
4147                    (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
4148                    (cursora_wm << DSPFW_CURSORA_SHIFT));
4149         /* HPLL off in SR has some issues on G4x... disable it */
4150         I915_WRITE(DSPFW3,
4151                    (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
4152                    (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
4153 }
4154
4155 static void i965_update_wm(struct drm_device *dev)
4156 {
4157         struct drm_i915_private *dev_priv = dev->dev_private;
4158         struct drm_crtc *crtc;
4159         int srwm = 1;
4160         int cursor_sr = 16;
4161
4162         /* Calc sr entries for one plane configs */
4163         crtc = single_enabled_crtc(dev);
4164         if (crtc) {
4165                 /* self-refresh has much higher latency */
4166                 static const int sr_latency_ns = 12000;
4167                 int clock = crtc->mode.clock;
4168                 int htotal = crtc->mode.htotal;
4169                 int hdisplay = crtc->mode.hdisplay;
4170                 int pixel_size = crtc->fb->bits_per_pixel / 8;
4171                 unsigned long line_time_us;
4172                 int entries;
4173
4174                 line_time_us = ((htotal * 1000) / clock);
4175
4176                 /* Use ns/us then divide to preserve precision */
4177                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
4178                         pixel_size * hdisplay;
4179                 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
4180                 srwm = I965_FIFO_SIZE - entries;
4181                 if (srwm < 0)
4182                         srwm = 1;
4183                 srwm &= 0x1ff;
4184                 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
4185                               entries, srwm);
4186
4187                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
4188                         pixel_size * 64;
4189                 entries = DIV_ROUND_UP(entries,
4190                                           i965_cursor_wm_info.cacheline_size);
4191                 cursor_sr = i965_cursor_wm_info.fifo_size -
4192                         (entries + i965_cursor_wm_info.guard_size);
4193
4194                 if (cursor_sr > i965_cursor_wm_info.max_wm)
4195                         cursor_sr = i965_cursor_wm_info.max_wm;
4196
4197                 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
4198                               "cursor %d\n", srwm, cursor_sr);
4199
4200                 if (IS_CRESTLINE(dev))
4201                         I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
4202         } else {
4203                 /* Turn off self refresh if both pipes are enabled */
4204                 if (IS_CRESTLINE(dev))
4205                         I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
4206                                    & ~FW_BLC_SELF_EN);
4207         }
4208
4209         DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
4210                       srwm);
4211
4212         /* 965 has limitations... */
4213         I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
4214                    (8 << 16) | (8 << 8) | (8 << 0));
4215         I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
4216         /* update cursor SR watermark */
4217         I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
4218 }
4219
4220 static void i9xx_update_wm(struct drm_device *dev)
4221 {
4222         struct drm_i915_private *dev_priv = dev->dev_private;
4223         const struct intel_watermark_params *wm_info;
4224         uint32_t fwater_lo;
4225         uint32_t fwater_hi;
4226         int cwm, srwm = 1;
4227         int fifo_size;
4228         int planea_wm, planeb_wm;
4229         struct drm_crtc *crtc, *enabled = NULL;
4230
4231         if (IS_I945GM(dev))
4232                 wm_info = &i945_wm_info;
4233         else if (!IS_GEN2(dev))
4234                 wm_info = &i915_wm_info;
4235         else
4236                 wm_info = &i855_wm_info;
4237
4238         fifo_size = dev_priv->display.get_fifo_size(dev, 0);
4239         crtc = intel_get_crtc_for_plane(dev, 0);
4240         if (crtc->enabled && crtc->fb) {
4241                 planea_wm = intel_calculate_wm(crtc->mode.clock,
4242                                                wm_info, fifo_size,
4243                                                crtc->fb->bits_per_pixel / 8,
4244                                                latency_ns);
4245                 enabled = crtc;
4246         } else
4247                 planea_wm = fifo_size - wm_info->guard_size;
4248
4249         fifo_size = dev_priv->display.get_fifo_size(dev, 1);
4250         crtc = intel_get_crtc_for_plane(dev, 1);
4251         if (crtc->enabled && crtc->fb) {
4252                 planeb_wm = intel_calculate_wm(crtc->mode.clock,
4253                                                wm_info, fifo_size,
4254                                                crtc->fb->bits_per_pixel / 8,
4255                                                latency_ns);
4256                 if (enabled == NULL)
4257                         enabled = crtc;
4258                 else
4259                         enabled = NULL;
4260         } else
4261                 planeb_wm = fifo_size - wm_info->guard_size;
4262
4263         DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
4264
4265         /*
4266          * Overlay gets an aggressive default since video jitter is bad.
4267          */
4268         cwm = 2;
4269
4270         /* Play safe and disable self-refresh before adjusting watermarks. */
4271         if (IS_I945G(dev) || IS_I945GM(dev))
4272                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0);
4273         else if (IS_I915GM(dev))
4274                 I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
4275
4276         /* Calc sr entries for one plane configs */
4277         if (HAS_FW_BLC(dev) && enabled) {
4278                 /* self-refresh has much higher latency */
4279                 static const int sr_latency_ns = 6000;
4280                 int clock = enabled->mode.clock;
4281                 int htotal = enabled->mode.htotal;
4282                 int hdisplay = enabled->mode.hdisplay;
4283                 int pixel_size = enabled->fb->bits_per_pixel / 8;
4284                 unsigned long line_time_us;
4285                 int entries;
4286
4287                 line_time_us = (htotal * 1000) / clock;
4288
4289                 /* Use ns/us then divide to preserve precision */
4290                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
4291                         pixel_size * hdisplay;
4292                 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
4293                 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
4294                 srwm = wm_info->fifo_size - entries;
4295                 if (srwm < 0)
4296                         srwm = 1;
4297
4298                 if (IS_I945G(dev) || IS_I945GM(dev))
4299                         I915_WRITE(FW_BLC_SELF,
4300                                    FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
4301                 else if (IS_I915GM(dev))
4302                         I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
4303         }
4304
4305         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
4306                       planea_wm, planeb_wm, cwm, srwm);
4307
4308         fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
4309         fwater_hi = (cwm & 0x1f);
4310
4311         /* Set request length to 8 cachelines per fetch */
4312         fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
4313         fwater_hi = fwater_hi | (1 << 8);
4314
4315         I915_WRITE(FW_BLC, fwater_lo);
4316         I915_WRITE(FW_BLC2, fwater_hi);
4317
4318         if (HAS_FW_BLC(dev)) {
4319                 if (enabled) {
4320                         if (IS_I945G(dev) || IS_I945GM(dev))
4321                                 I915_WRITE(FW_BLC_SELF,
4322                                            FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
4323                         else if (IS_I915GM(dev))
4324                                 I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
4325                         DRM_DEBUG_KMS("memory self refresh enabled\n");
4326                 } else
4327                         DRM_DEBUG_KMS("memory self refresh disabled\n");
4328         }
4329 }
4330
4331 static void i830_update_wm(struct drm_device *dev)
4332 {
4333         struct drm_i915_private *dev_priv = dev->dev_private;
4334         struct drm_crtc *crtc;
4335         uint32_t fwater_lo;
4336         int planea_wm;
4337
4338         crtc = single_enabled_crtc(dev);
4339         if (crtc == NULL)
4340                 return;
4341
4342         planea_wm = intel_calculate_wm(crtc->mode.clock, &i830_wm_info,
4343                                        dev_priv->display.get_fifo_size(dev, 0),
4344                                        crtc->fb->bits_per_pixel / 8,
4345                                        latency_ns);
4346         fwater_lo = I915_READ(FW_BLC) & ~0xfff;
4347         fwater_lo |= (3<<8) | planea_wm;
4348
4349         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
4350
4351         I915_WRITE(FW_BLC, fwater_lo);
4352 }
4353
4354 #define ILK_LP0_PLANE_LATENCY           700
4355 #define ILK_LP0_CURSOR_LATENCY          1300
4356
4357 /*
4358  * Check the wm result.
4359  *
4360  * If any calculated watermark values is larger than the maximum value that
4361  * can be programmed into the associated watermark register, that watermark
4362  * must be disabled.
4363  */
4364 static bool ironlake_check_srwm(struct drm_device *dev, int level,
4365                                 int fbc_wm, int display_wm, int cursor_wm,
4366                                 const struct intel_watermark_params *display,
4367                                 const struct intel_watermark_params *cursor)
4368 {
4369         struct drm_i915_private *dev_priv = dev->dev_private;
4370
4371         DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d,"
4372                       " cursor %d\n", level, display_wm, fbc_wm, cursor_wm);
4373
4374         if (fbc_wm > SNB_FBC_MAX_SRWM) {
4375                 DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n",
4376                               fbc_wm, SNB_FBC_MAX_SRWM, level);
4377
4378                 /* fbc has it's own way to disable FBC WM */
4379                 I915_WRITE(DISP_ARB_CTL,
4380                            I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS);
4381                 return false;
4382         }
4383
4384         if (display_wm > display->max_wm) {
4385                 DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n",
4386                               display_wm, SNB_DISPLAY_MAX_SRWM, level);
4387                 return false;
4388         }
4389
4390         if (cursor_wm > cursor->max_wm) {
4391                 DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n",
4392                               cursor_wm, SNB_CURSOR_MAX_SRWM, level);
4393                 return false;
4394         }
4395
4396         if (!(fbc_wm || display_wm || cursor_wm)) {
4397                 DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level);
4398                 return false;
4399         }
4400
4401         return true;
4402 }
4403
4404 /*
4405  * Compute watermark values of WM[1-3],
4406  */
4407 static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane,
4408                                   int latency_ns,
4409                                   const struct intel_watermark_params *display,
4410                                   const struct intel_watermark_params *cursor,
4411                                   int *fbc_wm, int *display_wm, int *cursor_wm)
4412 {
4413         struct drm_crtc *crtc;
4414         unsigned long line_time_us;
4415         int hdisplay, htotal, pixel_size, clock;
4416         int line_count, line_size;
4417         int small, large;
4418         int entries;
4419
4420         if (!latency_ns) {
4421                 *fbc_wm = *display_wm = *cursor_wm = 0;
4422                 return false;
4423         }
4424
4425         crtc = intel_get_crtc_for_plane(dev, plane);
4426         hdisplay = crtc->mode.hdisplay;
4427         htotal = crtc->mode.htotal;
4428         clock = crtc->mode.clock;
4429         pixel_size = crtc->fb->bits_per_pixel / 8;
4430
4431         line_time_us = (htotal * 1000) / clock;
4432         line_count = (latency_ns / line_time_us + 1000) / 1000;
4433         line_size = hdisplay * pixel_size;
4434
4435         /* Use the minimum of the small and large buffer method for primary */
4436         small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
4437         large = line_count * line_size;
4438
4439         entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
4440         *display_wm = entries + display->guard_size;
4441
4442         /*
4443          * Spec says:
4444          * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2
4445          */
4446         *fbc_wm = DIV_ROUND_UP(*display_wm * 64, line_size) + 2;
4447
4448         /* calculate the self-refresh watermark for display cursor */
4449         entries = line_count * pixel_size * 64;
4450         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
4451         *cursor_wm = entries + cursor->guard_size;
4452
4453         return ironlake_check_srwm(dev, level,
4454                                    *fbc_wm, *display_wm, *cursor_wm,
4455                                    display, cursor);
4456 }
4457
4458 static void ironlake_update_wm(struct drm_device *dev)
4459 {
4460         struct drm_i915_private *dev_priv = dev->dev_private;
4461         int fbc_wm, plane_wm, cursor_wm;
4462         unsigned int enabled;
4463
4464         enabled = 0;
4465         if (g4x_compute_wm0(dev, 0,
4466                             &ironlake_display_wm_info,
4467                             ILK_LP0_PLANE_LATENCY,
4468                             &ironlake_cursor_wm_info,
4469                             ILK_LP0_CURSOR_LATENCY,
4470                             &plane_wm, &cursor_wm)) {
4471                 I915_WRITE(WM0_PIPEA_ILK,
4472                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4473                 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
4474                               " plane %d, " "cursor: %d\n",
4475                               plane_wm, cursor_wm);
4476                 enabled |= 1;
4477         }
4478
4479         if (g4x_compute_wm0(dev, 1,
4480                             &ironlake_display_wm_info,
4481                             ILK_LP0_PLANE_LATENCY,
4482                             &ironlake_cursor_wm_info,
4483                             ILK_LP0_CURSOR_LATENCY,
4484                             &plane_wm, &cursor_wm)) {
4485                 I915_WRITE(WM0_PIPEB_ILK,
4486                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4487                 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
4488                               " plane %d, cursor: %d\n",
4489                               plane_wm, cursor_wm);
4490                 enabled |= 2;
4491         }
4492
4493         /*
4494          * Calculate and update the self-refresh watermark only when one
4495          * display plane is used.
4496          */
4497         I915_WRITE(WM3_LP_ILK, 0);
4498         I915_WRITE(WM2_LP_ILK, 0);
4499         I915_WRITE(WM1_LP_ILK, 0);
4500
4501         if (!single_plane_enabled(enabled))
4502                 return;
4503         enabled = ffs(enabled) - 1;
4504
4505         /* WM1 */
4506         if (!ironlake_compute_srwm(dev, 1, enabled,
4507                                    ILK_READ_WM1_LATENCY() * 500,
4508                                    &ironlake_display_srwm_info,
4509                                    &ironlake_cursor_srwm_info,
4510                                    &fbc_wm, &plane_wm, &cursor_wm))
4511                 return;
4512
4513         I915_WRITE(WM1_LP_ILK,
4514                    WM1_LP_SR_EN |
4515                    (ILK_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4516                    (fbc_wm << WM1_LP_FBC_SHIFT) |
4517                    (plane_wm << WM1_LP_SR_SHIFT) |
4518                    cursor_wm);
4519
4520         /* WM2 */
4521         if (!ironlake_compute_srwm(dev, 2, enabled,
4522                                    ILK_READ_WM2_LATENCY() * 500,
4523                                    &ironlake_display_srwm_info,
4524                                    &ironlake_cursor_srwm_info,
4525                                    &fbc_wm, &plane_wm, &cursor_wm))
4526                 return;
4527
4528         I915_WRITE(WM2_LP_ILK,
4529                    WM2_LP_EN |
4530                    (ILK_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4531                    (fbc_wm << WM1_LP_FBC_SHIFT) |
4532                    (plane_wm << WM1_LP_SR_SHIFT) |
4533                    cursor_wm);
4534
4535         /*
4536          * WM3 is unsupported on ILK, probably because we don't have latency
4537          * data for that power state
4538          */
4539 }
4540
4541 static void sandybridge_update_wm(struct drm_device *dev)
4542 {
4543         struct drm_i915_private *dev_priv = dev->dev_private;
4544         int latency = SNB_READ_WM0_LATENCY() * 100;     /* In unit 0.1us */
4545         int fbc_wm, plane_wm, cursor_wm;
4546         unsigned int enabled;
4547
4548         enabled = 0;
4549         if (g4x_compute_wm0(dev, 0,
4550                             &sandybridge_display_wm_info, latency,
4551                             &sandybridge_cursor_wm_info, latency,
4552                             &plane_wm, &cursor_wm)) {
4553                 I915_WRITE(WM0_PIPEA_ILK,
4554                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4555                 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
4556                               " plane %d, " "cursor: %d\n",
4557                               plane_wm, cursor_wm);
4558                 enabled |= 1;
4559         }
4560
4561         if (g4x_compute_wm0(dev, 1,
4562                             &sandybridge_display_wm_info, latency,
4563                             &sandybridge_cursor_wm_info, latency,
4564                             &plane_wm, &cursor_wm)) {
4565                 I915_WRITE(WM0_PIPEB_ILK,
4566                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4567                 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
4568                               " plane %d, cursor: %d\n",
4569                               plane_wm, cursor_wm);
4570                 enabled |= 2;
4571         }
4572
4573         /* IVB has 3 pipes */
4574         if (IS_IVYBRIDGE(dev) &&
4575             g4x_compute_wm0(dev, 2,
4576                             &sandybridge_display_wm_info, latency,
4577                             &sandybridge_cursor_wm_info, latency,
4578                             &plane_wm, &cursor_wm)) {
4579                 I915_WRITE(WM0_PIPEC_IVB,
4580                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4581                 DRM_DEBUG_KMS("FIFO watermarks For pipe C -"
4582                               " plane %d, cursor: %d\n",
4583                               plane_wm, cursor_wm);
4584                 enabled |= 3;
4585         }
4586
4587         /*
4588          * Calculate and update the self-refresh watermark only when one
4589          * display plane is used.
4590          *
4591          * SNB support 3 levels of watermark.
4592          *
4593          * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
4594          * and disabled in the descending order
4595          *
4596          */
4597         I915_WRITE(WM3_LP_ILK, 0);
4598         I915_WRITE(WM2_LP_ILK, 0);
4599         I915_WRITE(WM1_LP_ILK, 0);
4600
4601         if (!single_plane_enabled(enabled))
4602                 return;
4603         enabled = ffs(enabled) - 1;
4604
4605         /* WM1 */
4606         if (!ironlake_compute_srwm(dev, 1, enabled,
4607                                    SNB_READ_WM1_LATENCY() * 500,
4608                                    &sandybridge_display_srwm_info,
4609                                    &sandybridge_cursor_srwm_info,
4610                                    &fbc_wm, &plane_wm, &cursor_wm))
4611                 return;
4612
4613         I915_WRITE(WM1_LP_ILK,
4614                    WM1_LP_SR_EN |
4615                    (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4616                    (fbc_wm << WM1_LP_FBC_SHIFT) |
4617                    (plane_wm << WM1_LP_SR_SHIFT) |
4618                    cursor_wm);
4619
4620         /* WM2 */
4621         if (!ironlake_compute_srwm(dev, 2, enabled,
4622                                    SNB_READ_WM2_LATENCY() * 500,
4623                                    &sandybridge_display_srwm_info,
4624                                    &sandybridge_cursor_srwm_info,
4625                                    &fbc_wm, &plane_wm, &cursor_wm))
4626                 return;
4627
4628         I915_WRITE(WM2_LP_ILK,
4629                    WM2_LP_EN |
4630                    (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4631                    (fbc_wm << WM1_LP_FBC_SHIFT) |
4632                    (plane_wm << WM1_LP_SR_SHIFT) |
4633                    cursor_wm);
4634
4635         /* WM3 */
4636         if (!ironlake_compute_srwm(dev, 3, enabled,
4637                                    SNB_READ_WM3_LATENCY() * 500,
4638                                    &sandybridge_display_srwm_info,
4639                                    &sandybridge_cursor_srwm_info,
4640                                    &fbc_wm, &plane_wm, &cursor_wm))
4641                 return;
4642
4643         I915_WRITE(WM3_LP_ILK,
4644                    WM3_LP_EN |
4645                    (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4646                    (fbc_wm << WM1_LP_FBC_SHIFT) |
4647                    (plane_wm << WM1_LP_SR_SHIFT) |
4648                    cursor_wm);
4649 }
4650
4651 /**
4652  * intel_update_watermarks - update FIFO watermark values based on current modes
4653  *
4654  * Calculate watermark values for the various WM regs based on current mode
4655  * and plane configuration.
4656  *
4657  * There are several cases to deal with here:
4658  *   - normal (i.e. non-self-refresh)
4659  *   - self-refresh (SR) mode
4660  *   - lines are large relative to FIFO size (buffer can hold up to 2)
4661  *   - lines are small relative to FIFO size (buffer can hold more than 2
4662  *     lines), so need to account for TLB latency
4663  *
4664  *   The normal calculation is:
4665  *     watermark = dotclock * bytes per pixel * latency
4666  *   where latency is platform & configuration dependent (we assume pessimal
4667  *   values here).
4668  *
4669  *   The SR calculation is:
4670  *     watermark = (trunc(latency/line time)+1) * surface width *
4671  *       bytes per pixel
4672  *   where
4673  *     line time = htotal / dotclock
4674  *     surface width = hdisplay for normal plane and 64 for cursor
4675  *   and latency is assumed to be high, as above.
4676  *
4677  * The final value programmed to the register should always be rounded up,
4678  * and include an extra 2 entries to account for clock crossings.
4679  *
4680  * We don't use the sprite, so we can ignore that.  And on Crestline we have
4681  * to set the non-SR watermarks to 8.
4682  */
4683 static void intel_update_watermarks(struct drm_device *dev)
4684 {
4685         struct drm_i915_private *dev_priv = dev->dev_private;
4686
4687         if (dev_priv->display.update_wm)
4688                 dev_priv->display.update_wm(dev);
4689 }
4690
4691 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4692 {
4693         if (i915_panel_use_ssc >= 0)
4694                 return i915_panel_use_ssc != 0;
4695         return dev_priv->lvds_use_ssc
4696                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
4697 }
4698
4699 /**
4700  * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
4701  * @crtc: CRTC structure
4702  * @mode: requested mode
4703  *
4704  * A pipe may be connected to one or more outputs.  Based on the depth of the
4705  * attached framebuffer, choose a good color depth to use on the pipe.
4706  *
4707  * If possible, match the pipe depth to the fb depth.  In some cases, this
4708  * isn't ideal, because the connected output supports a lesser or restricted
4709  * set of depths.  Resolve that here:
4710  *    LVDS typically supports only 6bpc, so clamp down in that case
4711  *    HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
4712  *    Displays may support a restricted set as well, check EDID and clamp as
4713  *      appropriate.
4714  *    DP may want to dither down to 6bpc to fit larger modes
4715  *
4716  * RETURNS:
4717  * Dithering requirement (i.e. false if display bpc and pipe bpc match,
4718  * true if they don't match).
4719  */
4720 static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
4721                                          unsigned int *pipe_bpp,
4722                                          struct drm_display_mode *mode)
4723 {
4724         struct drm_device *dev = crtc->dev;
4725         struct drm_i915_private *dev_priv = dev->dev_private;
4726         struct drm_encoder *encoder;
4727         struct drm_connector *connector;
4728         unsigned int display_bpc = UINT_MAX, bpc;
4729
4730         /* Walk the encoders & connectors on this crtc, get min bpc */
4731         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
4732                 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
4733
4734                 if (encoder->crtc != crtc)
4735                         continue;
4736
4737                 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
4738                         unsigned int lvds_bpc;
4739
4740                         if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
4741                             LVDS_A3_POWER_UP)
4742                                 lvds_bpc = 8;
4743                         else
4744                                 lvds_bpc = 6;
4745
4746                         if (lvds_bpc < display_bpc) {
4747                                 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
4748                                 display_bpc = lvds_bpc;
4749                         }
4750                         continue;
4751                 }
4752
4753                 /* Not one of the known troublemakers, check the EDID */
4754                 list_for_each_entry(connector, &dev->mode_config.connector_list,
4755                                     head) {
4756                         if (connector->encoder != encoder)
4757                                 continue;
4758
4759                         /* Don't use an invalid EDID bpc value */
4760                         if (connector->display_info.bpc &&
4761                             connector->display_info.bpc < display_bpc) {
4762                                 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
4763                                 display_bpc = connector->display_info.bpc;
4764                         }
4765                 }
4766
4767                 /*
4768                  * HDMI is either 12 or 8, so if the display lets 10bpc sneak
4769                  * through, clamp it down.  (Note: >12bpc will be caught below.)
4770                  */
4771                 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
4772                         if (display_bpc > 8 && display_bpc < 12) {
4773                                 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
4774                                 display_bpc = 12;
4775                         } else {
4776                                 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
4777                                 display_bpc = 8;
4778                         }
4779                 }
4780         }
4781
4782         if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4783                 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
4784                 display_bpc = 6;
4785         }
4786
4787         /*
4788          * We could just drive the pipe at the highest bpc all the time and
4789          * enable dithering as needed, but that costs bandwidth.  So choose
4790          * the minimum value that expresses the full color range of the fb but
4791          * also stays within the max display bpc discovered above.
4792          */
4793
4794         switch (crtc->fb->depth) {
4795         case 8:
4796                 bpc = 8; /* since we go through a colormap */
4797                 break;
4798         case 15:
4799         case 16:
4800                 bpc = 6; /* min is 18bpp */
4801                 break;
4802         case 24:
4803                 bpc = 8;
4804                 break;
4805         case 30:
4806                 bpc = 10;
4807                 break;
4808         case 48:
4809                 bpc = 12;
4810                 break;
4811         default:
4812                 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
4813                 bpc = min((unsigned int)8, display_bpc);
4814                 break;
4815         }
4816
4817         display_bpc = min(display_bpc, bpc);
4818
4819         DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
4820                       bpc, display_bpc);
4821
4822         *pipe_bpp = display_bpc * 3;
4823
4824         return display_bpc != bpc;
4825 }
4826
4827 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4828                               struct drm_display_mode *mode,
4829                               struct drm_display_mode *adjusted_mode,
4830                               int x, int y,
4831                               struct drm_framebuffer *old_fb)
4832 {
4833         struct drm_device *dev = crtc->dev;
4834         struct drm_i915_private *dev_priv = dev->dev_private;
4835         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4836         int pipe = intel_crtc->pipe;
4837         int plane = intel_crtc->plane;
4838         int refclk, num_connectors = 0;
4839         intel_clock_t clock, reduced_clock;
4840         u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
4841         bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
4842         bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
4843         struct drm_mode_config *mode_config = &dev->mode_config;
4844         struct intel_encoder *encoder;
4845         const intel_limit_t *limit;
4846         int ret;
4847         u32 temp;
4848         u32 lvds_sync = 0;
4849
4850         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
4851                 if (encoder->base.crtc != crtc)
4852                         continue;
4853
4854                 switch (encoder->type) {
4855                 case INTEL_OUTPUT_LVDS:
4856                         is_lvds = true;
4857                         break;
4858                 case INTEL_OUTPUT_SDVO:
4859                 case INTEL_OUTPUT_HDMI:
4860                         is_sdvo = true;
4861                         if (encoder->needs_tv_clock)
4862                                 is_tv = true;
4863                         break;
4864                 case INTEL_OUTPUT_DVO:
4865                         is_dvo = true;
4866                         break;
4867                 case INTEL_OUTPUT_TVOUT:
4868                         is_tv = true;
4869                         break;
4870                 case INTEL_OUTPUT_ANALOG:
4871                         is_crt = true;
4872                         break;
4873                 case INTEL_OUTPUT_DISPLAYPORT:
4874                         is_dp = true;
4875                         break;
4876                 }
4877
4878                 num_connectors++;
4879         }
4880
4881         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4882                 refclk = dev_priv->lvds_ssc_freq * 1000;
4883                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4884                               refclk / 1000);
4885         } else if (!IS_GEN2(dev)) {
4886                 refclk = 96000;
4887         } else {
4888                 refclk = 48000;
4889         }
4890
4891         /*
4892          * Returns a set of divisors for the desired target clock with the given
4893          * refclk, or FALSE.  The returned values represent the clock equation:
4894          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4895          */
4896         limit = intel_limit(crtc, refclk);
4897         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
4898         if (!ok) {
4899                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4900                 return -EINVAL;
4901         }
4902
4903         /* Ensure that the cursor is valid for the new mode before changing... */
4904         intel_crtc_update_cursor(crtc, true);
4905
4906         if (is_lvds && dev_priv->lvds_downclock_avail) {
4907                 has_reduced_clock = limit->find_pll(limit, crtc,
4908                                                     dev_priv->lvds_downclock,
4909                                                     refclk,
4910                                                     &reduced_clock);
4911                 if (has_reduced_clock && (clock.p != reduced_clock.p)) {
4912                         /*
4913                          * If the different P is found, it means that we can't
4914                          * switch the display clock by using the FP0/FP1.
4915                          * In such case we will disable the LVDS downclock
4916                          * feature.
4917                          */
4918                         DRM_DEBUG_KMS("Different P is found for "
4919                                       "LVDS clock/downclock\n");
4920                         has_reduced_clock = 0;
4921                 }
4922         }
4923         /* SDVO TV has fixed PLL values depend on its clock range,
4924            this mirrors vbios setting. */
4925         if (is_sdvo && is_tv) {
4926                 if (adjusted_mode->clock >= 100000
4927                     && adjusted_mode->clock < 140500) {
4928                         clock.p1 = 2;
4929                         clock.p2 = 10;
4930                         clock.n = 3;
4931                         clock.m1 = 16;
4932                         clock.m2 = 8;
4933                 } else if (adjusted_mode->clock >= 140500
4934                            && adjusted_mode->clock <= 200000) {
4935                         clock.p1 = 1;
4936                         clock.p2 = 10;
4937                         clock.n = 6;
4938                         clock.m1 = 12;
4939                         clock.m2 = 8;
4940                 }
4941         }
4942
4943         if (IS_PINEVIEW(dev)) {
4944                 fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
4945                 if (has_reduced_clock)
4946                         fp2 = (1 << reduced_clock.n) << 16 |
4947                                 reduced_clock.m1 << 8 | reduced_clock.m2;
4948         } else {
4949                 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
4950                 if (has_reduced_clock)
4951                         fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
4952                                 reduced_clock.m2;
4953         }
4954
4955         dpll = DPLL_VGA_MODE_DIS;
4956
4957         if (!IS_GEN2(dev)) {
4958                 if (is_lvds)
4959                         dpll |= DPLLB_MODE_LVDS;
4960                 else
4961                         dpll |= DPLLB_MODE_DAC_SERIAL;
4962                 if (is_sdvo) {
4963                         int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4964                         if (pixel_multiplier > 1) {
4965                                 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4966                                         dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
4967                         }
4968                         dpll |= DPLL_DVO_HIGH_SPEED;
4969                 }
4970                 if (is_dp)
4971                         dpll |= DPLL_DVO_HIGH_SPEED;
4972
4973                 /* compute bitmask from p1 value */
4974                 if (IS_PINEVIEW(dev))
4975                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4976                 else {
4977                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4978                         if (IS_G4X(dev) && has_reduced_clock)
4979                                 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4980                 }
4981                 switch (clock.p2) {
4982                 case 5:
4983                         dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4984                         break;
4985                 case 7:
4986                         dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4987                         break;
4988                 case 10:
4989                         dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4990                         break;
4991                 case 14:
4992                         dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4993                         break;
4994                 }
4995                 if (INTEL_INFO(dev)->gen >= 4)
4996                         dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4997         } else {
4998                 if (is_lvds) {
4999                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5000                 } else {
5001                         if (clock.p1 == 2)
5002                                 dpll |= PLL_P1_DIVIDE_BY_TWO;
5003                         else
5004                                 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5005                         if (clock.p2 == 4)
5006                                 dpll |= PLL_P2_DIVIDE_BY_4;
5007                 }
5008         }
5009
5010         if (is_sdvo && is_tv)
5011                 dpll |= PLL_REF_INPUT_TVCLKINBC;
5012         else if (is_tv)
5013                 /* XXX: just matching BIOS for now */
5014                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
5015                 dpll |= 3;
5016         else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5017                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5018         else
5019                 dpll |= PLL_REF_INPUT_DREFCLK;
5020
5021         /* setup pipeconf */
5022         pipeconf = I915_READ(PIPECONF(pipe));
5023
5024         /* Set up the display plane register */
5025         dspcntr = DISPPLANE_GAMMA_ENABLE;
5026
5027         /* Ironlake's plane is forced to pipe, bit 24 is to
5028            enable color space conversion */
5029         if (pipe == 0)
5030                 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
5031         else
5032                 dspcntr |= DISPPLANE_SEL_PIPE_B;
5033
5034         if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
5035                 /* Enable pixel doubling when the dot clock is > 90% of the (display)
5036                  * core speed.
5037                  *
5038                  * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
5039                  * pipe == 0 check?
5040                  */
5041                 if (mode->clock >
5042                     dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
5043                         pipeconf |= PIPECONF_DOUBLE_WIDE;
5044                 else
5045                         pipeconf &= ~PIPECONF_DOUBLE_WIDE;
5046         }
5047
5048         /* default to 8bpc */
5049         pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN);
5050         if (is_dp) {
5051                 if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
5052                         pipeconf |= PIPECONF_BPP_6 |
5053                                     PIPECONF_DITHER_EN |
5054                                     PIPECONF_DITHER_TYPE_SP;
5055                 }
5056         }
5057
5058         dpll |= DPLL_VCO_ENABLE;
5059
5060         DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
5061         drm_mode_debug_printmodeline(mode);
5062
5063         I915_WRITE(FP0(pipe), fp);
5064         I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
5065
5066         POSTING_READ(DPLL(pipe));
5067         udelay(150);
5068
5069         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5070          * This is an exception to the general rule that mode_set doesn't turn
5071          * things on.
5072          */
5073         if (is_lvds) {
5074                 temp = I915_READ(LVDS);
5075                 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
5076                 if (pipe == 1) {
5077                         temp |= LVDS_PIPEB_SELECT;
5078                 } else {
5079                         temp &= ~LVDS_PIPEB_SELECT;
5080                 }
5081                 /* set the corresponsding LVDS_BORDER bit */
5082                 temp |= dev_priv->lvds_border_bits;
5083                 /* Set the B0-B3 data pairs corresponding to whether we're going to
5084                  * set the DPLLs for dual-channel mode or not.
5085                  */
5086                 if (clock.p2 == 7)
5087                         temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
5088                 else
5089                         temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
5090
5091                 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
5092                  * appropriately here, but we need to look more thoroughly into how
5093                  * panels behave in the two modes.
5094                  */
5095                 /* set the dithering flag on LVDS as needed */
5096                 if (INTEL_INFO(dev)->gen >= 4) {
5097                         if (dev_priv->lvds_dither)
5098                                 temp |= LVDS_ENABLE_DITHER;
5099                         else
5100                                 temp &= ~LVDS_ENABLE_DITHER;
5101                 }
5102                 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5103                         lvds_sync |= LVDS_HSYNC_POLARITY;
5104                 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5105                         lvds_sync |= LVDS_VSYNC_POLARITY;
5106                 if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
5107                     != lvds_sync) {
5108                         char flags[2] = "-+";
5109                         DRM_INFO("Changing LVDS panel from "
5110                                  "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
5111                                  flags[!(temp & LVDS_HSYNC_POLARITY)],
5112                                  flags[!(temp & LVDS_VSYNC_POLARITY)],
5113                                  flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
5114                                  flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
5115                         temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5116                         temp |= lvds_sync;
5117                 }
5118                 I915_WRITE(LVDS, temp);
5119         }
5120
5121         if (is_dp) {
5122                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5123         }
5124
5125         I915_WRITE(DPLL(pipe), dpll);
5126
5127         /* Wait for the clocks to stabilize. */
5128         POSTING_READ(DPLL(pipe));
5129         udelay(150);
5130
5131         if (INTEL_INFO(dev)->gen >= 4) {
5132                 temp = 0;
5133                 if (is_sdvo) {
5134                         temp = intel_mode_get_pixel_multiplier(adjusted_mode);
5135                         if (temp > 1)
5136                                 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5137                         else
5138                                 temp = 0;
5139                 }
5140                 I915_WRITE(DPLL_MD(pipe), temp);
5141         } else {
5142                 /* The pixel multiplier can only be updated once the
5143                  * DPLL is enabled and the clocks are stable.
5144                  *
5145                  * So write it again.
5146                  */
5147                 I915_WRITE(DPLL(pipe), dpll);
5148         }
5149
5150         intel_crtc->lowfreq_avail = false;
5151         if (is_lvds && has_reduced_clock && i915_powersave) {
5152                 I915_WRITE(FP1(pipe), fp2);
5153                 intel_crtc->lowfreq_avail = true;
5154                 if (HAS_PIPE_CXSR(dev)) {
5155                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
5156                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5157                 }
5158         } else {
5159                 I915_WRITE(FP1(pipe), fp);
5160                 if (HAS_PIPE_CXSR(dev)) {
5161                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
5162                         pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
5163                 }
5164         }
5165
5166         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5167                 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5168                 /* the chip adds 2 halflines automatically */
5169                 adjusted_mode->crtc_vdisplay -= 1;
5170                 adjusted_mode->crtc_vtotal -= 1;
5171                 adjusted_mode->crtc_vblank_start -= 1;
5172                 adjusted_mode->crtc_vblank_end -= 1;
5173                 adjusted_mode->crtc_vsync_end -= 1;
5174                 adjusted_mode->crtc_vsync_start -= 1;
5175         } else
5176                 pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */
5177
5178         I915_WRITE(HTOTAL(pipe),
5179                    (adjusted_mode->crtc_hdisplay - 1) |
5180                    ((adjusted_mode->crtc_htotal - 1) << 16));
5181         I915_WRITE(HBLANK(pipe),
5182                    (adjusted_mode->crtc_hblank_start - 1) |
5183                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
5184         I915_WRITE(HSYNC(pipe),
5185                    (adjusted_mode->crtc_hsync_start - 1) |
5186                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
5187
5188         I915_WRITE(VTOTAL(pipe),
5189                    (adjusted_mode->crtc_vdisplay - 1) |
5190                    ((adjusted_mode->crtc_vtotal - 1) << 16));
5191         I915_WRITE(VBLANK(pipe),
5192                    (adjusted_mode->crtc_vblank_start - 1) |
5193                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
5194         I915_WRITE(VSYNC(pipe),
5195                    (adjusted_mode->crtc_vsync_start - 1) |
5196                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
5197
5198         /* pipesrc and dspsize control the size that is scaled from,
5199          * which should always be the user's requested size.
5200          */
5201         I915_WRITE(DSPSIZE(plane),
5202                    ((mode->vdisplay - 1) << 16) |
5203                    (mode->hdisplay - 1));
5204         I915_WRITE(DSPPOS(plane), 0);
5205         I915_WRITE(PIPESRC(pipe),
5206                    ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
5207
5208         I915_WRITE(PIPECONF(pipe), pipeconf);
5209         POSTING_READ(PIPECONF(pipe));
5210         intel_enable_pipe(dev_priv, pipe, false);
5211
5212         intel_wait_for_vblank(dev, pipe);
5213
5214         I915_WRITE(DSPCNTR(plane), dspcntr);
5215         POSTING_READ(DSPCNTR(plane));
5216         intel_enable_plane(dev_priv, plane, pipe);
5217
5218         ret = intel_pipe_set_base(crtc, x, y, old_fb);
5219
5220         intel_update_watermarks(dev);
5221
5222         return ret;
5223 }
5224
5225 /*
5226  * Initialize reference clocks when the driver loads
5227  */
5228 void ironlake_init_pch_refclk(struct drm_device *dev)
5229 {
5230         struct drm_i915_private *dev_priv = dev->dev_private;
5231         struct drm_mode_config *mode_config = &dev->mode_config;
5232         struct intel_encoder *encoder;
5233         u32 temp;
5234         bool has_lvds = false;
5235         bool has_cpu_edp = false;
5236         bool has_pch_edp = false;
5237         bool has_panel = false;
5238         bool has_ck505 = false;
5239         bool can_ssc = false;
5240
5241         /* We need to take the global config into account */
5242         list_for_each_entry(encoder, &mode_config->encoder_list,
5243                             base.head) {
5244                 switch (encoder->type) {
5245                 case INTEL_OUTPUT_LVDS:
5246                         has_panel = true;
5247                         has_lvds = true;
5248                         break;
5249                 case INTEL_OUTPUT_EDP:
5250                         has_panel = true;
5251                         if (intel_encoder_is_pch_edp(&encoder->base))
5252                                 has_pch_edp = true;
5253                         else
5254                                 has_cpu_edp = true;
5255                         break;
5256                 }
5257         }
5258
5259         if (HAS_PCH_IBX(dev)) {
5260                 has_ck505 = dev_priv->display_clock_mode;
5261                 can_ssc = has_ck505;
5262         } else {
5263                 has_ck505 = false;
5264                 can_ssc = true;
5265         }
5266
5267         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
5268                       has_panel, has_lvds, has_pch_edp, has_cpu_edp,
5269                       has_ck505);
5270
5271         /* Ironlake: try to setup display ref clock before DPLL
5272          * enabling. This is only under driver's control after
5273          * PCH B stepping, previous chipset stepping should be
5274          * ignoring this setting.
5275          */
5276         temp = I915_READ(PCH_DREF_CONTROL);
5277         /* Always enable nonspread source */
5278         temp &= ~DREF_NONSPREAD_SOURCE_MASK;
5279
5280         if (has_ck505)
5281                 temp |= DREF_NONSPREAD_CK505_ENABLE;
5282         else
5283                 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
5284
5285         if (has_panel) {
5286                 temp &= ~DREF_SSC_SOURCE_MASK;
5287                 temp |= DREF_SSC_SOURCE_ENABLE;
5288
5289                 /* SSC must be turned on before enabling the CPU output  */
5290                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5291                         DRM_DEBUG_KMS("Using SSC on panel\n");
5292                         temp |= DREF_SSC1_ENABLE;
5293                 }
5294
5295                 /* Get SSC going before enabling the outputs */
5296                 I915_WRITE(PCH_DREF_CONTROL, temp);
5297                 POSTING_READ(PCH_DREF_CONTROL);
5298                 udelay(200);
5299
5300                 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5301
5302                 /* Enable CPU source on CPU attached eDP */
5303                 if (has_cpu_edp) {
5304                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5305                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
5306                                 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5307                         }
5308                         else
5309                                 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5310                 } else
5311                         temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5312
5313                 I915_WRITE(PCH_DREF_CONTROL, temp);
5314                 POSTING_READ(PCH_DREF_CONTROL);
5315                 udelay(200);
5316         } else {
5317                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5318
5319                 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5320
5321                 /* Turn off CPU output */
5322                 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5323
5324                 I915_WRITE(PCH_DREF_CONTROL, temp);
5325                 POSTING_READ(PCH_DREF_CONTROL);
5326                 udelay(200);
5327
5328                 /* Turn off the SSC source */
5329                 temp &= ~DREF_SSC_SOURCE_MASK;
5330                 temp |= DREF_SSC_SOURCE_DISABLE;
5331
5332                 /* Turn off SSC1 */
5333                 temp &= ~ DREF_SSC1_ENABLE;
5334
5335                 I915_WRITE(PCH_DREF_CONTROL, temp);
5336                 POSTING_READ(PCH_DREF_CONTROL);
5337                 udelay(200);
5338         }
5339 }
5340
5341 static int ironlake_get_refclk(struct drm_crtc *crtc)
5342 {
5343         struct drm_device *dev = crtc->dev;
5344         struct drm_i915_private *dev_priv = dev->dev_private;
5345         struct intel_encoder *encoder;
5346         struct drm_mode_config *mode_config = &dev->mode_config;
5347         struct intel_encoder *edp_encoder = NULL;
5348         int num_connectors = 0;
5349         bool is_lvds = false;
5350
5351         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5352                 if (encoder->base.crtc != crtc)
5353                         continue;
5354
5355                 switch (encoder->type) {
5356                 case INTEL_OUTPUT_LVDS:
5357                         is_lvds = true;
5358                         break;
5359                 case INTEL_OUTPUT_EDP:
5360                         edp_encoder = encoder;
5361                         break;
5362                 }
5363                 num_connectors++;
5364         }
5365
5366         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5367                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5368                               dev_priv->lvds_ssc_freq);
5369                 return dev_priv->lvds_ssc_freq * 1000;
5370         }
5371
5372         return 120000;
5373 }
5374
5375 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5376                                   struct drm_display_mode *mode,
5377                                   struct drm_display_mode *adjusted_mode,
5378                                   int x, int y,
5379                                   struct drm_framebuffer *old_fb)
5380 {
5381         struct drm_device *dev = crtc->dev;
5382         struct drm_i915_private *dev_priv = dev->dev_private;
5383         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5384         int pipe = intel_crtc->pipe;
5385         int plane = intel_crtc->plane;
5386         int refclk, num_connectors = 0;
5387         intel_clock_t clock, reduced_clock;
5388         u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
5389         bool ok, has_reduced_clock = false, is_sdvo = false;
5390         bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
5391         struct intel_encoder *has_edp_encoder = NULL;
5392         struct drm_mode_config *mode_config = &dev->mode_config;
5393         struct intel_encoder *encoder;
5394         const intel_limit_t *limit;
5395         int ret;
5396         struct fdi_m_n m_n = {0};
5397         u32 temp;
5398         u32 lvds_sync = 0;
5399         int target_clock, pixel_multiplier, lane, link_bw, factor;
5400         unsigned int pipe_bpp;
5401         bool dither;
5402
5403         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5404                 if (encoder->base.crtc != crtc)
5405                         continue;
5406
5407                 switch (encoder->type) {
5408                 case INTEL_OUTPUT_LVDS:
5409                         is_lvds = true;
5410                         break;
5411                 case INTEL_OUTPUT_SDVO:
5412                 case INTEL_OUTPUT_HDMI:
5413                         is_sdvo = true;
5414                         if (encoder->needs_tv_clock)
5415                                 is_tv = true;
5416                         break;
5417                 case INTEL_OUTPUT_TVOUT:
5418                         is_tv = true;
5419                         break;
5420                 case INTEL_OUTPUT_ANALOG:
5421                         is_crt = true;
5422                         break;
5423                 case INTEL_OUTPUT_DISPLAYPORT:
5424                         is_dp = true;
5425                         break;
5426                 case INTEL_OUTPUT_EDP:
5427                         has_edp_encoder = encoder;
5428                         break;
5429                 }
5430
5431                 num_connectors++;
5432         }
5433
5434         refclk = ironlake_get_refclk(crtc);
5435
5436         /*
5437          * Returns a set of divisors for the desired target clock with the given
5438          * refclk, or FALSE.  The returned values represent the clock equation:
5439          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5440          */
5441         limit = intel_limit(crtc, refclk);
5442         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
5443         if (!ok) {
5444                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5445                 return -EINVAL;
5446         }
5447
5448         /* Ensure that the cursor is valid for the new mode before changing... */
5449         intel_crtc_update_cursor(crtc, true);
5450
5451         if (is_lvds && dev_priv->lvds_downclock_avail) {
5452                 has_reduced_clock = limit->find_pll(limit, crtc,
5453                                                     dev_priv->lvds_downclock,
5454                                                     refclk,
5455                                                     &reduced_clock);
5456                 if (has_reduced_clock && (clock.p != reduced_clock.p)) {
5457                         /*
5458                          * If the different P is found, it means that we can't
5459                          * switch the display clock by using the FP0/FP1.
5460                          * In such case we will disable the LVDS downclock
5461                          * feature.
5462                          */
5463                         DRM_DEBUG_KMS("Different P is found for "
5464                                       "LVDS clock/downclock\n");
5465                         has_reduced_clock = 0;
5466                 }
5467         }
5468         /* SDVO TV has fixed PLL values depend on its clock range,
5469            this mirrors vbios setting. */
5470         if (is_sdvo && is_tv) {
5471                 if (adjusted_mode->clock >= 100000
5472                     && adjusted_mode->clock < 140500) {
5473                         clock.p1 = 2;
5474                         clock.p2 = 10;
5475                         clock.n = 3;
5476                         clock.m1 = 16;
5477                         clock.m2 = 8;
5478                 } else if (adjusted_mode->clock >= 140500
5479                            && adjusted_mode->clock <= 200000) {
5480                         clock.p1 = 1;
5481                         clock.p2 = 10;
5482                         clock.n = 6;
5483                         clock.m1 = 12;
5484                         clock.m2 = 8;
5485                 }
5486         }
5487
5488         /* FDI link */
5489         pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5490         lane = 0;
5491         /* CPU eDP doesn't require FDI link, so just set DP M/N
5492            according to current link config */
5493         if (has_edp_encoder &&
5494             !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5495                 target_clock = mode->clock;
5496                 intel_edp_link_config(has_edp_encoder,
5497                                       &lane, &link_bw);
5498         } else {
5499                 /* [e]DP over FDI requires target mode clock
5500                    instead of link clock */
5501                 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
5502                         target_clock = mode->clock;
5503                 else
5504                         target_clock = adjusted_mode->clock;
5505
5506                 /* FDI is a binary signal running at ~2.7GHz, encoding
5507                  * each output octet as 10 bits. The actual frequency
5508                  * is stored as a divider into a 100MHz clock, and the
5509                  * mode pixel clock is stored in units of 1KHz.
5510                  * Hence the bw of each lane in terms of the mode signal
5511                  * is:
5512                  */
5513                 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5514         }
5515
5516         /* determine panel color depth */
5517         temp = I915_READ(PIPECONF(pipe));
5518         temp &= ~PIPE_BPC_MASK;
5519         dither = intel_choose_pipe_bpp_dither(crtc, &pipe_bpp, adjusted_mode);
5520         switch (pipe_bpp) {
5521         case 18:
5522                 temp |= PIPE_6BPC;
5523                 break;
5524         case 24:
5525                 temp |= PIPE_8BPC;
5526                 break;
5527         case 30:
5528                 temp |= PIPE_10BPC;
5529                 break;
5530         case 36:
5531                 temp |= PIPE_12BPC;
5532                 break;
5533         default:
5534                 WARN(1, "intel_choose_pipe_bpp returned invalid value %d\n",
5535                         pipe_bpp);
5536                 temp |= PIPE_8BPC;
5537                 pipe_bpp = 24;
5538                 break;
5539         }
5540
5541         intel_crtc->bpp = pipe_bpp;
5542         I915_WRITE(PIPECONF(pipe), temp);
5543
5544         if (!lane) {
5545                 /*
5546                  * Account for spread spectrum to avoid
5547                  * oversubscribing the link. Max center spread
5548                  * is 2.5%; use 5% for safety's sake.
5549                  */
5550                 u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
5551                 lane = bps / (link_bw * 8) + 1;
5552         }
5553
5554         intel_crtc->fdi_lanes = lane;
5555
5556         if (pixel_multiplier > 1)
5557                 link_bw *= pixel_multiplier;
5558         ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
5559                              &m_n);
5560
5561         fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5562         if (has_reduced_clock)
5563                 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5564                         reduced_clock.m2;
5565
5566         /* Enable autotuning of the PLL clock (if permissible) */
5567         factor = 21;
5568         if (is_lvds) {
5569                 if ((intel_panel_use_ssc(dev_priv) &&
5570                      dev_priv->lvds_ssc_freq == 100) ||
5571                     (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
5572                         factor = 25;
5573         } else if (is_sdvo && is_tv)
5574                 factor = 20;
5575
5576         if (clock.m < factor * clock.n)
5577                 fp |= FP_CB_TUNE;
5578
5579         dpll = 0;
5580
5581         if (is_lvds)
5582                 dpll |= DPLLB_MODE_LVDS;
5583         else
5584                 dpll |= DPLLB_MODE_DAC_SERIAL;
5585         if (is_sdvo) {
5586                 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5587                 if (pixel_multiplier > 1) {
5588                         dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
5589                 }
5590                 dpll |= DPLL_DVO_HIGH_SPEED;
5591         }
5592         if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
5593                 dpll |= DPLL_DVO_HIGH_SPEED;
5594
5595         /* compute bitmask from p1 value */
5596         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5597         /* also FPA1 */
5598         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5599
5600         switch (clock.p2) {
5601         case 5:
5602                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5603                 break;
5604         case 7:
5605                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5606                 break;
5607         case 10:
5608                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5609                 break;
5610         case 14:
5611                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5612                 break;
5613         }
5614
5615         if (is_sdvo && is_tv)
5616                 dpll |= PLL_REF_INPUT_TVCLKINBC;
5617         else if (is_tv)
5618                 /* XXX: just matching BIOS for now */
5619                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
5620                 dpll |= 3;
5621         else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5622                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5623         else
5624                 dpll |= PLL_REF_INPUT_DREFCLK;
5625
5626         /* setup pipeconf */
5627         pipeconf = I915_READ(PIPECONF(pipe));
5628
5629         /* Set up the display plane register */
5630         dspcntr = DISPPLANE_GAMMA_ENABLE;
5631
5632         DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5633         drm_mode_debug_printmodeline(mode);
5634
5635         /* PCH eDP needs FDI, but CPU eDP does not */
5636         if (!intel_crtc->no_pll) {
5637                 if (!has_edp_encoder ||
5638                     intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5639                         I915_WRITE(PCH_FP0(pipe), fp);
5640                         I915_WRITE(PCH_DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
5641
5642                         POSTING_READ(PCH_DPLL(pipe));
5643                         udelay(150);
5644                 }
5645         } else {
5646                 if (dpll == (I915_READ(PCH_DPLL(0)) & 0x7fffffff) &&
5647                     fp == I915_READ(PCH_FP0(0))) {
5648                         intel_crtc->use_pll_a = true;
5649                         DRM_DEBUG_KMS("using pipe a dpll\n");
5650                 } else if (dpll == (I915_READ(PCH_DPLL(1)) & 0x7fffffff) &&
5651                            fp == I915_READ(PCH_FP0(1))) {
5652                         intel_crtc->use_pll_a = false;
5653                         DRM_DEBUG_KMS("using pipe b dpll\n");
5654                 } else {
5655                         DRM_DEBUG_KMS("no matching PLL configuration for pipe 2\n");
5656                         return -EINVAL;
5657                 }
5658         }
5659
5660         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5661          * This is an exception to the general rule that mode_set doesn't turn
5662          * things on.
5663          */
5664         if (is_lvds) {
5665                 temp = I915_READ(PCH_LVDS);
5666                 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
5667                 if (HAS_PCH_CPT(dev)) {
5668                         temp &= ~PORT_TRANS_SEL_MASK;
5669                         temp |= PORT_TRANS_SEL_CPT(pipe);
5670                 } else {
5671                         if (pipe == 1)
5672                                 temp |= LVDS_PIPEB_SELECT;
5673                         else
5674                                 temp &= ~LVDS_PIPEB_SELECT;
5675                 }
5676
5677                 /* set the corresponsding LVDS_BORDER bit */
5678                 temp |= dev_priv->lvds_border_bits;
5679                 /* Set the B0-B3 data pairs corresponding to whether we're going to
5680                  * set the DPLLs for dual-channel mode or not.
5681                  */
5682                 if (clock.p2 == 7)
5683                         temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
5684                 else
5685                         temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
5686
5687                 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
5688                  * appropriately here, but we need to look more thoroughly into how
5689                  * panels behave in the two modes.
5690                  */
5691                 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5692                         lvds_sync |= LVDS_HSYNC_POLARITY;
5693                 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5694                         lvds_sync |= LVDS_VSYNC_POLARITY;
5695                 if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
5696                     != lvds_sync) {
5697                         char flags[2] = "-+";
5698                         DRM_INFO("Changing LVDS panel from "
5699                                  "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
5700                                  flags[!(temp & LVDS_HSYNC_POLARITY)],
5701                                  flags[!(temp & LVDS_VSYNC_POLARITY)],
5702                                  flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
5703                                  flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
5704                         temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5705                         temp |= lvds_sync;
5706                 }
5707                 I915_WRITE(PCH_LVDS, temp);
5708         }
5709
5710         pipeconf &= ~PIPECONF_DITHER_EN;
5711         pipeconf &= ~PIPECONF_DITHER_TYPE_MASK;
5712         if ((is_lvds && dev_priv->lvds_dither) || dither) {
5713                 pipeconf |= PIPECONF_DITHER_EN;
5714                 pipeconf |= PIPECONF_DITHER_TYPE_SP;
5715         }
5716         if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5717                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5718         } else {
5719                 /* For non-DP output, clear any trans DP clock recovery setting.*/
5720                 I915_WRITE(TRANSDATA_M1(pipe), 0);
5721                 I915_WRITE(TRANSDATA_N1(pipe), 0);
5722                 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5723                 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
5724         }
5725
5726         if (!intel_crtc->no_pll &&
5727             (!has_edp_encoder ||
5728              intel_encoder_is_pch_edp(&has_edp_encoder->base))) {
5729                 I915_WRITE(PCH_DPLL(pipe), dpll);
5730
5731                 /* Wait for the clocks to stabilize. */
5732                 POSTING_READ(PCH_DPLL(pipe));
5733                 udelay(150);
5734
5735                 /* The pixel multiplier can only be updated once the
5736                  * DPLL is enabled and the clocks are stable.
5737                  *
5738                  * So write it again.
5739                  */
5740                 I915_WRITE(PCH_DPLL(pipe), dpll);
5741         }
5742
5743         intel_crtc->lowfreq_avail = false;
5744         if (!intel_crtc->no_pll) {
5745                 if (is_lvds && has_reduced_clock && i915_powersave) {
5746                         I915_WRITE(PCH_FP1(pipe), fp2);
5747                         intel_crtc->lowfreq_avail = true;
5748                         if (HAS_PIPE_CXSR(dev)) {
5749                                 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
5750                                 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5751                         }
5752                 } else {
5753                         I915_WRITE(PCH_FP1(pipe), fp);
5754                         if (HAS_PIPE_CXSR(dev)) {
5755                                 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
5756                                 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
5757                         }
5758                 }
5759         }
5760
5761         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5762                 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5763                 /* the chip adds 2 halflines automatically */
5764                 adjusted_mode->crtc_vdisplay -= 1;
5765                 adjusted_mode->crtc_vtotal -= 1;
5766                 adjusted_mode->crtc_vblank_start -= 1;
5767                 adjusted_mode->crtc_vblank_end -= 1;
5768                 adjusted_mode->crtc_vsync_end -= 1;
5769                 adjusted_mode->crtc_vsync_start -= 1;
5770         } else
5771                 pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */
5772
5773         I915_WRITE(HTOTAL(pipe),
5774                    (adjusted_mode->crtc_hdisplay - 1) |
5775                    ((adjusted_mode->crtc_htotal - 1) << 16));
5776         I915_WRITE(HBLANK(pipe),
5777                    (adjusted_mode->crtc_hblank_start - 1) |
5778                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
5779         I915_WRITE(HSYNC(pipe),
5780                    (adjusted_mode->crtc_hsync_start - 1) |
5781                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
5782
5783         I915_WRITE(VTOTAL(pipe),
5784                    (adjusted_mode->crtc_vdisplay - 1) |
5785                    ((adjusted_mode->crtc_vtotal - 1) << 16));
5786         I915_WRITE(VBLANK(pipe),
5787                    (adjusted_mode->crtc_vblank_start - 1) |
5788                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
5789         I915_WRITE(VSYNC(pipe),
5790                    (adjusted_mode->crtc_vsync_start - 1) |
5791                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
5792
5793         /* pipesrc controls the size that is scaled from, which should
5794          * always be the user's requested size.
5795          */
5796         I915_WRITE(PIPESRC(pipe),
5797                    ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
5798
5799         I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
5800         I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
5801         I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
5802         I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
5803
5804         if (has_edp_encoder &&
5805             !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5806                 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
5807         }
5808
5809         I915_WRITE(PIPECONF(pipe), pipeconf);
5810         POSTING_READ(PIPECONF(pipe));
5811
5812         intel_wait_for_vblank(dev, pipe);
5813
5814         if (IS_GEN5(dev)) {
5815                 /* enable address swizzle for tiling buffer */
5816                 temp = I915_READ(DISP_ARB_CTL);
5817                 I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING);
5818         }
5819
5820         I915_WRITE(DSPCNTR(plane), dspcntr);
5821         POSTING_READ(DSPCNTR(plane));
5822
5823         ret = intel_pipe_set_base(crtc, x, y, old_fb);
5824
5825         intel_update_watermarks(dev);
5826
5827         return ret;
5828 }
5829
5830 static int intel_crtc_mode_set(struct drm_crtc *crtc,
5831                                struct drm_display_mode *mode,
5832                                struct drm_display_mode *adjusted_mode,
5833                                int x, int y,
5834                                struct drm_framebuffer *old_fb)
5835 {
5836         struct drm_device *dev = crtc->dev;
5837         struct drm_i915_private *dev_priv = dev->dev_private;
5838         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5839         int pipe = intel_crtc->pipe;
5840         int ret;
5841
5842         drm_vblank_pre_modeset(dev, pipe);
5843
5844         ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
5845                                               x, y, old_fb);
5846
5847         drm_vblank_post_modeset(dev, pipe);
5848
5849         intel_crtc->dpms_mode = DRM_MODE_DPMS_ON;
5850
5851         return ret;
5852 }
5853
5854 static void g4x_write_eld(struct drm_connector *connector,
5855                           struct drm_crtc *crtc)
5856 {
5857         struct drm_i915_private *dev_priv = connector->dev->dev_private;
5858         uint8_t *eld = connector->eld;
5859         uint32_t eldv;
5860         uint32_t len;
5861         uint32_t i;
5862
5863         i = I915_READ(G4X_AUD_VID_DID);
5864
5865         if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
5866                 eldv = G4X_ELDV_DEVCL_DEVBLC;
5867         else
5868                 eldv = G4X_ELDV_DEVCTG;
5869
5870         i = I915_READ(G4X_AUD_CNTL_ST);
5871         i &= ~(eldv | G4X_ELD_ADDR);
5872         len = (i >> 9) & 0x1f;          /* ELD buffer size */
5873         I915_WRITE(G4X_AUD_CNTL_ST, i);
5874
5875         if (!eld[0])
5876                 return;
5877
5878         len = min_t(uint8_t, eld[2], len);
5879         DRM_DEBUG_DRIVER("ELD size %d\n", len);
5880         for (i = 0; i < len; i++)
5881                 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
5882
5883         i = I915_READ(G4X_AUD_CNTL_ST);
5884         i |= eldv;
5885         I915_WRITE(G4X_AUD_CNTL_ST, i);
5886 }
5887
5888 static void ironlake_write_eld(struct drm_connector *connector,
5889                                      struct drm_crtc *crtc)
5890 {
5891         struct drm_i915_private *dev_priv = connector->dev->dev_private;
5892         uint8_t *eld = connector->eld;
5893         uint32_t eldv;
5894         uint32_t i;
5895         int len;
5896         int hdmiw_hdmiedid;
5897         int aud_cntl_st;
5898         int aud_cntrl_st2;
5899
5900         if (HAS_PCH_IBX(connector->dev)) {
5901                 hdmiw_hdmiedid = GEN5_HDMIW_HDMIEDID_A;
5902                 aud_cntl_st = GEN5_AUD_CNTL_ST_A;
5903                 aud_cntrl_st2 = GEN5_AUD_CNTL_ST2;
5904         } else {
5905                 hdmiw_hdmiedid = GEN7_HDMIW_HDMIEDID_A;
5906                 aud_cntl_st = GEN7_AUD_CNTRL_ST_A;
5907                 aud_cntrl_st2 = GEN7_AUD_CNTRL_ST2;
5908         }
5909
5910         i = to_intel_crtc(crtc)->pipe;
5911         hdmiw_hdmiedid += i * 0x100;
5912         aud_cntl_st += i * 0x100;
5913
5914         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(i));
5915
5916         i = I915_READ(aud_cntl_st);
5917         i = (i >> 29) & 0x3;            /* DIP_Port_Select, 0x1 = PortB */
5918         if (!i) {
5919                 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
5920                 /* operate blindly on all ports */
5921                 eldv = GEN5_ELD_VALIDB;
5922                 eldv |= GEN5_ELD_VALIDB << 4;
5923                 eldv |= GEN5_ELD_VALIDB << 8;
5924         } else {
5925                 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
5926                 eldv = GEN5_ELD_VALIDB << ((i - 1) * 4);
5927         }
5928
5929         i = I915_READ(aud_cntrl_st2);
5930         i &= ~eldv;
5931         I915_WRITE(aud_cntrl_st2, i);
5932
5933         if (!eld[0])
5934                 return;
5935
5936         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5937                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5938                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
5939         }
5940
5941         i = I915_READ(aud_cntl_st);
5942         i &= ~GEN5_ELD_ADDRESS;
5943         I915_WRITE(aud_cntl_st, i);
5944
5945         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
5946         DRM_DEBUG_DRIVER("ELD size %d\n", len);
5947         for (i = 0; i < len; i++)
5948                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
5949
5950         i = I915_READ(aud_cntrl_st2);
5951         i |= eldv;
5952         I915_WRITE(aud_cntrl_st2, i);
5953 }
5954
5955 void intel_write_eld(struct drm_encoder *encoder,
5956                      struct drm_display_mode *mode)
5957 {
5958         struct drm_crtc *crtc = encoder->crtc;
5959         struct drm_connector *connector;
5960         struct drm_device *dev = encoder->dev;
5961         struct drm_i915_private *dev_priv = dev->dev_private;
5962
5963         connector = drm_select_eld(encoder, mode);
5964         if (!connector)
5965                 return;
5966
5967         DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5968                          connector->base.id,
5969                          drm_get_connector_name(connector),
5970                          connector->encoder->base.id,
5971                          drm_get_encoder_name(connector->encoder));
5972
5973         connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
5974
5975         if (dev_priv->display.write_eld)
5976                 dev_priv->display.write_eld(connector, crtc);
5977 }
5978
5979 /** Loads the palette/gamma unit for the CRTC with the prepared values */
5980 void intel_crtc_load_lut(struct drm_crtc *crtc)
5981 {
5982         struct drm_device *dev = crtc->dev;
5983         struct drm_i915_private *dev_priv = dev->dev_private;
5984         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5985         int palreg = PALETTE(intel_crtc->pipe);
5986         int i;
5987
5988         /* The clocks have to be on to load the palette. */
5989         if (!crtc->enabled || !intel_crtc->active)
5990                 return;
5991
5992         /* use legacy palette for Ironlake */
5993         if (HAS_PCH_SPLIT(dev))
5994                 palreg = LGC_PALETTE(intel_crtc->pipe);
5995
5996         for (i = 0; i < 256; i++) {
5997                 I915_WRITE(palreg + 4 * i,
5998                            (intel_crtc->lut_r[i] << 16) |
5999                            (intel_crtc->lut_g[i] << 8) |
6000                            intel_crtc->lut_b[i]);
6001         }
6002 }
6003
6004 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6005 {
6006         struct drm_device *dev = crtc->dev;
6007         struct drm_i915_private *dev_priv = dev->dev_private;
6008         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6009         bool visible = base != 0;
6010         u32 cntl;
6011
6012         if (intel_crtc->cursor_visible == visible)
6013                 return;
6014
6015         cntl = I915_READ(_CURACNTR);
6016         if (visible) {
6017                 /* On these chipsets we can only modify the base whilst
6018                  * the cursor is disabled.
6019                  */
6020                 I915_WRITE(_CURABASE, base);
6021
6022                 cntl &= ~(CURSOR_FORMAT_MASK);
6023                 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6024                 cntl |= CURSOR_ENABLE |
6025                         CURSOR_GAMMA_ENABLE |
6026                         CURSOR_FORMAT_ARGB;
6027         } else
6028                 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
6029         I915_WRITE(_CURACNTR, cntl);
6030
6031         intel_crtc->cursor_visible = visible;
6032 }
6033
6034 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6035 {
6036         struct drm_device *dev = crtc->dev;
6037         struct drm_i915_private *dev_priv = dev->dev_private;
6038         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6039         int pipe = intel_crtc->pipe;
6040         bool visible = base != 0;
6041
6042         if (intel_crtc->cursor_visible != visible) {
6043                 uint32_t cntl = I915_READ(CURCNTR(pipe));
6044                 if (base) {
6045                         cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6046                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6047                         cntl |= pipe << 28; /* Connect to correct pipe */
6048                 } else {
6049                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6050                         cntl |= CURSOR_MODE_DISABLE;
6051                 }
6052                 I915_WRITE(CURCNTR(pipe), cntl);
6053
6054                 intel_crtc->cursor_visible = visible;
6055         }
6056         /* and commit changes on next vblank */
6057         I915_WRITE(CURBASE(pipe), base);
6058 }
6059
6060 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6061 {
6062         struct drm_device *dev = crtc->dev;
6063         struct drm_i915_private *dev_priv = dev->dev_private;
6064         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6065         int pipe = intel_crtc->pipe;
6066         bool visible = base != 0;
6067
6068         if (intel_crtc->cursor_visible != visible) {
6069                 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6070                 if (base) {
6071                         cntl &= ~CURSOR_MODE;
6072                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6073                 } else {
6074                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6075                         cntl |= CURSOR_MODE_DISABLE;
6076                 }
6077                 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6078
6079                 intel_crtc->cursor_visible = visible;
6080         }
6081         /* and commit changes on next vblank */
6082         I915_WRITE(CURBASE_IVB(pipe), base);
6083 }
6084
6085 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6086 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6087                                      bool on)
6088 {
6089         struct drm_device *dev = crtc->dev;
6090         struct drm_i915_private *dev_priv = dev->dev_private;
6091         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6092         int pipe = intel_crtc->pipe;
6093         int x = intel_crtc->cursor_x;
6094         int y = intel_crtc->cursor_y;
6095         u32 base, pos;
6096         bool visible;
6097
6098         pos = 0;
6099
6100         if (on && crtc->enabled && crtc->fb) {
6101                 base = intel_crtc->cursor_addr;
6102                 if (x > (int) crtc->fb->width)
6103                         base = 0;
6104
6105                 if (y > (int) crtc->fb->height)
6106                         base = 0;
6107         } else
6108                 base = 0;
6109
6110         if (x < 0) {
6111                 if (x + intel_crtc->cursor_width < 0)
6112                         base = 0;
6113
6114                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6115                 x = -x;
6116         }
6117         pos |= x << CURSOR_X_SHIFT;
6118
6119         if (y < 0) {
6120                 if (y + intel_crtc->cursor_height < 0)
6121                         base = 0;
6122
6123                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6124                 y = -y;
6125         }
6126         pos |= y << CURSOR_Y_SHIFT;
6127
6128         visible = base != 0;
6129         if (!visible && !intel_crtc->cursor_visible)
6130                 return;
6131
6132         if (IS_IVYBRIDGE(dev)) {
6133                 I915_WRITE(CURPOS_IVB(pipe), pos);
6134                 ivb_update_cursor(crtc, base);
6135         } else {
6136                 I915_WRITE(CURPOS(pipe), pos);
6137                 if (IS_845G(dev) || IS_I865G(dev))
6138                         i845_update_cursor(crtc, base);
6139                 else
6140                         i9xx_update_cursor(crtc, base);
6141         }
6142
6143         if (visible)
6144                 intel_mark_busy(dev, to_intel_framebuffer(crtc->fb)->obj);
6145 }
6146
6147 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
6148                                  struct drm_file *file,
6149                                  uint32_t handle,
6150                                  uint32_t width, uint32_t height)
6151 {
6152         struct drm_device *dev = crtc->dev;
6153         struct drm_i915_private *dev_priv = dev->dev_private;
6154         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6155         struct drm_i915_gem_object *obj;
6156         uint32_t addr;
6157         int ret;
6158
6159         DRM_DEBUG_KMS("\n");
6160
6161         /* if we want to turn off the cursor ignore width and height */
6162         if (!handle) {
6163                 DRM_DEBUG_KMS("cursor off\n");
6164                 addr = 0;
6165                 obj = NULL;
6166                 mutex_lock(&dev->struct_mutex);
6167                 goto finish;
6168         }
6169
6170         /* Currently we only support 64x64 cursors */
6171         if (width != 64 || height != 64) {
6172                 DRM_ERROR("we currently only support 64x64 cursors\n");
6173                 return -EINVAL;
6174         }
6175
6176         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
6177         if (&obj->base == NULL)
6178                 return -ENOENT;
6179
6180         if (obj->base.size < width * height * 4) {
6181                 DRM_ERROR("buffer is to small\n");
6182                 ret = -ENOMEM;
6183                 goto fail;
6184         }
6185
6186         /* we only need to pin inside GTT if cursor is non-phy */
6187         mutex_lock(&dev->struct_mutex);
6188         if (!dev_priv->info->cursor_needs_physical) {
6189                 if (obj->tiling_mode) {
6190                         DRM_ERROR("cursor cannot be tiled\n");
6191                         ret = -EINVAL;
6192                         goto fail_locked;
6193                 }
6194
6195                 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
6196                 if (ret) {
6197                         DRM_ERROR("failed to move cursor bo into the GTT\n");
6198                         goto fail_locked;
6199                 }
6200
6201                 ret = i915_gem_object_put_fence(obj);
6202                 if (ret) {
6203                         DRM_ERROR("failed to release fence for cursor");
6204                         goto fail_unpin;
6205                 }
6206
6207                 addr = obj->gtt_offset;
6208         } else {
6209                 int align = IS_I830(dev) ? 16 * 1024 : 256;
6210                 ret = i915_gem_attach_phys_object(dev, obj,
6211                                                   (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6212                                                   align);
6213                 if (ret) {
6214                         DRM_ERROR("failed to attach phys object\n");
6215                         goto fail_locked;
6216                 }
6217                 addr = obj->phys_obj->handle->busaddr;
6218         }
6219
6220         if (IS_GEN2(dev))
6221                 I915_WRITE(CURSIZE, (height << 12) | width);
6222
6223  finish:
6224         if (intel_crtc->cursor_bo) {
6225                 if (dev_priv->info->cursor_needs_physical) {
6226                         if (intel_crtc->cursor_bo != obj)
6227                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6228                 } else
6229                         i915_gem_object_unpin(intel_crtc->cursor_bo);
6230                 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
6231         }
6232
6233         mutex_unlock(&dev->struct_mutex);
6234
6235         intel_crtc->cursor_addr = addr;
6236         intel_crtc->cursor_bo = obj;
6237         intel_crtc->cursor_width = width;
6238         intel_crtc->cursor_height = height;
6239
6240         intel_crtc_update_cursor(crtc, true);
6241
6242         return 0;
6243 fail_unpin:
6244         i915_gem_object_unpin(obj);
6245 fail_locked:
6246         mutex_unlock(&dev->struct_mutex);
6247 fail:
6248         drm_gem_object_unreference_unlocked(&obj->base);
6249         return ret;
6250 }
6251
6252 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6253 {
6254         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6255
6256         intel_crtc->cursor_x = x;
6257         intel_crtc->cursor_y = y;
6258
6259         intel_crtc_update_cursor(crtc, true);
6260
6261         return 0;
6262 }
6263
6264 /** Sets the color ramps on behalf of RandR */
6265 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6266                                  u16 blue, int regno)
6267 {
6268         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6269
6270         intel_crtc->lut_r[regno] = red >> 8;
6271         intel_crtc->lut_g[regno] = green >> 8;
6272         intel_crtc->lut_b[regno] = blue >> 8;
6273 }
6274
6275 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6276                              u16 *blue, int regno)
6277 {
6278         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6279
6280         *red = intel_crtc->lut_r[regno] << 8;
6281         *green = intel_crtc->lut_g[regno] << 8;
6282         *blue = intel_crtc->lut_b[regno] << 8;
6283 }
6284
6285 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
6286                                  u16 *blue, uint32_t start, uint32_t size)
6287 {
6288         int end = (start + size > 256) ? 256 : start + size, i;
6289         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6290
6291         for (i = start; i < end; i++) {
6292                 intel_crtc->lut_r[i] = red[i] >> 8;
6293                 intel_crtc->lut_g[i] = green[i] >> 8;
6294                 intel_crtc->lut_b[i] = blue[i] >> 8;
6295         }
6296
6297         intel_crtc_load_lut(crtc);
6298 }
6299
6300 /**
6301  * Get a pipe with a simple mode set on it for doing load-based monitor
6302  * detection.
6303  *
6304  * It will be up to the load-detect code to adjust the pipe as appropriate for
6305  * its requirements.  The pipe will be connected to no other encoders.
6306  *
6307  * Currently this code will only succeed if there is a pipe with no encoders
6308  * configured for it.  In the future, it could choose to temporarily disable
6309  * some outputs to free up a pipe for its use.
6310  *
6311  * \return crtc, or NULL if no pipes are available.
6312  */
6313
6314 /* VESA 640x480x72Hz mode to set on the pipe */
6315 static struct drm_display_mode load_detect_mode = {
6316         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6317                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6318 };
6319
6320 static struct drm_framebuffer *
6321 intel_framebuffer_create(struct drm_device *dev,
6322                          struct drm_mode_fb_cmd *mode_cmd,
6323                          struct drm_i915_gem_object *obj)
6324 {
6325         struct intel_framebuffer *intel_fb;
6326         int ret;
6327
6328         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6329         if (!intel_fb) {
6330                 drm_gem_object_unreference_unlocked(&obj->base);
6331                 return ERR_PTR(-ENOMEM);
6332         }
6333
6334         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6335         if (ret) {
6336                 drm_gem_object_unreference_unlocked(&obj->base);
6337                 kfree(intel_fb);
6338                 return ERR_PTR(ret);
6339         }
6340
6341         return &intel_fb->base;
6342 }
6343
6344 static u32
6345 intel_framebuffer_pitch_for_width(int width, int bpp)
6346 {
6347         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6348         return ALIGN(pitch, 64);
6349 }
6350
6351 static u32
6352 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6353 {
6354         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6355         return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6356 }
6357
6358 static struct drm_framebuffer *
6359 intel_framebuffer_create_for_mode(struct drm_device *dev,
6360                                   struct drm_display_mode *mode,
6361                                   int depth, int bpp)
6362 {
6363         struct drm_i915_gem_object *obj;
6364         struct drm_mode_fb_cmd mode_cmd;
6365
6366         obj = i915_gem_alloc_object(dev,
6367                                     intel_framebuffer_size_for_mode(mode, bpp));
6368         if (obj == NULL)
6369                 return ERR_PTR(-ENOMEM);
6370
6371         mode_cmd.width = mode->hdisplay;
6372         mode_cmd.height = mode->vdisplay;
6373         mode_cmd.depth = depth;
6374         mode_cmd.bpp = bpp;
6375         mode_cmd.pitch = intel_framebuffer_pitch_for_width(mode_cmd.width, bpp);
6376
6377         return intel_framebuffer_create(dev, &mode_cmd, obj);
6378 }
6379
6380 static struct drm_framebuffer *
6381 mode_fits_in_fbdev(struct drm_device *dev,
6382                    struct drm_display_mode *mode)
6383 {
6384         struct drm_i915_private *dev_priv = dev->dev_private;
6385         struct drm_i915_gem_object *obj;
6386         struct drm_framebuffer *fb;
6387
6388         if (dev_priv->fbdev == NULL)
6389                 return NULL;
6390
6391         obj = dev_priv->fbdev->ifb.obj;
6392         if (obj == NULL)
6393                 return NULL;
6394
6395         fb = &dev_priv->fbdev->ifb.base;
6396         if (fb->pitch < intel_framebuffer_pitch_for_width(mode->hdisplay,
6397                                                           fb->bits_per_pixel))
6398                 return NULL;
6399
6400         if (obj->base.size < mode->vdisplay * fb->pitch)
6401                 return NULL;
6402
6403         return fb;
6404 }
6405
6406 bool intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
6407                                 struct drm_connector *connector,
6408                                 struct drm_display_mode *mode,
6409                                 struct intel_load_detect_pipe *old)
6410 {
6411         struct intel_crtc *intel_crtc;
6412         struct drm_crtc *possible_crtc;
6413         struct drm_encoder *encoder = &intel_encoder->base;
6414         struct drm_crtc *crtc = NULL;
6415         struct drm_device *dev = encoder->dev;
6416         struct drm_framebuffer *old_fb;
6417         int i = -1;
6418
6419         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6420                       connector->base.id, drm_get_connector_name(connector),
6421                       encoder->base.id, drm_get_encoder_name(encoder));
6422
6423         /*
6424          * Algorithm gets a little messy:
6425          *
6426          *   - if the connector already has an assigned crtc, use it (but make
6427          *     sure it's on first)
6428          *
6429          *   - try to find the first unused crtc that can drive this connector,
6430          *     and use that if we find one
6431          */
6432
6433         /* See if we already have a CRTC for this connector */
6434         if (encoder->crtc) {
6435                 crtc = encoder->crtc;
6436
6437                 intel_crtc = to_intel_crtc(crtc);
6438                 old->dpms_mode = intel_crtc->dpms_mode;
6439                 old->load_detect_temp = false;
6440
6441                 /* Make sure the crtc and connector are running */
6442                 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
6443                         struct drm_encoder_helper_funcs *encoder_funcs;
6444                         struct drm_crtc_helper_funcs *crtc_funcs;
6445
6446                         crtc_funcs = crtc->helper_private;
6447                         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
6448
6449                         encoder_funcs = encoder->helper_private;
6450                         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
6451                 }
6452
6453                 return true;
6454         }
6455
6456         /* Find an unused one (if possible) */
6457         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6458                 i++;
6459                 if (!(encoder->possible_crtcs & (1 << i)))
6460                         continue;
6461                 if (!possible_crtc->enabled) {
6462                         crtc = possible_crtc;
6463                         break;
6464                 }
6465         }
6466
6467         /*
6468          * If we didn't find an unused CRTC, don't use any.
6469          */
6470         if (!crtc) {
6471                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6472                 return false;
6473         }
6474
6475         encoder->crtc = crtc;
6476         connector->encoder = encoder;
6477
6478         intel_crtc = to_intel_crtc(crtc);
6479         old->dpms_mode = intel_crtc->dpms_mode;
6480         old->load_detect_temp = true;
6481         old->release_fb = NULL;
6482
6483         if (!mode)
6484                 mode = &load_detect_mode;
6485
6486         old_fb = crtc->fb;
6487
6488         /* We need a framebuffer large enough to accommodate all accesses
6489          * that the plane may generate whilst we perform load detection.
6490          * We can not rely on the fbcon either being present (we get called
6491          * during its initialisation to detect all boot displays, or it may
6492          * not even exist) or that it is large enough to satisfy the
6493          * requested mode.
6494          */
6495         crtc->fb = mode_fits_in_fbdev(dev, mode);
6496         if (crtc->fb == NULL) {
6497                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
6498                 crtc->fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6499                 old->release_fb = crtc->fb;
6500         } else
6501                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
6502         if (IS_ERR(crtc->fb)) {
6503                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
6504                 crtc->fb = old_fb;
6505                 return false;
6506         }
6507
6508         if (!drm_crtc_helper_set_mode(crtc, mode, 0, 0, old_fb)) {
6509                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
6510                 if (old->release_fb)
6511                         old->release_fb->funcs->destroy(old->release_fb);
6512                 crtc->fb = old_fb;
6513                 return false;
6514         }
6515
6516         /* let the connector get through one full cycle before testing */
6517         intel_wait_for_vblank(dev, intel_crtc->pipe);
6518
6519         return true;
6520 }
6521
6522 void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
6523                                     struct drm_connector *connector,
6524                                     struct intel_load_detect_pipe *old)
6525 {
6526         struct drm_encoder *encoder = &intel_encoder->base;
6527         struct drm_device *dev = encoder->dev;
6528         struct drm_crtc *crtc = encoder->crtc;
6529         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
6530         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
6531
6532         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6533                       connector->base.id, drm_get_connector_name(connector),
6534                       encoder->base.id, drm_get_encoder_name(encoder));
6535
6536         if (old->load_detect_temp) {
6537                 connector->encoder = NULL;
6538                 drm_helper_disable_unused_functions(dev);
6539
6540                 if (old->release_fb)
6541                         old->release_fb->funcs->destroy(old->release_fb);
6542
6543                 return;
6544         }
6545
6546         /* Switch crtc and encoder back off if necessary */
6547         if (old->dpms_mode != DRM_MODE_DPMS_ON) {
6548                 encoder_funcs->dpms(encoder, old->dpms_mode);
6549                 crtc_funcs->dpms(crtc, old->dpms_mode);
6550         }
6551 }
6552
6553 /* Returns the clock of the currently programmed mode of the given pipe. */
6554 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6555 {
6556         struct drm_i915_private *dev_priv = dev->dev_private;
6557         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6558         int pipe = intel_crtc->pipe;
6559         u32 dpll = I915_READ(DPLL(pipe));
6560         u32 fp;
6561         intel_clock_t clock;
6562
6563         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
6564                 fp = I915_READ(FP0(pipe));
6565         else
6566                 fp = I915_READ(FP1(pipe));
6567
6568         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
6569         if (IS_PINEVIEW(dev)) {
6570                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6571                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
6572         } else {
6573                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6574                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6575         }
6576
6577         if (!IS_GEN2(dev)) {
6578                 if (IS_PINEVIEW(dev))
6579                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6580                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
6581                 else
6582                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
6583                                DPLL_FPA01_P1_POST_DIV_SHIFT);
6584
6585                 switch (dpll & DPLL_MODE_MASK) {
6586                 case DPLLB_MODE_DAC_SERIAL:
6587                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6588                                 5 : 10;
6589                         break;
6590                 case DPLLB_MODE_LVDS:
6591                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6592                                 7 : 14;
6593                         break;
6594                 default:
6595                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
6596                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
6597                         return 0;
6598                 }
6599
6600                 /* XXX: Handle the 100Mhz refclk */
6601                 intel_clock(dev, 96000, &clock);
6602         } else {
6603                 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6604
6605                 if (is_lvds) {
6606                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6607                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
6608                         clock.p2 = 14;
6609
6610                         if ((dpll & PLL_REF_INPUT_MASK) ==
6611                             PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6612                                 /* XXX: might not be 66MHz */
6613                                 intel_clock(dev, 66000, &clock);
6614                         } else
6615                                 intel_clock(dev, 48000, &clock);
6616                 } else {
6617                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
6618                                 clock.p1 = 2;
6619                         else {
6620                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6621                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6622                         }
6623                         if (dpll & PLL_P2_DIVIDE_BY_4)
6624                                 clock.p2 = 4;
6625                         else
6626                                 clock.p2 = 2;
6627
6628                         intel_clock(dev, 48000, &clock);
6629                 }
6630         }
6631
6632         /* XXX: It would be nice to validate the clocks, but we can't reuse
6633          * i830PllIsValid() because it relies on the xf86_config connector
6634          * configuration being accurate, which it isn't necessarily.
6635          */
6636
6637         return clock.dot;
6638 }
6639
6640 /** Returns the currently programmed mode of the given pipe. */
6641 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6642                                              struct drm_crtc *crtc)
6643 {
6644         struct drm_i915_private *dev_priv = dev->dev_private;
6645         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6646         int pipe = intel_crtc->pipe;
6647         struct drm_display_mode *mode;
6648         int htot = I915_READ(HTOTAL(pipe));
6649         int hsync = I915_READ(HSYNC(pipe));
6650         int vtot = I915_READ(VTOTAL(pipe));
6651         int vsync = I915_READ(VSYNC(pipe));
6652
6653         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6654         if (!mode)
6655                 return NULL;
6656
6657         mode->clock = intel_crtc_clock_get(dev, crtc);
6658         mode->hdisplay = (htot & 0xffff) + 1;
6659         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6660         mode->hsync_start = (hsync & 0xffff) + 1;
6661         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6662         mode->vdisplay = (vtot & 0xffff) + 1;
6663         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6664         mode->vsync_start = (vsync & 0xffff) + 1;
6665         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6666
6667         drm_mode_set_name(mode);
6668         drm_mode_set_crtcinfo(mode, 0);
6669
6670         return mode;
6671 }
6672
6673 #define GPU_IDLE_TIMEOUT 500 /* ms */
6674
6675 /* When this timer fires, we've been idle for awhile */
6676 static void intel_gpu_idle_timer(unsigned long arg)
6677 {
6678         struct drm_device *dev = (struct drm_device *)arg;
6679         drm_i915_private_t *dev_priv = dev->dev_private;
6680
6681         if (!list_empty(&dev_priv->mm.active_list)) {
6682                 /* Still processing requests, so just re-arm the timer. */
6683                 mod_timer(&dev_priv->idle_timer, jiffies +
6684                           msecs_to_jiffies(GPU_IDLE_TIMEOUT));
6685                 return;
6686         }
6687
6688         dev_priv->busy = false;
6689         queue_work(dev_priv->wq, &dev_priv->idle_work);
6690 }
6691
6692 #define CRTC_IDLE_TIMEOUT 1000 /* ms */
6693
6694 static void intel_crtc_idle_timer(unsigned long arg)
6695 {
6696         struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
6697         struct drm_crtc *crtc = &intel_crtc->base;
6698         drm_i915_private_t *dev_priv = crtc->dev->dev_private;
6699         struct intel_framebuffer *intel_fb;
6700
6701         intel_fb = to_intel_framebuffer(crtc->fb);
6702         if (intel_fb && intel_fb->obj->active) {
6703                 /* The framebuffer is still being accessed by the GPU. */
6704                 mod_timer(&intel_crtc->idle_timer, jiffies +
6705                           msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
6706                 return;
6707         }
6708
6709         intel_crtc->busy = false;
6710         queue_work(dev_priv->wq, &dev_priv->idle_work);
6711 }
6712
6713 static void intel_increase_pllclock(struct drm_crtc *crtc)
6714 {
6715         struct drm_device *dev = crtc->dev;
6716         drm_i915_private_t *dev_priv = dev->dev_private;
6717         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6718         int pipe = intel_crtc->pipe;
6719         int dpll_reg = DPLL(pipe);
6720         int dpll;
6721
6722         if (HAS_PCH_SPLIT(dev))
6723                 return;
6724
6725         if (!dev_priv->lvds_downclock_avail)
6726                 return;
6727
6728         dpll = I915_READ(dpll_reg);
6729         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
6730                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
6731
6732                 /* Unlock panel regs */
6733                 I915_WRITE(PP_CONTROL,
6734                            I915_READ(PP_CONTROL) | PANEL_UNLOCK_REGS);
6735
6736                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
6737                 I915_WRITE(dpll_reg, dpll);
6738                 intel_wait_for_vblank(dev, pipe);
6739
6740                 dpll = I915_READ(dpll_reg);
6741                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
6742                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
6743
6744                 /* ...and lock them again */
6745                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
6746         }
6747
6748         /* Schedule downclock */
6749         mod_timer(&intel_crtc->idle_timer, jiffies +
6750                   msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
6751 }
6752
6753 static void intel_decrease_pllclock(struct drm_crtc *crtc)
6754 {
6755         struct drm_device *dev = crtc->dev;
6756         drm_i915_private_t *dev_priv = dev->dev_private;
6757         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6758         int pipe = intel_crtc->pipe;
6759         int dpll_reg = DPLL(pipe);
6760         int dpll = I915_READ(dpll_reg);
6761
6762         if (HAS_PCH_SPLIT(dev))
6763                 return;
6764
6765         if (!dev_priv->lvds_downclock_avail)
6766                 return;
6767
6768         /*
6769          * Since this is called by a timer, we should never get here in
6770          * the manual case.
6771          */
6772         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
6773                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
6774
6775                 /* Unlock panel regs */
6776                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) |
6777                            PANEL_UNLOCK_REGS);
6778
6779                 dpll |= DISPLAY_RATE_SELECT_FPA1;
6780                 I915_WRITE(dpll_reg, dpll);
6781                 intel_wait_for_vblank(dev, pipe);
6782                 dpll = I915_READ(dpll_reg);
6783                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
6784                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
6785
6786                 /* ...and lock them again */
6787                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
6788         }
6789
6790 }
6791
6792 /**
6793  * intel_idle_update - adjust clocks for idleness
6794  * @work: work struct
6795  *
6796  * Either the GPU or display (or both) went idle.  Check the busy status
6797  * here and adjust the CRTC and GPU clocks as necessary.
6798  */
6799 static void intel_idle_update(struct work_struct *work)
6800 {
6801         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
6802                                                     idle_work);
6803         struct drm_device *dev = dev_priv->dev;
6804         struct drm_crtc *crtc;
6805         struct intel_crtc *intel_crtc;
6806
6807         if (!i915_powersave)
6808                 return;
6809
6810         mutex_lock(&dev->struct_mutex);
6811
6812         i915_update_gfx_val(dev_priv);
6813
6814         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6815                 /* Skip inactive CRTCs */
6816                 if (!crtc->fb)
6817                         continue;
6818
6819                 intel_crtc = to_intel_crtc(crtc);
6820                 if (!intel_crtc->busy)
6821                         intel_decrease_pllclock(crtc);
6822         }
6823
6824
6825         mutex_unlock(&dev->struct_mutex);
6826 }
6827
6828 /**
6829  * intel_mark_busy - mark the GPU and possibly the display busy
6830  * @dev: drm device
6831  * @obj: object we're operating on
6832  *
6833  * Callers can use this function to indicate that the GPU is busy processing
6834  * commands.  If @obj matches one of the CRTC objects (i.e. it's a scanout
6835  * buffer), we'll also mark the display as busy, so we know to increase its
6836  * clock frequency.
6837  */
6838 void intel_mark_busy(struct drm_device *dev, struct drm_i915_gem_object *obj)
6839 {
6840         drm_i915_private_t *dev_priv = dev->dev_private;
6841         struct drm_crtc *crtc = NULL;
6842         struct intel_framebuffer *intel_fb;
6843         struct intel_crtc *intel_crtc;
6844
6845         if (!drm_core_check_feature(dev, DRIVER_MODESET))
6846                 return;
6847
6848         if (!dev_priv->busy)
6849                 dev_priv->busy = true;
6850         else
6851                 mod_timer(&dev_priv->idle_timer, jiffies +
6852                           msecs_to_jiffies(GPU_IDLE_TIMEOUT));
6853
6854         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6855                 if (!crtc->fb)
6856                         continue;
6857
6858                 intel_crtc = to_intel_crtc(crtc);
6859                 intel_fb = to_intel_framebuffer(crtc->fb);
6860                 if (intel_fb->obj == obj) {
6861                         if (!intel_crtc->busy) {
6862                                 /* Non-busy -> busy, upclock */
6863                                 intel_increase_pllclock(crtc);
6864                                 intel_crtc->busy = true;
6865                         } else {
6866                                 /* Busy -> busy, put off timer */
6867                                 mod_timer(&intel_crtc->idle_timer, jiffies +
6868                                           msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
6869                         }
6870                 }
6871         }
6872 }
6873
6874 static void intel_crtc_destroy(struct drm_crtc *crtc)
6875 {
6876         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6877         struct drm_device *dev = crtc->dev;
6878         struct intel_unpin_work *work;
6879         unsigned long flags;
6880
6881         spin_lock_irqsave(&dev->event_lock, flags);
6882         work = intel_crtc->unpin_work;
6883         intel_crtc->unpin_work = NULL;
6884         spin_unlock_irqrestore(&dev->event_lock, flags);
6885
6886         if (work) {
6887                 cancel_work_sync(&work->work);
6888                 kfree(work);
6889         }
6890
6891         drm_crtc_cleanup(crtc);
6892
6893         kfree(intel_crtc);
6894 }
6895
6896 static void intel_unpin_work_fn(struct work_struct *__work)
6897 {
6898         struct intel_unpin_work *work =
6899                 container_of(__work, struct intel_unpin_work, work);
6900
6901         mutex_lock(&work->dev->struct_mutex);
6902         i915_gem_object_unpin(work->old_fb_obj);
6903         drm_gem_object_unreference(&work->pending_flip_obj->base);
6904         drm_gem_object_unreference(&work->old_fb_obj->base);
6905
6906         intel_update_fbc(work->dev);
6907         mutex_unlock(&work->dev->struct_mutex);
6908         kfree(work);
6909 }
6910
6911 static void do_intel_finish_page_flip(struct drm_device *dev,
6912                                       struct drm_crtc *crtc)
6913 {
6914         drm_i915_private_t *dev_priv = dev->dev_private;
6915         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6916         struct intel_unpin_work *work;
6917         struct drm_i915_gem_object *obj;
6918         struct drm_pending_vblank_event *e;
6919         struct timeval tnow, tvbl;
6920         unsigned long flags;
6921
6922         /* Ignore early vblank irqs */
6923         if (intel_crtc == NULL)
6924                 return;
6925
6926         do_gettimeofday(&tnow);
6927
6928         spin_lock_irqsave(&dev->event_lock, flags);
6929         work = intel_crtc->unpin_work;
6930         if (work == NULL || !work->pending) {
6931                 spin_unlock_irqrestore(&dev->event_lock, flags);
6932                 return;
6933         }
6934
6935         intel_crtc->unpin_work = NULL;
6936
6937         if (work->event) {
6938                 e = work->event;
6939                 e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
6940
6941                 /* Called before vblank count and timestamps have
6942                  * been updated for the vblank interval of flip
6943                  * completion? Need to increment vblank count and
6944                  * add one videorefresh duration to returned timestamp
6945                  * to account for this. We assume this happened if we
6946                  * get called over 0.9 frame durations after the last
6947                  * timestamped vblank.
6948                  *
6949                  * This calculation can not be used with vrefresh rates
6950                  * below 5Hz (10Hz to be on the safe side) without
6951                  * promoting to 64 integers.
6952                  */
6953                 if (10 * (timeval_to_ns(&tnow) - timeval_to_ns(&tvbl)) >
6954                     9 * crtc->framedur_ns) {
6955                         e->event.sequence++;
6956                         tvbl = ns_to_timeval(timeval_to_ns(&tvbl) +
6957                                              crtc->framedur_ns);
6958                 }
6959
6960                 e->event.tv_sec = tvbl.tv_sec;
6961                 e->event.tv_usec = tvbl.tv_usec;
6962
6963                 list_add_tail(&e->base.link,
6964                               &e->base.file_priv->event_list);
6965                 wake_up_interruptible(&e->base.file_priv->event_wait);
6966         }
6967
6968         drm_vblank_put(dev, intel_crtc->pipe);
6969
6970         spin_unlock_irqrestore(&dev->event_lock, flags);
6971
6972         obj = work->old_fb_obj;
6973
6974         atomic_clear_mask(1 << intel_crtc->plane,
6975                           &obj->pending_flip.counter);
6976
6977         wake_up(&dev_priv->pending_flip_queue);
6978         schedule_work(&work->work);
6979
6980         trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6981 }
6982
6983 void intel_finish_page_flip(struct drm_device *dev, int pipe)
6984 {
6985         drm_i915_private_t *dev_priv = dev->dev_private;
6986         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
6987
6988         do_intel_finish_page_flip(dev, crtc);
6989 }
6990
6991 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
6992 {
6993         drm_i915_private_t *dev_priv = dev->dev_private;
6994         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
6995
6996         do_intel_finish_page_flip(dev, crtc);
6997 }
6998
6999 void intel_prepare_page_flip(struct drm_device *dev, int plane)
7000 {
7001         drm_i915_private_t *dev_priv = dev->dev_private;
7002         struct intel_crtc *intel_crtc =
7003                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7004         unsigned long flags;
7005
7006         spin_lock_irqsave(&dev->event_lock, flags);
7007         if (intel_crtc->unpin_work) {
7008                 if ((++intel_crtc->unpin_work->pending) > 1)
7009                         DRM_ERROR("Prepared flip multiple times\n");
7010         } else {
7011                 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
7012         }
7013         spin_unlock_irqrestore(&dev->event_lock, flags);
7014 }
7015
7016 static int intel_gen2_queue_flip(struct drm_device *dev,
7017                                  struct drm_crtc *crtc,
7018                                  struct drm_framebuffer *fb,
7019                                  struct drm_i915_gem_object *obj)
7020 {
7021         struct drm_i915_private *dev_priv = dev->dev_private;
7022         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7023         unsigned long offset;
7024         u32 flip_mask;
7025         int ret;
7026
7027         ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
7028         if (ret)
7029                 goto err;
7030
7031         /* Offset into the new buffer for cases of shared fbs between CRTCs */
7032         offset = crtc->y * fb->pitch + crtc->x * fb->bits_per_pixel/8;
7033
7034         ret = BEGIN_LP_RING(6);
7035         if (ret)
7036                 goto err_unpin;
7037
7038         /* Can't queue multiple flips, so wait for the previous
7039          * one to finish before executing the next.
7040          */
7041         if (intel_crtc->plane)
7042                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7043         else
7044                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7045         OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
7046         OUT_RING(MI_NOOP);
7047         OUT_RING(MI_DISPLAY_FLIP |
7048                  MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7049         OUT_RING(fb->pitch);
7050         OUT_RING(obj->gtt_offset + offset);
7051         OUT_RING(MI_NOOP);
7052         ADVANCE_LP_RING();
7053         return 0;
7054
7055 err_unpin:
7056         i915_gem_object_unpin(obj);
7057 err:
7058         return ret;
7059 }
7060
7061 static int intel_gen3_queue_flip(struct drm_device *dev,
7062                                  struct drm_crtc *crtc,
7063                                  struct drm_framebuffer *fb,
7064                                  struct drm_i915_gem_object *obj)
7065 {
7066         struct drm_i915_private *dev_priv = dev->dev_private;
7067         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7068         unsigned long offset;
7069         u32 flip_mask;
7070         int ret;
7071
7072         ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
7073         if (ret)
7074                 goto err;
7075
7076         /* Offset into the new buffer for cases of shared fbs between CRTCs */
7077         offset = crtc->y * fb->pitch + crtc->x * fb->bits_per_pixel/8;
7078
7079         ret = BEGIN_LP_RING(6);
7080         if (ret)
7081                 goto err_unpin;
7082
7083         if (intel_crtc->plane)
7084                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7085         else
7086                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7087         OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
7088         OUT_RING(MI_NOOP);
7089         OUT_RING(MI_DISPLAY_FLIP_I915 |
7090                  MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7091         OUT_RING(fb->pitch);
7092         OUT_RING(obj->gtt_offset + offset);
7093         OUT_RING(MI_NOOP);
7094
7095         ADVANCE_LP_RING();
7096         return 0;
7097
7098 err_unpin:
7099         i915_gem_object_unpin(obj);
7100 err:
7101         return ret;
7102 }
7103
7104 static int intel_gen4_queue_flip(struct drm_device *dev,
7105                                  struct drm_crtc *crtc,
7106                                  struct drm_framebuffer *fb,
7107                                  struct drm_i915_gem_object *obj)
7108 {
7109         struct drm_i915_private *dev_priv = dev->dev_private;
7110         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7111         uint32_t pf, pipesrc;
7112         int ret;
7113
7114         ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
7115         if (ret)
7116                 goto err;
7117
7118         ret = BEGIN_LP_RING(4);
7119         if (ret)
7120                 goto err_unpin;
7121
7122         /* i965+ uses the linear or tiled offsets from the
7123          * Display Registers (which do not change across a page-flip)
7124          * so we need only reprogram the base address.
7125          */
7126         OUT_RING(MI_DISPLAY_FLIP |
7127                  MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7128         OUT_RING(fb->pitch);
7129         OUT_RING(obj->gtt_offset | obj->tiling_mode);
7130
7131         /* XXX Enabling the panel-fitter across page-flip is so far
7132          * untested on non-native modes, so ignore it for now.
7133          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7134          */
7135         pf = 0;
7136         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7137         OUT_RING(pf | pipesrc);
7138         ADVANCE_LP_RING();
7139         return 0;
7140
7141 err_unpin:
7142         i915_gem_object_unpin(obj);
7143 err:
7144         return ret;
7145 }
7146
7147 static int intel_gen6_queue_flip(struct drm_device *dev,
7148                                  struct drm_crtc *crtc,
7149                                  struct drm_framebuffer *fb,
7150                                  struct drm_i915_gem_object *obj)
7151 {
7152         struct drm_i915_private *dev_priv = dev->dev_private;
7153         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7154         uint32_t pf, pipesrc;
7155         int ret;
7156
7157         ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
7158         if (ret)
7159                 goto err;
7160
7161         ret = BEGIN_LP_RING(4);
7162         if (ret)
7163                 goto err_unpin;
7164
7165         OUT_RING(MI_DISPLAY_FLIP |
7166                  MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7167         OUT_RING(fb->pitch | obj->tiling_mode);
7168         OUT_RING(obj->gtt_offset);
7169
7170         pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7171         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7172         OUT_RING(pf | pipesrc);
7173         ADVANCE_LP_RING();
7174         return 0;
7175
7176 err_unpin:
7177         i915_gem_object_unpin(obj);
7178 err:
7179         return ret;
7180 }
7181
7182 /*
7183  * On gen7 we currently use the blit ring because (in early silicon at least)
7184  * the render ring doesn't give us interrpts for page flip completion, which
7185  * means clients will hang after the first flip is queued.  Fortunately the
7186  * blit ring generates interrupts properly, so use it instead.
7187  */
7188 static int intel_gen7_queue_flip(struct drm_device *dev,
7189                                  struct drm_crtc *crtc,
7190                                  struct drm_framebuffer *fb,
7191                                  struct drm_i915_gem_object *obj)
7192 {
7193         struct drm_i915_private *dev_priv = dev->dev_private;
7194         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7195         struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
7196         uint32_t plane_bit = 0;
7197         int ret;
7198
7199         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7200         if (ret)
7201                 goto err;
7202
7203         switch(intel_crtc->plane) {
7204         case PLANE_A:
7205                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7206                 break;
7207         case PLANE_B:
7208                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7209                 break;
7210         case PLANE_C:
7211                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7212                 break;
7213         default:
7214                 WARN_ONCE(1, "unknown plane in flip command\n");
7215                 ret = -ENODEV;
7216                 goto err_unpin;
7217         }
7218
7219         ret = intel_ring_begin(ring, 4);
7220         if (ret)
7221                 goto err_unpin;
7222
7223         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
7224         intel_ring_emit(ring, (fb->pitch | obj->tiling_mode));
7225         intel_ring_emit(ring, (obj->gtt_offset));
7226         intel_ring_emit(ring, (MI_NOOP));
7227         intel_ring_advance(ring);
7228         return 0;
7229
7230 err_unpin:
7231         i915_gem_object_unpin(obj);
7232 err:
7233         return ret;
7234 }
7235
7236 static int intel_default_queue_flip(struct drm_device *dev,
7237                                     struct drm_crtc *crtc,
7238                                     struct drm_framebuffer *fb,
7239                                     struct drm_i915_gem_object *obj)
7240 {
7241         return -ENODEV;
7242 }
7243
7244 static int intel_crtc_page_flip(struct drm_crtc *crtc,
7245                                 struct drm_framebuffer *fb,
7246                                 struct drm_pending_vblank_event *event)
7247 {
7248         struct drm_device *dev = crtc->dev;
7249         struct drm_i915_private *dev_priv = dev->dev_private;
7250         struct intel_framebuffer *intel_fb;
7251         struct drm_i915_gem_object *obj;
7252         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7253         struct intel_unpin_work *work;
7254         unsigned long flags;
7255         int ret;
7256
7257         work = kzalloc(sizeof *work, GFP_KERNEL);
7258         if (work == NULL)
7259                 return -ENOMEM;
7260
7261         work->event = event;
7262         work->dev = crtc->dev;
7263         intel_fb = to_intel_framebuffer(crtc->fb);
7264         work->old_fb_obj = intel_fb->obj;
7265         INIT_WORK(&work->work, intel_unpin_work_fn);
7266
7267         ret = drm_vblank_get(dev, intel_crtc->pipe);
7268         if (ret)
7269                 goto free_work;
7270
7271         /* We borrow the event spin lock for protecting unpin_work */
7272         spin_lock_irqsave(&dev->event_lock, flags);
7273         if (intel_crtc->unpin_work) {
7274                 spin_unlock_irqrestore(&dev->event_lock, flags);
7275                 kfree(work);
7276                 drm_vblank_put(dev, intel_crtc->pipe);
7277
7278                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
7279                 return -EBUSY;
7280         }
7281         intel_crtc->unpin_work = work;
7282         spin_unlock_irqrestore(&dev->event_lock, flags);
7283
7284         intel_fb = to_intel_framebuffer(fb);
7285         obj = intel_fb->obj;
7286
7287         mutex_lock(&dev->struct_mutex);
7288
7289         /* Reference the objects for the scheduled work. */
7290         drm_gem_object_reference(&work->old_fb_obj->base);
7291         drm_gem_object_reference(&obj->base);
7292
7293         crtc->fb = fb;
7294
7295         work->pending_flip_obj = obj;
7296
7297         work->enable_stall_check = true;
7298
7299         /* Block clients from rendering to the new back buffer until
7300          * the flip occurs and the object is no longer visible.
7301          */
7302         atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
7303
7304         ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7305         if (ret)
7306                 goto cleanup_pending;
7307
7308         intel_disable_fbc(dev);
7309         mutex_unlock(&dev->struct_mutex);
7310
7311         trace_i915_flip_request(intel_crtc->plane, obj);
7312
7313         return 0;
7314
7315 cleanup_pending:
7316         atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
7317         drm_gem_object_unreference(&work->old_fb_obj->base);
7318         drm_gem_object_unreference(&obj->base);
7319         mutex_unlock(&dev->struct_mutex);
7320
7321         spin_lock_irqsave(&dev->event_lock, flags);
7322         intel_crtc->unpin_work = NULL;
7323         spin_unlock_irqrestore(&dev->event_lock, flags);
7324
7325         drm_vblank_put(dev, intel_crtc->pipe);
7326 free_work:
7327         kfree(work);
7328
7329         return ret;
7330 }
7331
7332 static void intel_sanitize_modesetting(struct drm_device *dev,
7333                                        int pipe, int plane)
7334 {
7335         struct drm_i915_private *dev_priv = dev->dev_private;
7336         u32 reg, val;
7337         int i;
7338
7339         /* Clear any frame start delays used for debugging left by the BIOS */
7340         for_each_pipe(i) {
7341                 reg = PIPECONF(i);
7342                 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
7343         }
7344
7345         if (HAS_PCH_SPLIT(dev))
7346                 return;
7347
7348         /* Who knows what state these registers were left in by the BIOS or
7349          * grub?
7350          *
7351          * If we leave the registers in a conflicting state (e.g. with the
7352          * display plane reading from the other pipe than the one we intend
7353          * to use) then when we attempt to teardown the active mode, we will
7354          * not disable the pipes and planes in the correct order -- leaving
7355          * a plane reading from a disabled pipe and possibly leading to
7356          * undefined behaviour.
7357          */
7358
7359         reg = DSPCNTR(plane);
7360         val = I915_READ(reg);
7361
7362         if ((val & DISPLAY_PLANE_ENABLE) == 0)
7363                 return;
7364         if (!!(val & DISPPLANE_SEL_PIPE_MASK) == pipe)
7365                 return;
7366
7367         /* This display plane is active and attached to the other CPU pipe. */
7368         pipe = !pipe;
7369
7370         /* Disable the plane and wait for it to stop reading from the pipe. */
7371         intel_disable_plane(dev_priv, plane, pipe);
7372         intel_disable_pipe(dev_priv, pipe);
7373 }
7374
7375 static void intel_crtc_reset(struct drm_crtc *crtc)
7376 {
7377         struct drm_device *dev = crtc->dev;
7378         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7379
7380         /* Reset flags back to the 'unknown' status so that they
7381          * will be correctly set on the initial modeset.
7382          */
7383         intel_crtc->dpms_mode = -1;
7384
7385         /* We need to fix up any BIOS configuration that conflicts with
7386          * our expectations.
7387          */
7388         intel_sanitize_modesetting(dev, intel_crtc->pipe, intel_crtc->plane);
7389 }
7390
7391 static struct drm_crtc_helper_funcs intel_helper_funcs = {
7392         .dpms = intel_crtc_dpms,
7393         .mode_fixup = intel_crtc_mode_fixup,
7394         .mode_set = intel_crtc_mode_set,
7395         .mode_set_base = intel_pipe_set_base,
7396         .mode_set_base_atomic = intel_pipe_set_base_atomic,
7397         .load_lut = intel_crtc_load_lut,
7398         .disable = intel_crtc_disable,
7399 };
7400
7401 static const struct drm_crtc_funcs intel_crtc_funcs = {
7402         .reset = intel_crtc_reset,
7403         .cursor_set = intel_crtc_cursor_set,
7404         .cursor_move = intel_crtc_cursor_move,
7405         .gamma_set = intel_crtc_gamma_set,
7406         .set_config = drm_crtc_helper_set_config,
7407         .destroy = intel_crtc_destroy,
7408         .page_flip = intel_crtc_page_flip,
7409 };
7410
7411 static void intel_crtc_init(struct drm_device *dev, int pipe)
7412 {
7413         drm_i915_private_t *dev_priv = dev->dev_private;
7414         struct intel_crtc *intel_crtc;
7415         int i;
7416
7417         intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
7418         if (intel_crtc == NULL)
7419                 return;
7420
7421         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
7422
7423         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
7424         for (i = 0; i < 256; i++) {
7425                 intel_crtc->lut_r[i] = i;
7426                 intel_crtc->lut_g[i] = i;
7427                 intel_crtc->lut_b[i] = i;
7428         }
7429
7430         /* Swap pipes & planes for FBC on pre-965 */
7431         intel_crtc->pipe = pipe;
7432         intel_crtc->plane = pipe;
7433         if (IS_MOBILE(dev) && IS_GEN3(dev)) {
7434                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
7435                 intel_crtc->plane = !pipe;
7436         }
7437
7438         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
7439                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
7440         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
7441         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
7442
7443         intel_crtc_reset(&intel_crtc->base);
7444         intel_crtc->active = true; /* force the pipe off on setup_init_config */
7445         intel_crtc->bpp = 24; /* default for pre-Ironlake */
7446
7447         if (HAS_PCH_SPLIT(dev)) {
7448                 if (pipe == 2 && IS_IVYBRIDGE(dev))
7449                         intel_crtc->no_pll = true;
7450                 intel_helper_funcs.prepare = ironlake_crtc_prepare;
7451                 intel_helper_funcs.commit = ironlake_crtc_commit;
7452         } else {
7453                 intel_helper_funcs.prepare = i9xx_crtc_prepare;
7454                 intel_helper_funcs.commit = i9xx_crtc_commit;
7455         }
7456
7457         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
7458
7459         intel_crtc->busy = false;
7460
7461         setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
7462                     (unsigned long)intel_crtc);
7463 }
7464
7465 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
7466                                 struct drm_file *file)
7467 {
7468         drm_i915_private_t *dev_priv = dev->dev_private;
7469         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
7470         struct drm_mode_object *drmmode_obj;
7471         struct intel_crtc *crtc;
7472
7473         if (!dev_priv) {
7474                 DRM_ERROR("called with no initialization\n");
7475                 return -EINVAL;
7476         }
7477
7478         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
7479                         DRM_MODE_OBJECT_CRTC);
7480
7481         if (!drmmode_obj) {
7482                 DRM_ERROR("no such CRTC id\n");
7483                 return -EINVAL;
7484         }
7485
7486         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
7487         pipe_from_crtc_id->pipe = crtc->pipe;
7488
7489         return 0;
7490 }
7491
7492 static int intel_encoder_clones(struct drm_device *dev, int type_mask)
7493 {
7494         struct intel_encoder *encoder;
7495         int index_mask = 0;
7496         int entry = 0;
7497
7498         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7499                 if (type_mask & encoder->clone_mask)
7500                         index_mask |= (1 << entry);
7501                 entry++;
7502         }
7503
7504         return index_mask;
7505 }
7506
7507 static bool has_edp_a(struct drm_device *dev)
7508 {
7509         struct drm_i915_private *dev_priv = dev->dev_private;
7510
7511         if (!IS_MOBILE(dev))
7512                 return false;
7513
7514         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
7515                 return false;
7516
7517         if (IS_GEN5(dev) &&
7518             (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
7519                 return false;
7520
7521         return true;
7522 }
7523
7524 static void intel_setup_outputs(struct drm_device *dev)
7525 {
7526         struct drm_i915_private *dev_priv = dev->dev_private;
7527         struct intel_encoder *encoder;
7528         bool dpd_is_edp = false;
7529         bool has_lvds = false;
7530
7531         if (IS_MOBILE(dev) && !IS_I830(dev))
7532                 has_lvds = intel_lvds_init(dev);
7533         if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
7534                 /* disable the panel fitter on everything but LVDS */
7535                 I915_WRITE(PFIT_CONTROL, 0);
7536         }
7537
7538         if (HAS_PCH_SPLIT(dev)) {
7539                 dpd_is_edp = intel_dpd_is_edp(dev);
7540
7541                 if (has_edp_a(dev))
7542                         intel_dp_init(dev, DP_A);
7543
7544                 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
7545                         intel_dp_init(dev, PCH_DP_D);
7546         }
7547
7548         intel_crt_init(dev);
7549
7550         if (HAS_PCH_SPLIT(dev)) {
7551                 int found;
7552
7553                 if (I915_READ(HDMIB) & PORT_DETECTED) {
7554                         /* PCH SDVOB multiplex with HDMIB */
7555                         found = intel_sdvo_init(dev, PCH_SDVOB);
7556                         if (!found)
7557                                 intel_hdmi_init(dev, HDMIB);
7558                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
7559                                 intel_dp_init(dev, PCH_DP_B);
7560                 }
7561
7562                 if (I915_READ(HDMIC) & PORT_DETECTED)
7563                         intel_hdmi_init(dev, HDMIC);
7564
7565                 if (I915_READ(HDMID) & PORT_DETECTED)
7566                         intel_hdmi_init(dev, HDMID);
7567
7568                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
7569                         intel_dp_init(dev, PCH_DP_C);
7570
7571                 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
7572                         intel_dp_init(dev, PCH_DP_D);
7573
7574         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
7575                 bool found = false;
7576
7577                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
7578                         DRM_DEBUG_KMS("probing SDVOB\n");
7579                         found = intel_sdvo_init(dev, SDVOB);
7580                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
7581                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
7582                                 intel_hdmi_init(dev, SDVOB);
7583                         }
7584
7585                         if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
7586                                 DRM_DEBUG_KMS("probing DP_B\n");
7587                                 intel_dp_init(dev, DP_B);
7588                         }
7589                 }
7590
7591                 /* Before G4X SDVOC doesn't have its own detect register */
7592
7593                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
7594                         DRM_DEBUG_KMS("probing SDVOC\n");
7595                         found = intel_sdvo_init(dev, SDVOC);
7596                 }
7597
7598                 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
7599
7600                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
7601                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
7602                                 intel_hdmi_init(dev, SDVOC);
7603                         }
7604                         if (SUPPORTS_INTEGRATED_DP(dev)) {
7605                                 DRM_DEBUG_KMS("probing DP_C\n");
7606                                 intel_dp_init(dev, DP_C);
7607                         }
7608                 }
7609
7610                 if (SUPPORTS_INTEGRATED_DP(dev) &&
7611                     (I915_READ(DP_D) & DP_DETECTED)) {
7612                         DRM_DEBUG_KMS("probing DP_D\n");
7613                         intel_dp_init(dev, DP_D);
7614                 }
7615         } else if (IS_GEN2(dev))
7616                 intel_dvo_init(dev);
7617
7618         if (SUPPORTS_TV(dev))
7619                 intel_tv_init(dev);
7620
7621         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7622                 encoder->base.possible_crtcs = encoder->crtc_mask;
7623                 encoder->base.possible_clones =
7624                         intel_encoder_clones(dev, encoder->clone_mask);
7625         }
7626
7627         /* disable all the possible outputs/crtcs before entering KMS mode */
7628         drm_helper_disable_unused_functions(dev);
7629
7630         if (HAS_PCH_SPLIT(dev))
7631                 ironlake_init_pch_refclk(dev);
7632 }
7633
7634 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
7635 {
7636         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
7637
7638         drm_framebuffer_cleanup(fb);
7639         drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
7640
7641         kfree(intel_fb);
7642 }
7643
7644 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
7645                                                 struct drm_file *file,
7646                                                 unsigned int *handle)
7647 {
7648         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
7649         struct drm_i915_gem_object *obj = intel_fb->obj;
7650
7651         return drm_gem_handle_create(file, &obj->base, handle);
7652 }
7653
7654 static const struct drm_framebuffer_funcs intel_fb_funcs = {
7655         .destroy = intel_user_framebuffer_destroy,
7656         .create_handle = intel_user_framebuffer_create_handle,
7657 };
7658
7659 int intel_framebuffer_init(struct drm_device *dev,
7660                            struct intel_framebuffer *intel_fb,
7661                            struct drm_mode_fb_cmd *mode_cmd,
7662                            struct drm_i915_gem_object *obj)
7663 {
7664         int ret;
7665
7666         if (obj->tiling_mode == I915_TILING_Y)
7667                 return -EINVAL;
7668
7669         if (mode_cmd->pitch & 63)
7670                 return -EINVAL;
7671
7672         switch (mode_cmd->bpp) {
7673         case 8:
7674         case 16:
7675                 /* Only pre-ILK can handle 5:5:5 */
7676                 if (mode_cmd->depth == 15 && !HAS_PCH_SPLIT(dev))
7677                         return -EINVAL;
7678                 break;
7679
7680         case 24:
7681         case 32:
7682                 break;
7683         default:
7684                 return -EINVAL;
7685         }
7686
7687         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
7688         if (ret) {
7689                 DRM_ERROR("framebuffer init failed %d\n", ret);
7690                 return ret;
7691         }
7692
7693         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
7694         intel_fb->obj = obj;
7695         return 0;
7696 }
7697
7698 static struct drm_framebuffer *
7699 intel_user_framebuffer_create(struct drm_device *dev,
7700                               struct drm_file *filp,
7701                               struct drm_mode_fb_cmd *mode_cmd)
7702 {
7703         struct drm_i915_gem_object *obj;
7704
7705         obj = to_intel_bo(drm_gem_object_lookup(dev, filp, mode_cmd->handle));
7706         if (&obj->base == NULL)
7707                 return ERR_PTR(-ENOENT);
7708
7709         return intel_framebuffer_create(dev, mode_cmd, obj);
7710 }
7711
7712 static const struct drm_mode_config_funcs intel_mode_funcs = {
7713         .fb_create = intel_user_framebuffer_create,
7714         .output_poll_changed = intel_fb_output_poll_changed,
7715 };
7716
7717 static struct drm_i915_gem_object *
7718 intel_alloc_context_page(struct drm_device *dev)
7719 {
7720         struct drm_i915_gem_object *ctx;
7721         int ret;
7722
7723         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
7724
7725         ctx = i915_gem_alloc_object(dev, 4096);
7726         if (!ctx) {
7727                 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
7728                 return NULL;
7729         }
7730
7731         ret = i915_gem_object_pin(ctx, 4096, true);
7732         if (ret) {
7733                 DRM_ERROR("failed to pin power context: %d\n", ret);
7734                 goto err_unref;
7735         }
7736
7737         ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
7738         if (ret) {
7739                 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
7740                 goto err_unpin;
7741         }
7742
7743         return ctx;
7744
7745 err_unpin:
7746         i915_gem_object_unpin(ctx);
7747 err_unref:
7748         drm_gem_object_unreference(&ctx->base);
7749         mutex_unlock(&dev->struct_mutex);
7750         return NULL;
7751 }
7752
7753 bool ironlake_set_drps(struct drm_device *dev, u8 val)
7754 {
7755         struct drm_i915_private *dev_priv = dev->dev_private;
7756         u16 rgvswctl;
7757
7758         rgvswctl = I915_READ16(MEMSWCTL);
7759         if (rgvswctl & MEMCTL_CMD_STS) {
7760                 DRM_DEBUG("gpu busy, RCS change rejected\n");
7761                 return false; /* still busy with another command */
7762         }
7763
7764         rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
7765                 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
7766         I915_WRITE16(MEMSWCTL, rgvswctl);
7767         POSTING_READ16(MEMSWCTL);
7768
7769         rgvswctl |= MEMCTL_CMD_STS;
7770         I915_WRITE16(MEMSWCTL, rgvswctl);
7771
7772         return true;
7773 }
7774
7775 void ironlake_enable_drps(struct drm_device *dev)
7776 {
7777         struct drm_i915_private *dev_priv = dev->dev_private;
7778         u32 rgvmodectl = I915_READ(MEMMODECTL);
7779         u8 fmax, fmin, fstart, vstart;
7780
7781         /* Enable temp reporting */
7782         I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
7783         I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
7784
7785         /* 100ms RC evaluation intervals */
7786         I915_WRITE(RCUPEI, 100000);
7787         I915_WRITE(RCDNEI, 100000);
7788
7789         /* Set max/min thresholds to 90ms and 80ms respectively */
7790         I915_WRITE(RCBMAXAVG, 90000);
7791         I915_WRITE(RCBMINAVG, 80000);
7792
7793         I915_WRITE(MEMIHYST, 1);
7794
7795         /* Set up min, max, and cur for interrupt handling */
7796         fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
7797         fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
7798         fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
7799                 MEMMODE_FSTART_SHIFT;
7800
7801         vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
7802                 PXVFREQ_PX_SHIFT;
7803
7804         dev_priv->fmax = fmax; /* IPS callback will increase this */
7805         dev_priv->fstart = fstart;
7806
7807         dev_priv->max_delay = fstart;
7808         dev_priv->min_delay = fmin;
7809         dev_priv->cur_delay = fstart;
7810
7811         DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
7812                          fmax, fmin, fstart);
7813
7814         I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
7815
7816         /*
7817          * Interrupts will be enabled in ironlake_irq_postinstall
7818          */
7819
7820         I915_WRITE(VIDSTART, vstart);
7821         POSTING_READ(VIDSTART);
7822
7823         rgvmodectl |= MEMMODE_SWMODE_EN;
7824         I915_WRITE(MEMMODECTL, rgvmodectl);
7825
7826         if (wait_for((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
7827                 DRM_ERROR("stuck trying to change perf mode\n");
7828         msleep(1);
7829
7830         ironlake_set_drps(dev, fstart);
7831
7832         dev_priv->last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
7833                 I915_READ(0x112e0);
7834         dev_priv->last_time1 = jiffies_to_msecs(jiffies);
7835         dev_priv->last_count2 = I915_READ(0x112f4);
7836         getrawmonotonic(&dev_priv->last_time2);
7837 }
7838
7839 void ironlake_disable_drps(struct drm_device *dev)
7840 {
7841         struct drm_i915_private *dev_priv = dev->dev_private;
7842         u16 rgvswctl = I915_READ16(MEMSWCTL);
7843
7844         /* Ack interrupts, disable EFC interrupt */
7845         I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
7846         I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
7847         I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
7848         I915_WRITE(DEIIR, DE_PCU_EVENT);
7849         I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
7850
7851         /* Go back to the starting frequency */
7852         ironlake_set_drps(dev, dev_priv->fstart);
7853         msleep(1);
7854         rgvswctl |= MEMCTL_CMD_STS;
7855         I915_WRITE(MEMSWCTL, rgvswctl);
7856         msleep(1);
7857
7858 }
7859
7860 void gen6_set_rps(struct drm_device *dev, u8 val)
7861 {
7862         struct drm_i915_private *dev_priv = dev->dev_private;
7863         u32 swreq;
7864
7865         swreq = (val & 0x3ff) << 25;
7866         I915_WRITE(GEN6_RPNSWREQ, swreq);
7867 }
7868
7869 void gen6_disable_rps(struct drm_device *dev)
7870 {
7871         struct drm_i915_private *dev_priv = dev->dev_private;
7872
7873         I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
7874         I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
7875         I915_WRITE(GEN6_PMIER, 0);
7876         /* Complete PM interrupt masking here doesn't race with the rps work
7877          * item again unmasking PM interrupts because that is using a different
7878          * register (PMIMR) to mask PM interrupts. The only risk is in leaving
7879          * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */
7880
7881         spin_lock_irq(&dev_priv->rps_lock);
7882         dev_priv->pm_iir = 0;
7883         spin_unlock_irq(&dev_priv->rps_lock);
7884
7885         I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
7886 }
7887
7888 static unsigned long intel_pxfreq(u32 vidfreq)
7889 {
7890         unsigned long freq;
7891         int div = (vidfreq & 0x3f0000) >> 16;
7892         int post = (vidfreq & 0x3000) >> 12;
7893         int pre = (vidfreq & 0x7);
7894
7895         if (!pre)
7896                 return 0;
7897
7898         freq = ((div * 133333) / ((1<<post) * pre));
7899
7900         return freq;
7901 }
7902
7903 void intel_init_emon(struct drm_device *dev)
7904 {
7905         struct drm_i915_private *dev_priv = dev->dev_private;
7906         u32 lcfuse;
7907         u8 pxw[16];
7908         int i;
7909
7910         /* Disable to program */
7911         I915_WRITE(ECR, 0);
7912         POSTING_READ(ECR);
7913
7914         /* Program energy weights for various events */
7915         I915_WRITE(SDEW, 0x15040d00);
7916         I915_WRITE(CSIEW0, 0x007f0000);
7917         I915_WRITE(CSIEW1, 0x1e220004);
7918         I915_WRITE(CSIEW2, 0x04000004);
7919
7920         for (i = 0; i < 5; i++)
7921                 I915_WRITE(PEW + (i * 4), 0);
7922         for (i = 0; i < 3; i++)
7923                 I915_WRITE(DEW + (i * 4), 0);
7924
7925         /* Program P-state weights to account for frequency power adjustment */
7926         for (i = 0; i < 16; i++) {
7927                 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
7928                 unsigned long freq = intel_pxfreq(pxvidfreq);
7929                 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
7930                         PXVFREQ_PX_SHIFT;
7931                 unsigned long val;
7932
7933                 val = vid * vid;
7934                 val *= (freq / 1000);
7935                 val *= 255;
7936                 val /= (127*127*900);
7937                 if (val > 0xff)
7938                         DRM_ERROR("bad pxval: %ld\n", val);
7939                 pxw[i] = val;
7940         }
7941         /* Render standby states get 0 weight */
7942         pxw[14] = 0;
7943         pxw[15] = 0;
7944
7945         for (i = 0; i < 4; i++) {
7946                 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
7947                         (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
7948                 I915_WRITE(PXW + (i * 4), val);
7949         }
7950
7951         /* Adjust magic regs to magic values (more experimental results) */
7952         I915_WRITE(OGW0, 0);
7953         I915_WRITE(OGW1, 0);
7954         I915_WRITE(EG0, 0x00007f00);
7955         I915_WRITE(EG1, 0x0000000e);
7956         I915_WRITE(EG2, 0x000e0000);
7957         I915_WRITE(EG3, 0x68000300);
7958         I915_WRITE(EG4, 0x42000000);
7959         I915_WRITE(EG5, 0x00140031);
7960         I915_WRITE(EG6, 0);
7961         I915_WRITE(EG7, 0);
7962
7963         for (i = 0; i < 8; i++)
7964                 I915_WRITE(PXWL + (i * 4), 0);
7965
7966         /* Enable PMON + select events */
7967         I915_WRITE(ECR, 0x80000019);
7968
7969         lcfuse = I915_READ(LCFUSE02);
7970
7971         dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK);
7972 }
7973
7974 static bool intel_enable_rc6(struct drm_device *dev)
7975 {
7976         /*
7977          * Respect the kernel parameter if it is set
7978          */
7979         if (i915_enable_rc6 >= 0)
7980                 return i915_enable_rc6;
7981
7982         /*
7983          * Disable RC6 on Ironlake
7984          */
7985         if (INTEL_INFO(dev)->gen == 5)
7986                 return 0;
7987
7988         /*
7989          * Disable rc6 on Sandybridge
7990          */
7991         if (INTEL_INFO(dev)->gen == 6) {
7992                 DRM_DEBUG_DRIVER("Sandybridge: RC6 disabled\n");
7993                 return 0;
7994         }
7995         DRM_DEBUG_DRIVER("RC6 enabled\n");
7996         return 1;
7997 }
7998
7999 void gen6_enable_rps(struct drm_i915_private *dev_priv)
8000 {
8001         u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
8002         u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
8003         u32 pcu_mbox, rc6_mask = 0;
8004         int cur_freq, min_freq, max_freq;
8005         int i;
8006
8007         /* Here begins a magic sequence of register writes to enable
8008          * auto-downclocking.
8009          *
8010          * Perhaps there might be some value in exposing these to
8011          * userspace...
8012          */
8013         I915_WRITE(GEN6_RC_STATE, 0);
8014         mutex_lock(&dev_priv->dev->struct_mutex);
8015         gen6_gt_force_wake_get(dev_priv);
8016
8017         /* disable the counters and set deterministic thresholds */
8018         I915_WRITE(GEN6_RC_CONTROL, 0);
8019
8020         I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
8021         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
8022         I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
8023         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
8024         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
8025
8026         for (i = 0; i < I915_NUM_RINGS; i++)
8027                 I915_WRITE(RING_MAX_IDLE(dev_priv->ring[i].mmio_base), 10);
8028
8029         I915_WRITE(GEN6_RC_SLEEP, 0);
8030         I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
8031         I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
8032         I915_WRITE(GEN6_RC6p_THRESHOLD, 100000);
8033         I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
8034
8035         if (intel_enable_rc6(dev_priv->dev))
8036                 rc6_mask = GEN6_RC_CTL_RC6_ENABLE |
8037                         ((IS_GEN7(dev_priv->dev)) ? GEN6_RC_CTL_RC6p_ENABLE : 0);
8038
8039         I915_WRITE(GEN6_RC_CONTROL,
8040                    rc6_mask |
8041                    GEN6_RC_CTL_EI_MODE(1) |
8042                    GEN6_RC_CTL_HW_ENABLE);
8043
8044         I915_WRITE(GEN6_RPNSWREQ,
8045                    GEN6_FREQUENCY(10) |
8046                    GEN6_OFFSET(0) |
8047                    GEN6_AGGRESSIVE_TURBO);
8048         I915_WRITE(GEN6_RC_VIDEO_FREQ,
8049                    GEN6_FREQUENCY(12));
8050
8051         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
8052         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
8053                    18 << 24 |
8054                    6 << 16);
8055         I915_WRITE(GEN6_RP_UP_THRESHOLD, 10000);
8056         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 1000000);
8057         I915_WRITE(GEN6_RP_UP_EI, 100000);
8058         I915_WRITE(GEN6_RP_DOWN_EI, 5000000);
8059         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
8060         I915_WRITE(GEN6_RP_CONTROL,
8061                    GEN6_RP_MEDIA_TURBO |
8062                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
8063                    GEN6_RP_MEDIA_IS_GFX |
8064                    GEN6_RP_ENABLE |
8065                    GEN6_RP_UP_BUSY_AVG |
8066                    GEN6_RP_DOWN_IDLE_CONT);
8067
8068         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
8069                      500))
8070                 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
8071
8072         I915_WRITE(GEN6_PCODE_DATA, 0);
8073         I915_WRITE(GEN6_PCODE_MAILBOX,
8074                    GEN6_PCODE_READY |
8075                    GEN6_PCODE_WRITE_MIN_FREQ_TABLE);
8076         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
8077                      500))
8078                 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
8079
8080         min_freq = (rp_state_cap & 0xff0000) >> 16;
8081         max_freq = rp_state_cap & 0xff;
8082         cur_freq = (gt_perf_status & 0xff00) >> 8;
8083
8084         /* Check for overclock support */
8085         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
8086                      500))
8087                 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
8088         I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_READ_OC_PARAMS);
8089         pcu_mbox = I915_READ(GEN6_PCODE_DATA);
8090         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
8091                      500))
8092                 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
8093         if (pcu_mbox & (1<<31)) { /* OC supported */
8094                 max_freq = pcu_mbox & 0xff;
8095                 DRM_DEBUG_DRIVER("overclocking supported, adjusting frequency max to %dMHz\n", pcu_mbox * 50);
8096         }
8097
8098         /* In units of 100MHz */
8099         dev_priv->max_delay = max_freq;
8100         dev_priv->min_delay = min_freq;
8101         dev_priv->cur_delay = cur_freq;
8102
8103         /* requires MSI enabled */
8104         I915_WRITE(GEN6_PMIER,
8105                    GEN6_PM_MBOX_EVENT |
8106                    GEN6_PM_THERMAL_EVENT |
8107                    GEN6_PM_RP_DOWN_TIMEOUT |
8108                    GEN6_PM_RP_UP_THRESHOLD |
8109                    GEN6_PM_RP_DOWN_THRESHOLD |
8110                    GEN6_PM_RP_UP_EI_EXPIRED |
8111                    GEN6_PM_RP_DOWN_EI_EXPIRED);
8112         spin_lock_irq(&dev_priv->rps_lock);
8113         WARN_ON(dev_priv->pm_iir != 0);
8114         I915_WRITE(GEN6_PMIMR, 0);
8115         spin_unlock_irq(&dev_priv->rps_lock);
8116         /* enable all PM interrupts */
8117         I915_WRITE(GEN6_PMINTRMSK, 0);
8118
8119         gen6_gt_force_wake_put(dev_priv);
8120         mutex_unlock(&dev_priv->dev->struct_mutex);
8121 }
8122
8123 void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
8124 {
8125         int min_freq = 15;
8126         int gpu_freq, ia_freq, max_ia_freq;
8127         int scaling_factor = 180;
8128
8129         max_ia_freq = cpufreq_quick_get_max(0);
8130         /*
8131          * Default to measured freq if none found, PCU will ensure we don't go
8132          * over
8133          */
8134         if (!max_ia_freq)
8135                 max_ia_freq = tsc_khz;
8136
8137         /* Convert from kHz to MHz */
8138         max_ia_freq /= 1000;
8139
8140         mutex_lock(&dev_priv->dev->struct_mutex);
8141
8142         /*
8143          * For each potential GPU frequency, load a ring frequency we'd like
8144          * to use for memory access.  We do this by specifying the IA frequency
8145          * the PCU should use as a reference to determine the ring frequency.
8146          */
8147         for (gpu_freq = dev_priv->max_delay; gpu_freq >= dev_priv->min_delay;
8148              gpu_freq--) {
8149                 int diff = dev_priv->max_delay - gpu_freq;
8150
8151                 /*
8152                  * For GPU frequencies less than 750MHz, just use the lowest
8153                  * ring freq.
8154                  */
8155                 if (gpu_freq < min_freq)
8156                         ia_freq = 800;
8157                 else
8158                         ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
8159                 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
8160
8161                 I915_WRITE(GEN6_PCODE_DATA,
8162                            (ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT) |
8163                            gpu_freq);
8164                 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY |
8165                            GEN6_PCODE_WRITE_MIN_FREQ_TABLE);
8166                 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) &
8167                               GEN6_PCODE_READY) == 0, 10)) {
8168                         DRM_ERROR("pcode write of freq table timed out\n");
8169                         continue;
8170                 }
8171         }
8172
8173         mutex_unlock(&dev_priv->dev->struct_mutex);
8174 }
8175
8176 static void ironlake_init_clock_gating(struct drm_device *dev)
8177 {
8178         struct drm_i915_private *dev_priv = dev->dev_private;
8179         uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
8180
8181         /* Required for FBC */
8182         dspclk_gate |= DPFCUNIT_CLOCK_GATE_DISABLE |
8183                 DPFCRUNIT_CLOCK_GATE_DISABLE |
8184                 DPFDUNIT_CLOCK_GATE_DISABLE;
8185         /* Required for CxSR */
8186         dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE;
8187
8188         I915_WRITE(PCH_3DCGDIS0,
8189                    MARIUNIT_CLOCK_GATE_DISABLE |
8190                    SVSMUNIT_CLOCK_GATE_DISABLE);
8191         I915_WRITE(PCH_3DCGDIS1,
8192                    VFMUNIT_CLOCK_GATE_DISABLE);
8193
8194         I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
8195
8196         /*
8197          * According to the spec the following bits should be set in
8198          * order to enable memory self-refresh
8199          * The bit 22/21 of 0x42004
8200          * The bit 5 of 0x42020
8201          * The bit 15 of 0x45000
8202          */
8203         I915_WRITE(ILK_DISPLAY_CHICKEN2,
8204                    (I915_READ(ILK_DISPLAY_CHICKEN2) |
8205                     ILK_DPARB_GATE | ILK_VSDPFD_FULL));
8206         I915_WRITE(ILK_DSPCLK_GATE,
8207                    (I915_READ(ILK_DSPCLK_GATE) |
8208                     ILK_DPARB_CLK_GATE));
8209         I915_WRITE(DISP_ARB_CTL,
8210                    (I915_READ(DISP_ARB_CTL) |
8211                     DISP_FBC_WM_DIS));
8212         I915_WRITE(WM3_LP_ILK, 0);
8213         I915_WRITE(WM2_LP_ILK, 0);
8214         I915_WRITE(WM1_LP_ILK, 0);
8215
8216         /*
8217          * Based on the document from hardware guys the following bits
8218          * should be set unconditionally in order to enable FBC.
8219          * The bit 22 of 0x42000
8220          * The bit 22 of 0x42004
8221          * The bit 7,8,9 of 0x42020.
8222          */
8223         if (IS_IRONLAKE_M(dev)) {
8224                 I915_WRITE(ILK_DISPLAY_CHICKEN1,
8225                            I915_READ(ILK_DISPLAY_CHICKEN1) |
8226                            ILK_FBCQ_DIS);
8227                 I915_WRITE(ILK_DISPLAY_CHICKEN2,
8228                            I915_READ(ILK_DISPLAY_CHICKEN2) |
8229                            ILK_DPARB_GATE);
8230                 I915_WRITE(ILK_DSPCLK_GATE,
8231                            I915_READ(ILK_DSPCLK_GATE) |
8232                            ILK_DPFC_DIS1 |
8233                            ILK_DPFC_DIS2 |
8234                            ILK_CLK_FBC);
8235         }
8236
8237         I915_WRITE(ILK_DISPLAY_CHICKEN2,
8238                    I915_READ(ILK_DISPLAY_CHICKEN2) |
8239                    ILK_ELPIN_409_SELECT);
8240         I915_WRITE(_3D_CHICKEN2,
8241                    _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
8242                    _3D_CHICKEN2_WM_READ_PIPELINED);
8243 }
8244
8245 static void gen6_init_clock_gating(struct drm_device *dev)
8246 {
8247         struct drm_i915_private *dev_priv = dev->dev_private;
8248         int pipe;
8249         uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
8250
8251         I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
8252
8253         I915_WRITE(ILK_DISPLAY_CHICKEN2,
8254                    I915_READ(ILK_DISPLAY_CHICKEN2) |
8255                    ILK_ELPIN_409_SELECT);
8256
8257         I915_WRITE(WM3_LP_ILK, 0);
8258         I915_WRITE(WM2_LP_ILK, 0);
8259         I915_WRITE(WM1_LP_ILK, 0);
8260
8261         /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
8262          * gating disable must be set.  Failure to set it results in
8263          * flickering pixels due to Z write ordering failures after
8264          * some amount of runtime in the Mesa "fire" demo, and Unigine
8265          * Sanctuary and Tropics, and apparently anything else with
8266          * alpha test or pixel discard.
8267          *
8268          * According to the spec, bit 11 (RCCUNIT) must also be set,
8269          * but we didn't debug actual testcases to find it out.
8270          */
8271         I915_WRITE(GEN6_UCGCTL2,
8272                    GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
8273                    GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
8274
8275         /*
8276          * According to the spec the following bits should be
8277          * set in order to enable memory self-refresh and fbc:
8278          * The bit21 and bit22 of 0x42000
8279          * The bit21 and bit22 of 0x42004
8280          * The bit5 and bit7 of 0x42020
8281          * The bit14 of 0x70180
8282          * The bit14 of 0x71180
8283          */
8284         I915_WRITE(ILK_DISPLAY_CHICKEN1,
8285                    I915_READ(ILK_DISPLAY_CHICKEN1) |
8286                    ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
8287         I915_WRITE(ILK_DISPLAY_CHICKEN2,
8288                    I915_READ(ILK_DISPLAY_CHICKEN2) |
8289                    ILK_DPARB_GATE | ILK_VSDPFD_FULL);
8290         I915_WRITE(ILK_DSPCLK_GATE,
8291                    I915_READ(ILK_DSPCLK_GATE) |
8292                    ILK_DPARB_CLK_GATE  |
8293                    ILK_DPFD_CLK_GATE);
8294
8295         for_each_pipe(pipe) {
8296                 I915_WRITE(DSPCNTR(pipe),
8297                            I915_READ(DSPCNTR(pipe)) |
8298                            DISPPLANE_TRICKLE_FEED_DISABLE);
8299                 intel_flush_display_plane(dev_priv, pipe);
8300         }
8301
8302         /* The default value should be 0x200 according to docs, but the two
8303          * platforms I checked have a 0 for this. (Maybe BIOS overrides?) */
8304         I915_WRITE(GEN6_GT_MODE, 0xffff << 16);
8305         I915_WRITE(GEN6_GT_MODE, GEN6_GT_MODE_HI << 16 | GEN6_GT_MODE_HI);
8306 }
8307
8308 static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
8309 {
8310         uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
8311
8312         reg &= ~GEN7_FF_SCHED_MASK;
8313         reg |= GEN7_FF_TS_SCHED_HW;
8314         reg |= GEN7_FF_VS_SCHED_HW;
8315         reg |= GEN7_FF_DS_SCHED_HW;
8316
8317         I915_WRITE(GEN7_FF_THREAD_MODE, reg);
8318 }
8319
8320 static void ivybridge_init_clock_gating(struct drm_device *dev)
8321 {
8322         struct drm_i915_private *dev_priv = dev->dev_private;
8323         int pipe;
8324         uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
8325
8326         I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
8327
8328         I915_WRITE(WM3_LP_ILK, 0);
8329         I915_WRITE(WM2_LP_ILK, 0);
8330         I915_WRITE(WM1_LP_ILK, 0);
8331
8332         /* According to the spec, bit 13 (RCZUNIT) must be set on IVB.
8333          * This implements the WaDisableRCZUnitClockGating workaround.
8334          */
8335         I915_WRITE(GEN6_UCGCTL2, GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
8336
8337         I915_WRITE(ILK_DSPCLK_GATE, IVB_VRHUNIT_CLK_GATE);
8338
8339         /* Apply the WaDisableRHWOOptimizationForRenderHang workaround. */
8340         I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
8341                    GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
8342
8343         /* WaApplyL3ControlAndL3ChickenMode requires those two on Ivy Bridge */
8344         I915_WRITE(GEN7_L3CNTLREG1,
8345                         GEN7_WA_FOR_GEN7_L3_CONTROL);
8346         I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
8347                         GEN7_WA_L3_CHICKEN_MODE);
8348
8349         /* This is required by WaCatErrorRejectionIssue */
8350         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
8351                         I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
8352                         GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
8353
8354         for_each_pipe(pipe) {
8355                 I915_WRITE(DSPCNTR(pipe),
8356                            I915_READ(DSPCNTR(pipe)) |
8357                            DISPPLANE_TRICKLE_FEED_DISABLE);
8358                 intel_flush_display_plane(dev_priv, pipe);
8359         }
8360
8361         gen7_setup_fixed_func_scheduler(dev_priv);
8362 }
8363
8364 static void g4x_init_clock_gating(struct drm_device *dev)
8365 {
8366         struct drm_i915_private *dev_priv = dev->dev_private;
8367         uint32_t dspclk_gate;
8368
8369         I915_WRITE(RENCLK_GATE_D1, 0);
8370         I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
8371                    GS_UNIT_CLOCK_GATE_DISABLE |
8372                    CL_UNIT_CLOCK_GATE_DISABLE);
8373         I915_WRITE(RAMCLK_GATE_D, 0);
8374         dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
8375                 OVRUNIT_CLOCK_GATE_DISABLE |
8376                 OVCUNIT_CLOCK_GATE_DISABLE;
8377         if (IS_GM45(dev))
8378                 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
8379         I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
8380 }
8381
8382 static void crestline_init_clock_gating(struct drm_device *dev)
8383 {
8384         struct drm_i915_private *dev_priv = dev->dev_private;
8385
8386         I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
8387         I915_WRITE(RENCLK_GATE_D2, 0);
8388         I915_WRITE(DSPCLK_GATE_D, 0);
8389         I915_WRITE(RAMCLK_GATE_D, 0);
8390         I915_WRITE16(DEUC, 0);
8391 }
8392
8393 static void broadwater_init_clock_gating(struct drm_device *dev)
8394 {
8395         struct drm_i915_private *dev_priv = dev->dev_private;
8396
8397         I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
8398                    I965_RCC_CLOCK_GATE_DISABLE |
8399                    I965_RCPB_CLOCK_GATE_DISABLE |
8400                    I965_ISC_CLOCK_GATE_DISABLE |
8401                    I965_FBC_CLOCK_GATE_DISABLE);
8402         I915_WRITE(RENCLK_GATE_D2, 0);
8403 }
8404
8405 static void gen3_init_clock_gating(struct drm_device *dev)
8406 {
8407         struct drm_i915_private *dev_priv = dev->dev_private;
8408         u32 dstate = I915_READ(D_STATE);
8409
8410         dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
8411                 DSTATE_DOT_CLOCK_GATING;
8412         I915_WRITE(D_STATE, dstate);
8413 }
8414
8415 static void i85x_init_clock_gating(struct drm_device *dev)
8416 {
8417         struct drm_i915_private *dev_priv = dev->dev_private;
8418
8419         I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
8420 }
8421
8422 static void i830_init_clock_gating(struct drm_device *dev)
8423 {
8424         struct drm_i915_private *dev_priv = dev->dev_private;
8425
8426         I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
8427 }
8428
8429 static void ibx_init_clock_gating(struct drm_device *dev)
8430 {
8431         struct drm_i915_private *dev_priv = dev->dev_private;
8432
8433         /*
8434          * On Ibex Peak and Cougar Point, we need to disable clock
8435          * gating for the panel power sequencer or it will fail to
8436          * start up when no ports are active.
8437          */
8438         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
8439 }
8440
8441 static void cpt_init_clock_gating(struct drm_device *dev)
8442 {
8443         struct drm_i915_private *dev_priv = dev->dev_private;
8444         int pipe;
8445
8446         /*
8447          * On Ibex Peak and Cougar Point, we need to disable clock
8448          * gating for the panel power sequencer or it will fail to
8449          * start up when no ports are active.
8450          */
8451         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
8452         I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
8453                    DPLS_EDP_PPS_FIX_DIS);
8454         /* Without this, mode sets may fail silently on FDI */
8455         for_each_pipe(pipe)
8456                 I915_WRITE(TRANS_CHICKEN2(pipe), TRANS_AUTOTRAIN_GEN_STALL_DIS);
8457 }
8458
8459 static void ironlake_teardown_rc6(struct drm_device *dev)
8460 {
8461         struct drm_i915_private *dev_priv = dev->dev_private;
8462
8463         if (dev_priv->renderctx) {
8464                 i915_gem_object_unpin(dev_priv->renderctx);
8465                 drm_gem_object_unreference(&dev_priv->renderctx->base);
8466                 dev_priv->renderctx = NULL;
8467         }
8468
8469         if (dev_priv->pwrctx) {
8470                 i915_gem_object_unpin(dev_priv->pwrctx);
8471                 drm_gem_object_unreference(&dev_priv->pwrctx->base);
8472                 dev_priv->pwrctx = NULL;
8473         }
8474 }
8475
8476 static void ironlake_disable_rc6(struct drm_device *dev)
8477 {
8478         struct drm_i915_private *dev_priv = dev->dev_private;
8479
8480         if (I915_READ(PWRCTXA)) {
8481                 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
8482                 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
8483                 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
8484                          50);
8485
8486                 I915_WRITE(PWRCTXA, 0);
8487                 POSTING_READ(PWRCTXA);
8488
8489                 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
8490                 POSTING_READ(RSTDBYCTL);
8491         }
8492
8493         ironlake_teardown_rc6(dev);
8494 }
8495
8496 static int ironlake_setup_rc6(struct drm_device *dev)
8497 {
8498         struct drm_i915_private *dev_priv = dev->dev_private;
8499
8500         if (dev_priv->renderctx == NULL)
8501                 dev_priv->renderctx = intel_alloc_context_page(dev);
8502         if (!dev_priv->renderctx)
8503                 return -ENOMEM;
8504
8505         if (dev_priv->pwrctx == NULL)
8506                 dev_priv->pwrctx = intel_alloc_context_page(dev);
8507         if (!dev_priv->pwrctx) {
8508                 ironlake_teardown_rc6(dev);
8509                 return -ENOMEM;
8510         }
8511
8512         return 0;
8513 }
8514
8515 void ironlake_enable_rc6(struct drm_device *dev)
8516 {
8517         struct drm_i915_private *dev_priv = dev->dev_private;
8518         int ret;
8519
8520         /* rc6 disabled by default due to repeated reports of hanging during
8521          * boot and resume.
8522          */
8523         if (!intel_enable_rc6(dev))
8524                 return;
8525
8526         mutex_lock(&dev->struct_mutex);
8527         ret = ironlake_setup_rc6(dev);
8528         if (ret) {
8529                 mutex_unlock(&dev->struct_mutex);
8530                 return;
8531         }
8532
8533         /*
8534          * GPU can automatically power down the render unit if given a page
8535          * to save state.
8536          */
8537         ret = BEGIN_LP_RING(6);
8538         if (ret) {
8539                 ironlake_teardown_rc6(dev);
8540                 mutex_unlock(&dev->struct_mutex);
8541                 return;
8542         }
8543
8544         OUT_RING(MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
8545         OUT_RING(MI_SET_CONTEXT);
8546         OUT_RING(dev_priv->renderctx->gtt_offset |
8547                  MI_MM_SPACE_GTT |
8548                  MI_SAVE_EXT_STATE_EN |
8549                  MI_RESTORE_EXT_STATE_EN |
8550                  MI_RESTORE_INHIBIT);
8551         OUT_RING(MI_SUSPEND_FLUSH);
8552         OUT_RING(MI_NOOP);
8553         OUT_RING(MI_FLUSH);
8554         ADVANCE_LP_RING();
8555
8556         /*
8557          * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
8558          * does an implicit flush, combined with MI_FLUSH above, it should be
8559          * safe to assume that renderctx is valid
8560          */
8561         ret = intel_wait_ring_idle(LP_RING(dev_priv));
8562         if (ret) {
8563                 DRM_ERROR("failed to enable ironlake power power savings\n");
8564                 ironlake_teardown_rc6(dev);
8565                 mutex_unlock(&dev->struct_mutex);
8566                 return;
8567         }
8568
8569         I915_WRITE(PWRCTXA, dev_priv->pwrctx->gtt_offset | PWRCTX_EN);
8570         I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
8571         mutex_unlock(&dev->struct_mutex);
8572 }
8573
8574 void intel_init_clock_gating(struct drm_device *dev)
8575 {
8576         struct drm_i915_private *dev_priv = dev->dev_private;
8577
8578         dev_priv->display.init_clock_gating(dev);
8579
8580         if (dev_priv->display.init_pch_clock_gating)
8581                 dev_priv->display.init_pch_clock_gating(dev);
8582 }
8583
8584 /* Set up chip specific display functions */
8585 static void intel_init_display(struct drm_device *dev)
8586 {
8587         struct drm_i915_private *dev_priv = dev->dev_private;
8588
8589         /* We always want a DPMS function */
8590         if (HAS_PCH_SPLIT(dev)) {
8591                 dev_priv->display.dpms = ironlake_crtc_dpms;
8592                 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
8593                 dev_priv->display.update_plane = ironlake_update_plane;
8594         } else {
8595                 dev_priv->display.dpms = i9xx_crtc_dpms;
8596                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
8597                 dev_priv->display.update_plane = i9xx_update_plane;
8598         }
8599
8600         if (I915_HAS_FBC(dev)) {
8601                 if (HAS_PCH_SPLIT(dev)) {
8602                         dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
8603                         dev_priv->display.enable_fbc = ironlake_enable_fbc;
8604                         dev_priv->display.disable_fbc = ironlake_disable_fbc;
8605                 } else if (IS_GM45(dev)) {
8606                         dev_priv->display.fbc_enabled = g4x_fbc_enabled;
8607                         dev_priv->display.enable_fbc = g4x_enable_fbc;
8608                         dev_priv->display.disable_fbc = g4x_disable_fbc;
8609                 } else if (IS_CRESTLINE(dev)) {
8610                         dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
8611                         dev_priv->display.enable_fbc = i8xx_enable_fbc;
8612                         dev_priv->display.disable_fbc = i8xx_disable_fbc;
8613                 }
8614                 /* 855GM needs testing */
8615         }
8616
8617         /* Returns the core display clock speed */
8618         if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
8619                 dev_priv->display.get_display_clock_speed =
8620                         i945_get_display_clock_speed;
8621         else if (IS_I915G(dev))
8622                 dev_priv->display.get_display_clock_speed =
8623                         i915_get_display_clock_speed;
8624         else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
8625                 dev_priv->display.get_display_clock_speed =
8626                         i9xx_misc_get_display_clock_speed;
8627         else if (IS_I915GM(dev))
8628                 dev_priv->display.get_display_clock_speed =
8629                         i915gm_get_display_clock_speed;
8630         else if (IS_I865G(dev))
8631                 dev_priv->display.get_display_clock_speed =
8632                         i865_get_display_clock_speed;
8633         else if (IS_I85X(dev))
8634                 dev_priv->display.get_display_clock_speed =
8635                         i855_get_display_clock_speed;
8636         else /* 852, 830 */
8637                 dev_priv->display.get_display_clock_speed =
8638                         i830_get_display_clock_speed;
8639
8640         /* For FIFO watermark updates */
8641         if (HAS_PCH_SPLIT(dev)) {
8642                 dev_priv->display.force_wake_get = __gen6_gt_force_wake_get;
8643                 dev_priv->display.force_wake_put = __gen6_gt_force_wake_put;
8644
8645                 /* IVB configs may use multi-threaded forcewake */
8646                 if (IS_IVYBRIDGE(dev)) {
8647                         u32     ecobus;
8648
8649                         mutex_lock(&dev->struct_mutex);
8650                         __gen6_gt_force_wake_mt_get(dev_priv);
8651                         ecobus = I915_READ(ECOBUS);
8652                         __gen6_gt_force_wake_mt_put(dev_priv);
8653                         mutex_unlock(&dev->struct_mutex);
8654
8655                         if (ecobus & FORCEWAKE_MT_ENABLE) {
8656                                 DRM_DEBUG_KMS("Using MT version of forcewake\n");
8657                                 dev_priv->display.force_wake_get =
8658                                         __gen6_gt_force_wake_mt_get;
8659                                 dev_priv->display.force_wake_put =
8660                                         __gen6_gt_force_wake_mt_put;
8661                         }
8662                 }
8663
8664                 if (HAS_PCH_IBX(dev))
8665                         dev_priv->display.init_pch_clock_gating = ibx_init_clock_gating;
8666                 else if (HAS_PCH_CPT(dev))
8667                         dev_priv->display.init_pch_clock_gating = cpt_init_clock_gating;
8668
8669                 if (IS_GEN5(dev)) {
8670                         if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
8671                                 dev_priv->display.update_wm = ironlake_update_wm;
8672                         else {
8673                                 DRM_DEBUG_KMS("Failed to get proper latency. "
8674                                               "Disable CxSR\n");
8675                                 dev_priv->display.update_wm = NULL;
8676                         }
8677                         dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
8678                         dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
8679                         dev_priv->display.write_eld = ironlake_write_eld;
8680                 } else if (IS_GEN6(dev)) {
8681                         if (SNB_READ_WM0_LATENCY()) {
8682                                 dev_priv->display.update_wm = sandybridge_update_wm;
8683                         } else {
8684                                 DRM_DEBUG_KMS("Failed to read display plane latency. "
8685                                               "Disable CxSR\n");
8686                                 dev_priv->display.update_wm = NULL;
8687                         }
8688                         dev_priv->display.fdi_link_train = gen6_fdi_link_train;
8689                         dev_priv->display.init_clock_gating = gen6_init_clock_gating;
8690                         dev_priv->display.write_eld = ironlake_write_eld;
8691                 } else if (IS_IVYBRIDGE(dev)) {
8692                         /* FIXME: detect B0+ stepping and use auto training */
8693                         dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
8694                         if (SNB_READ_WM0_LATENCY()) {
8695                                 dev_priv->display.update_wm = sandybridge_update_wm;
8696                         } else {
8697                                 DRM_DEBUG_KMS("Failed to read display plane latency. "
8698                                               "Disable CxSR\n");
8699                                 dev_priv->display.update_wm = NULL;
8700                         }
8701                         dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
8702                         dev_priv->display.write_eld = ironlake_write_eld;
8703                 } else
8704                         dev_priv->display.update_wm = NULL;
8705         } else if (IS_PINEVIEW(dev)) {
8706                 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
8707                                             dev_priv->is_ddr3,
8708                                             dev_priv->fsb_freq,
8709                                             dev_priv->mem_freq)) {
8710                         DRM_INFO("failed to find known CxSR latency "
8711                                  "(found ddr%s fsb freq %d, mem freq %d), "
8712                                  "disabling CxSR\n",
8713                                  (dev_priv->is_ddr3 == 1) ? "3" : "2",
8714                                  dev_priv->fsb_freq, dev_priv->mem_freq);
8715                         /* Disable CxSR and never update its watermark again */
8716                         pineview_disable_cxsr(dev);
8717                         dev_priv->display.update_wm = NULL;
8718                 } else
8719                         dev_priv->display.update_wm = pineview_update_wm;
8720                 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
8721         } else if (IS_G4X(dev)) {
8722                 dev_priv->display.write_eld = g4x_write_eld;
8723                 dev_priv->display.update_wm = g4x_update_wm;
8724                 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
8725         } else if (IS_GEN4(dev)) {
8726                 dev_priv->display.update_wm = i965_update_wm;
8727                 if (IS_CRESTLINE(dev))
8728                         dev_priv->display.init_clock_gating = crestline_init_clock_gating;
8729                 else if (IS_BROADWATER(dev))
8730                         dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
8731         } else if (IS_GEN3(dev)) {
8732                 dev_priv->display.update_wm = i9xx_update_wm;
8733                 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
8734                 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
8735         } else if (IS_I865G(dev)) {
8736                 dev_priv->display.update_wm = i830_update_wm;
8737                 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
8738                 dev_priv->display.get_fifo_size = i830_get_fifo_size;
8739         } else if (IS_I85X(dev)) {
8740                 dev_priv->display.update_wm = i9xx_update_wm;
8741                 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
8742                 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
8743         } else {
8744                 dev_priv->display.update_wm = i830_update_wm;
8745                 dev_priv->display.init_clock_gating = i830_init_clock_gating;
8746                 if (IS_845G(dev))
8747                         dev_priv->display.get_fifo_size = i845_get_fifo_size;
8748                 else
8749                         dev_priv->display.get_fifo_size = i830_get_fifo_size;
8750         }
8751
8752         /* Default just returns -ENODEV to indicate unsupported */
8753         dev_priv->display.queue_flip = intel_default_queue_flip;
8754
8755         switch (INTEL_INFO(dev)->gen) {
8756         case 2:
8757                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
8758                 break;
8759
8760         case 3:
8761                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
8762                 break;
8763
8764         case 4:
8765         case 5:
8766                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
8767                 break;
8768
8769         case 6:
8770                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
8771                 break;
8772         case 7:
8773                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
8774                 break;
8775         }
8776 }
8777
8778 /*
8779  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
8780  * resume, or other times.  This quirk makes sure that's the case for
8781  * affected systems.
8782  */
8783 static void quirk_pipea_force(struct drm_device *dev)
8784 {
8785         struct drm_i915_private *dev_priv = dev->dev_private;
8786
8787         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
8788         DRM_DEBUG_DRIVER("applying pipe a force quirk\n");
8789 }
8790
8791 /*
8792  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
8793  */
8794 static void quirk_ssc_force_disable(struct drm_device *dev)
8795 {
8796         struct drm_i915_private *dev_priv = dev->dev_private;
8797         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
8798 }
8799
8800 struct intel_quirk {
8801         int device;
8802         int subsystem_vendor;
8803         int subsystem_device;
8804         void (*hook)(struct drm_device *dev);
8805 };
8806
8807 struct intel_quirk intel_quirks[] = {
8808         /* HP Compaq 2730p needs pipe A force quirk (LP: #291555) */
8809         { 0x2a42, 0x103c, 0x30eb, quirk_pipea_force },
8810         /* HP Mini needs pipe A force quirk (LP: #322104) */
8811         { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
8812
8813         /* Thinkpad R31 needs pipe A force quirk */
8814         { 0x3577, 0x1014, 0x0505, quirk_pipea_force },
8815         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
8816         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
8817
8818         /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
8819         { 0x3577,  0x1014, 0x0513, quirk_pipea_force },
8820         /* ThinkPad X40 needs pipe A force quirk */
8821
8822         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
8823         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
8824
8825         /* 855 & before need to leave pipe A & dpll A up */
8826         { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
8827         { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
8828
8829         /* Lenovo U160 cannot use SSC on LVDS */
8830         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
8831
8832         /* Sony Vaio Y cannot use SSC on LVDS */
8833         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
8834 };
8835
8836 static void intel_init_quirks(struct drm_device *dev)
8837 {
8838         struct pci_dev *d = dev->pdev;
8839         int i;
8840
8841         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
8842                 struct intel_quirk *q = &intel_quirks[i];
8843
8844                 if (d->device == q->device &&
8845                     (d->subsystem_vendor == q->subsystem_vendor ||
8846                      q->subsystem_vendor == PCI_ANY_ID) &&
8847                     (d->subsystem_device == q->subsystem_device ||
8848                      q->subsystem_device == PCI_ANY_ID))
8849                         q->hook(dev);
8850         }
8851 }
8852
8853 /* Disable the VGA plane that we never use */
8854 static void i915_disable_vga(struct drm_device *dev)
8855 {
8856         struct drm_i915_private *dev_priv = dev->dev_private;
8857         u8 sr1;
8858         u32 vga_reg;
8859
8860         if (HAS_PCH_SPLIT(dev))
8861                 vga_reg = CPU_VGACNTRL;
8862         else
8863                 vga_reg = VGACNTRL;
8864
8865         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
8866         outb(1, VGA_SR_INDEX);
8867         sr1 = inb(VGA_SR_DATA);
8868         outb(sr1 | 1<<5, VGA_SR_DATA);
8869         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
8870         udelay(300);
8871
8872         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
8873         POSTING_READ(vga_reg);
8874 }
8875
8876 void intel_modeset_init(struct drm_device *dev)
8877 {
8878         struct drm_i915_private *dev_priv = dev->dev_private;
8879         int i;
8880
8881         drm_mode_config_init(dev);
8882
8883         dev->mode_config.min_width = 0;
8884         dev->mode_config.min_height = 0;
8885
8886         dev->mode_config.funcs = (void *)&intel_mode_funcs;
8887
8888         intel_init_quirks(dev);
8889
8890         intel_init_display(dev);
8891
8892         if (IS_GEN2(dev)) {
8893                 dev->mode_config.max_width = 2048;
8894                 dev->mode_config.max_height = 2048;
8895         } else if (IS_GEN3(dev)) {
8896                 dev->mode_config.max_width = 4096;
8897                 dev->mode_config.max_height = 4096;
8898         } else {
8899                 dev->mode_config.max_width = 8192;
8900                 dev->mode_config.max_height = 8192;
8901         }
8902         dev->mode_config.fb_base = dev->agp->base;
8903
8904         DRM_DEBUG_KMS("%d display pipe%s available.\n",
8905                       dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
8906
8907         for (i = 0; i < dev_priv->num_pipe; i++) {
8908                 intel_crtc_init(dev, i);
8909         }
8910
8911         /* Just disable it once at startup */
8912         i915_disable_vga(dev);
8913         intel_setup_outputs(dev);
8914
8915         intel_init_clock_gating(dev);
8916
8917         if (IS_IRONLAKE_M(dev)) {
8918                 ironlake_enable_drps(dev);
8919                 intel_init_emon(dev);
8920         }
8921
8922         if (IS_GEN6(dev) || IS_GEN7(dev)) {
8923                 gen6_enable_rps(dev_priv);
8924                 gen6_update_ring_freq(dev_priv);
8925         }
8926
8927         INIT_WORK(&dev_priv->idle_work, intel_idle_update);
8928         setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
8929                     (unsigned long)dev);
8930 }
8931
8932 void intel_modeset_gem_init(struct drm_device *dev)
8933 {
8934         if (IS_IRONLAKE_M(dev))
8935                 ironlake_enable_rc6(dev);
8936
8937         intel_setup_overlay(dev);
8938 }
8939
8940 void intel_modeset_cleanup(struct drm_device *dev)
8941 {
8942         struct drm_i915_private *dev_priv = dev->dev_private;
8943         struct drm_crtc *crtc;
8944         struct intel_crtc *intel_crtc;
8945
8946         drm_kms_helper_poll_fini(dev);
8947         mutex_lock(&dev->struct_mutex);
8948
8949         intel_unregister_dsm_handler();
8950
8951
8952         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
8953                 /* Skip inactive CRTCs */
8954                 if (!crtc->fb)
8955                         continue;
8956
8957                 intel_crtc = to_intel_crtc(crtc);
8958                 intel_increase_pllclock(crtc);
8959         }
8960
8961         intel_disable_fbc(dev);
8962
8963         if (IS_IRONLAKE_M(dev))
8964                 ironlake_disable_drps(dev);
8965         if (IS_GEN6(dev) || IS_GEN7(dev))
8966                 gen6_disable_rps(dev);
8967
8968         if (IS_IRONLAKE_M(dev))
8969                 ironlake_disable_rc6(dev);
8970
8971         mutex_unlock(&dev->struct_mutex);
8972
8973         /* Disable the irq before mode object teardown, for the irq might
8974          * enqueue unpin/hotplug work. */
8975         drm_irq_uninstall(dev);
8976         cancel_work_sync(&dev_priv->hotplug_work);
8977         cancel_work_sync(&dev_priv->rps_work);
8978
8979         /* flush any delayed tasks or pending work */
8980         flush_scheduled_work();
8981
8982         /* Shut off idle work before the crtcs get freed. */
8983         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
8984                 intel_crtc = to_intel_crtc(crtc);
8985                 del_timer_sync(&intel_crtc->idle_timer);
8986         }
8987         del_timer_sync(&dev_priv->idle_timer);
8988         cancel_work_sync(&dev_priv->idle_work);
8989
8990         drm_mode_config_cleanup(dev);
8991 }
8992
8993 /*
8994  * Return which encoder is currently attached for connector.
8995  */
8996 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
8997 {
8998         return &intel_attached_encoder(connector)->base;
8999 }
9000
9001 void intel_connector_attach_encoder(struct intel_connector *connector,
9002                                     struct intel_encoder *encoder)
9003 {
9004         connector->encoder = encoder;
9005         drm_mode_connector_attach_encoder(&connector->base,
9006                                           &encoder->base);
9007 }
9008
9009 /*
9010  * set vga decode state - true == enable VGA decode
9011  */
9012 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
9013 {
9014         struct drm_i915_private *dev_priv = dev->dev_private;
9015         u16 gmch_ctrl;
9016
9017         pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
9018         if (state)
9019                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
9020         else
9021                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
9022         pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
9023         return 0;
9024 }
9025
9026 #ifdef CONFIG_DEBUG_FS
9027 #include <linux/seq_file.h>
9028
9029 struct intel_display_error_state {
9030         struct intel_cursor_error_state {
9031                 u32 control;
9032                 u32 position;
9033                 u32 base;
9034                 u32 size;
9035         } cursor[2];
9036
9037         struct intel_pipe_error_state {
9038                 u32 conf;
9039                 u32 source;
9040
9041                 u32 htotal;
9042                 u32 hblank;
9043                 u32 hsync;
9044                 u32 vtotal;
9045                 u32 vblank;
9046                 u32 vsync;
9047         } pipe[2];
9048
9049         struct intel_plane_error_state {
9050                 u32 control;
9051                 u32 stride;
9052                 u32 size;
9053                 u32 pos;
9054                 u32 addr;
9055                 u32 surface;
9056                 u32 tile_offset;
9057         } plane[2];
9058 };
9059
9060 struct intel_display_error_state *
9061 intel_display_capture_error_state(struct drm_device *dev)
9062 {
9063         drm_i915_private_t *dev_priv = dev->dev_private;
9064         struct intel_display_error_state *error;
9065         int i;
9066
9067         error = kmalloc(sizeof(*error), GFP_ATOMIC);
9068         if (error == NULL)
9069                 return NULL;
9070
9071         for (i = 0; i < 2; i++) {
9072                 error->cursor[i].control = I915_READ(CURCNTR(i));
9073                 error->cursor[i].position = I915_READ(CURPOS(i));
9074                 error->cursor[i].base = I915_READ(CURBASE(i));
9075
9076                 error->plane[i].control = I915_READ(DSPCNTR(i));
9077                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
9078                 error->plane[i].size = I915_READ(DSPSIZE(i));
9079                 error->plane[i].pos = I915_READ(DSPPOS(i));
9080                 error->plane[i].addr = I915_READ(DSPADDR(i));
9081                 if (INTEL_INFO(dev)->gen >= 4) {
9082                         error->plane[i].surface = I915_READ(DSPSURF(i));
9083                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
9084                 }
9085
9086                 error->pipe[i].conf = I915_READ(PIPECONF(i));
9087                 error->pipe[i].source = I915_READ(PIPESRC(i));
9088                 error->pipe[i].htotal = I915_READ(HTOTAL(i));
9089                 error->pipe[i].hblank = I915_READ(HBLANK(i));
9090                 error->pipe[i].hsync = I915_READ(HSYNC(i));
9091                 error->pipe[i].vtotal = I915_READ(VTOTAL(i));
9092                 error->pipe[i].vblank = I915_READ(VBLANK(i));
9093                 error->pipe[i].vsync = I915_READ(VSYNC(i));
9094         }
9095
9096         return error;
9097 }
9098
9099 void
9100 intel_display_print_error_state(struct seq_file *m,
9101                                 struct drm_device *dev,
9102                                 struct intel_display_error_state *error)
9103 {
9104         int i;
9105
9106         for (i = 0; i < 2; i++) {
9107                 seq_printf(m, "Pipe [%d]:\n", i);
9108                 seq_printf(m, "  CONF: %08x\n", error->pipe[i].conf);
9109                 seq_printf(m, "  SRC: %08x\n", error->pipe[i].source);
9110                 seq_printf(m, "  HTOTAL: %08x\n", error->pipe[i].htotal);
9111                 seq_printf(m, "  HBLANK: %08x\n", error->pipe[i].hblank);
9112                 seq_printf(m, "  HSYNC: %08x\n", error->pipe[i].hsync);
9113                 seq_printf(m, "  VTOTAL: %08x\n", error->pipe[i].vtotal);
9114                 seq_printf(m, "  VBLANK: %08x\n", error->pipe[i].vblank);
9115                 seq_printf(m, "  VSYNC: %08x\n", error->pipe[i].vsync);
9116
9117                 seq_printf(m, "Plane [%d]:\n", i);
9118                 seq_printf(m, "  CNTR: %08x\n", error->plane[i].control);
9119                 seq_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
9120                 seq_printf(m, "  SIZE: %08x\n", error->plane[i].size);
9121                 seq_printf(m, "  POS: %08x\n", error->plane[i].pos);
9122                 seq_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
9123                 if (INTEL_INFO(dev)->gen >= 4) {
9124                         seq_printf(m, "  SURF: %08x\n", error->plane[i].surface);
9125                         seq_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
9126                 }
9127
9128                 seq_printf(m, "Cursor [%d]:\n", i);
9129                 seq_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
9130                 seq_printf(m, "  POS: %08x\n", error->cursor[i].position);
9131                 seq_printf(m, "  BASE: %08x\n", error->cursor[i].base);
9132         }
9133 }
9134 #endif