drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/cpufreq.h>
  28 #include <linux/dmi.h>
  29 #include <linux/module.h>
  30 #include <linux/input.h>
  31 #include <linux/i2c.h>
  32 #include <linux/kernel.h>
  33 #include <linux/slab.h>
  34 #include <linux/vgaarb.h>
  35 #include <drm/drm_edid.h>
  36 #include "drmP.h"
  37 #include "intel_drv.h"
  38 #include "i915_drm.h"
  39 #include "i915_drv.h"
  40 #include "i915_trace.h"
  41 #include "drm_dp_helper.h"
  42 #include "drm_crtc_helper.h"
  43 #include <linux/dma_remapping.h>
  44
  45 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
  46
  47 bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
  48 static void intel_update_watermarks(struct drm_device *dev);
  49 static void intel_increase_pllclock(struct drm_crtc *crtc);
  50 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  51
  52 typedef struct {
  53         /* given values */
  54         int n;
  55         int m1, m2;
  56         int p1, p2;
  57         /* derived values */
  58         int     dot;
  59         int     vco;
  60         int     m;
  61         int     p;
  62 } intel_clock_t;
  63
  64 typedef struct {
  65         int     min, max;
  66 } intel_range_t;
  67
  68 typedef struct {
  69         int     dot_limit;
  70         int     p2_slow, p2_fast;
  71 } intel_p2_t;
  72
  73 #define INTEL_P2_NUM                  2
  74 typedef struct intel_limit intel_limit_t;
  75 struct intel_limit {
  76         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  77         intel_p2_t          p2;
  78         bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
  79                         int, int, intel_clock_t *);
  80 };
  81
  82 /* FDI */
  83 #define IRONLAKE_FDI_FREQ               2700000 /* in kHz for mode->clock */
  84
  85 static bool
  86 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  87                     int target, int refclk, intel_clock_t *best_clock);
  88 static bool
  89 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  90                         int target, int refclk, intel_clock_t *best_clock);
  91
  92 static bool
  93 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
  94                       int target, int refclk, intel_clock_t *best_clock);
  95 static bool
  96 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
  97                            int target, int refclk, intel_clock_t *best_clock);
  98
  99 static inline u32 /* units of 100MHz */
 100 intel_fdi_link_freq(struct drm_device *dev)
 101 {
 102         if (IS_GEN5(dev)) {
 103                 struct drm_i915_private *dev_priv = dev->dev_private;
 104                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
 105         } else
 106                 return 27;
 107 }
 108
 109 static const intel_limit_t intel_limits_i8xx_dvo = {
 110         .dot = { .min = 25000, .max = 350000 },
 111         .vco = { .min = 930000, .max = 1400000 },
 112         .n = { .min = 3, .max = 16 },
 113         .m = { .min = 96, .max = 140 },
 114         .m1 = { .min = 18, .max = 26 },
 115         .m2 = { .min = 6, .max = 16 },
 116         .p = { .min = 4, .max = 128 },
 117         .p1 = { .min = 2, .max = 33 },
 118         .p2 = { .dot_limit = 165000,
 119                 .p2_slow = 4, .p2_fast = 2 },
 120         .find_pll = intel_find_best_PLL,
 121 };
 122
 123 static const intel_limit_t intel_limits_i8xx_lvds = {
 124         .dot = { .min = 25000, .max = 350000 },
 125         .vco = { .min = 930000, .max = 1400000 },
 126         .n = { .min = 3, .max = 16 },
 127         .m = { .min = 96, .max = 140 },
 128         .m1 = { .min = 18, .max = 26 },
 129         .m2 = { .min = 6, .max = 16 },
 130         .p = { .min = 4, .max = 128 },
 131         .p1 = { .min = 1, .max = 6 },
 132         .p2 = { .dot_limit = 165000,
 133                 .p2_slow = 14, .p2_fast = 7 },
 134         .find_pll = intel_find_best_PLL,
 135 };
 136
 137 static const intel_limit_t intel_limits_i9xx_sdvo = {
 138         .dot = { .min = 20000, .max = 400000 },
 139         .vco = { .min = 1400000, .max = 2800000 },
 140         .n = { .min = 1, .max = 6 },
 141         .m = { .min = 70, .max = 120 },
 142         .m1 = { .min = 8, .max = 18 },
 143         .m2 = { .min = 3, .max = 7 },
 144         .p = { .min = 5, .max = 80 },
 145         .p1 = { .min = 1, .max = 8 },
 146         .p2 = { .dot_limit = 200000,
 147                 .p2_slow = 10, .p2_fast = 5 },
 148         .find_pll = intel_find_best_PLL,
 149 };
 150
 151 static const intel_limit_t intel_limits_i9xx_lvds = {
 152         .dot = { .min = 20000, .max = 400000 },
 153         .vco = { .min = 1400000, .max = 2800000 },
 154         .n = { .min = 1, .max = 6 },
 155         .m = { .min = 70, .max = 120 },
 156         .m1 = { .min = 10, .max = 22 },
 157         .m2 = { .min = 5, .max = 9 },
 158         .p = { .min = 7, .max = 98 },
 159         .p1 = { .min = 1, .max = 8 },
 160         .p2 = { .dot_limit = 112000,
 161                 .p2_slow = 14, .p2_fast = 7 },
 162         .find_pll = intel_find_best_PLL,
 163 };
 164
 165
 166 static const intel_limit_t intel_limits_g4x_sdvo = {
 167         .dot = { .min = 25000, .max = 270000 },
 168         .vco = { .min = 1750000, .max = 3500000},
 169         .n = { .min = 1, .max = 4 },
 170         .m = { .min = 104, .max = 138 },
 171         .m1 = { .min = 17, .max = 23 },
 172         .m2 = { .min = 5, .max = 11 },
 173         .p = { .min = 10, .max = 30 },
 174         .p1 = { .min = 1, .max = 3},
 175         .p2 = { .dot_limit = 270000,
 176                 .p2_slow = 10,
 177                 .p2_fast = 10
 178         },
 179         .find_pll = intel_g4x_find_best_PLL,
 180 };
 181
 182 static const intel_limit_t intel_limits_g4x_hdmi = {
 183         .dot = { .min = 22000, .max = 400000 },
 184         .vco = { .min = 1750000, .max = 3500000},
 185         .n = { .min = 1, .max = 4 },
 186         .m = { .min = 104, .max = 138 },
 187         .m1 = { .min = 16, .max = 23 },
 188         .m2 = { .min = 5, .max = 11 },
 189         .p = { .min = 5, .max = 80 },
 190         .p1 = { .min = 1, .max = 8},
 191         .p2 = { .dot_limit = 165000,
 192                 .p2_slow = 10, .p2_fast = 5 },
 193         .find_pll = intel_g4x_find_best_PLL,
 194 };
 195
 196 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 197         .dot = { .min = 20000, .max = 115000 },
 198         .vco = { .min = 1750000, .max = 3500000 },
 199         .n = { .min = 1, .max = 3 },
 200         .m = { .min = 104, .max = 138 },
 201         .m1 = { .min = 17, .max = 23 },
 202         .m2 = { .min = 5, .max = 11 },
 203         .p = { .min = 28, .max = 112 },
 204         .p1 = { .min = 2, .max = 8 },
 205         .p2 = { .dot_limit = 0,
 206                 .p2_slow = 14, .p2_fast = 14
 207         },
 208         .find_pll = intel_g4x_find_best_PLL,
 209 };
 210
 211 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 212         .dot = { .min = 80000, .max = 224000 },
 213         .vco = { .min = 1750000, .max = 3500000 },
 214         .n = { .min = 1, .max = 3 },
 215         .m = { .min = 104, .max = 138 },
 216         .m1 = { .min = 17, .max = 23 },
 217         .m2 = { .min = 5, .max = 11 },
 218         .p = { .min = 14, .max = 42 },
 219         .p1 = { .min = 2, .max = 6 },
 220         .p2 = { .dot_limit = 0,
 221                 .p2_slow = 7, .p2_fast = 7
 222         },
 223         .find_pll = intel_g4x_find_best_PLL,
 224 };
 225
 226 static const intel_limit_t intel_limits_g4x_display_port = {
 227         .dot = { .min = 161670, .max = 227000 },
 228         .vco = { .min = 1750000, .max = 3500000},
 229         .n = { .min = 1, .max = 2 },
 230         .m = { .min = 97, .max = 108 },
 231         .m1 = { .min = 0x10, .max = 0x12 },
 232         .m2 = { .min = 0x05, .max = 0x06 },
 233         .p = { .min = 10, .max = 20 },
 234         .p1 = { .min = 1, .max = 2},
 235         .p2 = { .dot_limit = 0,
 236                 .p2_slow = 10, .p2_fast = 10 },
 237         .find_pll = intel_find_pll_g4x_dp,
 238 };
 239
 240 static const intel_limit_t intel_limits_pineview_sdvo = {
 241         .dot = { .min = 20000, .max = 400000},
 242         .vco = { .min = 1700000, .max = 3500000 },
 243         /* Pineview's Ncounter is a ring counter */
 244         .n = { .min = 3, .max = 6 },
 245         .m = { .min = 2, .max = 256 },
 246         /* Pineview only has one combined m divider, which we treat as m2. */
 247         .m1 = { .min = 0, .max = 0 },
 248         .m2 = { .min = 0, .max = 254 },
 249         .p = { .min = 5, .max = 80 },
 250         .p1 = { .min = 1, .max = 8 },
 251         .p2 = { .dot_limit = 200000,
 252                 .p2_slow = 10, .p2_fast = 5 },
 253         .find_pll = intel_find_best_PLL,
 254 };
 255
 256 static const intel_limit_t intel_limits_pineview_lvds = {
 257         .dot = { .min = 20000, .max = 400000 },
 258         .vco = { .min = 1700000, .max = 3500000 },
 259         .n = { .min = 3, .max = 6 },
 260         .m = { .min = 2, .max = 256 },
 261         .m1 = { .min = 0, .max = 0 },
 262         .m2 = { .min = 0, .max = 254 },
 263         .p = { .min = 7, .max = 112 },
 264         .p1 = { .min = 1, .max = 8 },
 265         .p2 = { .dot_limit = 112000,
 266                 .p2_slow = 14, .p2_fast = 14 },
 267         .find_pll = intel_find_best_PLL,
 268 };
 269
 270 /* Ironlake / Sandybridge
 271  *
 272  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 273  * the range value for them is (actual_value - 2).
 274  */
 275 static const intel_limit_t intel_limits_ironlake_dac = {
 276         .dot = { .min = 25000, .max = 350000 },
 277         .vco = { .min = 1760000, .max = 3510000 },
 278         .n = { .min = 1, .max = 5 },
 279         .m = { .min = 79, .max = 127 },
 280         .m1 = { .min = 12, .max = 22 },
 281         .m2 = { .min = 5, .max = 9 },
 282         .p = { .min = 5, .max = 80 },
 283         .p1 = { .min = 1, .max = 8 },
 284         .p2 = { .dot_limit = 225000,
 285                 .p2_slow = 10, .p2_fast = 5 },
 286         .find_pll = intel_g4x_find_best_PLL,
 287 };
 288
 289 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 290         .dot = { .min = 25000, .max = 350000 },
 291         .vco = { .min = 1760000, .max = 3510000 },
 292         .n = { .min = 1, .max = 3 },
 293         .m = { .min = 79, .max = 118 },
 294         .m1 = { .min = 12, .max = 22 },
 295         .m2 = { .min = 5, .max = 9 },
 296         .p = { .min = 28, .max = 112 },
 297         .p1 = { .min = 2, .max = 8 },
 298         .p2 = { .dot_limit = 225000,
 299                 .p2_slow = 14, .p2_fast = 14 },
 300         .find_pll = intel_g4x_find_best_PLL,
 301 };
 302
 303 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 304         .dot = { .min = 25000, .max = 350000 },
 305         .vco = { .min = 1760000, .max = 3510000 },
 306         .n = { .min = 1, .max = 3 },
 307         .m = { .min = 79, .max = 127 },
 308         .m1 = { .min = 12, .max = 22 },
 309         .m2 = { .min = 5, .max = 9 },
 310         .p = { .min = 14, .max = 56 },
 311         .p1 = { .min = 2, .max = 8 },
 312         .p2 = { .dot_limit = 225000,
 313                 .p2_slow = 7, .p2_fast = 7 },
 314         .find_pll = intel_g4x_find_best_PLL,
 315 };
 316
 317 /* LVDS 100mhz refclk limits. */
 318 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 319         .dot = { .min = 25000, .max = 350000 },
 320         .vco = { .min = 1760000, .max = 3510000 },
 321         .n = { .min = 1, .max = 2 },
 322         .m = { .min = 79, .max = 126 },
 323         .m1 = { .min = 12, .max = 22 },
 324         .m2 = { .min = 5, .max = 9 },
 325         .p = { .min = 28, .max = 112 },
 326         .p1 = { .min = 2, .max = 8 },
 327         .p2 = { .dot_limit = 225000,
 328                 .p2_slow = 14, .p2_fast = 14 },
 329         .find_pll = intel_g4x_find_best_PLL,
 330 };
 331
 332 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 333         .dot = { .min = 25000, .max = 350000 },
 334         .vco = { .min = 1760000, .max = 3510000 },
 335         .n = { .min = 1, .max = 3 },
 336         .m = { .min = 79, .max = 126 },
 337         .m1 = { .min = 12, .max = 22 },
 338         .m2 = { .min = 5, .max = 9 },
 339         .p = { .min = 14, .max = 42 },
 340         .p1 = { .min = 2, .max = 6 },
 341         .p2 = { .dot_limit = 225000,
 342                 .p2_slow = 7, .p2_fast = 7 },
 343         .find_pll = intel_g4x_find_best_PLL,
 344 };
 345
 346 static const intel_limit_t intel_limits_ironlake_display_port = {
 347         .dot = { .min = 25000, .max = 350000 },
 348         .vco = { .min = 1760000, .max = 3510000},
 349         .n = { .min = 1, .max = 2 },
 350         .m = { .min = 81, .max = 90 },
 351         .m1 = { .min = 12, .max = 22 },
 352         .m2 = { .min = 5, .max = 9 },
 353         .p = { .min = 10, .max = 20 },
 354         .p1 = { .min = 1, .max = 2},
 355         .p2 = { .dot_limit = 0,
 356                 .p2_slow = 10, .p2_fast = 10 },
 357         .find_pll = intel_find_pll_ironlake_dp,
 358 };
 359
 360 static bool is_dual_link_lvds(struct drm_i915_private *dev_priv,
 361                               unsigned int reg)
 362 {
 363         unsigned int val;
 364
 365         if (dev_priv->lvds_val)
 366                 val = dev_priv->lvds_val;
 367         else {
 368                 /* BIOS should set the proper LVDS register value at boot, but
 369                  * in reality, it doesn't set the value when the lid is closed;
 370                  * we need to check "the value to be set" in VBT when LVDS
 371                  * register is uninitialized.
 372                  */
 373                 val = I915_READ(reg);
 374                 if (!(val & ~LVDS_DETECTED))
 375                         val = dev_priv->bios_lvds_val;
 376                 dev_priv->lvds_val = val;
 377         }
 378         return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP;
 379 }
 380
 381 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
 382                                                 int refclk)
 383 {
 384         struct drm_device *dev = crtc->dev;
 385         struct drm_i915_private *dev_priv = dev->dev_private;
 386         const intel_limit_t *limit;
 387
 388         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 389                 if (is_dual_link_lvds(dev_priv, PCH_LVDS)) {
 390                         /* LVDS dual channel */
 391                         if (refclk == 100000)
 392                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 393                         else
 394                                 limit = &intel_limits_ironlake_dual_lvds;
 395                 } else {
 396                         if (refclk == 100000)
 397                                 limit = &intel_limits_ironlake_single_lvds_100m;
 398                         else
 399                                 limit = &intel_limits_ironlake_single_lvds;
 400                 }
 401         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
 402                         HAS_eDP)
 403                 limit = &intel_limits_ironlake_display_port;
 404         else
 405                 limit = &intel_limits_ironlake_dac;
 406
 407         return limit;
 408 }
 409
 410 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 411 {
 412         struct drm_device *dev = crtc->dev;
 413         struct drm_i915_private *dev_priv = dev->dev_private;
 414         const intel_limit_t *limit;
 415
 416         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 417                 if (is_dual_link_lvds(dev_priv, LVDS))
 418                         /* LVDS with dual channel */
 419                         limit = &intel_limits_g4x_dual_channel_lvds;
 420                 else
 421                         /* LVDS with dual channel */
 422                         limit = &intel_limits_g4x_single_channel_lvds;
 423         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 424                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 425                 limit = &intel_limits_g4x_hdmi;
 426         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 427                 limit = &intel_limits_g4x_sdvo;
 428         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
 429                 limit = &intel_limits_g4x_display_port;
 430         } else /* The option is for other outputs */
 431                 limit = &intel_limits_i9xx_sdvo;
 432
 433         return limit;
 434 }
 435
 436 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
 437 {
 438         struct drm_device *dev = crtc->dev;
 439         const intel_limit_t *limit;
 440
 441         if (HAS_PCH_SPLIT(dev))
 442                 limit = intel_ironlake_limit(crtc, refclk);
 443         else if (IS_G4X(dev)) {
 444                 limit = intel_g4x_limit(crtc);
 445         } else if (IS_PINEVIEW(dev)) {
 446                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 447                         limit = &intel_limits_pineview_lvds;
 448                 else
 449                         limit = &intel_limits_pineview_sdvo;
 450         } else if (!IS_GEN2(dev)) {
 451                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 452                         limit = &intel_limits_i9xx_lvds;
 453                 else
 454                         limit = &intel_limits_i9xx_sdvo;
 455         } else {
 456                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 457                         limit = &intel_limits_i8xx_lvds;
 458                 else
 459                         limit = &intel_limits_i8xx_dvo;
 460         }
 461         return limit;
 462 }
 463
 464 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 465 static void pineview_clock(int refclk, intel_clock_t *clock)
 466 {
 467         clock->m = clock->m2 + 2;
 468         clock->p = clock->p1 * clock->p2;
 469         clock->vco = refclk * clock->m / clock->n;
 470         clock->dot = clock->vco / clock->p;
 471 }
 472
 473 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
 474 {
 475         if (IS_PINEVIEW(dev)) {
 476                 pineview_clock(refclk, clock);
 477                 return;
 478         }
 479         clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
 480         clock->p = clock->p1 * clock->p2;
 481         clock->vco = refclk * clock->m / (clock->n + 2);
 482         clock->dot = clock->vco / clock->p;
 483 }
 484
 485 /**
 486  * Returns whether any output on the specified pipe is of the specified type
 487  */
 488 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
 489 {
 490         struct drm_device *dev = crtc->dev;
 491         struct drm_mode_config *mode_config = &dev->mode_config;
 492         struct intel_encoder *encoder;
 493
 494         list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
 495                 if (encoder->base.crtc == crtc && encoder->type == type)
 496                         return true;
 497
 498         return false;
 499 }
 500
 501 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 502 /**
 503  * Returns whether the given set of divisors are valid for a given refclk with
 504  * the given connectors.
 505  */
 506
 507 static bool intel_PLL_is_valid(struct drm_device *dev,
 508                                const intel_limit_t *limit,
 509                                const intel_clock_t *clock)
 510 {
 511         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 512                 INTELPllInvalid("p1 out of range\n");
 513         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
 514                 INTELPllInvalid("p out of range\n");
 515         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 516                 INTELPllInvalid("m2 out of range\n");
 517         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 518                 INTELPllInvalid("m1 out of range\n");
 519         if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
 520                 INTELPllInvalid("m1 <= m2\n");
 521         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
 522                 INTELPllInvalid("m out of range\n");
 523         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 524                 INTELPllInvalid("n out of range\n");
 525         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 526                 INTELPllInvalid("vco out of range\n");
 527         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 528          * connector, etc., rather than just a single range.
 529          */
 530         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 531                 INTELPllInvalid("dot out of range\n");
 532
 533         return true;
 534 }
 535
 536 static bool
 537 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 538                     int target, int refclk, intel_clock_t *best_clock)
 539
 540 {
 541         struct drm_device *dev = crtc->dev;
 542         struct drm_i915_private *dev_priv = dev->dev_private;
 543         intel_clock_t clock;
 544         int err = target;
 545
 546         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
 547             (I915_READ(LVDS)) != 0) {
 548                 /*
 549                  * For LVDS, if the panel is on, just rely on its current
 550                  * settings for dual-channel.  We haven't figured out how to
 551                  * reliably set up different single/dual channel state, if we
 552                  * even can.
 553                  */
 554                 if (is_dual_link_lvds(dev_priv, LVDS))
 555                         clock.p2 = limit->p2.p2_fast;
 556                 else
 557                         clock.p2 = limit->p2.p2_slow;
 558         } else {
 559                 if (target < limit->p2.dot_limit)
 560                         clock.p2 = limit->p2.p2_slow;
 561                 else
 562                         clock.p2 = limit->p2.p2_fast;
 563         }
 564
 565         memset(best_clock, 0, sizeof(*best_clock));
 566
 567         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 568              clock.m1++) {
 569                 for (clock.m2 = limit->m2.min;
 570                      clock.m2 <= limit->m2.max; clock.m2++) {
 571                         /* m1 is always 0 in Pineview */
 572                         if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
 573                                 break;
 574                         for (clock.n = limit->n.min;
 575                              clock.n <= limit->n.max; clock.n++) {
 576                                 for (clock.p1 = limit->p1.min;
 577                                         clock.p1 <= limit->p1.max; clock.p1++) {
 578                                         int this_err;
 579
 580                                         intel_clock(dev, refclk, &clock);
 581                                         if (!intel_PLL_is_valid(dev, limit,
 582                                                                 &clock))
 583                                                 continue;
 584
 585                                         this_err = abs(clock.dot - target);
 586                                         if (this_err < err) {
 587                                                 *best_clock = clock;
 588                                                 err = this_err;
 589                                         }
 590                                 }
 591                         }
 592                 }
 593         }
 594
 595         return (err != target);
 596 }
 597
 598 static bool
 599 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 600                         int target, int refclk, intel_clock_t *best_clock)
 601 {
 602         struct drm_device *dev = crtc->dev;
 603         struct drm_i915_private *dev_priv = dev->dev_private;
 604         intel_clock_t clock;
 605         int max_n;
 606         bool found;
 607         /* approximately equals target * 0.00585 */
 608         int err_most = (target >> 8) + (target >> 9);
 609         found = false;
 610
 611         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 612                 int lvds_reg;
 613
 614                 if (HAS_PCH_SPLIT(dev))
 615                         lvds_reg = PCH_LVDS;
 616                 else
 617                         lvds_reg = LVDS;
 618                 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
 619                     LVDS_CLKB_POWER_UP)
 620                         clock.p2 = limit->p2.p2_fast;
 621                 else
 622                         clock.p2 = limit->p2.p2_slow;
 623         } else {
 624                 if (target < limit->p2.dot_limit)
 625                         clock.p2 = limit->p2.p2_slow;
 626                 else
 627                         clock.p2 = limit->p2.p2_fast;
 628         }
 629
 630         memset(best_clock, 0, sizeof(*best_clock));
 631         max_n = limit->n.max;
 632         /* based on hardware requirement, prefer smaller n to precision */
 633         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 634                 /* based on hardware requirement, prefere larger m1,m2 */
 635                 for (clock.m1 = limit->m1.max;
 636                      clock.m1 >= limit->m1.min; clock.m1--) {
 637                         for (clock.m2 = limit->m2.max;
 638                              clock.m2 >= limit->m2.min; clock.m2--) {
 639                                 for (clock.p1 = limit->p1.max;
 640                                      clock.p1 >= limit->p1.min; clock.p1--) {
 641                                         int this_err;
 642
 643                                         intel_clock(dev, refclk, &clock);
 644                                         if (!intel_PLL_is_valid(dev, limit,
 645                                                                 &clock))
 646                                                 continue;
 647
 648                                         this_err = abs(clock.dot - target);
 649                                         if (this_err < err_most) {
 650                                                 *best_clock = clock;
 651                                                 err_most = this_err;
 652                                                 max_n = clock.n;
 653                                                 found = true;
 654                                         }
 655                                 }
 656                         }
 657                 }
 658         }
 659         return found;
 660 }
 661
 662 static bool
 663 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 664                            int target, int refclk, intel_clock_t *best_clock)
 665 {
 666         struct drm_device *dev = crtc->dev;
 667         intel_clock_t clock;
 668
 669         if (target < 200000) {
 670                 clock.n = 1;
 671                 clock.p1 = 2;
 672                 clock.p2 = 10;
 673                 clock.m1 = 12;
 674                 clock.m2 = 9;
 675         } else {
 676                 clock.n = 2;
 677                 clock.p1 = 1;
 678                 clock.p2 = 10;
 679                 clock.m1 = 14;
 680                 clock.m2 = 8;
 681         }
 682         intel_clock(dev, refclk, &clock);
 683         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 684         return true;
 685 }
 686
 687 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
 688 static bool
 689 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 690                       int target, int refclk, intel_clock_t *best_clock)
 691 {
 692         intel_clock_t clock;
 693         if (target < 200000) {
 694                 clock.p1 = 2;
 695                 clock.p2 = 10;
 696                 clock.n = 2;
 697                 clock.m1 = 23;
 698                 clock.m2 = 8;
 699         } else {
 700                 clock.p1 = 1;
 701                 clock.p2 = 10;
 702                 clock.n = 1;
 703                 clock.m1 = 14;
 704                 clock.m2 = 2;
 705         }
 706         clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
 707         clock.p = (clock.p1 * clock.p2);
 708         clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
 709         clock.vco = 0;
 710         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 711         return true;
 712 }
 713
 714 /**
 715  * intel_wait_for_vblank - wait for vblank on a given pipe
 716  * @dev: drm device
 717  * @pipe: pipe to wait for
 718  *
 719  * Wait for vblank to occur on a given pipe.  Needed for various bits of
 720  * mode setting code.
 721  */
 722 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
 723 {
 724         struct drm_i915_private *dev_priv = dev->dev_private;
 725         int pipestat_reg = PIPESTAT(pipe);
 726
 727         /* Clear existing vblank status. Note this will clear any other
 728          * sticky status fields as well.
 729          *
 730          * This races with i915_driver_irq_handler() with the result
 731          * that either function could miss a vblank event.  Here it is not
 732          * fatal, as we will either wait upon the next vblank interrupt or
 733          * timeout.  Generally speaking intel_wait_for_vblank() is only
 734          * called during modeset at which time the GPU should be idle and
 735          * should *not* be performing page flips and thus not waiting on
 736          * vblanks...
 737          * Currently, the result of us stealing a vblank from the irq
 738          * handler is that a single frame will be skipped during swapbuffers.
 739          */
 740         I915_WRITE(pipestat_reg,
 741                    I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
 742
 743         /* Wait for vblank interrupt bit to set */
 744         if (wait_for(I915_READ(pipestat_reg) &
 745                      PIPE_VBLANK_INTERRUPT_STATUS,
 746                      50))
 747                 DRM_DEBUG_KMS("vblank wait timed out\n");
 748 }
 749
 750 /*
 751  * intel_wait_for_pipe_off - wait for pipe to turn off
 752  * @dev: drm device
 753  * @pipe: pipe to wait for
 754  *
 755  * After disabling a pipe, we can't wait for vblank in the usual way,
 756  * spinning on the vblank interrupt status bit, since we won't actually
 757  * see an interrupt when the pipe is disabled.
 758  *
 759  * On Gen4 and above:
 760  *   wait for the pipe register state bit to turn off
 761  *
 762  * Otherwise:
 763  *   wait for the display line value to settle (it usually
 764  *   ends up stopping at the start of the next frame).
 765  *
 766  */
 767 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
 768 {
 769         struct drm_i915_private *dev_priv = dev->dev_private;
 770
 771         if (INTEL_INFO(dev)->gen >= 4) {
 772                 int reg = PIPECONF(pipe);
 773
 774                 /* Wait for the Pipe State to go off */
 775                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
 776                              100))
 777                         DRM_DEBUG_KMS("pipe_off wait timed out\n");
 778         } else {
 779                 u32 last_line;
 780                 int reg = PIPEDSL(pipe);
 781                 unsigned long timeout = jiffies + msecs_to_jiffies(100);
 782
 783                 /* Wait for the display line to settle */
 784                 do {
 785                         last_line = I915_READ(reg) & DSL_LINEMASK;
 786                         mdelay(5);
 787                 } while (((I915_READ(reg) & DSL_LINEMASK) != last_line) &&
 788                          time_after(timeout, jiffies));
 789                 if (time_after(jiffies, timeout))
 790                         DRM_DEBUG_KMS("pipe_off wait timed out\n");
 791         }
 792 }
 793
 794 static const char *state_string(bool enabled)
 795 {
 796         return enabled ? "on" : "off";
 797 }
 798
 799 /* Only for pre-ILK configs */
 800 static void assert_pll(struct drm_i915_private *dev_priv,
 801                        enum pipe pipe, bool state)
 802 {
 803         int reg;
 804         u32 val;
 805         bool cur_state;
 806
 807         reg = DPLL(pipe);
 808         val = I915_READ(reg);
 809         cur_state = !!(val & DPLL_VCO_ENABLE);
 810         WARN(cur_state != state,
 811              "PLL state assertion failure (expected %s, current %s)\n",
 812              state_string(state), state_string(cur_state));
 813 }
 814 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
 815 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
 816
 817 /* For ILK+ */
 818 static void assert_pch_pll(struct drm_i915_private *dev_priv,
 819                            enum pipe pipe, bool state)
 820 {
 821         int reg;
 822         u32 val;
 823         bool cur_state;
 824
 825         if (HAS_PCH_CPT(dev_priv->dev)) {
 826                 u32 pch_dpll;
 827
 828                 pch_dpll = I915_READ(PCH_DPLL_SEL);
 829
 830                 /* Make sure the selected PLL is enabled to the transcoder */
 831                 WARN(!((pch_dpll >> (4 * pipe)) & 8),
 832                      "transcoder %d PLL not enabled\n", pipe);
 833
 834                 /* Convert the transcoder pipe number to a pll pipe number */
 835                 pipe = (pch_dpll >> (4 * pipe)) & 1;
 836         }
 837
 838         reg = PCH_DPLL(pipe);
 839         val = I915_READ(reg);
 840         cur_state = !!(val & DPLL_VCO_ENABLE);
 841         WARN(cur_state != state,
 842              "PCH PLL state assertion failure (expected %s, current %s)\n",
 843              state_string(state), state_string(cur_state));
 844 }
 845 #define assert_pch_pll_enabled(d, p) assert_pch_pll(d, p, true)
 846 #define assert_pch_pll_disabled(d, p) assert_pch_pll(d, p, false)
 847
 848 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
 849                           enum pipe pipe, bool state)
 850 {
 851         int reg;
 852         u32 val;
 853         bool cur_state;
 854
 855         reg = FDI_TX_CTL(pipe);
 856         val = I915_READ(reg);
 857         cur_state = !!(val & FDI_TX_ENABLE);
 858         WARN(cur_state != state,
 859              "FDI TX state assertion failure (expected %s, current %s)\n",
 860              state_string(state), state_string(cur_state));
 861 }
 862 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
 863 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
 864
 865 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
 866                           enum pipe pipe, bool state)
 867 {
 868         int reg;
 869         u32 val;
 870         bool cur_state;
 871
 872         reg = FDI_RX_CTL(pipe);
 873         val = I915_READ(reg);
 874         cur_state = !!(val & FDI_RX_ENABLE);
 875         WARN(cur_state != state,
 876              "FDI RX state assertion failure (expected %s, current %s)\n",
 877              state_string(state), state_string(cur_state));
 878 }
 879 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
 880 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
 881
 882 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
 883                                       enum pipe pipe)
 884 {
 885         int reg;
 886         u32 val;
 887
 888         /* ILK FDI PLL is always enabled */
 889         if (dev_priv->info->gen == 5)
 890                 return;
 891
 892         reg = FDI_TX_CTL(pipe);
 893         val = I915_READ(reg);
 894         WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
 895 }
 896
 897 static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
 898                                       enum pipe pipe)
 899 {
 900         int reg;
 901         u32 val;
 902
 903         reg = FDI_RX_CTL(pipe);
 904         val = I915_READ(reg);
 905         WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
 906 }
 907
 908 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
 909                                   enum pipe pipe)
 910 {
 911         int pp_reg, lvds_reg;
 912         u32 val;
 913         enum pipe panel_pipe = PIPE_A;
 914         bool locked = true;
 915
 916         if (HAS_PCH_SPLIT(dev_priv->dev)) {
 917                 pp_reg = PCH_PP_CONTROL;
 918                 lvds_reg = PCH_LVDS;
 919         } else {
 920                 pp_reg = PP_CONTROL;
 921                 lvds_reg = LVDS;
 922         }
 923
 924         val = I915_READ(pp_reg);
 925         if (!(val & PANEL_POWER_ON) ||
 926             ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
 927                 locked = false;
 928
 929         if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
 930                 panel_pipe = PIPE_B;
 931
 932         WARN(panel_pipe == pipe && locked,
 933              "panel assertion failure, pipe %c regs locked\n",
 934              pipe_name(pipe));
 935 }
 936
 937 static void assert_pipe(struct drm_i915_private *dev_priv,
 938                         enum pipe pipe, bool state)
 939 {
 940         int reg;
 941         u32 val;
 942         bool cur_state;
 943
 944         reg = PIPECONF(pipe);
 945         val = I915_READ(reg);
 946         cur_state = !!(val & PIPECONF_ENABLE);
 947         WARN(cur_state != state,
 948              "pipe %c assertion failure (expected %s, current %s)\n",
 949              pipe_name(pipe), state_string(state), state_string(cur_state));
 950 }
 951 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
 952 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
 953
 954 static void assert_plane_enabled(struct drm_i915_private *dev_priv,
 955                                  enum plane plane)
 956 {
 957         int reg;
 958         u32 val;
 959
 960         reg = DSPCNTR(plane);
 961         val = I915_READ(reg);
 962         WARN(!(val & DISPLAY_PLANE_ENABLE),
 963              "plane %c assertion failure, should be active but is disabled\n",
 964              plane_name(plane));
 965 }
 966
 967 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
 968                                    enum pipe pipe)
 969 {
 970         int reg, i;
 971         u32 val;
 972         int cur_pipe;
 973
 974         /* Planes are fixed to pipes on ILK+ */
 975         if (HAS_PCH_SPLIT(dev_priv->dev))
 976                 return;
 977
 978         /* Need to check both planes against the pipe */
 979         for (i = 0; i < 2; i++) {
 980                 reg = DSPCNTR(i);
 981                 val = I915_READ(reg);
 982                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
 983                         DISPPLANE_SEL_PIPE_SHIFT;
 984                 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
 985                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
 986                      plane_name(i), pipe_name(pipe));
 987         }
 988 }
 989
 990 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
 991 {
 992         u32 val;
 993         bool enabled;
 994
 995         val = I915_READ(PCH_DREF_CONTROL);
 996         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
 997                             DREF_SUPERSPREAD_SOURCE_MASK));
 998         WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
 999 }
1000
1001 static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1002                                        enum pipe pipe)
1003 {
1004         int reg;
1005         u32 val;
1006         bool enabled;
1007
1008         reg = TRANSCONF(pipe);
1009         val = I915_READ(reg);
1010         enabled = !!(val & TRANS_ENABLE);
1011         WARN(enabled,
1012              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1013              pipe_name(pipe));
1014 }
1015
1016 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1017                             enum pipe pipe, u32 port_sel, u32 val)
1018 {
1019         if ((val & DP_PORT_EN) == 0)
1020                 return false;
1021
1022         if (HAS_PCH_CPT(dev_priv->dev)) {
1023                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1024                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1025                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1026                         return false;
1027         } else {
1028                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1029                         return false;
1030         }
1031         return true;
1032 }
1033
1034 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1035                               enum pipe pipe, u32 val)
1036 {
1037         if ((val & PORT_ENABLE) == 0)
1038                 return false;
1039
1040         if (HAS_PCH_CPT(dev_priv->dev)) {
1041                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1042                         return false;
1043         } else {
1044                 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1045                         return false;
1046         }
1047         return true;
1048 }
1049
1050 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1051                               enum pipe pipe, u32 val)
1052 {
1053         if ((val & LVDS_PORT_EN) == 0)
1054                 return false;
1055
1056         if (HAS_PCH_CPT(dev_priv->dev)) {
1057                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1058                         return false;
1059         } else {
1060                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1061                         return false;
1062         }
1063         return true;
1064 }
1065
1066 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1067                               enum pipe pipe, u32 val)
1068 {
1069         if ((val & ADPA_DAC_ENABLE) == 0)
1070                 return false;
1071         if (HAS_PCH_CPT(dev_priv->dev)) {
1072                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1073                         return false;
1074         } else {
1075                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1076                         return false;
1077         }
1078         return true;
1079 }
1080
1081 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1082                                    enum pipe pipe, int reg, u32 port_sel)
1083 {
1084         u32 val = I915_READ(reg);
1085         WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1086              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1087              reg, pipe_name(pipe));
1088 }
1089
1090 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1091                                      enum pipe pipe, int reg)
1092 {
1093         u32 val = I915_READ(reg);
1094         WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1095              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1096              reg, pipe_name(pipe));
1097 }
1098
1099 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1100                                       enum pipe pipe)
1101 {
1102         int reg;
1103         u32 val;
1104
1105         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1106         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1107         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1108
1109         reg = PCH_ADPA;
1110         val = I915_READ(reg);
1111         WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1112              "PCH VGA enabled on transcoder %c, should be disabled\n",
1113              pipe_name(pipe));
1114
1115         reg = PCH_LVDS;
1116         val = I915_READ(reg);
1117         WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1118              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1119              pipe_name(pipe));
1120
1121         assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1122         assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1123         assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1124 }
1125
1126 /**
1127  * intel_enable_pll - enable a PLL
1128  * @dev_priv: i915 private structure
1129  * @pipe: pipe PLL to enable
1130  *
1131  * Enable @pipe's PLL so we can start pumping pixels from a plane.  Check to
1132  * make sure the PLL reg is writable first though, since the panel write
1133  * protect mechanism may be enabled.
1134  *
1135  * Note!  This is for pre-ILK only.
1136  */
1137 static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1138 {
1139         int reg;
1140         u32 val;
1141
1142         /* No really, not for ILK+ */
1143         BUG_ON(dev_priv->info->gen >= 5);
1144
1145         /* PLL is protected by panel, make sure we can write it */
1146         if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1147                 assert_panel_unlocked(dev_priv, pipe);
1148
1149         reg = DPLL(pipe);
1150         val = I915_READ(reg);
1151         val |= DPLL_VCO_ENABLE;
1152
1153         /* We do this three times for luck */
1154         I915_WRITE(reg, val);
1155         POSTING_READ(reg);
1156         udelay(150); /* wait for warmup */
1157         I915_WRITE(reg, val);
1158         POSTING_READ(reg);
1159         udelay(150); /* wait for warmup */
1160         I915_WRITE(reg, val);
1161         POSTING_READ(reg);
1162         udelay(150); /* wait for warmup */
1163 }
1164
1165 /**
1166  * intel_disable_pll - disable a PLL
1167  * @dev_priv: i915 private structure
1168  * @pipe: pipe PLL to disable
1169  *
1170  * Disable the PLL for @pipe, making sure the pipe is off first.
1171  *
1172  * Note!  This is for pre-ILK only.
1173  */
1174 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1175 {
1176         int reg;
1177         u32 val;
1178
1179         /* Don't disable pipe A or pipe A PLLs if needed */
1180         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1181                 return;
1182
1183         /* Make sure the pipe isn't still relying on us */
1184         assert_pipe_disabled(dev_priv, pipe);
1185
1186         reg = DPLL(pipe);
1187         val = I915_READ(reg);
1188         val &= ~DPLL_VCO_ENABLE;
1189         I915_WRITE(reg, val);
1190         POSTING_READ(reg);
1191 }
1192
1193 /**
1194  * intel_enable_pch_pll - enable PCH PLL
1195  * @dev_priv: i915 private structure
1196  * @pipe: pipe PLL to enable
1197  *
1198  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1199  * drives the transcoder clock.
1200  */
1201 static void intel_enable_pch_pll(struct drm_i915_private *dev_priv,
1202                                  enum pipe pipe)
1203 {
1204         int reg;
1205         u32 val;
1206
1207         if (pipe > 1)
1208                 return;
1209
1210         /* PCH only available on ILK+ */
1211         BUG_ON(dev_priv->info->gen < 5);
1212
1213         /* PCH refclock must be enabled first */
1214         assert_pch_refclk_enabled(dev_priv);
1215
1216         reg = PCH_DPLL(pipe);
1217         val = I915_READ(reg);
1218         val |= DPLL_VCO_ENABLE;
1219         I915_WRITE(reg, val);
1220         POSTING_READ(reg);
1221         udelay(200);
1222 }
1223
1224 static void intel_disable_pch_pll(struct drm_i915_private *dev_priv,
1225                                   enum pipe pipe)
1226 {
1227         int reg;
1228         u32 val;
1229
1230         if (pipe > 1)
1231                 return;
1232
1233         /* PCH only available on ILK+ */
1234         BUG_ON(dev_priv->info->gen < 5);
1235
1236         /* Make sure transcoder isn't still depending on us */
1237         assert_transcoder_disabled(dev_priv, pipe);
1238
1239         reg = PCH_DPLL(pipe);
1240         val = I915_READ(reg);
1241         val &= ~DPLL_VCO_ENABLE;
1242         I915_WRITE(reg, val);
1243         POSTING_READ(reg);
1244         udelay(200);
1245 }
1246
1247 static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
1248                                     enum pipe pipe)
1249 {
1250         int reg;
1251         u32 val;
1252
1253         /* PCH only available on ILK+ */
1254         BUG_ON(dev_priv->info->gen < 5);
1255
1256         /* Make sure PCH DPLL is enabled */
1257         assert_pch_pll_enabled(dev_priv, pipe);
1258
1259         /* FDI must be feeding us bits for PCH ports */
1260         assert_fdi_tx_enabled(dev_priv, pipe);
1261         assert_fdi_rx_enabled(dev_priv, pipe);
1262
1263         reg = TRANSCONF(pipe);
1264         val = I915_READ(reg);
1265
1266         if (HAS_PCH_IBX(dev_priv->dev)) {
1267                 /*
1268                  * make the BPC in transcoder be consistent with
1269                  * that in pipeconf reg.
1270                  */
1271                 val &= ~PIPE_BPC_MASK;
1272                 val |= I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK;
1273         }
1274         I915_WRITE(reg, val | TRANS_ENABLE);
1275         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1276                 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1277 }
1278
1279 static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
1280                                      enum pipe pipe)
1281 {
1282         int reg;
1283         u32 val;
1284
1285         /* FDI relies on the transcoder */
1286         assert_fdi_tx_disabled(dev_priv, pipe);
1287         assert_fdi_rx_disabled(dev_priv, pipe);
1288
1289         /* Ports must be off as well */
1290         assert_pch_ports_disabled(dev_priv, pipe);
1291
1292         reg = TRANSCONF(pipe);
1293         val = I915_READ(reg);
1294         val &= ~TRANS_ENABLE;
1295         I915_WRITE(reg, val);
1296         /* wait for PCH transcoder off, transcoder state */
1297         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1298                 DRM_ERROR("failed to disable transcoder %d\n", pipe);
1299 }
1300
1301 /**
1302  * intel_enable_pipe - enable a pipe, asserting requirements
1303  * @dev_priv: i915 private structure
1304  * @pipe: pipe to enable
1305  * @pch_port: on ILK+, is this pipe driving a PCH port or not
1306  *
1307  * Enable @pipe, making sure that various hardware specific requirements
1308  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1309  *
1310  * @pipe should be %PIPE_A or %PIPE_B.
1311  *
1312  * Will wait until the pipe is actually running (i.e. first vblank) before
1313  * returning.
1314  */
1315 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1316                               bool pch_port)
1317 {
1318         int reg;
1319         u32 val;
1320
1321         /*
1322          * A pipe without a PLL won't actually be able to drive bits from
1323          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1324          * need the check.
1325          */
1326         if (!HAS_PCH_SPLIT(dev_priv->dev))
1327                 assert_pll_enabled(dev_priv, pipe);
1328         else {
1329                 if (pch_port) {
1330                         /* if driving the PCH, we need FDI enabled */
1331                         assert_fdi_rx_pll_enabled(dev_priv, pipe);
1332                         assert_fdi_tx_pll_enabled(dev_priv, pipe);
1333                 }
1334                 /* FIXME: assert CPU port conditions for SNB+ */
1335         }
1336
1337         reg = PIPECONF(pipe);
1338         val = I915_READ(reg);
1339         if (val & PIPECONF_ENABLE)
1340                 return;
1341
1342         I915_WRITE(reg, val | PIPECONF_ENABLE);
1343         intel_wait_for_vblank(dev_priv->dev, pipe);
1344 }
1345
1346 /**
1347  * intel_disable_pipe - disable a pipe, asserting requirements
1348  * @dev_priv: i915 private structure
1349  * @pipe: pipe to disable
1350  *
1351  * Disable @pipe, making sure that various hardware specific requirements
1352  * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1353  *
1354  * @pipe should be %PIPE_A or %PIPE_B.
1355  *
1356  * Will wait until the pipe has shut down before returning.
1357  */
1358 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1359                                enum pipe pipe)
1360 {
1361         int reg;
1362         u32 val;
1363
1364         /*
1365          * Make sure planes won't keep trying to pump pixels to us,
1366          * or we might hang the display.
1367          */
1368         assert_planes_disabled(dev_priv, pipe);
1369
1370         /* Don't disable pipe A or pipe A PLLs if needed */
1371         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1372                 return;
1373
1374         reg = PIPECONF(pipe);
1375         val = I915_READ(reg);
1376         if ((val & PIPECONF_ENABLE) == 0)
1377                 return;
1378
1379         I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1380         intel_wait_for_pipe_off(dev_priv->dev, pipe);
1381 }
1382
1383 /*
1384  * Plane regs are double buffered, going from enabled->disabled needs a
1385  * trigger in order to latch.  The display address reg provides this.
1386  */
1387 static void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1388                                       enum plane plane)
1389 {
1390         I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1391         I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1392 }
1393
1394 /**
1395  * intel_enable_plane - enable a display plane on a given pipe
1396  * @dev_priv: i915 private structure
1397  * @plane: plane to enable
1398  * @pipe: pipe being fed
1399  *
1400  * Enable @plane on @pipe, making sure that @pipe is running first.
1401  */
1402 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1403                                enum plane plane, enum pipe pipe)
1404 {
1405         int reg;
1406         u32 val;
1407
1408         /* If the pipe isn't enabled, we can't pump pixels and may hang */
1409         assert_pipe_enabled(dev_priv, pipe);
1410
1411         reg = DSPCNTR(plane);
1412         val = I915_READ(reg);
1413         if (val & DISPLAY_PLANE_ENABLE)
1414                 return;
1415
1416         I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1417         intel_flush_display_plane(dev_priv, plane);
1418         intel_wait_for_vblank(dev_priv->dev, pipe);
1419 }
1420
1421 /**
1422  * intel_disable_plane - disable a display plane
1423  * @dev_priv: i915 private structure
1424  * @plane: plane to disable
1425  * @pipe: pipe consuming the data
1426  *
1427  * Disable @plane; should be an independent operation.
1428  */
1429 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1430                                 enum plane plane, enum pipe pipe)
1431 {
1432         int reg;
1433         u32 val;
1434
1435         reg = DSPCNTR(plane);
1436         val = I915_READ(reg);
1437         if ((val & DISPLAY_PLANE_ENABLE) == 0)
1438                 return;
1439
1440         I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1441         intel_flush_display_plane(dev_priv, plane);
1442         intel_wait_for_vblank(dev_priv->dev, pipe);
1443 }
1444
1445 static void disable_pch_dp(struct drm_i915_private *dev_priv,
1446                            enum pipe pipe, int reg, u32 port_sel)
1447 {
1448         u32 val = I915_READ(reg);
1449         if (dp_pipe_enabled(dev_priv, pipe, port_sel, val)) {
1450                 DRM_DEBUG_KMS("Disabling pch dp %x on pipe %d\n", reg, pipe);
1451                 I915_WRITE(reg, val & ~DP_PORT_EN);
1452         }
1453 }
1454
1455 static void disable_pch_hdmi(struct drm_i915_private *dev_priv,
1456                              enum pipe pipe, int reg)
1457 {
1458         u32 val = I915_READ(reg);
1459         if (hdmi_pipe_enabled(dev_priv, pipe, val)) {
1460                 DRM_DEBUG_KMS("Disabling pch HDMI %x on pipe %d\n",
1461                               reg, pipe);
1462                 I915_WRITE(reg, val & ~PORT_ENABLE);
1463         }
1464 }
1465
1466 /* Disable any ports connected to this transcoder */
1467 static void intel_disable_pch_ports(struct drm_i915_private *dev_priv,
1468                                     enum pipe pipe)
1469 {
1470         u32 reg, val;
1471
1472         val = I915_READ(PCH_PP_CONTROL);
1473         I915_WRITE(PCH_PP_CONTROL, val | PANEL_UNLOCK_REGS);
1474
1475         disable_pch_dp(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1476         disable_pch_dp(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1477         disable_pch_dp(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1478
1479         reg = PCH_ADPA;
1480         val = I915_READ(reg);
1481         if (adpa_pipe_enabled(dev_priv, pipe, val))
1482                 I915_WRITE(reg, val & ~ADPA_DAC_ENABLE);
1483
1484         reg = PCH_LVDS;
1485         val = I915_READ(reg);
1486         if (lvds_pipe_enabled(dev_priv, pipe, val)) {
1487                 DRM_DEBUG_KMS("disable lvds on pipe %d val 0x%08x\n", pipe, val);
1488                 I915_WRITE(reg, val & ~LVDS_PORT_EN);
1489                 POSTING_READ(reg);
1490                 udelay(100);
1491         }
1492
1493         disable_pch_hdmi(dev_priv, pipe, HDMIB);
1494         disable_pch_hdmi(dev_priv, pipe, HDMIC);
1495         disable_pch_hdmi(dev_priv, pipe, HDMID);
1496 }
1497
1498 static void i8xx_disable_fbc(struct drm_device *dev)
1499 {
1500         struct drm_i915_private *dev_priv = dev->dev_private;
1501         u32 fbc_ctl;
1502
1503         /* Disable compression */
1504         fbc_ctl = I915_READ(FBC_CONTROL);
1505         if ((fbc_ctl & FBC_CTL_EN) == 0)
1506                 return;
1507
1508         fbc_ctl &= ~FBC_CTL_EN;
1509         I915_WRITE(FBC_CONTROL, fbc_ctl);
1510
1511         /* Wait for compressing bit to clear */
1512         if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
1513                 DRM_DEBUG_KMS("FBC idle timed out\n");
1514                 return;
1515         }
1516
1517         DRM_DEBUG_KMS("disabled FBC\n");
1518 }
1519
1520 static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1521 {
1522         struct drm_device *dev = crtc->dev;
1523         struct drm_i915_private *dev_priv = dev->dev_private;
1524         struct drm_framebuffer *fb = crtc->fb;
1525         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1526         struct drm_i915_gem_object *obj = intel_fb->obj;
1527         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1528         int cfb_pitch;
1529         int plane, i;
1530         u32 fbc_ctl, fbc_ctl2;
1531
1532         cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
1533         if (fb->pitch < cfb_pitch)
1534                 cfb_pitch = fb->pitch;
1535
1536         /* FBC_CTL wants 64B units */
1537         cfb_pitch = (cfb_pitch / 64) - 1;
1538         plane = intel_crtc->plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
1539
1540         /* Clear old tags */
1541         for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
1542                 I915_WRITE(FBC_TAG + (i * 4), 0);
1543
1544         /* Set it up... */
1545         fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
1546         fbc_ctl2 |= plane;
1547         I915_WRITE(FBC_CONTROL2, fbc_ctl2);
1548         I915_WRITE(FBC_FENCE_OFF, crtc->y);
1549
1550         /* enable it... */
1551         fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
1552         if (IS_I945GM(dev))
1553                 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
1554         fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
1555         fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
1556         fbc_ctl |= obj->fence_reg;
1557         I915_WRITE(FBC_CONTROL, fbc_ctl);
1558
1559         DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %d, ",
1560                       cfb_pitch, crtc->y, intel_crtc->plane);
1561 }
1562
1563 static bool i8xx_fbc_enabled(struct drm_device *dev)
1564 {
1565         struct drm_i915_private *dev_priv = dev->dev_private;
1566
1567         return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
1568 }
1569
1570 static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1571 {
1572         struct drm_device *dev = crtc->dev;
1573         struct drm_i915_private *dev_priv = dev->dev_private;
1574         struct drm_framebuffer *fb = crtc->fb;
1575         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1576         struct drm_i915_gem_object *obj = intel_fb->obj;
1577         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1578         int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
1579         unsigned long stall_watermark = 200;
1580         u32 dpfc_ctl;
1581
1582         dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
1583         dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg;
1584         I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
1585
1586         I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1587                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1588                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1589         I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
1590
1591         /* enable it... */
1592         I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
1593
1594         DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1595 }
1596
1597 static void g4x_disable_fbc(struct drm_device *dev)
1598 {
1599         struct drm_i915_private *dev_priv = dev->dev_private;
1600         u32 dpfc_ctl;
1601
1602         /* Disable compression */
1603         dpfc_ctl = I915_READ(DPFC_CONTROL);
1604         if (dpfc_ctl & DPFC_CTL_EN) {
1605                 dpfc_ctl &= ~DPFC_CTL_EN;
1606                 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1607
1608                 DRM_DEBUG_KMS("disabled FBC\n");
1609         }
1610 }
1611
1612 static bool g4x_fbc_enabled(struct drm_device *dev)
1613 {
1614         struct drm_i915_private *dev_priv = dev->dev_private;
1615
1616         return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
1617 }
1618
1619 static void sandybridge_blit_fbc_update(struct drm_device *dev)
1620 {
1621         struct drm_i915_private *dev_priv = dev->dev_private;
1622         u32 blt_ecoskpd;
1623
1624         /* Make sure blitter notifies FBC of writes */
1625         gen6_gt_force_wake_get(dev_priv);
1626         blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
1627         blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
1628                 GEN6_BLITTER_LOCK_SHIFT;
1629         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1630         blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
1631         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1632         blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
1633                          GEN6_BLITTER_LOCK_SHIFT);
1634         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1635         POSTING_READ(GEN6_BLITTER_ECOSKPD);
1636         gen6_gt_force_wake_put(dev_priv);
1637 }
1638
1639 static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1640 {
1641         struct drm_device *dev = crtc->dev;
1642         struct drm_i915_private *dev_priv = dev->dev_private;
1643         struct drm_framebuffer *fb = crtc->fb;
1644         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1645         struct drm_i915_gem_object *obj = intel_fb->obj;
1646         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1647         int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
1648         unsigned long stall_watermark = 200;
1649         u32 dpfc_ctl;
1650
1651         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1652         dpfc_ctl &= DPFC_RESERVED;
1653         dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
1654         /* Set persistent mode for front-buffer rendering, ala X. */
1655         dpfc_ctl |= DPFC_CTL_PERSISTENT_MODE;
1656         dpfc_ctl |= (DPFC_CTL_FENCE_EN | obj->fence_reg);
1657         I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
1658
1659         I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1660                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1661                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1662         I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
1663         I915_WRITE(ILK_FBC_RT_BASE, obj->gtt_offset | ILK_FBC_RT_VALID);
1664         /* enable it... */
1665         I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
1666
1667         if (IS_GEN6(dev)) {
1668                 I915_WRITE(SNB_DPFC_CTL_SA,
1669                            SNB_CPU_FENCE_ENABLE | obj->fence_reg);
1670                 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
1671                 sandybridge_blit_fbc_update(dev);
1672         }
1673
1674         DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1675 }
1676
1677 static void ironlake_disable_fbc(struct drm_device *dev)
1678 {
1679         struct drm_i915_private *dev_priv = dev->dev_private;
1680         u32 dpfc_ctl;
1681
1682         /* Disable compression */
1683         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1684         if (dpfc_ctl & DPFC_CTL_EN) {
1685                 dpfc_ctl &= ~DPFC_CTL_EN;
1686                 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
1687
1688                 DRM_DEBUG_KMS("disabled FBC\n");
1689         }
1690 }
1691
1692 static bool ironlake_fbc_enabled(struct drm_device *dev)
1693 {
1694         struct drm_i915_private *dev_priv = dev->dev_private;
1695
1696         return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
1697 }
1698
1699 bool intel_fbc_enabled(struct drm_device *dev)
1700 {
1701         struct drm_i915_private *dev_priv = dev->dev_private;
1702
1703         if (!dev_priv->display.fbc_enabled)
1704                 return false;
1705
1706         return dev_priv->display.fbc_enabled(dev);
1707 }
1708
1709 static void intel_fbc_work_fn(struct work_struct *__work)
1710 {
1711         struct intel_fbc_work *work =
1712                 container_of(to_delayed_work(__work),
1713                              struct intel_fbc_work, work);
1714         struct drm_device *dev = work->crtc->dev;
1715         struct drm_i915_private *dev_priv = dev->dev_private;
1716
1717         mutex_lock(&dev->struct_mutex);
1718         if (work == dev_priv->fbc_work) {
1719                 /* Double check that we haven't switched fb without cancelling
1720                  * the prior work.
1721                  */
1722                 if (work->crtc->fb == work->fb) {
1723                         dev_priv->display.enable_fbc(work->crtc,
1724                                                      work->interval);
1725
1726                         dev_priv->cfb_plane = to_intel_crtc(work->crtc)->plane;
1727                         dev_priv->cfb_fb = work->crtc->fb->base.id;
1728                         dev_priv->cfb_y = work->crtc->y;
1729                 }
1730
1731                 dev_priv->fbc_work = NULL;
1732         }
1733         mutex_unlock(&dev->struct_mutex);
1734
1735         kfree(work);
1736 }
1737
1738 static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv)
1739 {
1740         if (dev_priv->fbc_work == NULL)
1741                 return;
1742
1743         DRM_DEBUG_KMS("cancelling pending FBC enable\n");
1744
1745         /* Synchronisation is provided by struct_mutex and checking of
1746          * dev_priv->fbc_work, so we can perform the cancellation
1747          * entirely asynchronously.
1748          */
1749         if (cancel_delayed_work(&dev_priv->fbc_work->work))
1750                 /* tasklet was killed before being run, clean up */
1751                 kfree(dev_priv->fbc_work);
1752
1753         /* Mark the work as no longer wanted so that if it does
1754          * wake-up (because the work was already running and waiting
1755          * for our mutex), it will discover that is no longer
1756          * necessary to run.
1757          */
1758         dev_priv->fbc_work = NULL;
1759 }
1760
1761 static void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1762 {
1763         struct intel_fbc_work *work;
1764         struct drm_device *dev = crtc->dev;
1765         struct drm_i915_private *dev_priv = dev->dev_private;
1766
1767         if (!dev_priv->display.enable_fbc)
1768                 return;
1769
1770         intel_cancel_fbc_work(dev_priv);
1771
1772         work = kzalloc(sizeof *work, GFP_KERNEL);
1773         if (work == NULL) {
1774                 dev_priv->display.enable_fbc(crtc, interval);
1775                 return;
1776         }
1777
1778         work->crtc = crtc;
1779         work->fb = crtc->fb;
1780         work->interval = interval;
1781         INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn);
1782
1783         dev_priv->fbc_work = work;
1784
1785         DRM_DEBUG_KMS("scheduling delayed FBC enable\n");
1786
1787         /* Delay the actual enabling to let pageflipping cease and the
1788          * display to settle before starting the compression. Note that
1789          * this delay also serves a second purpose: it allows for a
1790          * vblank to pass after disabling the FBC before we attempt
1791          * to modify the control registers.
1792          *
1793          * A more complicated solution would involve tracking vblanks
1794          * following the termination of the page-flipping sequence
1795          * and indeed performing the enable as a co-routine and not
1796          * waiting synchronously upon the vblank.
1797          */
1798         schedule_delayed_work(&work->work, msecs_to_jiffies(50));
1799 }
1800
1801 void intel_disable_fbc(struct drm_device *dev)
1802 {
1803         struct drm_i915_private *dev_priv = dev->dev_private;
1804
1805         intel_cancel_fbc_work(dev_priv);
1806
1807         if (!dev_priv->display.disable_fbc)
1808                 return;
1809
1810         dev_priv->display.disable_fbc(dev);
1811         dev_priv->cfb_plane = -1;
1812 }
1813
1814 /**
1815  * intel_update_fbc - enable/disable FBC as needed
1816  * @dev: the drm_device
1817  *
1818  * Set up the framebuffer compression hardware at mode set time.  We
1819  * enable it if possible:
1820  *   - plane A only (on pre-965)
1821  *   - no pixel mulitply/line duplication
1822  *   - no alpha buffer discard
1823  *   - no dual wide
1824  *   - framebuffer <= 2048 in width, 1536 in height
1825  *
1826  * We can't assume that any compression will take place (worst case),
1827  * so the compressed buffer has to be the same size as the uncompressed
1828  * one.  It also must reside (along with the line length buffer) in
1829  * stolen memory.
1830  *
1831  * We need to enable/disable FBC on a global basis.
1832  */
1833 static void intel_update_fbc(struct drm_device *dev)
1834 {
1835         struct drm_i915_private *dev_priv = dev->dev_private;
1836         struct drm_crtc *crtc = NULL, *tmp_crtc;
1837         struct intel_crtc *intel_crtc;
1838         struct drm_framebuffer *fb;
1839         struct intel_framebuffer *intel_fb;
1840         struct drm_i915_gem_object *obj;
1841         int enable_fbc;
1842
1843         DRM_DEBUG_KMS("\n");
1844
1845         if (!i915_powersave)
1846                 return;
1847
1848         if (!I915_HAS_FBC(dev))
1849                 return;
1850
1851         /*
1852          * If FBC is already on, we just have to verify that we can
1853          * keep it that way...
1854          * Need to disable if:
1855          *   - more than one pipe is active
1856          *   - changing FBC params (stride, fence, mode)
1857          *   - new fb is too large to fit in compressed buffer
1858          *   - going to an unsupported config (interlace, pixel multiply, etc.)
1859          */
1860         list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
1861                 if (tmp_crtc->enabled && tmp_crtc->fb) {
1862                         if (crtc) {
1863                                 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
1864                                 dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
1865                                 goto out_disable;
1866                         }
1867                         crtc = tmp_crtc;
1868                 }
1869         }
1870
1871         if (!crtc || crtc->fb == NULL) {
1872                 DRM_DEBUG_KMS("no output, disabling\n");
1873                 dev_priv->no_fbc_reason = FBC_NO_OUTPUT;
1874                 goto out_disable;
1875         }
1876
1877         intel_crtc = to_intel_crtc(crtc);
1878         fb = crtc->fb;
1879         intel_fb = to_intel_framebuffer(fb);
1880         obj = intel_fb->obj;
1881
1882         enable_fbc = i915_enable_fbc;
1883         if (enable_fbc < 0) {
1884                 DRM_DEBUG_KMS("fbc set to per-chip default\n");
1885                 enable_fbc = 1;
1886                 if (INTEL_INFO(dev)->gen <= 6)
1887                         enable_fbc = 0;
1888         }
1889         if (!enable_fbc) {
1890                 DRM_DEBUG_KMS("fbc disabled per module param\n");
1891                 dev_priv->no_fbc_reason = FBC_MODULE_PARAM;
1892                 goto out_disable;
1893         }
1894         if (intel_fb->obj->base.size > dev_priv->cfb_size) {
1895                 DRM_DEBUG_KMS("framebuffer too large, disabling "
1896                               "compression\n");
1897                 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
1898                 goto out_disable;
1899         }
1900         if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) ||
1901             (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) {
1902                 DRM_DEBUG_KMS("mode incompatible with compression, "
1903                               "disabling\n");
1904                 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
1905                 goto out_disable;
1906         }
1907         if ((crtc->mode.hdisplay > 2048) ||
1908             (crtc->mode.vdisplay > 1536)) {
1909                 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
1910                 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
1911                 goto out_disable;
1912         }
1913         if ((IS_I915GM(dev) || IS_I945GM(dev)) && intel_crtc->plane != 0) {
1914                 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
1915                 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
1916                 goto out_disable;
1917         }
1918
1919         /* The use of a CPU fence is mandatory in order to detect writes
1920          * by the CPU to the scanout and trigger updates to the FBC.
1921          */
1922         if (obj->tiling_mode != I915_TILING_X ||
1923             obj->fence_reg == I915_FENCE_REG_NONE) {
1924                 DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
1925                 dev_priv->no_fbc_reason = FBC_NOT_TILED;
1926                 goto out_disable;
1927         }
1928
1929         /* If the kernel debugger is active, always disable compression */
1930         if (in_dbg_master())
1931                 goto out_disable;
1932
1933         /* If the scanout has not changed, don't modify the FBC settings.
1934          * Note that we make the fundamental assumption that the fb->obj
1935          * cannot be unpinned (and have its GTT offset and fence revoked)
1936          * without first being decoupled from the scanout and FBC disabled.
1937          */
1938         if (dev_priv->cfb_plane == intel_crtc->plane &&
1939             dev_priv->cfb_fb == fb->base.id &&
1940             dev_priv->cfb_y == crtc->y)
1941                 return;
1942
1943         if (intel_fbc_enabled(dev)) {
1944                 /* We update FBC along two paths, after changing fb/crtc
1945                  * configuration (modeswitching) and after page-flipping
1946                  * finishes. For the latter, we know that not only did
1947                  * we disable the FBC at the start of the page-flip
1948                  * sequence, but also more than one vblank has passed.
1949                  *
1950                  * For the former case of modeswitching, it is possible
1951                  * to switch between two FBC valid configurations
1952                  * instantaneously so we do need to disable the FBC
1953                  * before we can modify its control registers. We also
1954                  * have to wait for the next vblank for that to take
1955                  * effect. However, since we delay enabling FBC we can
1956                  * assume that a vblank has passed since disabling and
1957                  * that we can safely alter the registers in the deferred
1958                  * callback.
1959                  *
1960                  * In the scenario that we go from a valid to invalid
1961                  * and then back to valid FBC configuration we have
1962                  * no strict enforcement that a vblank occurred since
1963                  * disabling the FBC. However, along all current pipe
1964                  * disabling paths we do need to wait for a vblank at
1965                  * some point. And we wait before enabling FBC anyway.
1966                  */
1967                 DRM_DEBUG_KMS("disabling active FBC for update\n");
1968                 intel_disable_fbc(dev);
1969         }
1970
1971         intel_enable_fbc(crtc, 500);
1972         return;
1973
1974 out_disable:
1975         /* Multiple disables should be harmless */
1976         if (intel_fbc_enabled(dev)) {
1977                 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
1978                 intel_disable_fbc(dev);
1979         }
1980 }
1981
1982 int
1983 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1984                            struct drm_i915_gem_object *obj,
1985                            struct intel_ring_buffer *pipelined)
1986 {
1987         struct drm_i915_private *dev_priv = dev->dev_private;
1988         u32 alignment;
1989         int ret;
1990
1991         switch (obj->tiling_mode) {
1992         case I915_TILING_NONE:
1993                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1994                         alignment = 128 * 1024;
1995                 else if (INTEL_INFO(dev)->gen >= 4)
1996                         alignment = 4 * 1024;
1997                 else
1998                         alignment = 64 * 1024;
1999                 break;
2000         case I915_TILING_X:
2001                 /* pin() will align the object as required by fence */
2002                 alignment = 0;
2003                 break;
2004         case I915_TILING_Y:
2005                 /* FIXME: Is this true? */
2006                 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
2007                 return -EINVAL;
2008         default:
2009                 BUG();
2010         }
2011
2012         dev_priv->mm.interruptible = false;
2013         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
2014         if (ret)
2015                 goto err_interruptible;
2016
2017         /* Install a fence for tiled scan-out. Pre-i965 always needs a
2018          * fence, whereas 965+ only requires a fence if using
2019          * framebuffer compression.  For simplicity, we always install
2020          * a fence as the cost is not that onerous.
2021          */
2022         if (obj->tiling_mode != I915_TILING_NONE) {
2023                 ret = i915_gem_object_get_fence(obj, pipelined);
2024                 if (ret)
2025                         goto err_unpin;
2026         }
2027
2028         dev_priv->mm.interruptible = true;
2029         return 0;
2030
2031 err_unpin:
2032         i915_gem_object_unpin(obj);
2033 err_interruptible:
2034         dev_priv->mm.interruptible = true;
2035         return ret;
2036 }
2037
2038 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2039                              int x, int y)
2040 {
2041         struct drm_device *dev = crtc->dev;
2042         struct drm_i915_private *dev_priv = dev->dev_private;
2043         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2044         struct intel_framebuffer *intel_fb;
2045         struct drm_i915_gem_object *obj;
2046         int plane = intel_crtc->plane;
2047         unsigned long Start, Offset;
2048         u32 dspcntr;
2049         u32 reg;
2050
2051         switch (plane) {
2052         case 0:
2053         case 1:
2054                 break;
2055         default:
2056                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2057                 return -EINVAL;
2058         }
2059
2060         intel_fb = to_intel_framebuffer(fb);
2061         obj = intel_fb->obj;
2062
2063         reg = DSPCNTR(plane);
2064         dspcntr = I915_READ(reg);
2065         /* Mask out pixel format bits in case we change it */
2066         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2067         switch (fb->bits_per_pixel) {
2068         case 8:
2069                 dspcntr |= DISPPLANE_8BPP;
2070                 break;
2071         case 16:
2072                 if (fb->depth == 15)
2073                         dspcntr |= DISPPLANE_15_16BPP;
2074                 else
2075                         dspcntr |= DISPPLANE_16BPP;
2076                 break;
2077         case 24:
2078         case 32:
2079                 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2080                 break;
2081         default:
2082                 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
2083                 return -EINVAL;
2084         }
2085         if (INTEL_INFO(dev)->gen >= 4) {
2086                 if (obj->tiling_mode != I915_TILING_NONE)
2087                         dspcntr |= DISPPLANE_TILED;
2088                 else
2089                         dspcntr &= ~DISPPLANE_TILED;
2090         }
2091
2092         I915_WRITE(reg, dspcntr);
2093
2094         Start = obj->gtt_offset;
2095         Offset = y * fb->pitch + x * (fb->bits_per_pixel / 8);
2096
2097         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2098                       Start, Offset, x, y, fb->pitch);
2099         I915_WRITE(DSPSTRIDE(plane), fb->pitch);
2100         if (INTEL_INFO(dev)->gen >= 4) {
2101                 I915_WRITE(DSPSURF(plane), Start);
2102                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2103                 I915_WRITE(DSPADDR(plane), Offset);
2104         } else
2105                 I915_WRITE(DSPADDR(plane), Start + Offset);
2106         POSTING_READ(reg);
2107
2108         return 0;
2109 }
2110
2111 static int ironlake_update_plane(struct drm_crtc *crtc,
2112                                  struct drm_framebuffer *fb, int x, int y)
2113 {
2114         struct drm_device *dev = crtc->dev;
2115         struct drm_i915_private *dev_priv = dev->dev_private;
2116         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2117         struct intel_framebuffer *intel_fb;
2118         struct drm_i915_gem_object *obj;
2119         int plane = intel_crtc->plane;
2120         unsigned long Start, Offset;
2121         u32 dspcntr;
2122         u32 reg;
2123
2124         switch (plane) {
2125         case 0:
2126         case 1:
2127         case 2:
2128                 break;
2129         default:
2130                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2131                 return -EINVAL;
2132         }
2133
2134         intel_fb = to_intel_framebuffer(fb);
2135         obj = intel_fb->obj;
2136
2137         reg = DSPCNTR(plane);
2138         dspcntr = I915_READ(reg);
2139         /* Mask out pixel format bits in case we change it */
2140         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2141         switch (fb->bits_per_pixel) {
2142         case 8:
2143                 dspcntr |= DISPPLANE_8BPP;
2144                 break;
2145         case 16:
2146                 if (fb->depth != 16)
2147                         return -EINVAL;
2148
2149                 dspcntr |= DISPPLANE_16BPP;
2150                 break;
2151         case 24:
2152         case 32:
2153                 if (fb->depth == 24)
2154                         dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2155                 else if (fb->depth == 30)
2156                         dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
2157                 else
2158                         return -EINVAL;
2159                 break;
2160         default:
2161                 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
2162                 return -EINVAL;
2163         }
2164
2165         if (obj->tiling_mode != I915_TILING_NONE)
2166                 dspcntr |= DISPPLANE_TILED;
2167         else
2168                 dspcntr &= ~DISPPLANE_TILED;
2169
2170         /* must disable */
2171         dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2172
2173         I915_WRITE(reg, dspcntr);
2174
2175         Start = obj->gtt_offset;
2176         Offset = y * fb->pitch + x * (fb->bits_per_pixel / 8);
2177
2178         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2179                       Start, Offset, x, y, fb->pitch);
2180         I915_WRITE(DSPSTRIDE(plane), fb->pitch);
2181         I915_WRITE(DSPSURF(plane), Start);
2182         I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2183         I915_WRITE(DSPADDR(plane), Offset);
2184         POSTING_READ(reg);
2185
2186         return 0;
2187 }
2188
2189 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2190 static int
2191 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2192                            int x, int y, enum mode_set_atomic state)
2193 {
2194         struct drm_device *dev = crtc->dev;
2195         struct drm_i915_private *dev_priv = dev->dev_private;
2196         int ret;
2197
2198         ret = dev_priv->display.update_plane(crtc, fb, x, y);
2199         if (ret)
2200                 return ret;
2201
2202         intel_update_fbc(dev);
2203         intel_increase_pllclock(crtc);
2204
2205         return 0;
2206 }
2207
2208 static int
2209 intel_finish_fb(struct drm_framebuffer *old_fb)
2210 {
2211         struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2212         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2213         bool was_interruptible = dev_priv->mm.interruptible;
2214         int ret;
2215
2216         wait_event(dev_priv->pending_flip_queue,
2217                    atomic_read(&dev_priv->mm.wedged) ||
2218                    atomic_read(&obj->pending_flip) == 0);
2219
2220         /* Big Hammer, we also need to ensure that any pending
2221          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2222          * current scanout is retired before unpinning the old
2223          * framebuffer.
2224          *
2225          * This should only fail upon a hung GPU, in which case we
2226          * can safely continue.
2227          */
2228         dev_priv->mm.interruptible = false;
2229         ret = i915_gem_object_finish_gpu(obj);
2230         dev_priv->mm.interruptible = was_interruptible;
2231
2232         return ret;
2233 }
2234
2235 static int
2236 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2237                     struct drm_framebuffer *old_fb)
2238 {
2239         struct drm_device *dev = crtc->dev;
2240         struct drm_i915_master_private *master_priv;
2241         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2242         int ret;
2243
2244         /* no fb bound */
2245         if (!crtc->fb) {
2246                 DRM_ERROR("No FB bound\n");
2247                 return 0;
2248         }
2249
2250         switch (intel_crtc->plane) {
2251         case 0:
2252         case 1:
2253                 break;
2254         case 2:
2255                 if (IS_IVYBRIDGE(dev))
2256                         break;
2257                 /* fall through otherwise */
2258         default:
2259                 DRM_ERROR("no plane for crtc\n");
2260                 return -EINVAL;
2261         }
2262
2263         mutex_lock(&dev->struct_mutex);
2264         ret = intel_pin_and_fence_fb_obj(dev,
2265                                          to_intel_framebuffer(crtc->fb)->obj,
2266                                          NULL);
2267         if (ret != 0) {
2268                 mutex_unlock(&dev->struct_mutex);
2269                 DRM_ERROR("pin & fence failed\n");
2270                 return ret;
2271         }
2272
2273         if (old_fb)
2274                 intel_finish_fb(old_fb);
2275
2276         ret = intel_pipe_set_base_atomic(crtc, crtc->fb, x, y,
2277                                          LEAVE_ATOMIC_MODE_SET);
2278         if (ret) {
2279                 i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
2280                 mutex_unlock(&dev->struct_mutex);
2281                 DRM_ERROR("failed to update base address\n");
2282                 return ret;
2283         }
2284
2285         if (old_fb) {
2286                 intel_wait_for_vblank(dev, intel_crtc->pipe);
2287                 i915_gem_object_unpin(to_intel_framebuffer(old_fb)->obj);
2288         }
2289
2290         mutex_unlock(&dev->struct_mutex);
2291
2292         if (!dev->primary->master)
2293                 return 0;
2294
2295         master_priv = dev->primary->master->driver_priv;
2296         if (!master_priv->sarea_priv)
2297                 return 0;
2298
2299         if (intel_crtc->pipe) {
2300                 master_priv->sarea_priv->pipeB_x = x;
2301                 master_priv->sarea_priv->pipeB_y = y;
2302         } else {
2303                 master_priv->sarea_priv->pipeA_x = x;
2304                 master_priv->sarea_priv->pipeA_y = y;
2305         }
2306
2307         return 0;
2308 }
2309
2310 static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
2311 {
2312         struct drm_device *dev = crtc->dev;
2313         struct drm_i915_private *dev_priv = dev->dev_private;
2314         u32 dpa_ctl;
2315
2316         DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
2317         dpa_ctl = I915_READ(DP_A);
2318         dpa_ctl &= ~DP_PLL_FREQ_MASK;
2319
2320         if (clock < 200000) {
2321                 u32 temp;
2322                 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2323                 /* workaround for 160Mhz:
2324                    1) program 0x4600c bits 15:0 = 0x8124
2325                    2) program 0x46010 bit 0 = 1
2326                    3) program 0x46034 bit 24 = 1
2327                    4) program 0x64000 bit 14 = 1
2328                    */
2329                 temp = I915_READ(0x4600c);
2330                 temp &= 0xffff0000;
2331                 I915_WRITE(0x4600c, temp | 0x8124);
2332
2333                 temp = I915_READ(0x46010);
2334                 I915_WRITE(0x46010, temp | 1);
2335
2336                 temp = I915_READ(0x46034);
2337                 I915_WRITE(0x46034, temp | (1 << 24));
2338         } else {
2339                 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2340         }
2341         I915_WRITE(DP_A, dpa_ctl);
2342
2343         POSTING_READ(DP_A);
2344         udelay(500);
2345 }
2346
2347 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2348 {
2349         struct drm_device *dev = crtc->dev;
2350         struct drm_i915_private *dev_priv = dev->dev_private;
2351         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2352         int pipe = intel_crtc->pipe;
2353         u32 reg, temp;
2354
2355         /* enable normal train */
2356         reg = FDI_TX_CTL(pipe);
2357         temp = I915_READ(reg);
2358         if (IS_IVYBRIDGE(dev)) {
2359                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2360                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2361         } else {
2362                 temp &= ~FDI_LINK_TRAIN_NONE;
2363                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2364         }
2365         I915_WRITE(reg, temp);
2366
2367         reg = FDI_RX_CTL(pipe);
2368         temp = I915_READ(reg);
2369         if (HAS_PCH_CPT(dev)) {
2370                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2371                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2372         } else {
2373                 temp &= ~FDI_LINK_TRAIN_NONE;
2374                 temp |= FDI_LINK_TRAIN_NONE;
2375         }
2376         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2377
2378         /* wait one idle pattern time */
2379         POSTING_READ(reg);
2380         udelay(1000);
2381
2382         /* IVB wants error correction enabled */
2383         if (IS_IVYBRIDGE(dev))
2384                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2385                            FDI_FE_ERRC_ENABLE);
2386 }
2387
2388 /* The FDI link training functions for ILK/Ibexpeak. */
2389 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2390 {
2391         struct drm_device *dev = crtc->dev;
2392         struct drm_i915_private *dev_priv = dev->dev_private;
2393         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2394         int pipe = intel_crtc->pipe;
2395         int plane = intel_crtc->plane;
2396         u32 reg, temp, tries;
2397
2398         /* FDI needs bits from pipe & plane first */
2399         assert_pipe_enabled(dev_priv, pipe);
2400         assert_plane_enabled(dev_priv, plane);
2401
2402         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2403            for train result */
2404         reg = FDI_RX_IMR(pipe);
2405         temp = I915_READ(reg);
2406         temp &= ~FDI_RX_SYMBOL_LOCK;
2407         temp &= ~FDI_RX_BIT_LOCK;
2408         I915_WRITE(reg, temp);
2409         I915_READ(reg);
2410         udelay(150);
2411
2412         /* enable CPU FDI TX and PCH FDI RX */
2413         reg = FDI_TX_CTL(pipe);
2414         temp = I915_READ(reg);
2415         temp &= ~(7 << 19);
2416         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2417         temp &= ~FDI_LINK_TRAIN_NONE;
2418         temp |= FDI_LINK_TRAIN_PATTERN_1;
2419         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2420
2421         reg = FDI_RX_CTL(pipe);
2422         temp = I915_READ(reg);
2423         temp &= ~FDI_LINK_TRAIN_NONE;
2424         temp |= FDI_LINK_TRAIN_PATTERN_1;
2425         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2426
2427         POSTING_READ(reg);
2428         udelay(150);
2429
2430         /* Ironlake workaround, enable clock pointer after FDI enable*/
2431         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2432         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2433                    FDI_RX_PHASE_SYNC_POINTER_EN);
2434
2435         reg = FDI_RX_IIR(pipe);
2436         for (tries = 0; tries < 5; tries++) {
2437                 temp = I915_READ(reg);
2438                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2439
2440                 if ((temp & FDI_RX_BIT_LOCK)) {
2441                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2442                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2443                         break;
2444                 }
2445         }
2446         if (tries == 5)
2447                 DRM_ERROR("FDI train 1 fail!\n");
2448
2449         /* Train 2 */
2450         reg = FDI_TX_CTL(pipe);
2451         temp = I915_READ(reg);
2452         temp &= ~FDI_LINK_TRAIN_NONE;
2453         temp |= FDI_LINK_TRAIN_PATTERN_2;
2454         I915_WRITE(reg, temp);
2455
2456         reg = FDI_RX_CTL(pipe);
2457         temp = I915_READ(reg);
2458         temp &= ~FDI_LINK_TRAIN_NONE;
2459         temp |= FDI_LINK_TRAIN_PATTERN_2;
2460         I915_WRITE(reg, temp);
2461
2462         POSTING_READ(reg);
2463         udelay(150);
2464
2465         reg = FDI_RX_IIR(pipe);
2466         for (tries = 0; tries < 5; tries++) {
2467                 temp = I915_READ(reg);
2468                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2469
2470                 if (temp & FDI_RX_SYMBOL_LOCK) {
2471                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2472                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2473                         break;
2474                 }
2475         }
2476         if (tries == 5)
2477                 DRM_ERROR("FDI train 2 fail!\n");
2478
2479         DRM_DEBUG_KMS("FDI train done\n");
2480
2481 }
2482
2483 static const int snb_b_fdi_train_param[] = {
2484         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2485         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2486         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2487         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2488 };
2489
2490 /* The FDI link training functions for SNB/Cougarpoint. */
2491 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2492 {
2493         struct drm_device *dev = crtc->dev;
2494         struct drm_i915_private *dev_priv = dev->dev_private;
2495         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2496         int pipe = intel_crtc->pipe;
2497         u32 reg, temp, i;
2498
2499         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2500            for train result */
2501         reg = FDI_RX_IMR(pipe);
2502         temp = I915_READ(reg);
2503         temp &= ~FDI_RX_SYMBOL_LOCK;
2504         temp &= ~FDI_RX_BIT_LOCK;
2505         I915_WRITE(reg, temp);
2506
2507         POSTING_READ(reg);
2508         udelay(150);
2509
2510         /* enable CPU FDI TX and PCH FDI RX */
2511         reg = FDI_TX_CTL(pipe);
2512         temp = I915_READ(reg);
2513         temp &= ~(7 << 19);
2514         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2515         temp &= ~FDI_LINK_TRAIN_NONE;
2516         temp |= FDI_LINK_TRAIN_PATTERN_1;
2517         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2518         /* SNB-B */
2519         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2520         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2521
2522         reg = FDI_RX_CTL(pipe);
2523         temp = I915_READ(reg);
2524         if (HAS_PCH_CPT(dev)) {
2525                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2526                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2527         } else {
2528                 temp &= ~FDI_LINK_TRAIN_NONE;
2529                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2530         }
2531         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2532
2533         POSTING_READ(reg);
2534         udelay(150);
2535
2536         for (i = 0; i < 4; i++) {
2537                 reg = FDI_TX_CTL(pipe);
2538                 temp = I915_READ(reg);
2539                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2540                 temp |= snb_b_fdi_train_param[i];
2541                 I915_WRITE(reg, temp);
2542
2543                 POSTING_READ(reg);
2544                 udelay(500);
2545
2546                 reg = FDI_RX_IIR(pipe);
2547                 temp = I915_READ(reg);
2548                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2549
2550                 if (temp & FDI_RX_BIT_LOCK) {
2551                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2552                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2553                         break;
2554                 }
2555         }
2556         if (i == 4)
2557                 DRM_ERROR("FDI train 1 fail!\n");
2558
2559         /* Train 2 */
2560         reg = FDI_TX_CTL(pipe);
2561         temp = I915_READ(reg);
2562         temp &= ~FDI_LINK_TRAIN_NONE;
2563         temp |= FDI_LINK_TRAIN_PATTERN_2;
2564         if (IS_GEN6(dev)) {
2565                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2566                 /* SNB-B */
2567                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2568         }
2569         I915_WRITE(reg, temp);
2570
2571         reg = FDI_RX_CTL(pipe);
2572         temp = I915_READ(reg);
2573         if (HAS_PCH_CPT(dev)) {
2574                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2575                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2576         } else {
2577                 temp &= ~FDI_LINK_TRAIN_NONE;
2578                 temp |= FDI_LINK_TRAIN_PATTERN_2;
2579         }
2580         I915_WRITE(reg, temp);
2581
2582         POSTING_READ(reg);
2583         udelay(150);
2584
2585         for (i = 0; i < 4; i++) {
2586                 reg = FDI_TX_CTL(pipe);
2587                 temp = I915_READ(reg);
2588                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2589                 temp |= snb_b_fdi_train_param[i];
2590                 I915_WRITE(reg, temp);
2591
2592                 POSTING_READ(reg);
2593                 udelay(500);
2594
2595                 reg = FDI_RX_IIR(pipe);
2596                 temp = I915_READ(reg);
2597                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2598
2599                 if (temp & FDI_RX_SYMBOL_LOCK) {
2600                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2601                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2602                         break;
2603                 }
2604         }
2605         if (i == 4)
2606                 DRM_ERROR("FDI train 2 fail!\n");
2607
2608         DRM_DEBUG_KMS("FDI train done.\n");
2609 }
2610
2611 /* Manual link training for Ivy Bridge A0 parts */
2612 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2613 {
2614         struct drm_device *dev = crtc->dev;
2615         struct drm_i915_private *dev_priv = dev->dev_private;
2616         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2617         int pipe = intel_crtc->pipe;
2618         u32 reg, temp, i;
2619
2620         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2621            for train result */
2622         reg = FDI_RX_IMR(pipe);
2623         temp = I915_READ(reg);
2624         temp &= ~FDI_RX_SYMBOL_LOCK;
2625         temp &= ~FDI_RX_BIT_LOCK;
2626         I915_WRITE(reg, temp);
2627
2628         POSTING_READ(reg);
2629         udelay(150);
2630
2631         /* enable CPU FDI TX and PCH FDI RX */
2632         reg = FDI_TX_CTL(pipe);
2633         temp = I915_READ(reg);
2634         temp &= ~(7 << 19);
2635         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2636         temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2637         temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2638         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2639         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2640         temp |= FDI_COMPOSITE_SYNC;
2641         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2642
2643         reg = FDI_RX_CTL(pipe);
2644         temp = I915_READ(reg);
2645         temp &= ~FDI_LINK_TRAIN_AUTO;
2646         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2647         temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2648         temp |= FDI_COMPOSITE_SYNC;
2649         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2650
2651         POSTING_READ(reg);
2652         udelay(150);
2653
2654         for (i = 0; i < 4; i++) {
2655                 reg = FDI_TX_CTL(pipe);
2656                 temp = I915_READ(reg);
2657                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2658                 temp |= snb_b_fdi_train_param[i];
2659                 I915_WRITE(reg, temp);
2660
2661                 POSTING_READ(reg);
2662                 udelay(500);
2663
2664                 reg = FDI_RX_IIR(pipe);
2665                 temp = I915_READ(reg);
2666                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2667
2668                 if (temp & FDI_RX_BIT_LOCK ||
2669                     (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2670                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2671                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2672                         break;
2673                 }
2674         }
2675         if (i == 4)
2676                 DRM_ERROR("FDI train 1 fail!\n");
2677
2678         /* Train 2 */
2679         reg = FDI_TX_CTL(pipe);
2680         temp = I915_READ(reg);
2681         temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2682         temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2683         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2684         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2685         I915_WRITE(reg, temp);
2686
2687         reg = FDI_RX_CTL(pipe);
2688         temp = I915_READ(reg);
2689         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2690         temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2691         I915_WRITE(reg, temp);
2692
2693         POSTING_READ(reg);
2694         udelay(150);
2695
2696         for (i = 0; i < 4; i++) {
2697                 reg = FDI_TX_CTL(pipe);
2698                 temp = I915_READ(reg);
2699                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2700                 temp |= snb_b_fdi_train_param[i];
2701                 I915_WRITE(reg, temp);
2702
2703                 POSTING_READ(reg);
2704                 udelay(500);
2705
2706                 reg = FDI_RX_IIR(pipe);
2707                 temp = I915_READ(reg);
2708                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2709
2710                 if (temp & FDI_RX_SYMBOL_LOCK) {
2711                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2712                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2713                         break;
2714                 }
2715         }
2716         if (i == 4)
2717                 DRM_ERROR("FDI train 2 fail!\n");
2718
2719         DRM_DEBUG_KMS("FDI train done.\n");
2720 }
2721
2722 static void ironlake_fdi_pll_enable(struct drm_crtc *crtc)
2723 {
2724         struct drm_device *dev = crtc->dev;
2725         struct drm_i915_private *dev_priv = dev->dev_private;
2726         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2727         int pipe = intel_crtc->pipe;
2728         u32 reg, temp;
2729
2730         /* Write the TU size bits so error detection works */
2731         I915_WRITE(FDI_RX_TUSIZE1(pipe),
2732                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
2733
2734         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2735         reg = FDI_RX_CTL(pipe);
2736         temp = I915_READ(reg);
2737         temp &= ~((0x7 << 19) | (0x7 << 16));
2738         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2739         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2740         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2741
2742         POSTING_READ(reg);
2743         udelay(200);
2744
2745         /* Switch from Rawclk to PCDclk */
2746         temp = I915_READ(reg);
2747         I915_WRITE(reg, temp | FDI_PCDCLK);
2748
2749         POSTING_READ(reg);
2750         udelay(200);
2751
2752         /* Enable CPU FDI TX PLL, always on for Ironlake */
2753         reg = FDI_TX_CTL(pipe);
2754         temp = I915_READ(reg);
2755         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2756                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2757
2758                 POSTING_READ(reg);
2759                 udelay(100);
2760         }
2761 }
2762
2763 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2764 {
2765         struct drm_device *dev = crtc->dev;
2766         struct drm_i915_private *dev_priv = dev->dev_private;
2767         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2768         int pipe = intel_crtc->pipe;
2769         u32 reg, temp;
2770
2771         /* disable CPU FDI tx and PCH FDI rx */
2772         reg = FDI_TX_CTL(pipe);
2773         temp = I915_READ(reg);
2774         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2775         POSTING_READ(reg);
2776
2777         reg = FDI_RX_CTL(pipe);
2778         temp = I915_READ(reg);
2779         temp &= ~(0x7 << 16);
2780         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2781         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2782
2783         POSTING_READ(reg);
2784         udelay(100);
2785
2786         /* Ironlake workaround, disable clock pointer after downing FDI */
2787         if (HAS_PCH_IBX(dev)) {
2788                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2789                 I915_WRITE(FDI_RX_CHICKEN(pipe),
2790                            I915_READ(FDI_RX_CHICKEN(pipe) &
2791                                      ~FDI_RX_PHASE_SYNC_POINTER_EN));
2792         }
2793
2794         /* still set train pattern 1 */
2795         reg = FDI_TX_CTL(pipe);
2796         temp = I915_READ(reg);
2797         temp &= ~FDI_LINK_TRAIN_NONE;
2798         temp |= FDI_LINK_TRAIN_PATTERN_1;
2799         I915_WRITE(reg, temp);
2800
2801         reg = FDI_RX_CTL(pipe);
2802         temp = I915_READ(reg);
2803         if (HAS_PCH_CPT(dev)) {
2804                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2805                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2806         } else {
2807                 temp &= ~FDI_LINK_TRAIN_NONE;
2808                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2809         }
2810         /* BPC in FDI rx is consistent with that in PIPECONF */
2811         temp &= ~(0x07 << 16);
2812         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2813         I915_WRITE(reg, temp);
2814
2815         POSTING_READ(reg);
2816         udelay(100);
2817 }
2818
2819 /*
2820  * When we disable a pipe, we need to clear any pending scanline wait events
2821  * to avoid hanging the ring, which we assume we are waiting on.
2822  */
2823 static void intel_clear_scanline_wait(struct drm_device *dev)
2824 {
2825         struct drm_i915_private *dev_priv = dev->dev_private;
2826         struct intel_ring_buffer *ring;
2827         u32 tmp;
2828
2829         if (IS_GEN2(dev))
2830                 /* Can't break the hang on i8xx */
2831                 return;
2832
2833         ring = LP_RING(dev_priv);
2834         tmp = I915_READ_CTL(ring);
2835         if (tmp & RING_WAIT)
2836                 I915_WRITE_CTL(ring, tmp);
2837 }
2838
2839 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2840 {
2841         struct drm_device *dev = crtc->dev;
2842         struct drm_i915_private *dev_priv = dev->dev_private;
2843         unsigned long flags;
2844         bool pending;
2845
2846         if (atomic_read(&dev_priv->mm.wedged))
2847                 return false;
2848
2849         spin_lock_irqsave(&dev->event_lock, flags);
2850         pending = to_intel_crtc(crtc)->unpin_work != NULL;
2851         spin_unlock_irqrestore(&dev->event_lock, flags);
2852
2853         return pending;
2854 }
2855
2856 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2857 {
2858         struct drm_device *dev = crtc->dev;
2859         struct drm_i915_private *dev_priv = dev->dev_private;
2860
2861         if (crtc->fb == NULL)
2862                 return;
2863
2864         wait_event(dev_priv->pending_flip_queue,
2865                    !intel_crtc_has_pending_flip(crtc));
2866
2867         mutex_lock(&dev->struct_mutex);
2868         intel_finish_fb(crtc->fb);
2869         mutex_unlock(&dev->struct_mutex);
2870 }
2871
2872 static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
2873 {
2874         struct drm_device *dev = crtc->dev;
2875         struct drm_mode_config *mode_config = &dev->mode_config;
2876         struct intel_encoder *encoder;
2877
2878         /*
2879          * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2880          * must be driven by its own crtc; no sharing is possible.
2881          */
2882         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
2883                 if (encoder->base.crtc != crtc)
2884                         continue;
2885
2886                 switch (encoder->type) {
2887                 case INTEL_OUTPUT_EDP:
2888                         if (!intel_encoder_is_pch_edp(&encoder->base))
2889                                 return false;
2890                         continue;
2891                 }
2892         }
2893
2894         return true;
2895 }
2896
2897 /*
2898  * Enable PCH resources required for PCH ports:
2899  *   - PCH PLLs
2900  *   - FDI training & RX/TX
2901  *   - update transcoder timings
2902  *   - DP transcoding bits
2903  *   - transcoder
2904  */
2905 static void ironlake_pch_enable(struct drm_crtc *crtc)
2906 {
2907         struct drm_device *dev = crtc->dev;
2908         struct drm_i915_private *dev_priv = dev->dev_private;
2909         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2910         int pipe = intel_crtc->pipe;
2911         u32 reg, temp, transc_sel;
2912
2913         /* For PCH output, training FDI link */
2914         dev_priv->display.fdi_link_train(crtc);
2915
2916         intel_enable_pch_pll(dev_priv, pipe);
2917
2918         if (HAS_PCH_CPT(dev)) {
2919                 transc_sel = intel_crtc->use_pll_a ? TRANSC_DPLLA_SEL :
2920                         TRANSC_DPLLB_SEL;
2921
2922                 /* Be sure PCH DPLL SEL is set */
2923                 temp = I915_READ(PCH_DPLL_SEL);
2924                 if (pipe == 0) {
2925                         temp &= ~(TRANSA_DPLLB_SEL);
2926                         temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
2927                 } else if (pipe == 1) {
2928                         temp &= ~(TRANSB_DPLLB_SEL);
2929                         temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2930                 } else if (pipe == 2) {
2931                         temp &= ~(TRANSC_DPLLB_SEL);
2932                         temp |= (TRANSC_DPLL_ENABLE | transc_sel);
2933                 }
2934                 I915_WRITE(PCH_DPLL_SEL, temp);
2935         }
2936
2937         /* set transcoder timing, panel must allow it */
2938         assert_panel_unlocked(dev_priv, pipe);
2939         I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
2940         I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
2941         I915_WRITE(TRANS_HSYNC(pipe),  I915_READ(HSYNC(pipe)));
2942
2943         I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
2944         I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
2945         I915_WRITE(TRANS_VSYNC(pipe),  I915_READ(VSYNC(pipe)));
2946
2947         intel_fdi_normal_train(crtc);
2948
2949         /* For PCH DP, enable TRANS_DP_CTL */
2950         if (HAS_PCH_CPT(dev) &&
2951             (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
2952              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2953                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
2954                 reg = TRANS_DP_CTL(pipe);
2955                 temp = I915_READ(reg);
2956                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
2957                           TRANS_DP_SYNC_MASK |
2958                           TRANS_DP_BPC_MASK);
2959                 temp |= (TRANS_DP_OUTPUT_ENABLE |
2960                          TRANS_DP_ENH_FRAMING);
2961                 temp |= bpc << 9; /* same format but at 11:9 */
2962
2963                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
2964                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
2965                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
2966                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
2967
2968                 switch (intel_trans_dp_port_sel(crtc)) {
2969                 case PCH_DP_B:
2970                         temp |= TRANS_DP_PORT_SEL_B;
2971                         break;
2972                 case PCH_DP_C:
2973                         temp |= TRANS_DP_PORT_SEL_C;
2974                         break;
2975                 case PCH_DP_D:
2976                         temp |= TRANS_DP_PORT_SEL_D;
2977                         break;
2978                 default:
2979                         DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
2980                         temp |= TRANS_DP_PORT_SEL_B;
2981                         break;
2982                 }
2983
2984                 I915_WRITE(reg, temp);
2985         }
2986
2987         intel_enable_transcoder(dev_priv, pipe);
2988 }
2989
2990 void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
2991 {
2992         struct drm_i915_private *dev_priv = dev->dev_private;
2993         int dslreg = PIPEDSL(pipe), tc2reg = TRANS_CHICKEN2(pipe);
2994         u32 temp;
2995
2996         temp = I915_READ(dslreg);
2997         udelay(500);
2998         if (wait_for(I915_READ(dslreg) != temp, 5)) {
2999                 /* Without this, mode sets may fail silently on FDI */
3000                 I915_WRITE(tc2reg, TRANS_AUTOTRAIN_GEN_STALL_DIS);
3001                 udelay(250);
3002                 I915_WRITE(tc2reg, 0);
3003                 if (wait_for(I915_READ(dslreg) != temp, 5))
3004                         DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
3005         }
3006 }
3007
3008 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3009 {
3010         struct drm_device *dev = crtc->dev;
3011         struct drm_i915_private *dev_priv = dev->dev_private;
3012         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3013         int pipe = intel_crtc->pipe;
3014         int plane = intel_crtc->plane;
3015         u32 temp;
3016         bool is_pch_port;
3017
3018         if (intel_crtc->active)
3019                 return;
3020
3021         intel_crtc->active = true;
3022         intel_update_watermarks(dev);
3023
3024         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3025                 temp = I915_READ(PCH_LVDS);
3026                 if ((temp & LVDS_PORT_EN) == 0)
3027                         I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3028         }
3029
3030         is_pch_port = intel_crtc_driving_pch(crtc);
3031
3032         if (is_pch_port)
3033                 ironlake_fdi_pll_enable(crtc);
3034         else
3035                 ironlake_fdi_disable(crtc);
3036
3037         /* Enable panel fitting for LVDS */
3038         if (dev_priv->pch_pf_size &&
3039             (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
3040                 /* Force use of hard-coded filter coefficients
3041                  * as some pre-programmed values are broken,
3042                  * e.g. x201.
3043                  */
3044                 if (IS_IVYBRIDGE(dev))
3045                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3046                                                  PF_PIPE_SEL_IVB(pipe));
3047                 else
3048                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3049                 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3050                 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3051         }
3052
3053         /*
3054          * On ILK+ LUT must be loaded before the pipe is running but with
3055          * clocks enabled
3056          */
3057         intel_crtc_load_lut(crtc);
3058
3059         intel_enable_pipe(dev_priv, pipe, is_pch_port);
3060         intel_enable_plane(dev_priv, plane, pipe);
3061
3062         if (is_pch_port)
3063                 ironlake_pch_enable(crtc);
3064
3065         mutex_lock(&dev->struct_mutex);
3066         intel_update_fbc(dev);
3067         mutex_unlock(&dev->struct_mutex);
3068
3069         intel_crtc_update_cursor(crtc, true);
3070 }
3071
3072 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3073 {
3074         struct drm_device *dev = crtc->dev;
3075         struct drm_i915_private *dev_priv = dev->dev_private;
3076         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3077         int pipe = intel_crtc->pipe;
3078         int plane = intel_crtc->plane;
3079         u32 reg, temp;
3080
3081         if (!intel_crtc->active)
3082                 return;
3083
3084         intel_crtc_wait_for_pending_flips(crtc);
3085         drm_vblank_off(dev, pipe);
3086         intel_crtc_update_cursor(crtc, false);
3087
3088         intel_disable_plane(dev_priv, plane, pipe);
3089
3090         if (dev_priv->cfb_plane == plane)
3091                 intel_disable_fbc(dev);
3092
3093         intel_disable_pipe(dev_priv, pipe);
3094
3095         /* Disable PF */
3096         I915_WRITE(PF_CTL(pipe), 0);
3097         I915_WRITE(PF_WIN_SZ(pipe), 0);
3098
3099         ironlake_fdi_disable(crtc);
3100
3101         /* This is a horrible layering violation; we should be doing this in
3102          * the connector/encoder ->prepare instead, but we don't always have
3103          * enough information there about the config to know whether it will
3104          * actually be necessary or just cause undesired flicker.
3105          */
3106         intel_disable_pch_ports(dev_priv, pipe);
3107
3108         intel_disable_transcoder(dev_priv, pipe);
3109
3110         if (HAS_PCH_CPT(dev)) {
3111                 /* disable TRANS_DP_CTL */
3112                 reg = TRANS_DP_CTL(pipe);
3113                 temp = I915_READ(reg);
3114                 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
3115                 temp |= TRANS_DP_PORT_SEL_NONE;
3116                 I915_WRITE(reg, temp);
3117
3118                 /* disable DPLL_SEL */
3119                 temp = I915_READ(PCH_DPLL_SEL);
3120                 switch (pipe) {
3121                 case 0:
3122                         temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
3123                         break;
3124                 case 1:
3125                         temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3126                         break;
3127                 case 2:
3128                         /* C shares PLL A or B */
3129                         temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
3130                         break;
3131                 default:
3132                         BUG(); /* wtf */
3133                 }
3134                 I915_WRITE(PCH_DPLL_SEL, temp);
3135         }
3136
3137         /* disable PCH DPLL */
3138         if (!intel_crtc->no_pll)
3139                 intel_disable_pch_pll(dev_priv, pipe);
3140
3141         /* Switch from PCDclk to Rawclk */
3142         reg = FDI_RX_CTL(pipe);
3143         temp = I915_READ(reg);
3144         I915_WRITE(reg, temp & ~FDI_PCDCLK);
3145
3146         /* Disable CPU FDI TX PLL */
3147         reg = FDI_TX_CTL(pipe);
3148         temp = I915_READ(reg);
3149         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3150
3151         POSTING_READ(reg);
3152         udelay(100);
3153
3154         reg = FDI_RX_CTL(pipe);
3155         temp = I915_READ(reg);
3156         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3157
3158         /* Wait for the clocks to turn off. */
3159         POSTING_READ(reg);
3160         udelay(100);
3161
3162         intel_crtc->active = false;
3163         intel_update_watermarks(dev);
3164
3165         mutex_lock(&dev->struct_mutex);
3166         intel_update_fbc(dev);
3167         intel_clear_scanline_wait(dev);
3168         mutex_unlock(&dev->struct_mutex);
3169 }
3170
3171 static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
3172 {
3173         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3174         int pipe = intel_crtc->pipe;
3175         int plane = intel_crtc->plane;
3176
3177         /* XXX: When our outputs are all unaware of DPMS modes other than off
3178          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3179          */
3180         switch (mode) {
3181         case DRM_MODE_DPMS_ON:
3182         case DRM_MODE_DPMS_STANDBY:
3183         case DRM_MODE_DPMS_SUSPEND:
3184                 DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane);
3185                 ironlake_crtc_enable(crtc);
3186                 break;
3187
3188         case DRM_MODE_DPMS_OFF:
3189                 DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane);
3190                 ironlake_crtc_disable(crtc);
3191                 break;
3192         }
3193 }
3194
3195 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3196 {
3197         if (!enable && intel_crtc->overlay) {
3198                 struct drm_device *dev = intel_crtc->base.dev;
3199                 struct drm_i915_private *dev_priv = dev->dev_private;
3200
3201                 mutex_lock(&dev->struct_mutex);
3202                 dev_priv->mm.interruptible = false;
3203                 (void) intel_overlay_switch_off(intel_crtc->overlay);
3204                 dev_priv->mm.interruptible = true;
3205                 mutex_unlock(&dev->struct_mutex);
3206         }
3207
3208         /* Let userspace switch the overlay on again. In most cases userspace
3209          * has to recompute where to put it anyway.
3210          */
3211 }
3212
3213 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3214 {
3215         struct drm_device *dev = crtc->dev;
3216         struct drm_i915_private *dev_priv = dev->dev_private;
3217         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3218         int pipe = intel_crtc->pipe;
3219         int plane = intel_crtc->plane;
3220
3221         if (intel_crtc->active)
3222                 return;
3223
3224         intel_crtc->active = true;
3225         intel_update_watermarks(dev);
3226
3227         intel_enable_pll(dev_priv, pipe);
3228         intel_enable_pipe(dev_priv, pipe, false);
3229         intel_enable_plane(dev_priv, plane, pipe);
3230
3231         intel_crtc_load_lut(crtc);
3232         intel_update_fbc(dev);
3233
3234         /* Give the overlay scaler a chance to enable if it's on this pipe */
3235         intel_crtc_dpms_overlay(intel_crtc, true);
3236         intel_crtc_update_cursor(crtc, true);
3237 }
3238
3239 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3240 {
3241         struct drm_device *dev = crtc->dev;
3242         struct drm_i915_private *dev_priv = dev->dev_private;
3243         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3244         int pipe = intel_crtc->pipe;
3245         int plane = intel_crtc->plane;
3246         u32 pctl;
3247
3248         if (!intel_crtc->active)
3249                 return;
3250
3251         /* Give the overlay scaler a chance to disable if it's on this pipe */
3252         intel_crtc_wait_for_pending_flips(crtc);
3253         drm_vblank_off(dev, pipe);
3254         intel_crtc_dpms_overlay(intel_crtc, false);
3255         intel_crtc_update_cursor(crtc, false);
3256
3257         if (dev_priv->cfb_plane == plane)
3258                 intel_disable_fbc(dev);
3259
3260         intel_disable_plane(dev_priv, plane, pipe);
3261         intel_disable_pipe(dev_priv, pipe);
3262
3263         /* Disable pannel fitter if it is on this pipe. */
3264         pctl = I915_READ(PFIT_CONTROL);
3265         if ((pctl & PFIT_ENABLE) &&
3266             ((pctl & PFIT_PIPE_MASK) >> PFIT_PIPE_SHIFT) == pipe)
3267                 I915_WRITE(PFIT_CONTROL, 0);
3268
3269         intel_disable_pll(dev_priv, pipe);
3270
3271         intel_crtc->active = false;
3272         intel_update_fbc(dev);
3273         intel_update_watermarks(dev);
3274         intel_clear_scanline_wait(dev);
3275 }
3276
3277 static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
3278 {
3279         /* XXX: When our outputs are all unaware of DPMS modes other than off
3280          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3281          */
3282         switch (mode) {
3283         case DRM_MODE_DPMS_ON:
3284         case DRM_MODE_DPMS_STANDBY:
3285         case DRM_MODE_DPMS_SUSPEND:
3286                 i9xx_crtc_enable(crtc);
3287                 break;
3288         case DRM_MODE_DPMS_OFF:
3289                 i9xx_crtc_disable(crtc);
3290                 break;
3291         }
3292 }
3293
3294 /**
3295  * Sets the power management mode of the pipe and plane.
3296  */
3297 static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
3298 {
3299         struct drm_device *dev = crtc->dev;
3300         struct drm_i915_private *dev_priv = dev->dev_private;
3301         struct drm_i915_master_private *master_priv;
3302         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3303         int pipe = intel_crtc->pipe;
3304         bool enabled;
3305
3306         if (intel_crtc->dpms_mode == mode)
3307                 return;
3308
3309         intel_crtc->dpms_mode = mode;
3310
3311         dev_priv->display.dpms(crtc, mode);
3312
3313         if (!dev->primary->master)
3314                 return;
3315
3316         master_priv = dev->primary->master->driver_priv;
3317         if (!master_priv->sarea_priv)
3318                 return;
3319
3320         enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
3321
3322         switch (pipe) {
3323         case 0:
3324                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3325                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3326                 break;
3327         case 1:
3328                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3329                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3330                 break;
3331         default:
3332                 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3333                 break;
3334         }
3335 }
3336
3337 static void intel_crtc_disable(struct drm_crtc *crtc)
3338 {
3339         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
3340         struct drm_device *dev = crtc->dev;
3341
3342         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
3343
3344         if (crtc->fb) {
3345                 mutex_lock(&dev->struct_mutex);
3346                 i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
3347                 mutex_unlock(&dev->struct_mutex);
3348         }
3349 }
3350
3351 /* Prepare for a mode set.
3352  *
3353  * Note we could be a lot smarter here.  We need to figure out which outputs
3354  * will be enabled, which disabled (in short, how the config will changes)
3355  * and perform the minimum necessary steps to accomplish that, e.g. updating
3356  * watermarks, FBC configuration, making sure PLLs are programmed correctly,
3357  * panel fitting is in the proper state, etc.
3358  */
3359 static void i9xx_crtc_prepare(struct drm_crtc *crtc)
3360 {
3361         i9xx_crtc_disable(crtc);
3362 }
3363
3364 static void i9xx_crtc_commit(struct drm_crtc *crtc)
3365 {
3366         i9xx_crtc_enable(crtc);
3367 }
3368
3369 static void ironlake_crtc_prepare(struct drm_crtc *crtc)
3370 {
3371         ironlake_crtc_disable(crtc);
3372 }
3373
3374 static void ironlake_crtc_commit(struct drm_crtc *crtc)
3375 {
3376         ironlake_crtc_enable(crtc);
3377 }
3378
3379 void intel_encoder_prepare(struct drm_encoder *encoder)
3380 {
3381         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3382         /* lvds has its own version of prepare see intel_lvds_prepare */
3383         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
3384 }
3385
3386 void intel_encoder_commit(struct drm_encoder *encoder)
3387 {
3388         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3389         struct drm_device *dev = encoder->dev;
3390         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3391         struct intel_crtc *intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
3392
3393         /* lvds has its own version of commit see intel_lvds_commit */
3394         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
3395
3396         if (HAS_PCH_CPT(dev))
3397                 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
3398 }
3399
3400 void intel_encoder_destroy(struct drm_encoder *encoder)
3401 {
3402         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3403
3404         drm_encoder_cleanup(encoder);
3405         kfree(intel_encoder);
3406 }
3407
3408 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
3409                                   struct drm_display_mode *mode,
3410                                   struct drm_display_mode *adjusted_mode)
3411 {
3412         struct drm_device *dev = crtc->dev;
3413
3414         if (HAS_PCH_SPLIT(dev)) {
3415                 /* FDI link clock is fixed at 2.7G */
3416                 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3417                         return false;
3418         }
3419
3420         /* XXX some encoders set the crtcinfo, others don't.
3421          * Obviously we need some form of conflict resolution here...
3422          */
3423         if (adjusted_mode->crtc_htotal == 0)
3424                 drm_mode_set_crtcinfo(adjusted_mode, 0);
3425
3426         return true;
3427 }
3428
3429 static int i945_get_display_clock_speed(struct drm_device *dev)
3430 {
3431         return 400000;
3432 }
3433
3434 static int i915_get_display_clock_speed(struct drm_device *dev)
3435 {
3436         return 333000;
3437 }
3438
3439 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3440 {
3441         return 200000;
3442 }
3443
3444 static int i915gm_get_display_clock_speed(struct drm_device *dev)
3445 {
3446         u16 gcfgc = 0;
3447
3448         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3449
3450         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
3451                 return 133000;
3452         else {
3453                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3454                 case GC_DISPLAY_CLOCK_333_MHZ:
3455                         return 333000;
3456                 default:
3457                 case GC_DISPLAY_CLOCK_190_200_MHZ:
3458                         return 190000;
3459                 }
3460         }
3461 }
3462
3463 static int i865_get_display_clock_speed(struct drm_device *dev)
3464 {
3465         return 266000;
3466 }
3467
3468 static int i855_get_display_clock_speed(struct drm_device *dev)
3469 {
3470         u16 hpllcc = 0;
3471         /* Assume that the hardware is in the high speed state.  This
3472          * should be the default.
3473          */
3474         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3475         case GC_CLOCK_133_200:
3476         case GC_CLOCK_100_200:
3477                 return 200000;
3478         case GC_CLOCK_166_250:
3479                 return 250000;
3480         case GC_CLOCK_100_133:
3481                 return 133000;
3482         }
3483
3484         /* Shouldn't happen */
3485         return 0;
3486 }
3487
3488 static int i830_get_display_clock_speed(struct drm_device *dev)
3489 {
3490         return 133000;
3491 }
3492
3493 struct fdi_m_n {
3494         u32        tu;
3495         u32        gmch_m;
3496         u32        gmch_n;
3497         u32        link_m;
3498         u32        link_n;
3499 };
3500
3501 static void
3502 fdi_reduce_ratio(u32 *num, u32 *den)
3503 {
3504         while (*num > 0xffffff || *den > 0xffffff) {
3505                 *num >>= 1;
3506                 *den >>= 1;
3507         }
3508 }
3509
3510 static void
3511 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
3512                      int link_clock, struct fdi_m_n *m_n)
3513 {
3514         m_n->tu = 64; /* default size */
3515
3516         /* BUG_ON(pixel_clock > INT_MAX / 36); */
3517         m_n->gmch_m = bits_per_pixel * pixel_clock;
3518         m_n->gmch_n = link_clock * nlanes * 8;
3519         fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
3520
3521         m_n->link_m = pixel_clock;
3522         m_n->link_n = link_clock;
3523         fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
3524 }
3525
3526
3527 struct intel_watermark_params {
3528         unsigned long fifo_size;
3529         unsigned long max_wm;
3530         unsigned long default_wm;
3531         unsigned long guard_size;
3532         unsigned long cacheline_size;
3533 };
3534
3535 /* Pineview has different values for various configs */
3536 static const struct intel_watermark_params pineview_display_wm = {
3537         PINEVIEW_DISPLAY_FIFO,
3538         PINEVIEW_MAX_WM,
3539         PINEVIEW_DFT_WM,
3540         PINEVIEW_GUARD_WM,
3541         PINEVIEW_FIFO_LINE_SIZE
3542 };
3543 static const struct intel_watermark_params pineview_display_hplloff_wm = {
3544         PINEVIEW_DISPLAY_FIFO,
3545         PINEVIEW_MAX_WM,
3546         PINEVIEW_DFT_HPLLOFF_WM,
3547         PINEVIEW_GUARD_WM,
3548         PINEVIEW_FIFO_LINE_SIZE
3549 };
3550 static const struct intel_watermark_params pineview_cursor_wm = {
3551         PINEVIEW_CURSOR_FIFO,
3552         PINEVIEW_CURSOR_MAX_WM,
3553         PINEVIEW_CURSOR_DFT_WM,
3554         PINEVIEW_CURSOR_GUARD_WM,
3555         PINEVIEW_FIFO_LINE_SIZE,
3556 };
3557 static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
3558         PINEVIEW_CURSOR_FIFO,
3559         PINEVIEW_CURSOR_MAX_WM,
3560         PINEVIEW_CURSOR_DFT_WM,
3561         PINEVIEW_CURSOR_GUARD_WM,
3562         PINEVIEW_FIFO_LINE_SIZE
3563 };
3564 static const struct intel_watermark_params g4x_wm_info = {
3565         G4X_FIFO_SIZE,
3566         G4X_MAX_WM,
3567         G4X_MAX_WM,
3568         2,
3569         G4X_FIFO_LINE_SIZE,
3570 };
3571 static const struct intel_watermark_params g4x_cursor_wm_info = {
3572         I965_CURSOR_FIFO,
3573         I965_CURSOR_MAX_WM,
3574         I965_CURSOR_DFT_WM,
3575         2,
3576         G4X_FIFO_LINE_SIZE,
3577 };
3578 static const struct intel_watermark_params i965_cursor_wm_info = {
3579         I965_CURSOR_FIFO,
3580         I965_CURSOR_MAX_WM,
3581         I965_CURSOR_DFT_WM,
3582         2,
3583         I915_FIFO_LINE_SIZE,
3584 };
3585 static const struct intel_watermark_params i945_wm_info = {
3586         I945_FIFO_SIZE,
3587         I915_MAX_WM,
3588         1,
3589         2,
3590         I915_FIFO_LINE_SIZE
3591 };
3592 static const struct intel_watermark_params i915_wm_info = {
3593         I915_FIFO_SIZE,
3594         I915_MAX_WM,
3595         1,
3596         2,
3597         I915_FIFO_LINE_SIZE
3598 };
3599 static const struct intel_watermark_params i855_wm_info = {
3600         I855GM_FIFO_SIZE,
3601         I915_MAX_WM,
3602         1,
3603         2,
3604         I830_FIFO_LINE_SIZE
3605 };
3606 static const struct intel_watermark_params i830_wm_info = {
3607         I830_FIFO_SIZE,
3608         I915_MAX_WM,
3609         1,
3610         2,
3611         I830_FIFO_LINE_SIZE
3612 };
3613
3614 static const struct intel_watermark_params ironlake_display_wm_info = {
3615         ILK_DISPLAY_FIFO,
3616         ILK_DISPLAY_MAXWM,
3617         ILK_DISPLAY_DFTWM,
3618         2,
3619         ILK_FIFO_LINE_SIZE
3620 };
3621 static const struct intel_watermark_params ironlake_cursor_wm_info = {
3622         ILK_CURSOR_FIFO,
3623         ILK_CURSOR_MAXWM,
3624         ILK_CURSOR_DFTWM,
3625         2,
3626         ILK_FIFO_LINE_SIZE
3627 };
3628 static const struct intel_watermark_params ironlake_display_srwm_info = {
3629         ILK_DISPLAY_SR_FIFO,
3630         ILK_DISPLAY_MAX_SRWM,
3631         ILK_DISPLAY_DFT_SRWM,
3632         2,
3633         ILK_FIFO_LINE_SIZE
3634 };
3635 static const struct intel_watermark_params ironlake_cursor_srwm_info = {
3636         ILK_CURSOR_SR_FIFO,
3637         ILK_CURSOR_MAX_SRWM,
3638         ILK_CURSOR_DFT_SRWM,
3639         2,
3640         ILK_FIFO_LINE_SIZE
3641 };
3642
3643 static const struct intel_watermark_params sandybridge_display_wm_info = {
3644         SNB_DISPLAY_FIFO,
3645         SNB_DISPLAY_MAXWM,
3646         SNB_DISPLAY_DFTWM,
3647         2,
3648         SNB_FIFO_LINE_SIZE
3649 };
3650 static const struct intel_watermark_params sandybridge_cursor_wm_info = {
3651         SNB_CURSOR_FIFO,
3652         SNB_CURSOR_MAXWM,
3653         SNB_CURSOR_DFTWM,
3654         2,
3655         SNB_FIFO_LINE_SIZE
3656 };
3657 static const struct intel_watermark_params sandybridge_display_srwm_info = {
3658         SNB_DISPLAY_SR_FIFO,
3659         SNB_DISPLAY_MAX_SRWM,
3660         SNB_DISPLAY_DFT_SRWM,
3661         2,
3662         SNB_FIFO_LINE_SIZE
3663 };
3664 static const struct intel_watermark_params sandybridge_cursor_srwm_info = {
3665         SNB_CURSOR_SR_FIFO,
3666         SNB_CURSOR_MAX_SRWM,
3667         SNB_CURSOR_DFT_SRWM,
3668         2,
3669         SNB_FIFO_LINE_SIZE
3670 };
3671
3672
3673 /**
3674  * intel_calculate_wm - calculate watermark level
3675  * @clock_in_khz: pixel clock
3676  * @wm: chip FIFO params
3677  * @pixel_size: display pixel size
3678  * @latency_ns: memory latency for the platform
3679  *
3680  * Calculate the watermark level (the level at which the display plane will
3681  * start fetching from memory again).  Each chip has a different display
3682  * FIFO size and allocation, so the caller needs to figure that out and pass
3683  * in the correct intel_watermark_params structure.
3684  *
3685  * As the pixel clock runs, the FIFO will be drained at a rate that depends
3686  * on the pixel size.  When it reaches the watermark level, it'll start
3687  * fetching FIFO line sized based chunks from memory until the FIFO fills
3688  * past the watermark point.  If the FIFO drains completely, a FIFO underrun
3689  * will occur, and a display engine hang could result.
3690  */
3691 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
3692                                         const struct intel_watermark_params *wm,
3693                                         int fifo_size,
3694                                         int pixel_size,
3695                                         unsigned long latency_ns)
3696 {
3697         long entries_required, wm_size;
3698
3699         /*
3700          * Note: we need to make sure we don't overflow for various clock &
3701          * latency values.
3702          * clocks go from a few thousand to several hundred thousand.
3703          * latency is usually a few thousand
3704          */
3705         entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
3706                 1000;
3707         entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
3708
3709         DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
3710
3711         wm_size = fifo_size - (entries_required + wm->guard_size);
3712
3713         DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
3714
3715         /* Don't promote wm_size to unsigned... */
3716         if (wm_size > (long)wm->max_wm)
3717                 wm_size = wm->max_wm;
3718         if (wm_size <= 0)
3719                 wm_size = wm->default_wm;
3720         return wm_size;
3721 }
3722
3723 struct cxsr_latency {
3724         int is_desktop;
3725         int is_ddr3;
3726         unsigned long fsb_freq;
3727         unsigned long mem_freq;
3728         unsigned long display_sr;
3729         unsigned long display_hpll_disable;
3730         unsigned long cursor_sr;
3731         unsigned long cursor_hpll_disable;
3732 };
3733
3734 static const struct cxsr_latency cxsr_latency_table[] = {
3735         {1, 0, 800, 400, 3382, 33382, 3983, 33983},    /* DDR2-400 SC */
3736         {1, 0, 800, 667, 3354, 33354, 3807, 33807},    /* DDR2-667 SC */
3737         {1, 0, 800, 800, 3347, 33347, 3763, 33763},    /* DDR2-800 SC */
3738         {1, 1, 800, 667, 6420, 36420, 6873, 36873},    /* DDR3-667 SC */
3739         {1, 1, 800, 800, 5902, 35902, 6318, 36318},    /* DDR3-800 SC */
3740
3741         {1, 0, 667, 400, 3400, 33400, 4021, 34021},    /* DDR2-400 SC */
3742         {1, 0, 667, 667, 3372, 33372, 3845, 33845},    /* DDR2-667 SC */
3743         {1, 0, 667, 800, 3386, 33386, 3822, 33822},    /* DDR2-800 SC */
3744         {1, 1, 667, 667, 6438, 36438, 6911, 36911},    /* DDR3-667 SC */
3745         {1, 1, 667, 800, 5941, 35941, 6377, 36377},    /* DDR3-800 SC */
3746
3747         {1, 0, 400, 400, 3472, 33472, 4173, 34173},    /* DDR2-400 SC */
3748         {1, 0, 400, 667, 3443, 33443, 3996, 33996},    /* DDR2-667 SC */
3749         {1, 0, 400, 800, 3430, 33430, 3946, 33946},    /* DDR2-800 SC */
3750         {1, 1, 400, 667, 6509, 36509, 7062, 37062},    /* DDR3-667 SC */
3751         {1, 1, 400, 800, 5985, 35985, 6501, 36501},    /* DDR3-800 SC */
3752
3753         {0, 0, 800, 400, 3438, 33438, 4065, 34065},    /* DDR2-400 SC */
3754         {0, 0, 800, 667, 3410, 33410, 3889, 33889},    /* DDR2-667 SC */
3755         {0, 0, 800, 800, 3403, 33403, 3845, 33845},    /* DDR2-800 SC */
3756         {0, 1, 800, 667, 6476, 36476, 6955, 36955},    /* DDR3-667 SC */
3757         {0, 1, 800, 800, 5958, 35958, 6400, 36400},    /* DDR3-800 SC */
3758
3759         {0, 0, 667, 400, 3456, 33456, 4103, 34106},    /* DDR2-400 SC */
3760         {0, 0, 667, 667, 3428, 33428, 3927, 33927},    /* DDR2-667 SC */
3761         {0, 0, 667, 800, 3443, 33443, 3905, 33905},    /* DDR2-800 SC */
3762         {0, 1, 667, 667, 6494, 36494, 6993, 36993},    /* DDR3-667 SC */
3763         {0, 1, 667, 800, 5998, 35998, 6460, 36460},    /* DDR3-800 SC */
3764
3765         {0, 0, 400, 400, 3528, 33528, 4255, 34255},    /* DDR2-400 SC */
3766         {0, 0, 400, 667, 3500, 33500, 4079, 34079},    /* DDR2-667 SC */
3767         {0, 0, 400, 800, 3487, 33487, 4029, 34029},    /* DDR2-800 SC */
3768         {0, 1, 400, 667, 6566, 36566, 7145, 37145},    /* DDR3-667 SC */
3769         {0, 1, 400, 800, 6042, 36042, 6584, 36584},    /* DDR3-800 SC */
3770 };
3771
3772 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
3773                                                          int is_ddr3,
3774                                                          int fsb,
3775                                                          int mem)
3776 {
3777         const struct cxsr_latency *latency;
3778         int i;
3779
3780         if (fsb == 0 || mem == 0)
3781                 return NULL;
3782
3783         for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
3784                 latency = &cxsr_latency_table[i];
3785                 if (is_desktop == latency->is_desktop &&
3786                     is_ddr3 == latency->is_ddr3 &&
3787                     fsb == latency->fsb_freq && mem == latency->mem_freq)
3788                         return latency;
3789         }
3790
3791         DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3792
3793         return NULL;
3794 }
3795
3796 static void pineview_disable_cxsr(struct drm_device *dev)
3797 {
3798         struct drm_i915_private *dev_priv = dev->dev_private;
3799
3800         /* deactivate cxsr */
3801         I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
3802 }
3803
3804 /*
3805  * Latency for FIFO fetches is dependent on several factors:
3806  *   - memory configuration (speed, channels)
3807  *   - chipset
3808  *   - current MCH state
3809  * It can be fairly high in some situations, so here we assume a fairly
3810  * pessimal value.  It's a tradeoff between extra memory fetches (if we
3811  * set this value too high, the FIFO will fetch frequently to stay full)
3812  * and power consumption (set it too low to save power and we might see
3813  * FIFO underruns and display "flicker").
3814  *
3815  * A value of 5us seems to be a good balance; safe for very low end
3816  * platforms but not overly aggressive on lower latency configs.
3817  */
3818 static const int latency_ns = 5000;
3819
3820 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
3821 {
3822         struct drm_i915_private *dev_priv = dev->dev_private;
3823         uint32_t dsparb = I915_READ(DSPARB);
3824         int size;
3825
3826         size = dsparb & 0x7f;
3827         if (plane)
3828                 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
3829
3830         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3831                       plane ? "B" : "A", size);
3832
3833         return size;
3834 }
3835
3836 static int i85x_get_fifo_size(struct drm_device *dev, int plane)
3837 {
3838         struct drm_i915_private *dev_priv = dev->dev_private;
3839         uint32_t dsparb = I915_READ(DSPARB);
3840         int size;
3841
3842         size = dsparb & 0x1ff;
3843         if (plane)
3844                 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
3845         size >>= 1; /* Convert to cachelines */
3846
3847         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3848                       plane ? "B" : "A", size);
3849
3850         return size;
3851 }
3852
3853 static int i845_get_fifo_size(struct drm_device *dev, int plane)
3854 {
3855         struct drm_i915_private *dev_priv = dev->dev_private;
3856         uint32_t dsparb = I915_READ(DSPARB);
3857         int size;
3858
3859         size = dsparb & 0x7f;
3860         size >>= 2; /* Convert to cachelines */
3861
3862         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3863                       plane ? "B" : "A",
3864                       size);
3865
3866         return size;
3867 }
3868
3869 static int i830_get_fifo_size(struct drm_device *dev, int plane)
3870 {
3871         struct drm_i915_private *dev_priv = dev->dev_private;
3872         uint32_t dsparb = I915_READ(DSPARB);
3873         int size;
3874
3875         size = dsparb & 0x7f;
3876         size >>= 1; /* Convert to cachelines */
3877
3878         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3879                       plane ? "B" : "A", size);
3880
3881         return size;
3882 }
3883
3884 static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
3885 {
3886         struct drm_crtc *crtc, *enabled = NULL;
3887
3888         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3889                 if (crtc->enabled && crtc->fb) {
3890                         if (enabled)
3891                                 return NULL;
3892                         enabled = crtc;
3893                 }
3894         }
3895
3896         return enabled;
3897 }
3898
3899 static void pineview_update_wm(struct drm_device *dev)
3900 {
3901         struct drm_i915_private *dev_priv = dev->dev_private;
3902         struct drm_crtc *crtc;
3903         const struct cxsr_latency *latency;
3904         u32 reg;
3905         unsigned long wm;
3906
3907         latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
3908                                          dev_priv->fsb_freq, dev_priv->mem_freq);
3909         if (!latency) {
3910                 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3911                 pineview_disable_cxsr(dev);
3912                 return;
3913         }
3914
3915         crtc = single_enabled_crtc(dev);
3916         if (crtc) {
3917                 int clock = crtc->mode.clock;
3918                 int pixel_size = crtc->fb->bits_per_pixel / 8;
3919
3920                 /* Display SR */
3921                 wm = intel_calculate_wm(clock, &pineview_display_wm,
3922                                         pineview_display_wm.fifo_size,
3923                                         pixel_size, latency->display_sr);
3924                 reg = I915_READ(DSPFW1);
3925                 reg &= ~DSPFW_SR_MASK;
3926                 reg |= wm << DSPFW_SR_SHIFT;
3927                 I915_WRITE(DSPFW1, reg);
3928                 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
3929
3930                 /* cursor SR */
3931                 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
3932                                         pineview_display_wm.fifo_size,
3933                                         pixel_size, latency->cursor_sr);
3934                 reg = I915_READ(DSPFW3);
3935                 reg &= ~DSPFW_CURSOR_SR_MASK;
3936                 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
3937                 I915_WRITE(DSPFW3, reg);
3938
3939                 /* Display HPLL off SR */
3940                 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
3941                                         pineview_display_hplloff_wm.fifo_size,
3942                                         pixel_size, latency->display_hpll_disable);
3943                 reg = I915_READ(DSPFW3);
3944                 reg &= ~DSPFW_HPLL_SR_MASK;
3945                 reg |= wm & DSPFW_HPLL_SR_MASK;
3946                 I915_WRITE(DSPFW3, reg);
3947
3948                 /* cursor HPLL off SR */
3949                 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
3950                                         pineview_display_hplloff_wm.fifo_size,
3951                                         pixel_size, latency->cursor_hpll_disable);
3952                 reg = I915_READ(DSPFW3);
3953                 reg &= ~DSPFW_HPLL_CURSOR_MASK;
3954                 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
3955                 I915_WRITE(DSPFW3, reg);
3956                 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
3957
3958                 /* activate cxsr */
3959                 I915_WRITE(DSPFW3,
3960                            I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
3961                 DRM_DEBUG_KMS("Self-refresh is enabled\n");
3962         } else {
3963                 pineview_disable_cxsr(dev);
3964                 DRM_DEBUG_KMS("Self-refresh is disabled\n");
3965         }
3966 }
3967
3968 static bool g4x_compute_wm0(struct drm_device *dev,
3969                             int plane,
3970                             const struct intel_watermark_params *display,
3971                             int display_latency_ns,
3972                             const struct intel_watermark_params *cursor,
3973                             int cursor_latency_ns,
3974                             int *plane_wm,
3975                             int *cursor_wm)
3976 {
3977         struct drm_crtc *crtc;
3978         int htotal, hdisplay, clock, pixel_size;
3979         int line_time_us, line_count;
3980         int entries, tlb_miss;
3981
3982         crtc = intel_get_crtc_for_plane(dev, plane);
3983         if (crtc->fb == NULL || !crtc->enabled) {
3984                 *cursor_wm = cursor->guard_size;
3985                 *plane_wm = display->guard_size;
3986                 return false;
3987         }
3988
3989         htotal = crtc->mode.htotal;
3990         hdisplay = crtc->mode.hdisplay;
3991         clock = crtc->mode.clock;
3992         pixel_size = crtc->fb->bits_per_pixel / 8;
3993
3994         /* Use the small buffer method to calculate plane watermark */
3995         entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
3996         tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
3997         if (tlb_miss > 0)
3998                 entries += tlb_miss;
3999         entries = DIV_ROUND_UP(entries, display->cacheline_size);
4000         *plane_wm = entries + display->guard_size;
4001         if (*plane_wm > (int)display->max_wm)
4002                 *plane_wm = display->max_wm;
4003
4004         /* Use the large buffer method to calculate cursor watermark */
4005         line_time_us = ((htotal * 1000) / clock);
4006         line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
4007         entries = line_count * 64 * pixel_size;
4008         tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
4009         if (tlb_miss > 0)
4010                 entries += tlb_miss;
4011         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
4012         *cursor_wm = entries + cursor->guard_size;
4013         if (*cursor_wm > (int)cursor->max_wm)
4014                 *cursor_wm = (int)cursor->max_wm;
4015
4016         return true;
4017 }
4018
4019 /*
4020  * Check the wm result.
4021  *
4022  * If any calculated watermark values is larger than the maximum value that
4023  * can be programmed into the associated watermark register, that watermark
4024  * must be disabled.
4025  */
4026 static bool g4x_check_srwm(struct drm_device *dev,
4027                            int display_wm, int cursor_wm,
4028                            const struct intel_watermark_params *display,
4029                            const struct intel_watermark_params *cursor)
4030 {
4031         DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
4032                       display_wm, cursor_wm);
4033
4034         if (display_wm > display->max_wm) {
4035                 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
4036                               display_wm, display->max_wm);
4037                 return false;
4038         }
4039
4040         if (cursor_wm > cursor->max_wm) {
4041                 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
4042                               cursor_wm, cursor->max_wm);
4043                 return false;
4044         }
4045
4046         if (!(display_wm || cursor_wm)) {
4047                 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
4048                 return false;
4049         }
4050
4051         return true;
4052 }
4053
4054 static bool g4x_compute_srwm(struct drm_device *dev,
4055                              int plane,
4056                              int latency_ns,
4057                              const struct intel_watermark_params *display,
4058                              const struct intel_watermark_params *cursor,
4059                              int *display_wm, int *cursor_wm)
4060 {
4061         struct drm_crtc *crtc;
4062         int hdisplay, htotal, pixel_size, clock;
4063         unsigned long line_time_us;
4064         int line_count, line_size;
4065         int small, large;
4066         int entries;
4067
4068         if (!latency_ns) {
4069                 *display_wm = *cursor_wm = 0;
4070                 return false;
4071         }
4072
4073         crtc = intel_get_crtc_for_plane(dev, plane);
4074         hdisplay = crtc->mode.hdisplay;
4075         htotal = crtc->mode.htotal;
4076         clock = crtc->mode.clock;
4077         pixel_size = crtc->fb->bits_per_pixel / 8;
4078
4079         line_time_us = (htotal * 1000) / clock;
4080         line_count = (latency_ns / line_time_us + 1000) / 1000;
4081         line_size = hdisplay * pixel_size;
4082
4083         /* Use the minimum of the small and large buffer method for primary */
4084         small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
4085         large = line_count * line_size;
4086
4087         entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
4088         *display_wm = entries + display->guard_size;
4089
4090         /* calculate the self-refresh watermark for display cursor */
4091         entries = line_count * pixel_size * 64;
4092         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
4093         *cursor_wm = entries + cursor->guard_size;
4094
4095         return g4x_check_srwm(dev,
4096                               *display_wm, *cursor_wm,
4097                               display, cursor);
4098 }
4099
4100 #define single_plane_enabled(mask) is_power_of_2(mask)
4101
4102 static void g4x_update_wm(struct drm_device *dev)
4103 {
4104         static const int sr_latency_ns = 12000;
4105         struct drm_i915_private *dev_priv = dev->dev_private;
4106         int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
4107         int plane_sr, cursor_sr;
4108         unsigned int enabled = 0;
4109
4110         if (g4x_compute_wm0(dev, 0,
4111                             &g4x_wm_info, latency_ns,
4112                             &g4x_cursor_wm_info, latency_ns,
4113                             &planea_wm, &cursora_wm))
4114                 enabled |= 1;
4115
4116         if (g4x_compute_wm0(dev, 1,
4117                             &g4x_wm_info, latency_ns,
4118                             &g4x_cursor_wm_info, latency_ns,
4119                             &planeb_wm, &cursorb_wm))
4120                 enabled |= 2;
4121
4122         plane_sr = cursor_sr = 0;
4123         if (single_plane_enabled(enabled) &&
4124             g4x_compute_srwm(dev, ffs(enabled) - 1,
4125                              sr_latency_ns,
4126                              &g4x_wm_info,
4127                              &g4x_cursor_wm_info,
4128                              &plane_sr, &cursor_sr))
4129                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
4130         else
4131                 I915_WRITE(FW_BLC_SELF,
4132                            I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
4133
4134         DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
4135                       planea_wm, cursora_wm,
4136                       planeb_wm, cursorb_wm,
4137                       plane_sr, cursor_sr);
4138
4139         I915_WRITE(DSPFW1,
4140                    (plane_sr << DSPFW_SR_SHIFT) |
4141                    (cursorb_wm << DSPFW_CURSORB_SHIFT) |
4142                    (planeb_wm << DSPFW_PLANEB_SHIFT) |
4143                    planea_wm);
4144         I915_WRITE(DSPFW2,
4145                    (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
4146                    (cursora_wm << DSPFW_CURSORA_SHIFT));
4147         /* HPLL off in SR has some issues on G4x... disable it */
4148         I915_WRITE(DSPFW3,
4149                    (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
4150                    (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
4151 }
4152
4153 static void i965_update_wm(struct drm_device *dev)
4154 {
4155         struct drm_i915_private *dev_priv = dev->dev_private;
4156         struct drm_crtc *crtc;
4157         int srwm = 1;
4158         int cursor_sr = 16;
4159
4160         /* Calc sr entries for one plane configs */
4161         crtc = single_enabled_crtc(dev);
4162         if (crtc) {
4163                 /* self-refresh has much higher latency */
4164                 static const int sr_latency_ns = 12000;
4165                 int clock = crtc->mode.clock;
4166                 int htotal = crtc->mode.htotal;
4167                 int hdisplay = crtc->mode.hdisplay;
4168                 int pixel_size = crtc->fb->bits_per_pixel / 8;
4169                 unsigned long line_time_us;
4170                 int entries;
4171
4172                 line_time_us = ((htotal * 1000) / clock);
4173
4174                 /* Use ns/us then divide to preserve precision */
4175                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
4176                         pixel_size * hdisplay;
4177                 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
4178                 srwm = I965_FIFO_SIZE - entries;
4179                 if (srwm < 0)
4180                         srwm = 1;
4181                 srwm &= 0x1ff;
4182                 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
4183                               entries, srwm);
4184
4185                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
4186                         pixel_size * 64;
4187                 entries = DIV_ROUND_UP(entries,
4188                                           i965_cursor_wm_info.cacheline_size);
4189                 cursor_sr = i965_cursor_wm_info.fifo_size -
4190                         (entries + i965_cursor_wm_info.guard_size);
4191
4192                 if (cursor_sr > i965_cursor_wm_info.max_wm)
4193                         cursor_sr = i965_cursor_wm_info.max_wm;
4194
4195                 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
4196                               "cursor %d\n", srwm, cursor_sr);
4197
4198                 if (IS_CRESTLINE(dev))
4199                         I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
4200         } else {
4201                 /* Turn off self refresh if both pipes are enabled */
4202                 if (IS_CRESTLINE(dev))
4203                         I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
4204                                    & ~FW_BLC_SELF_EN);
4205         }
4206
4207         DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
4208                       srwm);
4209
4210         /* 965 has limitations... */
4211         I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
4212                    (8 << 16) | (8 << 8) | (8 << 0));
4213         I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
4214         /* update cursor SR watermark */
4215         I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
4216 }
4217
4218 static void i9xx_update_wm(struct drm_device *dev)
4219 {
4220         struct drm_i915_private *dev_priv = dev->dev_private;
4221         const struct intel_watermark_params *wm_info;
4222         uint32_t fwater_lo;
4223         uint32_t fwater_hi;
4224         int cwm, srwm = 1;
4225         int fifo_size;
4226         int planea_wm, planeb_wm;
4227         struct drm_crtc *crtc, *enabled = NULL;
4228
4229         if (IS_I945GM(dev))
4230                 wm_info = &i945_wm_info;
4231         else if (!IS_GEN2(dev))
4232                 wm_info = &i915_wm_info;
4233         else
4234                 wm_info = &i855_wm_info;
4235
4236         fifo_size = dev_priv->display.get_fifo_size(dev, 0);
4237         crtc = intel_get_crtc_for_plane(dev, 0);
4238         if (crtc->enabled && crtc->fb) {
4239                 planea_wm = intel_calculate_wm(crtc->mode.clock,
4240                                                wm_info, fifo_size,
4241                                                crtc->fb->bits_per_pixel / 8,
4242                                                latency_ns);
4243                 enabled = crtc;
4244         } else
4245                 planea_wm = fifo_size - wm_info->guard_size;
4246
4247         fifo_size = dev_priv->display.get_fifo_size(dev, 1);
4248         crtc = intel_get_crtc_for_plane(dev, 1);
4249         if (crtc->enabled && crtc->fb) {
4250                 planeb_wm = intel_calculate_wm(crtc->mode.clock,
4251                                                wm_info, fifo_size,
4252                                                crtc->fb->bits_per_pixel / 8,
4253                                                latency_ns);
4254                 if (enabled == NULL)
4255                         enabled = crtc;
4256                 else
4257                         enabled = NULL;
4258         } else
4259                 planeb_wm = fifo_size - wm_info->guard_size;
4260
4261         DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
4262
4263         /*
4264          * Overlay gets an aggressive default since video jitter is bad.
4265          */
4266         cwm = 2;
4267
4268         /* Play safe and disable self-refresh before adjusting watermarks. */
4269         if (IS_I945G(dev) || IS_I945GM(dev))
4270                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0);
4271         else if (IS_I915GM(dev))
4272                 I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
4273
4274         /* Calc sr entries for one plane configs */
4275         if (HAS_FW_BLC(dev) && enabled) {
4276                 /* self-refresh has much higher latency */
4277                 static const int sr_latency_ns = 6000;
4278                 int clock = enabled->mode.clock;
4279                 int htotal = enabled->mode.htotal;
4280                 int hdisplay = enabled->mode.hdisplay;
4281                 int pixel_size = enabled->fb->bits_per_pixel / 8;
4282                 unsigned long line_time_us;
4283                 int entries;
4284
4285                 line_time_us = (htotal * 1000) / clock;
4286
4287                 /* Use ns/us then divide to preserve precision */
4288                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
4289                         pixel_size * hdisplay;
4290                 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
4291                 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
4292                 srwm = wm_info->fifo_size - entries;
4293                 if (srwm < 0)
4294                         srwm = 1;
4295
4296                 if (IS_I945G(dev) || IS_I945GM(dev))
4297                         I915_WRITE(FW_BLC_SELF,
4298                                    FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
4299                 else if (IS_I915GM(dev))
4300                         I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
4301         }
4302
4303         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
4304                       planea_wm, planeb_wm, cwm, srwm);
4305
4306         fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
4307         fwater_hi = (cwm & 0x1f);
4308
4309         /* Set request length to 8 cachelines per fetch */
4310         fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
4311         fwater_hi = fwater_hi | (1 << 8);
4312
4313         I915_WRITE(FW_BLC, fwater_lo);
4314         I915_WRITE(FW_BLC2, fwater_hi);
4315
4316         if (HAS_FW_BLC(dev)) {
4317                 if (enabled) {
4318                         if (IS_I945G(dev) || IS_I945GM(dev))
4319                                 I915_WRITE(FW_BLC_SELF,
4320                                            FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
4321                         else if (IS_I915GM(dev))
4322                                 I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
4323                         DRM_DEBUG_KMS("memory self refresh enabled\n");
4324                 } else
4325                         DRM_DEBUG_KMS("memory self refresh disabled\n");
4326         }
4327 }
4328
4329 static void i830_update_wm(struct drm_device *dev)
4330 {
4331         struct drm_i915_private *dev_priv = dev->dev_private;
4332         struct drm_crtc *crtc;
4333         uint32_t fwater_lo;
4334         int planea_wm;
4335
4336         crtc = single_enabled_crtc(dev);
4337         if (crtc == NULL)
4338                 return;
4339
4340         planea_wm = intel_calculate_wm(crtc->mode.clock, &i830_wm_info,
4341                                        dev_priv->display.get_fifo_size(dev, 0),
4342                                        crtc->fb->bits_per_pixel / 8,
4343                                        latency_ns);
4344         fwater_lo = I915_READ(FW_BLC) & ~0xfff;
4345         fwater_lo |= (3<<8) | planea_wm;
4346
4347         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
4348
4349         I915_WRITE(FW_BLC, fwater_lo);
4350 }
4351
4352 #define ILK_LP0_PLANE_LATENCY           700
4353 #define ILK_LP0_CURSOR_LATENCY          1300
4354
4355 /*
4356  * Check the wm result.
4357  *
4358  * If any calculated watermark values is larger than the maximum value that
4359  * can be programmed into the associated watermark register, that watermark
4360  * must be disabled.
4361  */
4362 static bool ironlake_check_srwm(struct drm_device *dev, int level,
4363                                 int fbc_wm, int display_wm, int cursor_wm,
4364                                 const struct intel_watermark_params *display,
4365                                 const struct intel_watermark_params *cursor)
4366 {
4367         struct drm_i915_private *dev_priv = dev->dev_private;
4368
4369         DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d,"
4370                       " cursor %d\n", level, display_wm, fbc_wm, cursor_wm);
4371
4372         if (fbc_wm > SNB_FBC_MAX_SRWM) {
4373                 DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n",
4374                               fbc_wm, SNB_FBC_MAX_SRWM, level);
4375
4376                 /* fbc has it's own way to disable FBC WM */
4377                 I915_WRITE(DISP_ARB_CTL,
4378                            I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS);
4379                 return false;
4380         }
4381
4382         if (display_wm > display->max_wm) {
4383                 DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n",
4384                               display_wm, SNB_DISPLAY_MAX_SRWM, level);
4385                 return false;
4386         }
4387
4388         if (cursor_wm > cursor->max_wm) {
4389                 DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n",
4390                               cursor_wm, SNB_CURSOR_MAX_SRWM, level);
4391                 return false;
4392         }
4393
4394         if (!(fbc_wm || display_wm || cursor_wm)) {
4395                 DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level);
4396                 return false;
4397         }
4398
4399         return true;
4400 }
4401
4402 /*
4403  * Compute watermark values of WM[1-3],
4404  */
4405 static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane,
4406                                   int latency_ns,
4407                                   const struct intel_watermark_params *display,
4408                                   const struct intel_watermark_params *cursor,
4409                                   int *fbc_wm, int *display_wm, int *cursor_wm)
4410 {
4411         struct drm_crtc *crtc;
4412         unsigned long line_time_us;
4413         int hdisplay, htotal, pixel_size, clock;
4414         int line_count, line_size;
4415         int small, large;
4416         int entries;
4417
4418         if (!latency_ns) {
4419                 *fbc_wm = *display_wm = *cursor_wm = 0;
4420                 return false;
4421         }
4422
4423         crtc = intel_get_crtc_for_plane(dev, plane);
4424         hdisplay = crtc->mode.hdisplay;
4425         htotal = crtc->mode.htotal;
4426         clock = crtc->mode.clock;
4427         pixel_size = crtc->fb->bits_per_pixel / 8;
4428
4429         line_time_us = (htotal * 1000) / clock;
4430         line_count = (latency_ns / line_time_us + 1000) / 1000;
4431         line_size = hdisplay * pixel_size;
4432
4433         /* Use the minimum of the small and large buffer method for primary */
4434         small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
4435         large = line_count * line_size;
4436
4437         entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
4438         *display_wm = entries + display->guard_size;
4439
4440         /*
4441          * Spec says:
4442          * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2
4443          */
4444         *fbc_wm = DIV_ROUND_UP(*display_wm * 64, line_size) + 2;
4445
4446         /* calculate the self-refresh watermark for display cursor */
4447         entries = line_count * pixel_size * 64;
4448         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
4449         *cursor_wm = entries + cursor->guard_size;
4450
4451         return ironlake_check_srwm(dev, level,
4452                                    *fbc_wm, *display_wm, *cursor_wm,
4453                                    display, cursor);
4454 }
4455
4456 static void ironlake_update_wm(struct drm_device *dev)
4457 {
4458         struct drm_i915_private *dev_priv = dev->dev_private;
4459         int fbc_wm, plane_wm, cursor_wm;
4460         unsigned int enabled;
4461
4462         enabled = 0;
4463         if (g4x_compute_wm0(dev, 0,
4464                             &ironlake_display_wm_info,
4465                             ILK_LP0_PLANE_LATENCY,
4466                             &ironlake_cursor_wm_info,
4467                             ILK_LP0_CURSOR_LATENCY,
4468                             &plane_wm, &cursor_wm)) {
4469                 I915_WRITE(WM0_PIPEA_ILK,
4470                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4471                 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
4472                               " plane %d, " "cursor: %d\n",
4473                               plane_wm, cursor_wm);
4474                 enabled |= 1;
4475         }
4476
4477         if (g4x_compute_wm0(dev, 1,
4478                             &ironlake_display_wm_info,
4479                             ILK_LP0_PLANE_LATENCY,
4480                             &ironlake_cursor_wm_info,
4481                             ILK_LP0_CURSOR_LATENCY,
4482                             &plane_wm, &cursor_wm)) {
4483                 I915_WRITE(WM0_PIPEB_ILK,
4484                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4485                 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
4486                               " plane %d, cursor: %d\n",
4487                               plane_wm, cursor_wm);
4488                 enabled |= 2;
4489         }
4490
4491         /*
4492          * Calculate and update the self-refresh watermark only when one
4493          * display plane is used.
4494          */
4495         I915_WRITE(WM3_LP_ILK, 0);
4496         I915_WRITE(WM2_LP_ILK, 0);
4497         I915_WRITE(WM1_LP_ILK, 0);
4498
4499         if (!single_plane_enabled(enabled))
4500                 return;
4501         enabled = ffs(enabled) - 1;
4502
4503         /* WM1 */
4504         if (!ironlake_compute_srwm(dev, 1, enabled,
4505                                    ILK_READ_WM1_LATENCY() * 500,
4506                                    &ironlake_display_srwm_info,
4507                                    &ironlake_cursor_srwm_info,
4508                                    &fbc_wm, &plane_wm, &cursor_wm))
4509                 return;
4510
4511         I915_WRITE(WM1_LP_ILK,
4512                    WM1_LP_SR_EN |
4513                    (ILK_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4514                    (fbc_wm << WM1_LP_FBC_SHIFT) |
4515                    (plane_wm << WM1_LP_SR_SHIFT) |
4516                    cursor_wm);
4517
4518         /* WM2 */
4519         if (!ironlake_compute_srwm(dev, 2, enabled,
4520                                    ILK_READ_WM2_LATENCY() * 500,
4521                                    &ironlake_display_srwm_info,
4522                                    &ironlake_cursor_srwm_info,
4523                                    &fbc_wm, &plane_wm, &cursor_wm))
4524                 return;
4525
4526         I915_WRITE(WM2_LP_ILK,
4527                    WM2_LP_EN |
4528                    (ILK_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4529                    (fbc_wm << WM1_LP_FBC_SHIFT) |
4530                    (plane_wm << WM1_LP_SR_SHIFT) |
4531                    cursor_wm);
4532
4533         /*
4534          * WM3 is unsupported on ILK, probably because we don't have latency
4535          * data for that power state
4536          */
4537 }
4538
4539 static void sandybridge_update_wm(struct drm_device *dev)
4540 {
4541         struct drm_i915_private *dev_priv = dev->dev_private;
4542         int latency = SNB_READ_WM0_LATENCY() * 100;     /* In unit 0.1us */
4543         int fbc_wm, plane_wm, cursor_wm;
4544         unsigned int enabled;
4545
4546         enabled = 0;
4547         if (g4x_compute_wm0(dev, 0,
4548                             &sandybridge_display_wm_info, latency,
4549                             &sandybridge_cursor_wm_info, latency,
4550                             &plane_wm, &cursor_wm)) {
4551                 I915_WRITE(WM0_PIPEA_ILK,
4552                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4553                 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
4554                               " plane %d, " "cursor: %d\n",
4555                               plane_wm, cursor_wm);
4556                 enabled |= 1;
4557         }
4558
4559         if (g4x_compute_wm0(dev, 1,
4560                             &sandybridge_display_wm_info, latency,
4561                             &sandybridge_cursor_wm_info, latency,
4562                             &plane_wm, &cursor_wm)) {
4563                 I915_WRITE(WM0_PIPEB_ILK,
4564                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4565                 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
4566                               " plane %d, cursor: %d\n",
4567                               plane_wm, cursor_wm);
4568                 enabled |= 2;
4569         }
4570
4571         /* IVB has 3 pipes */
4572         if (IS_IVYBRIDGE(dev) &&
4573             g4x_compute_wm0(dev, 2,
4574                             &sandybridge_display_wm_info, latency,
4575                             &sandybridge_cursor_wm_info, latency,
4576                             &plane_wm, &cursor_wm)) {
4577                 I915_WRITE(WM0_PIPEC_IVB,
4578                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4579                 DRM_DEBUG_KMS("FIFO watermarks For pipe C -"
4580                               " plane %d, cursor: %d\n",
4581                               plane_wm, cursor_wm);
4582                 enabled |= 3;
4583         }
4584
4585         /*
4586          * Calculate and update the self-refresh watermark only when one
4587          * display plane is used.
4588          *
4589          * SNB support 3 levels of watermark.
4590          *
4591          * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
4592          * and disabled in the descending order
4593          *
4594          */
4595         I915_WRITE(WM3_LP_ILK, 0);
4596         I915_WRITE(WM2_LP_ILK, 0);
4597         I915_WRITE(WM1_LP_ILK, 0);
4598
4599         if (!single_plane_enabled(enabled))
4600                 return;
4601         enabled = ffs(enabled) - 1;
4602
4603         /* WM1 */
4604         if (!ironlake_compute_srwm(dev, 1, enabled,
4605                                    SNB_READ_WM1_LATENCY() * 500,
4606                                    &sandybridge_display_srwm_info,
4607                                    &sandybridge_cursor_srwm_info,
4608                                    &fbc_wm, &plane_wm, &cursor_wm))
4609                 return;
4610
4611         I915_WRITE(WM1_LP_ILK,
4612                    WM1_LP_SR_EN |
4613                    (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4614                    (fbc_wm << WM1_LP_FBC_SHIFT) |
4615                    (plane_wm << WM1_LP_SR_SHIFT) |
4616                    cursor_wm);
4617
4618         /* WM2 */
4619         if (!ironlake_compute_srwm(dev, 2, enabled,
4620                                    SNB_READ_WM2_LATENCY() * 500,
4621                                    &sandybridge_display_srwm_info,
4622                                    &sandybridge_cursor_srwm_info,
4623                                    &fbc_wm, &plane_wm, &cursor_wm))
4624                 return;
4625
4626         I915_WRITE(WM2_LP_ILK,
4627                    WM2_LP_EN |
4628                    (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4629                    (fbc_wm << WM1_LP_FBC_SHIFT) |
4630                    (plane_wm << WM1_LP_SR_SHIFT) |
4631                    cursor_wm);
4632
4633         /* WM3 */
4634         if (!ironlake_compute_srwm(dev, 3, enabled,
4635                                    SNB_READ_WM3_LATENCY() * 500,
4636                                    &sandybridge_display_srwm_info,
4637                                    &sandybridge_cursor_srwm_info,
4638                                    &fbc_wm, &plane_wm, &cursor_wm))
4639                 return;
4640
4641         I915_WRITE(WM3_LP_ILK,
4642                    WM3_LP_EN |
4643                    (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4644                    (fbc_wm << WM1_LP_FBC_SHIFT) |
4645                    (plane_wm << WM1_LP_SR_SHIFT) |
4646                    cursor_wm);
4647 }
4648
4649 /**
4650  * intel_update_watermarks - update FIFO watermark values based on current modes
4651  *
4652  * Calculate watermark values for the various WM regs based on current mode
4653  * and plane configuration.
4654  *
4655  * There are several cases to deal with here:
4656  *   - normal (i.e. non-self-refresh)
4657  *   - self-refresh (SR) mode
4658  *   - lines are large relative to FIFO size (buffer can hold up to 2)
4659  *   - lines are small relative to FIFO size (buffer can hold more than 2
4660  *     lines), so need to account for TLB latency
4661  *
4662  *   The normal calculation is:
4663  *     watermark = dotclock * bytes per pixel * latency
4664  *   where latency is platform & configuration dependent (we assume pessimal
4665  *   values here).
4666  *
4667  *   The SR calculation is:
4668  *     watermark = (trunc(latency/line time)+1) * surface width *
4669  *       bytes per pixel
4670  *   where
4671  *     line time = htotal / dotclock
4672  *     surface width = hdisplay for normal plane and 64 for cursor
4673  *   and latency is assumed to be high, as above.
4674  *
4675  * The final value programmed to the register should always be rounded up,
4676  * and include an extra 2 entries to account for clock crossings.
4677  *
4678  * We don't use the sprite, so we can ignore that.  And on Crestline we have
4679  * to set the non-SR watermarks to 8.
4680  */
4681 static void intel_update_watermarks(struct drm_device *dev)
4682 {
4683         struct drm_i915_private *dev_priv = dev->dev_private;
4684
4685         if (dev_priv->display.update_wm)
4686                 dev_priv->display.update_wm(dev);
4687 }
4688
4689 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4690 {
4691         if (i915_panel_use_ssc >= 0)
4692                 return i915_panel_use_ssc != 0;
4693         return dev_priv->lvds_use_ssc
4694                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
4695 }
4696
4697 /**
4698  * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
4699  * @crtc: CRTC structure
4700  * @mode: requested mode
4701  *
4702  * A pipe may be connected to one or more outputs.  Based on the depth of the
4703  * attached framebuffer, choose a good color depth to use on the pipe.
4704  *
4705  * If possible, match the pipe depth to the fb depth.  In some cases, this
4706  * isn't ideal, because the connected output supports a lesser or restricted
4707  * set of depths.  Resolve that here:
4708  *    LVDS typically supports only 6bpc, so clamp down in that case
4709  *    HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
4710  *    Displays may support a restricted set as well, check EDID and clamp as
4711  *      appropriate.
4712  *    DP may want to dither down to 6bpc to fit larger modes
4713  *
4714  * RETURNS:
4715  * Dithering requirement (i.e. false if display bpc and pipe bpc match,
4716  * true if they don't match).
4717  */
4718 static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
4719                                          unsigned int *pipe_bpp,
4720                                          struct drm_display_mode *mode)
4721 {
4722         struct drm_device *dev = crtc->dev;
4723         struct drm_i915_private *dev_priv = dev->dev_private;
4724         struct drm_encoder *encoder;
4725         struct drm_connector *connector;
4726         unsigned int display_bpc = UINT_MAX, bpc;
4727
4728         /* Walk the encoders & connectors on this crtc, get min bpc */
4729         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
4730                 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
4731
4732                 if (encoder->crtc != crtc)
4733                         continue;
4734
4735                 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
4736                         unsigned int lvds_bpc;
4737
4738                         if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
4739                             LVDS_A3_POWER_UP)
4740                                 lvds_bpc = 8;
4741                         else
4742                                 lvds_bpc = 6;
4743
4744                         if (lvds_bpc < display_bpc) {
4745                                 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
4746                                 display_bpc = lvds_bpc;
4747                         }
4748                         continue;
4749                 }
4750
4751                 /* Not one of the known troublemakers, check the EDID */
4752                 list_for_each_entry(connector, &dev->mode_config.connector_list,
4753                                     head) {
4754                         if (connector->encoder != encoder)
4755                                 continue;
4756
4757                         /* Don't use an invalid EDID bpc value */
4758                         if (connector->display_info.bpc &&
4759                             connector->display_info.bpc < display_bpc) {
4760                                 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
4761                                 display_bpc = connector->display_info.bpc;
4762                         }
4763                 }
4764
4765                 if (intel_encoder->type == INTEL_OUTPUT_EDP) {
4766                         /* Use VBT settings if we have an eDP panel */
4767                         unsigned int edp_bpc = dev_priv->edp.bpp / 3;
4768
4769                         if (edp_bpc && edp_bpc < display_bpc) {
4770                                 DRM_DEBUG_KMS("clamping display bpc (was %d) to eDP (%d)\n", display_bpc, edp_bpc);
4771                                 display_bpc = edp_bpc;
4772                         }
4773                         continue;
4774                 }
4775
4776                 /*
4777                  * HDMI is either 12 or 8, so if the display lets 10bpc sneak
4778                  * through, clamp it down.  (Note: >12bpc will be caught below.)
4779                  */
4780                 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
4781                         if (display_bpc > 8 && display_bpc < 12) {
4782                                 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
4783                                 display_bpc = 12;
4784                         } else {
4785                                 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
4786                                 display_bpc = 8;
4787                         }
4788                 }
4789         }
4790
4791         if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4792                 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
4793                 display_bpc = 6;
4794         }
4795
4796         /*
4797          * We could just drive the pipe at the highest bpc all the time and
4798          * enable dithering as needed, but that costs bandwidth.  So choose
4799          * the minimum value that expresses the full color range of the fb but
4800          * also stays within the max display bpc discovered above.
4801          */
4802
4803         switch (crtc->fb->depth) {
4804         case 8:
4805                 bpc = 8; /* since we go through a colormap */
4806                 break;
4807         case 15:
4808         case 16:
4809                 bpc = 6; /* min is 18bpp */
4810                 break;
4811         case 24:
4812                 bpc = 8;
4813                 break;
4814         case 30:
4815                 bpc = 10;
4816                 break;
4817         case 48:
4818                 bpc = 12;
4819                 break;
4820         default:
4821                 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
4822                 bpc = min((unsigned int)8, display_bpc);
4823                 break;
4824         }
4825
4826         display_bpc = min(display_bpc, bpc);
4827
4828         DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
4829                       bpc, display_bpc);
4830
4831         *pipe_bpp = display_bpc * 3;
4832
4833         return display_bpc != bpc;
4834 }
4835
4836 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4837                               struct drm_display_mode *mode,
4838                               struct drm_display_mode *adjusted_mode,
4839                               int x, int y,
4840                               struct drm_framebuffer *old_fb)
4841 {
4842         struct drm_device *dev = crtc->dev;
4843         struct drm_i915_private *dev_priv = dev->dev_private;
4844         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4845         int pipe = intel_crtc->pipe;
4846         int plane = intel_crtc->plane;
4847         int refclk, num_connectors = 0;
4848         intel_clock_t clock, reduced_clock;
4849         u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
4850         bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
4851         bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
4852         struct drm_mode_config *mode_config = &dev->mode_config;
4853         struct intel_encoder *encoder;
4854         const intel_limit_t *limit;
4855         int ret;
4856         u32 temp;
4857         u32 lvds_sync = 0;
4858
4859         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
4860                 if (encoder->base.crtc != crtc)
4861                         continue;
4862
4863                 switch (encoder->type) {
4864                 case INTEL_OUTPUT_LVDS:
4865                         is_lvds = true;
4866                         break;
4867                 case INTEL_OUTPUT_SDVO:
4868                 case INTEL_OUTPUT_HDMI:
4869                         is_sdvo = true;
4870                         if (encoder->needs_tv_clock)
4871                                 is_tv = true;
4872                         break;
4873                 case INTEL_OUTPUT_DVO:
4874                         is_dvo = true;
4875                         break;
4876                 case INTEL_OUTPUT_TVOUT:
4877                         is_tv = true;
4878                         break;
4879                 case INTEL_OUTPUT_ANALOG:
4880                         is_crt = true;
4881                         break;
4882                 case INTEL_OUTPUT_DISPLAYPORT:
4883                         is_dp = true;
4884                         break;
4885                 }
4886
4887                 num_connectors++;
4888         }
4889
4890         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4891                 refclk = dev_priv->lvds_ssc_freq * 1000;
4892                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4893                               refclk / 1000);
4894         } else if (!IS_GEN2(dev)) {
4895                 refclk = 96000;
4896         } else {
4897                 refclk = 48000;
4898         }
4899
4900         /*
4901          * Returns a set of divisors for the desired target clock with the given
4902          * refclk, or FALSE.  The returned values represent the clock equation:
4903          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4904          */
4905         limit = intel_limit(crtc, refclk);
4906         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
4907         if (!ok) {
4908                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4909                 return -EINVAL;
4910         }
4911
4912         /* Ensure that the cursor is valid for the new mode before changing... */
4913         intel_crtc_update_cursor(crtc, true);
4914
4915         if (is_lvds && dev_priv->lvds_downclock_avail) {
4916                 has_reduced_clock = limit->find_pll(limit, crtc,
4917                                                     dev_priv->lvds_downclock,
4918                                                     refclk,
4919                                                     &reduced_clock);
4920                 if (has_reduced_clock && (clock.p != reduced_clock.p)) {
4921                         /*
4922                          * If the different P is found, it means that we can't
4923                          * switch the display clock by using the FP0/FP1.
4924                          * In such case we will disable the LVDS downclock
4925                          * feature.
4926                          */
4927                         DRM_DEBUG_KMS("Different P is found for "
4928                                       "LVDS clock/downclock\n");
4929                         has_reduced_clock = 0;
4930                 }
4931         }
4932         /* SDVO TV has fixed PLL values depend on its clock range,
4933            this mirrors vbios setting. */
4934         if (is_sdvo && is_tv) {
4935                 if (adjusted_mode->clock >= 100000
4936                     && adjusted_mode->clock < 140500) {
4937                         clock.p1 = 2;
4938                         clock.p2 = 10;
4939                         clock.n = 3;
4940                         clock.m1 = 16;
4941                         clock.m2 = 8;
4942                 } else if (adjusted_mode->clock >= 140500
4943                            && adjusted_mode->clock <= 200000) {
4944                         clock.p1 = 1;
4945                         clock.p2 = 10;
4946                         clock.n = 6;
4947                         clock.m1 = 12;
4948                         clock.m2 = 8;
4949                 }
4950         }
4951
4952         if (IS_PINEVIEW(dev)) {
4953                 fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
4954                 if (has_reduced_clock)
4955                         fp2 = (1 << reduced_clock.n) << 16 |
4956                                 reduced_clock.m1 << 8 | reduced_clock.m2;
4957         } else {
4958                 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
4959                 if (has_reduced_clock)
4960                         fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
4961                                 reduced_clock.m2;
4962         }
4963
4964         dpll = DPLL_VGA_MODE_DIS;
4965
4966         if (!IS_GEN2(dev)) {
4967                 if (is_lvds)
4968                         dpll |= DPLLB_MODE_LVDS;
4969                 else
4970                         dpll |= DPLLB_MODE_DAC_SERIAL;
4971                 if (is_sdvo) {
4972                         int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4973                         if (pixel_multiplier > 1) {
4974                                 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4975                                         dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
4976                         }
4977                         dpll |= DPLL_DVO_HIGH_SPEED;
4978                 }
4979                 if (is_dp)
4980                         dpll |= DPLL_DVO_HIGH_SPEED;
4981
4982                 /* compute bitmask from p1 value */
4983                 if (IS_PINEVIEW(dev))
4984                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4985                 else {
4986                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4987                         if (IS_G4X(dev) && has_reduced_clock)
4988                                 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4989                 }
4990                 switch (clock.p2) {
4991                 case 5:
4992                         dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4993                         break;
4994                 case 7:
4995                         dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4996                         break;
4997                 case 10:
4998                         dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4999                         break;
5000                 case 14:
5001                         dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5002                         break;
5003                 }
5004                 if (INTEL_INFO(dev)->gen >= 4)
5005                         dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
5006         } else {
5007                 if (is_lvds) {
5008                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5009                 } else {
5010                         if (clock.p1 == 2)
5011                                 dpll |= PLL_P1_DIVIDE_BY_TWO;
5012                         else
5013                                 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5014                         if (clock.p2 == 4)
5015                                 dpll |= PLL_P2_DIVIDE_BY_4;
5016                 }
5017         }
5018
5019         if (is_sdvo && is_tv)
5020                 dpll |= PLL_REF_INPUT_TVCLKINBC;
5021         else if (is_tv)
5022                 /* XXX: just matching BIOS for now */
5023                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
5024                 dpll |= 3;
5025         else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5026                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5027         else
5028                 dpll |= PLL_REF_INPUT_DREFCLK;
5029
5030         /* setup pipeconf */
5031         pipeconf = I915_READ(PIPECONF(pipe));
5032
5033         /* Set up the display plane register */
5034         dspcntr = DISPPLANE_GAMMA_ENABLE;
5035
5036         /* Ironlake's plane is forced to pipe, bit 24 is to
5037            enable color space conversion */
5038         if (pipe == 0)
5039                 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
5040         else
5041                 dspcntr |= DISPPLANE_SEL_PIPE_B;
5042
5043         if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
5044                 /* Enable pixel doubling when the dot clock is > 90% of the (display)
5045                  * core speed.
5046                  *
5047                  * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
5048                  * pipe == 0 check?
5049                  */
5050                 if (mode->clock >
5051                     dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
5052                         pipeconf |= PIPECONF_DOUBLE_WIDE;
5053                 else
5054                         pipeconf &= ~PIPECONF_DOUBLE_WIDE;
5055         }
5056
5057         /* default to 8bpc */
5058         pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN);
5059         if (is_dp) {
5060                 if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
5061                         pipeconf |= PIPECONF_BPP_6 |
5062                                     PIPECONF_DITHER_EN |
5063                                     PIPECONF_DITHER_TYPE_SP;
5064                 }
5065         }
5066
5067         dpll |= DPLL_VCO_ENABLE;
5068
5069         DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
5070         drm_mode_debug_printmodeline(mode);
5071
5072         I915_WRITE(FP0(pipe), fp);
5073         I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
5074
5075         POSTING_READ(DPLL(pipe));
5076         udelay(150);
5077
5078         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5079          * This is an exception to the general rule that mode_set doesn't turn
5080          * things on.
5081          */
5082         if (is_lvds) {
5083                 temp = I915_READ(LVDS);
5084                 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
5085                 if (pipe == 1) {
5086                         temp |= LVDS_PIPEB_SELECT;
5087                 } else {
5088                         temp &= ~LVDS_PIPEB_SELECT;
5089                 }
5090                 /* set the corresponsding LVDS_BORDER bit */
5091                 temp |= dev_priv->lvds_border_bits;
5092                 /* Set the B0-B3 data pairs corresponding to whether we're going to
5093                  * set the DPLLs for dual-channel mode or not.
5094                  */
5095                 if (clock.p2 == 7)
5096                         temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
5097                 else
5098                         temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
5099
5100                 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
5101                  * appropriately here, but we need to look more thoroughly into how
5102                  * panels behave in the two modes.
5103                  */
5104                 /* set the dithering flag on LVDS as needed */
5105                 if (INTEL_INFO(dev)->gen >= 4) {
5106                         if (dev_priv->lvds_dither)
5107                                 temp |= LVDS_ENABLE_DITHER;
5108                         else
5109                                 temp &= ~LVDS_ENABLE_DITHER;
5110                 }
5111                 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5112                         lvds_sync |= LVDS_HSYNC_POLARITY;
5113                 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5114                         lvds_sync |= LVDS_VSYNC_POLARITY;
5115                 if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
5116                     != lvds_sync) {
5117                         char flags[2] = "-+";
5118                         DRM_INFO("Changing LVDS panel from "
5119                                  "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
5120                                  flags[!(temp & LVDS_HSYNC_POLARITY)],
5121                                  flags[!(temp & LVDS_VSYNC_POLARITY)],
5122                                  flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
5123                                  flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
5124                         temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5125                         temp |= lvds_sync;
5126                 }
5127                 I915_WRITE(LVDS, temp);
5128         }
5129
5130         if (is_dp) {
5131                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5132         }
5133
5134         I915_WRITE(DPLL(pipe), dpll);
5135
5136         /* Wait for the clocks to stabilize. */
5137         POSTING_READ(DPLL(pipe));
5138         udelay(150);
5139
5140         if (INTEL_INFO(dev)->gen >= 4) {
5141                 temp = 0;
5142                 if (is_sdvo) {
5143                         temp = intel_mode_get_pixel_multiplier(adjusted_mode);
5144                         if (temp > 1)
5145                                 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5146                         else
5147                                 temp = 0;
5148                 }
5149                 I915_WRITE(DPLL_MD(pipe), temp);
5150         } else {
5151                 /* The pixel multiplier can only be updated once the
5152                  * DPLL is enabled and the clocks are stable.
5153                  *
5154                  * So write it again.
5155                  */
5156                 I915_WRITE(DPLL(pipe), dpll);
5157         }
5158
5159         intel_crtc->lowfreq_avail = false;
5160         if (is_lvds && has_reduced_clock && i915_powersave) {
5161                 I915_WRITE(FP1(pipe), fp2);
5162                 intel_crtc->lowfreq_avail = true;
5163                 if (HAS_PIPE_CXSR(dev)) {
5164                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
5165                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5166                 }
5167         } else {
5168                 I915_WRITE(FP1(pipe), fp);
5169                 if (HAS_PIPE_CXSR(dev)) {
5170                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
5171                         pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
5172                 }
5173         }
5174
5175         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5176                 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5177                 /* the chip adds 2 halflines automatically */
5178                 adjusted_mode->crtc_vdisplay -= 1;
5179                 adjusted_mode->crtc_vtotal -= 1;
5180                 adjusted_mode->crtc_vblank_start -= 1;
5181                 adjusted_mode->crtc_vblank_end -= 1;
5182                 adjusted_mode->crtc_vsync_end -= 1;
5183                 adjusted_mode->crtc_vsync_start -= 1;
5184         } else
5185                 pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */
5186
5187         I915_WRITE(HTOTAL(pipe),
5188                    (adjusted_mode->crtc_hdisplay - 1) |
5189                    ((adjusted_mode->crtc_htotal - 1) << 16));
5190         I915_WRITE(HBLANK(pipe),
5191                    (adjusted_mode->crtc_hblank_start - 1) |
5192                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
5193         I915_WRITE(HSYNC(pipe),
5194                    (adjusted_mode->crtc_hsync_start - 1) |
5195                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
5196
5197         I915_WRITE(VTOTAL(pipe),
5198                    (adjusted_mode->crtc_vdisplay - 1) |
5199                    ((adjusted_mode->crtc_vtotal - 1) << 16));
5200         I915_WRITE(VBLANK(pipe),
5201                    (adjusted_mode->crtc_vblank_start - 1) |
5202                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
5203         I915_WRITE(VSYNC(pipe),
5204                    (adjusted_mode->crtc_vsync_start - 1) |
5205                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
5206
5207         /* pipesrc and dspsize control the size that is scaled from,
5208          * which should always be the user's requested size.
5209          */
5210         I915_WRITE(DSPSIZE(plane),
5211                    ((mode->vdisplay - 1) << 16) |
5212                    (mode->hdisplay - 1));
5213         I915_WRITE(DSPPOS(plane), 0);
5214         I915_WRITE(PIPESRC(pipe),
5215                    ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
5216
5217         I915_WRITE(PIPECONF(pipe), pipeconf);
5218         POSTING_READ(PIPECONF(pipe));
5219         intel_enable_pipe(dev_priv, pipe, false);
5220
5221         intel_wait_for_vblank(dev, pipe);
5222
5223         I915_WRITE(DSPCNTR(plane), dspcntr);
5224         POSTING_READ(DSPCNTR(plane));
5225         intel_enable_plane(dev_priv, plane, pipe);
5226
5227         ret = intel_pipe_set_base(crtc, x, y, old_fb);
5228
5229         intel_update_watermarks(dev);
5230
5231         return ret;
5232 }
5233
5234 /*
5235  * Initialize reference clocks when the driver loads
5236  */
5237 void ironlake_init_pch_refclk(struct drm_device *dev)
5238 {
5239         struct drm_i915_private *dev_priv = dev->dev_private;
5240         struct drm_mode_config *mode_config = &dev->mode_config;
5241         struct intel_encoder *encoder;
5242         u32 temp;
5243         bool has_lvds = false;
5244         bool has_cpu_edp = false;
5245         bool has_pch_edp = false;
5246         bool has_panel = false;
5247         bool has_ck505 = false;
5248         bool can_ssc = false;
5249
5250         /* We need to take the global config into account */
5251         list_for_each_entry(encoder, &mode_config->encoder_list,
5252                             base.head) {
5253                 switch (encoder->type) {
5254                 case INTEL_OUTPUT_LVDS:
5255                         has_panel = true;
5256                         has_lvds = true;
5257                         break;
5258                 case INTEL_OUTPUT_EDP:
5259                         has_panel = true;
5260                         if (intel_encoder_is_pch_edp(&encoder->base))
5261                                 has_pch_edp = true;
5262                         else
5263                                 has_cpu_edp = true;
5264                         break;
5265                 }
5266         }
5267
5268         if (HAS_PCH_IBX(dev)) {
5269                 has_ck505 = dev_priv->display_clock_mode;
5270                 can_ssc = has_ck505;
5271         } else {
5272                 has_ck505 = false;
5273                 can_ssc = true;
5274         }
5275
5276         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
5277                       has_panel, has_lvds, has_pch_edp, has_cpu_edp,
5278                       has_ck505);
5279
5280         /* Ironlake: try to setup display ref clock before DPLL
5281          * enabling. This is only under driver's control after
5282          * PCH B stepping, previous chipset stepping should be
5283          * ignoring this setting.
5284          */
5285         temp = I915_READ(PCH_DREF_CONTROL);
5286         /* Always enable nonspread source */
5287         temp &= ~DREF_NONSPREAD_SOURCE_MASK;
5288
5289         if (has_ck505)
5290                 temp |= DREF_NONSPREAD_CK505_ENABLE;
5291         else
5292                 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
5293
5294         if (has_panel) {
5295                 temp &= ~DREF_SSC_SOURCE_MASK;
5296                 temp |= DREF_SSC_SOURCE_ENABLE;
5297
5298                 /* SSC must be turned on before enabling the CPU output  */
5299                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5300                         DRM_DEBUG_KMS("Using SSC on panel\n");
5301                         temp |= DREF_SSC1_ENABLE;
5302                 }
5303
5304                 /* Get SSC going before enabling the outputs */
5305                 I915_WRITE(PCH_DREF_CONTROL, temp);
5306                 POSTING_READ(PCH_DREF_CONTROL);
5307                 udelay(200);
5308
5309                 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5310
5311                 /* Enable CPU source on CPU attached eDP */
5312                 if (has_cpu_edp) {
5313                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5314                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
5315                                 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5316                         }
5317                         else
5318                                 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5319                 } else
5320                         temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5321
5322                 I915_WRITE(PCH_DREF_CONTROL, temp);
5323                 POSTING_READ(PCH_DREF_CONTROL);
5324                 udelay(200);
5325         } else {
5326                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5327
5328                 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5329
5330                 /* Turn off CPU output */
5331                 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5332
5333                 I915_WRITE(PCH_DREF_CONTROL, temp);
5334                 POSTING_READ(PCH_DREF_CONTROL);
5335                 udelay(200);
5336
5337                 /* Turn off the SSC source */
5338                 temp &= ~DREF_SSC_SOURCE_MASK;
5339                 temp |= DREF_SSC_SOURCE_DISABLE;
5340
5341                 /* Turn off SSC1 */
5342                 temp &= ~ DREF_SSC1_ENABLE;
5343
5344                 I915_WRITE(PCH_DREF_CONTROL, temp);
5345                 POSTING_READ(PCH_DREF_CONTROL);
5346                 udelay(200);
5347         }
5348 }
5349
5350 static int ironlake_get_refclk(struct drm_crtc *crtc)
5351 {
5352         struct drm_device *dev = crtc->dev;
5353         struct drm_i915_private *dev_priv = dev->dev_private;
5354         struct intel_encoder *encoder;
5355         struct drm_mode_config *mode_config = &dev->mode_config;
5356         struct intel_encoder *edp_encoder = NULL;
5357         int num_connectors = 0;
5358         bool is_lvds = false;
5359
5360         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5361                 if (encoder->base.crtc != crtc)
5362                         continue;
5363
5364                 switch (encoder->type) {
5365                 case INTEL_OUTPUT_LVDS:
5366                         is_lvds = true;
5367                         break;
5368                 case INTEL_OUTPUT_EDP:
5369                         edp_encoder = encoder;
5370                         break;
5371                 }
5372                 num_connectors++;
5373         }
5374
5375         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5376                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5377                               dev_priv->lvds_ssc_freq);
5378                 return dev_priv->lvds_ssc_freq * 1000;
5379         }
5380
5381         return 120000;
5382 }
5383
5384 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5385                                   struct drm_display_mode *mode,
5386                                   struct drm_display_mode *adjusted_mode,
5387                                   int x, int y,
5388                                   struct drm_framebuffer *old_fb)
5389 {
5390         struct drm_device *dev = crtc->dev;
5391         struct drm_i915_private *dev_priv = dev->dev_private;
5392         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5393         int pipe = intel_crtc->pipe;
5394         int plane = intel_crtc->plane;
5395         int refclk, num_connectors = 0;
5396         intel_clock_t clock, reduced_clock;
5397         u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
5398         bool ok, has_reduced_clock = false, is_sdvo = false;
5399         bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
5400         struct intel_encoder *has_edp_encoder = NULL;
5401         struct drm_mode_config *mode_config = &dev->mode_config;
5402         struct intel_encoder *encoder;
5403         const intel_limit_t *limit;
5404         int ret;
5405         struct fdi_m_n m_n = {0};
5406         u32 temp;
5407         u32 lvds_sync = 0;
5408         int target_clock, pixel_multiplier, lane, link_bw, factor;
5409         unsigned int pipe_bpp;
5410         bool dither;
5411
5412         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5413                 if (encoder->base.crtc != crtc)
5414                         continue;
5415
5416                 switch (encoder->type) {
5417                 case INTEL_OUTPUT_LVDS:
5418                         is_lvds = true;
5419                         break;
5420                 case INTEL_OUTPUT_SDVO:
5421                 case INTEL_OUTPUT_HDMI:
5422                         is_sdvo = true;
5423                         if (encoder->needs_tv_clock)
5424                                 is_tv = true;
5425                         break;
5426                 case INTEL_OUTPUT_TVOUT:
5427                         is_tv = true;
5428                         break;
5429                 case INTEL_OUTPUT_ANALOG:
5430                         is_crt = true;
5431                         break;
5432                 case INTEL_OUTPUT_DISPLAYPORT:
5433                         is_dp = true;
5434                         break;
5435                 case INTEL_OUTPUT_EDP:
5436                         has_edp_encoder = encoder;
5437                         break;
5438                 }
5439
5440                 num_connectors++;
5441         }
5442
5443         refclk = ironlake_get_refclk(crtc);
5444
5445         /*
5446          * Returns a set of divisors for the desired target clock with the given
5447          * refclk, or FALSE.  The returned values represent the clock equation:
5448          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5449          */
5450         limit = intel_limit(crtc, refclk);
5451         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
5452         if (!ok) {
5453                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5454                 return -EINVAL;
5455         }
5456
5457         /* Ensure that the cursor is valid for the new mode before changing... */
5458         intel_crtc_update_cursor(crtc, true);
5459
5460         if (is_lvds && dev_priv->lvds_downclock_avail) {
5461                 has_reduced_clock = limit->find_pll(limit, crtc,
5462                                                     dev_priv->lvds_downclock,
5463                                                     refclk,
5464                                                     &reduced_clock);
5465                 if (has_reduced_clock && (clock.p != reduced_clock.p)) {
5466                         /*
5467                          * If the different P is found, it means that we can't
5468                          * switch the display clock by using the FP0/FP1.
5469                          * In such case we will disable the LVDS downclock
5470                          * feature.
5471                          */
5472                         DRM_DEBUG_KMS("Different P is found for "
5473                                       "LVDS clock/downclock\n");
5474                         has_reduced_clock = 0;
5475                 }
5476         }
5477         /* SDVO TV has fixed PLL values depend on its clock range,
5478            this mirrors vbios setting. */
5479         if (is_sdvo && is_tv) {
5480                 if (adjusted_mode->clock >= 100000
5481                     && adjusted_mode->clock < 140500) {
5482                         clock.p1 = 2;
5483                         clock.p2 = 10;
5484                         clock.n = 3;
5485                         clock.m1 = 16;
5486                         clock.m2 = 8;
5487                 } else if (adjusted_mode->clock >= 140500
5488                            && adjusted_mode->clock <= 200000) {
5489                         clock.p1 = 1;
5490                         clock.p2 = 10;
5491                         clock.n = 6;
5492                         clock.m1 = 12;
5493                         clock.m2 = 8;
5494                 }
5495         }
5496
5497         /* FDI link */
5498         pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5499         lane = 0;
5500         /* CPU eDP doesn't require FDI link, so just set DP M/N
5501            according to current link config */
5502         if (has_edp_encoder &&
5503             !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5504                 target_clock = mode->clock;
5505                 intel_edp_link_config(has_edp_encoder,
5506                                       &lane, &link_bw);
5507         } else {
5508                 /* [e]DP over FDI requires target mode clock
5509                    instead of link clock */
5510                 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
5511                         target_clock = mode->clock;
5512                 else
5513                         target_clock = adjusted_mode->clock;
5514
5515                 /* FDI is a binary signal running at ~2.7GHz, encoding
5516                  * each output octet as 10 bits. The actual frequency
5517                  * is stored as a divider into a 100MHz clock, and the
5518                  * mode pixel clock is stored in units of 1KHz.
5519                  * Hence the bw of each lane in terms of the mode signal
5520                  * is:
5521                  */
5522                 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5523         }
5524
5525         /* determine panel color depth */
5526         temp = I915_READ(PIPECONF(pipe));
5527         temp &= ~PIPE_BPC_MASK;
5528         dither = intel_choose_pipe_bpp_dither(crtc, &pipe_bpp, adjusted_mode);
5529         switch (pipe_bpp) {
5530         case 18:
5531                 temp |= PIPE_6BPC;
5532                 break;
5533         case 24:
5534                 temp |= PIPE_8BPC;
5535                 break;
5536         case 30:
5537                 temp |= PIPE_10BPC;
5538                 break;
5539         case 36:
5540                 temp |= PIPE_12BPC;
5541                 break;
5542         default:
5543                 WARN(1, "intel_choose_pipe_bpp returned invalid value %d\n",
5544                         pipe_bpp);
5545                 temp |= PIPE_8BPC;
5546                 pipe_bpp = 24;
5547                 break;
5548         }
5549
5550         intel_crtc->bpp = pipe_bpp;
5551         I915_WRITE(PIPECONF(pipe), temp);
5552
5553         if (!lane) {
5554                 /*
5555                  * Account for spread spectrum to avoid
5556                  * oversubscribing the link. Max center spread
5557                  * is 2.5%; use 5% for safety's sake.
5558                  */
5559                 u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
5560                 lane = bps / (link_bw * 8) + 1;
5561         }
5562
5563         intel_crtc->fdi_lanes = lane;
5564
5565         if (pixel_multiplier > 1)
5566                 link_bw *= pixel_multiplier;
5567         ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
5568                              &m_n);
5569
5570         fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5571         if (has_reduced_clock)
5572                 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5573                         reduced_clock.m2;
5574
5575         /* Enable autotuning of the PLL clock (if permissible) */
5576         factor = 21;
5577         if (is_lvds) {
5578                 if ((intel_panel_use_ssc(dev_priv) &&
5579                      dev_priv->lvds_ssc_freq == 100) ||
5580                     (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
5581                         factor = 25;
5582         } else if (is_sdvo && is_tv)
5583                 factor = 20;
5584
5585         if (clock.m < factor * clock.n)
5586                 fp |= FP_CB_TUNE;
5587
5588         dpll = 0;
5589
5590         if (is_lvds)
5591                 dpll |= DPLLB_MODE_LVDS;
5592         else
5593                 dpll |= DPLLB_MODE_DAC_SERIAL;
5594         if (is_sdvo) {
5595                 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5596                 if (pixel_multiplier > 1) {
5597                         dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
5598                 }
5599                 dpll |= DPLL_DVO_HIGH_SPEED;
5600         }
5601         if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
5602                 dpll |= DPLL_DVO_HIGH_SPEED;
5603
5604         /* compute bitmask from p1 value */
5605         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5606         /* also FPA1 */
5607         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5608
5609         switch (clock.p2) {
5610         case 5:
5611                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5612                 break;
5613         case 7:
5614                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5615                 break;
5616         case 10:
5617                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5618                 break;
5619         case 14:
5620                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5621                 break;
5622         }
5623
5624         if (is_sdvo && is_tv)
5625                 dpll |= PLL_REF_INPUT_TVCLKINBC;
5626         else if (is_tv)
5627                 /* XXX: just matching BIOS for now */
5628                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
5629                 dpll |= 3;
5630         else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5631                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5632         else
5633                 dpll |= PLL_REF_INPUT_DREFCLK;
5634
5635         /* setup pipeconf */
5636         pipeconf = I915_READ(PIPECONF(pipe));
5637
5638         /* Set up the display plane register */
5639         dspcntr = DISPPLANE_GAMMA_ENABLE;
5640
5641         DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5642         drm_mode_debug_printmodeline(mode);
5643
5644         /* PCH eDP needs FDI, but CPU eDP does not */
5645         if (!intel_crtc->no_pll) {
5646                 if (!has_edp_encoder ||
5647                     intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5648                         I915_WRITE(PCH_FP0(pipe), fp);
5649                         I915_WRITE(PCH_DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
5650
5651                         POSTING_READ(PCH_DPLL(pipe));
5652                         udelay(150);
5653                 }
5654         } else {
5655                 if (dpll == (I915_READ(PCH_DPLL(0)) & 0x7fffffff) &&
5656                     fp == I915_READ(PCH_FP0(0))) {
5657                         intel_crtc->use_pll_a = true;
5658                         DRM_DEBUG_KMS("using pipe a dpll\n");
5659                 } else if (dpll == (I915_READ(PCH_DPLL(1)) & 0x7fffffff) &&
5660                            fp == I915_READ(PCH_FP0(1))) {
5661                         intel_crtc->use_pll_a = false;
5662                         DRM_DEBUG_KMS("using pipe b dpll\n");
5663                 } else {
5664                         DRM_DEBUG_KMS("no matching PLL configuration for pipe 2\n");
5665                         return -EINVAL;
5666                 }
5667         }
5668
5669         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5670          * This is an exception to the general rule that mode_set doesn't turn
5671          * things on.
5672          */
5673         if (is_lvds) {
5674                 temp = I915_READ(PCH_LVDS);
5675                 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
5676                 if (HAS_PCH_CPT(dev)) {
5677                         temp &= ~PORT_TRANS_SEL_MASK;
5678                         temp |= PORT_TRANS_SEL_CPT(pipe);
5679                 } else {
5680                         if (pipe == 1)
5681                                 temp |= LVDS_PIPEB_SELECT;
5682                         else
5683                                 temp &= ~LVDS_PIPEB_SELECT;
5684                 }
5685
5686                 /* set the corresponsding LVDS_BORDER bit */
5687                 temp |= dev_priv->lvds_border_bits;
5688                 /* Set the B0-B3 data pairs corresponding to whether we're going to
5689                  * set the DPLLs for dual-channel mode or not.
5690                  */
5691                 if (clock.p2 == 7)
5692                         temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
5693                 else
5694                         temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
5695
5696                 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
5697                  * appropriately here, but we need to look more thoroughly into how
5698                  * panels behave in the two modes.
5699                  */
5700                 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5701                         lvds_sync |= LVDS_HSYNC_POLARITY;
5702                 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5703                         lvds_sync |= LVDS_VSYNC_POLARITY;
5704                 if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
5705                     != lvds_sync) {
5706                         char flags[2] = "-+";
5707                         DRM_INFO("Changing LVDS panel from "
5708                                  "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
5709                                  flags[!(temp & LVDS_HSYNC_POLARITY)],
5710                                  flags[!(temp & LVDS_VSYNC_POLARITY)],
5711                                  flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
5712                                  flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
5713                         temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5714                         temp |= lvds_sync;
5715                 }
5716                 I915_WRITE(PCH_LVDS, temp);
5717         }
5718
5719         pipeconf &= ~PIPECONF_DITHER_EN;
5720         pipeconf &= ~PIPECONF_DITHER_TYPE_MASK;
5721         if ((is_lvds && dev_priv->lvds_dither) || dither) {
5722                 pipeconf |= PIPECONF_DITHER_EN;
5723                 pipeconf |= PIPECONF_DITHER_TYPE_SP;
5724         }
5725         if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5726                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5727         } else {
5728                 /* For non-DP output, clear any trans DP clock recovery setting.*/
5729                 I915_WRITE(TRANSDATA_M1(pipe), 0);
5730                 I915_WRITE(TRANSDATA_N1(pipe), 0);
5731                 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5732                 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
5733         }
5734
5735         if (!intel_crtc->no_pll &&
5736             (!has_edp_encoder ||
5737              intel_encoder_is_pch_edp(&has_edp_encoder->base))) {
5738                 I915_WRITE(PCH_DPLL(pipe), dpll);
5739
5740                 /* Wait for the clocks to stabilize. */
5741                 POSTING_READ(PCH_DPLL(pipe));
5742                 udelay(150);
5743
5744                 /* The pixel multiplier can only be updated once the
5745                  * DPLL is enabled and the clocks are stable.
5746                  *
5747                  * So write it again.
5748                  */
5749                 I915_WRITE(PCH_DPLL(pipe), dpll);
5750         }
5751
5752         intel_crtc->lowfreq_avail = false;
5753         if (!intel_crtc->no_pll) {
5754                 if (is_lvds && has_reduced_clock && i915_powersave) {
5755                         I915_WRITE(PCH_FP1(pipe), fp2);
5756                         intel_crtc->lowfreq_avail = true;
5757                         if (HAS_PIPE_CXSR(dev)) {
5758                                 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
5759                                 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5760                         }
5761                 } else {
5762                         I915_WRITE(PCH_FP1(pipe), fp);
5763                         if (HAS_PIPE_CXSR(dev)) {
5764                                 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
5765                                 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
5766                         }
5767                 }
5768         }
5769
5770         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5771                 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5772                 /* the chip adds 2 halflines automatically */
5773                 adjusted_mode->crtc_vdisplay -= 1;
5774                 adjusted_mode->crtc_vtotal -= 1;
5775                 adjusted_mode->crtc_vblank_start -= 1;
5776                 adjusted_mode->crtc_vblank_end -= 1;
5777                 adjusted_mode->crtc_vsync_end -= 1;
5778                 adjusted_mode->crtc_vsync_start -= 1;
5779         } else
5780                 pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */
5781
5782         I915_WRITE(HTOTAL(pipe),
5783                    (adjusted_mode->crtc_hdisplay - 1) |
5784                    ((adjusted_mode->crtc_htotal - 1) << 16));
5785         I915_WRITE(HBLANK(pipe),
5786                    (adjusted_mode->crtc_hblank_start - 1) |
5787                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
5788         I915_WRITE(HSYNC(pipe),
5789                    (adjusted_mode->crtc_hsync_start - 1) |
5790                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
5791
5792         I915_WRITE(VTOTAL(pipe),
5793                    (adjusted_mode->crtc_vdisplay - 1) |
5794                    ((adjusted_mode->crtc_vtotal - 1) << 16));
5795         I915_WRITE(VBLANK(pipe),
5796                    (adjusted_mode->crtc_vblank_start - 1) |
5797                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
5798         I915_WRITE(VSYNC(pipe),
5799                    (adjusted_mode->crtc_vsync_start - 1) |
5800                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
5801
5802         /* pipesrc controls the size that is scaled from, which should
5803          * always be the user's requested size.
5804          */
5805         I915_WRITE(PIPESRC(pipe),
5806                    ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
5807
5808         I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
5809         I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
5810         I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
5811         I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
5812
5813         if (has_edp_encoder &&
5814             !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5815                 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
5816         }
5817
5818         I915_WRITE(PIPECONF(pipe), pipeconf);
5819         POSTING_READ(PIPECONF(pipe));
5820
5821         intel_wait_for_vblank(dev, pipe);
5822
5823         if (IS_GEN5(dev)) {
5824                 /* enable address swizzle for tiling buffer */
5825                 temp = I915_READ(DISP_ARB_CTL);
5826                 I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING);
5827         }
5828
5829         I915_WRITE(DSPCNTR(plane), dspcntr);
5830         POSTING_READ(DSPCNTR(plane));
5831
5832         ret = intel_pipe_set_base(crtc, x, y, old_fb);
5833
5834         intel_update_watermarks(dev);
5835
5836         return ret;
5837 }
5838
5839 static int intel_crtc_mode_set(struct drm_crtc *crtc,
5840                                struct drm_display_mode *mode,
5841                                struct drm_display_mode *adjusted_mode,
5842                                int x, int y,
5843                                struct drm_framebuffer *old_fb)
5844 {
5845         struct drm_device *dev = crtc->dev;
5846         struct drm_i915_private *dev_priv = dev->dev_private;
5847         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5848         int pipe = intel_crtc->pipe;
5849         int ret;
5850
5851         drm_vblank_pre_modeset(dev, pipe);
5852
5853         ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
5854                                               x, y, old_fb);
5855
5856         drm_vblank_post_modeset(dev, pipe);
5857
5858         intel_crtc->dpms_mode = DRM_MODE_DPMS_ON;
5859
5860         return ret;
5861 }
5862
5863 static void g4x_write_eld(struct drm_connector *connector,
5864                           struct drm_crtc *crtc)
5865 {
5866         struct drm_i915_private *dev_priv = connector->dev->dev_private;
5867         uint8_t *eld = connector->eld;
5868         uint32_t eldv;
5869         uint32_t len;
5870         uint32_t i;
5871
5872         i = I915_READ(G4X_AUD_VID_DID);
5873
5874         if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
5875                 eldv = G4X_ELDV_DEVCL_DEVBLC;
5876         else
5877                 eldv = G4X_ELDV_DEVCTG;
5878
5879         i = I915_READ(G4X_AUD_CNTL_ST);
5880         i &= ~(eldv | G4X_ELD_ADDR);
5881         len = (i >> 9) & 0x1f;          /* ELD buffer size */
5882         I915_WRITE(G4X_AUD_CNTL_ST, i);
5883
5884         if (!eld[0])
5885                 return;
5886
5887         len = min_t(uint8_t, eld[2], len);
5888         DRM_DEBUG_DRIVER("ELD size %d\n", len);
5889         for (i = 0; i < len; i++)
5890                 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
5891
5892         i = I915_READ(G4X_AUD_CNTL_ST);
5893         i |= eldv;
5894         I915_WRITE(G4X_AUD_CNTL_ST, i);
5895 }
5896
5897 static void ironlake_write_eld(struct drm_connector *connector,
5898                                      struct drm_crtc *crtc)
5899 {
5900         struct drm_i915_private *dev_priv = connector->dev->dev_private;
5901         uint8_t *eld = connector->eld;
5902         uint32_t eldv;
5903         uint32_t i;
5904         int len;
5905         int hdmiw_hdmiedid;
5906         int aud_cntl_st;
5907         int aud_cntrl_st2;
5908
5909         if (HAS_PCH_IBX(connector->dev)) {
5910                 hdmiw_hdmiedid = GEN5_HDMIW_HDMIEDID_A;
5911                 aud_cntl_st = GEN5_AUD_CNTL_ST_A;
5912                 aud_cntrl_st2 = GEN5_AUD_CNTL_ST2;
5913         } else {
5914                 hdmiw_hdmiedid = GEN7_HDMIW_HDMIEDID_A;
5915                 aud_cntl_st = GEN7_AUD_CNTRL_ST_A;
5916                 aud_cntrl_st2 = GEN7_AUD_CNTRL_ST2;
5917         }
5918
5919         i = to_intel_crtc(crtc)->pipe;
5920         hdmiw_hdmiedid += i * 0x100;
5921         aud_cntl_st += i * 0x100;
5922
5923         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(i));
5924
5925         i = I915_READ(aud_cntl_st);
5926         i = (i >> 29) & 0x3;            /* DIP_Port_Select, 0x1 = PortB */
5927         if (!i) {
5928                 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
5929                 /* operate blindly on all ports */
5930                 eldv = GEN5_ELD_VALIDB;
5931                 eldv |= GEN5_ELD_VALIDB << 4;
5932                 eldv |= GEN5_ELD_VALIDB << 8;
5933         } else {
5934                 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
5935                 eldv = GEN5_ELD_VALIDB << ((i - 1) * 4);
5936         }
5937
5938         i = I915_READ(aud_cntrl_st2);
5939         i &= ~eldv;
5940         I915_WRITE(aud_cntrl_st2, i);
5941
5942         if (!eld[0])
5943                 return;
5944
5945         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5946                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5947                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
5948         }
5949
5950         i = I915_READ(aud_cntl_st);
5951         i &= ~GEN5_ELD_ADDRESS;
5952         I915_WRITE(aud_cntl_st, i);
5953
5954         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
5955         DRM_DEBUG_DRIVER("ELD size %d\n", len);
5956         for (i = 0; i < len; i++)
5957                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
5958
5959         i = I915_READ(aud_cntrl_st2);
5960         i |= eldv;
5961         I915_WRITE(aud_cntrl_st2, i);
5962 }
5963
5964 void intel_write_eld(struct drm_encoder *encoder,
5965                      struct drm_display_mode *mode)
5966 {
5967         struct drm_crtc *crtc = encoder->crtc;
5968         struct drm_connector *connector;
5969         struct drm_device *dev = encoder->dev;
5970         struct drm_i915_private *dev_priv = dev->dev_private;
5971
5972         connector = drm_select_eld(encoder, mode);
5973         if (!connector)
5974                 return;
5975
5976         DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5977                          connector->base.id,
5978                          drm_get_connector_name(connector),
5979                          connector->encoder->base.id,
5980                          drm_get_encoder_name(connector->encoder));
5981
5982         connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
5983
5984         if (dev_priv->display.write_eld)
5985                 dev_priv->display.write_eld(connector, crtc);
5986 }
5987
5988 /** Loads the palette/gamma unit for the CRTC with the prepared values */
5989 void intel_crtc_load_lut(struct drm_crtc *crtc)
5990 {
5991         struct drm_device *dev = crtc->dev;
5992         struct drm_i915_private *dev_priv = dev->dev_private;
5993         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5994         int palreg = PALETTE(intel_crtc->pipe);
5995         int i;
5996
5997         /* The clocks have to be on to load the palette. */
5998         if (!crtc->enabled || !intel_crtc->active)
5999                 return;
6000
6001         /* use legacy palette for Ironlake */
6002         if (HAS_PCH_SPLIT(dev))
6003                 palreg = LGC_PALETTE(intel_crtc->pipe);
6004
6005         for (i = 0; i < 256; i++) {
6006                 I915_WRITE(palreg + 4 * i,
6007                            (intel_crtc->lut_r[i] << 16) |
6008                            (intel_crtc->lut_g[i] << 8) |
6009                            intel_crtc->lut_b[i]);
6010         }
6011 }
6012
6013 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6014 {
6015         struct drm_device *dev = crtc->dev;
6016         struct drm_i915_private *dev_priv = dev->dev_private;
6017         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6018         bool visible = base != 0;
6019         u32 cntl;
6020
6021         if (intel_crtc->cursor_visible == visible)
6022                 return;
6023
6024         cntl = I915_READ(_CURACNTR);
6025         if (visible) {
6026                 /* On these chipsets we can only modify the base whilst
6027                  * the cursor is disabled.
6028                  */
6029                 I915_WRITE(_CURABASE, base);
6030
6031                 cntl &= ~(CURSOR_FORMAT_MASK);
6032                 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6033                 cntl |= CURSOR_ENABLE |
6034                         CURSOR_GAMMA_ENABLE |
6035                         CURSOR_FORMAT_ARGB;
6036         } else
6037                 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
6038         I915_WRITE(_CURACNTR, cntl);
6039
6040         intel_crtc->cursor_visible = visible;
6041 }
6042
6043 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6044 {
6045         struct drm_device *dev = crtc->dev;
6046         struct drm_i915_private *dev_priv = dev->dev_private;
6047         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6048         int pipe = intel_crtc->pipe;
6049         bool visible = base != 0;
6050
6051         if (intel_crtc->cursor_visible != visible) {
6052                 uint32_t cntl = I915_READ(CURCNTR(pipe));
6053                 if (base) {
6054                         cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6055                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6056                         cntl |= pipe << 28; /* Connect to correct pipe */
6057                 } else {
6058                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6059                         cntl |= CURSOR_MODE_DISABLE;
6060                 }
6061                 I915_WRITE(CURCNTR(pipe), cntl);
6062
6063                 intel_crtc->cursor_visible = visible;
6064         }
6065         /* and commit changes on next vblank */
6066         POSTING_READ(CURCNTR(pipe));
6067         I915_WRITE(CURBASE(pipe), base);
6068         POSTING_READ(CURBASE(pipe));
6069 }
6070
6071 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6072 {
6073         struct drm_device *dev = crtc->dev;
6074         struct drm_i915_private *dev_priv = dev->dev_private;
6075         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6076         int pipe = intel_crtc->pipe;
6077         bool visible = base != 0;
6078
6079         if (intel_crtc->cursor_visible != visible) {
6080                 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6081                 if (base) {
6082                         cntl &= ~CURSOR_MODE;
6083                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6084                 } else {
6085                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6086                         cntl |= CURSOR_MODE_DISABLE;
6087                 }
6088                 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6089
6090                 intel_crtc->cursor_visible = visible;
6091         }
6092         /* and commit changes on next vblank */
6093         POSTING_READ(CURCNTR_IVB(pipe));
6094         I915_WRITE(CURBASE_IVB(pipe), base);
6095         POSTING_READ(CURBASE_IVB(pipe));
6096 }
6097
6098 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6099 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6100                                      bool on)
6101 {
6102         struct drm_device *dev = crtc->dev;
6103         struct drm_i915_private *dev_priv = dev->dev_private;
6104         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6105         int pipe = intel_crtc->pipe;
6106         int x = intel_crtc->cursor_x;
6107         int y = intel_crtc->cursor_y;
6108         u32 base, pos;
6109         bool visible;
6110
6111         pos = 0;
6112
6113         if (on && crtc->enabled && crtc->fb) {
6114                 base = intel_crtc->cursor_addr;
6115                 if (x > (int) crtc->fb->width)
6116                         base = 0;
6117
6118                 if (y > (int) crtc->fb->height)
6119                         base = 0;
6120         } else
6121                 base = 0;
6122
6123         if (x < 0) {
6124                 if (x + intel_crtc->cursor_width < 0)
6125                         base = 0;
6126
6127                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6128                 x = -x;
6129         }
6130         pos |= x << CURSOR_X_SHIFT;
6131
6132         if (y < 0) {
6133                 if (y + intel_crtc->cursor_height < 0)
6134                         base = 0;
6135
6136                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6137                 y = -y;
6138         }
6139         pos |= y << CURSOR_Y_SHIFT;
6140
6141         visible = base != 0;
6142         if (!visible && !intel_crtc->cursor_visible)
6143                 return;
6144
6145         if (IS_IVYBRIDGE(dev)) {
6146                 I915_WRITE(CURPOS_IVB(pipe), pos);
6147                 ivb_update_cursor(crtc, base);
6148         } else {
6149                 I915_WRITE(CURPOS(pipe), pos);
6150                 if (IS_845G(dev) || IS_I865G(dev))
6151                         i845_update_cursor(crtc, base);
6152                 else
6153                         i9xx_update_cursor(crtc, base);
6154         }
6155
6156         if (visible)
6157                 intel_mark_busy(dev, to_intel_framebuffer(crtc->fb)->obj);
6158 }
6159
6160 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
6161                                  struct drm_file *file,
6162                                  uint32_t handle,
6163                                  uint32_t width, uint32_t height)
6164 {
6165         struct drm_device *dev = crtc->dev;
6166         struct drm_i915_private *dev_priv = dev->dev_private;
6167         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6168         struct drm_i915_gem_object *obj;
6169         uint32_t addr;
6170         int ret;
6171
6172         DRM_DEBUG_KMS("\n");
6173
6174         /* if we want to turn off the cursor ignore width and height */
6175         if (!handle) {
6176                 DRM_DEBUG_KMS("cursor off\n");
6177                 addr = 0;
6178                 obj = NULL;
6179                 mutex_lock(&dev->struct_mutex);
6180                 goto finish;
6181         }
6182
6183         /* Currently we only support 64x64 cursors */
6184         if (width != 64 || height != 64) {
6185                 DRM_ERROR("we currently only support 64x64 cursors\n");
6186                 return -EINVAL;
6187         }
6188
6189         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
6190         if (&obj->base == NULL)
6191                 return -ENOENT;
6192
6193         if (obj->base.size < width * height * 4) {
6194                 DRM_ERROR("buffer is to small\n");
6195                 ret = -ENOMEM;
6196                 goto fail;
6197         }
6198
6199         /* we only need to pin inside GTT if cursor is non-phy */
6200         mutex_lock(&dev->struct_mutex);
6201         if (!dev_priv->info->cursor_needs_physical) {
6202                 if (obj->tiling_mode) {
6203                         DRM_ERROR("cursor cannot be tiled\n");
6204                         ret = -EINVAL;
6205                         goto fail_locked;
6206                 }
6207
6208                 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
6209                 if (ret) {
6210                         DRM_ERROR("failed to move cursor bo into the GTT\n");
6211                         goto fail_locked;
6212                 }
6213
6214                 ret = i915_gem_object_put_fence(obj);
6215                 if (ret) {
6216                         DRM_ERROR("failed to release fence for cursor");
6217                         goto fail_unpin;
6218                 }
6219
6220                 addr = obj->gtt_offset;
6221         } else {
6222                 int align = IS_I830(dev) ? 16 * 1024 : 256;
6223                 ret = i915_gem_attach_phys_object(dev, obj,
6224                                                   (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6225                                                   align);
6226                 if (ret) {
6227                         DRM_ERROR("failed to attach phys object\n");
6228                         goto fail_locked;
6229                 }
6230                 addr = obj->phys_obj->handle->busaddr;
6231         }
6232
6233         if (IS_GEN2(dev))
6234                 I915_WRITE(CURSIZE, (height << 12) | width);
6235
6236  finish:
6237         if (intel_crtc->cursor_bo) {
6238                 if (dev_priv->info->cursor_needs_physical) {
6239                         if (intel_crtc->cursor_bo != obj)
6240                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6241                 } else
6242                         i915_gem_object_unpin(intel_crtc->cursor_bo);
6243                 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
6244         }
6245
6246         mutex_unlock(&dev->struct_mutex);
6247
6248         intel_crtc->cursor_addr = addr;
6249         intel_crtc->cursor_bo = obj;
6250         intel_crtc->cursor_width = width;
6251         intel_crtc->cursor_height = height;
6252
6253         intel_crtc_update_cursor(crtc, true);
6254
6255         return 0;
6256 fail_unpin:
6257         i915_gem_object_unpin(obj);
6258 fail_locked:
6259         mutex_unlock(&dev->struct_mutex);
6260 fail:
6261         drm_gem_object_unreference_unlocked(&obj->base);
6262         return ret;
6263 }
6264
6265 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6266 {
6267         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6268
6269         intel_crtc->cursor_x = x;
6270         intel_crtc->cursor_y = y;
6271
6272         intel_crtc_update_cursor(crtc, true);
6273
6274         return 0;
6275 }
6276
6277 /** Sets the color ramps on behalf of RandR */
6278 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6279                                  u16 blue, int regno)
6280 {
6281         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6282
6283         intel_crtc->lut_r[regno] = red >> 8;
6284         intel_crtc->lut_g[regno] = green >> 8;
6285         intel_crtc->lut_b[regno] = blue >> 8;
6286 }
6287
6288 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6289                              u16 *blue, int regno)
6290 {
6291         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6292
6293         *red = intel_crtc->lut_r[regno] << 8;
6294         *green = intel_crtc->lut_g[regno] << 8;
6295         *blue = intel_crtc->lut_b[regno] << 8;
6296 }
6297
6298 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
6299                                  u16 *blue, uint32_t start, uint32_t size)
6300 {
6301         int end = (start + size > 256) ? 256 : start + size, i;
6302         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6303
6304         for (i = start; i < end; i++) {
6305                 intel_crtc->lut_r[i] = red[i] >> 8;
6306                 intel_crtc->lut_g[i] = green[i] >> 8;
6307                 intel_crtc->lut_b[i] = blue[i] >> 8;
6308         }
6309
6310         intel_crtc_load_lut(crtc);
6311 }
6312
6313 /**
6314  * Get a pipe with a simple mode set on it for doing load-based monitor
6315  * detection.
6316  *
6317  * It will be up to the load-detect code to adjust the pipe as appropriate for
6318  * its requirements.  The pipe will be connected to no other encoders.
6319  *
6320  * Currently this code will only succeed if there is a pipe with no encoders
6321  * configured for it.  In the future, it could choose to temporarily disable
6322  * some outputs to free up a pipe for its use.
6323  *
6324  * \return crtc, or NULL if no pipes are available.
6325  */
6326
6327 /* VESA 640x480x72Hz mode to set on the pipe */
6328 static struct drm_display_mode load_detect_mode = {
6329         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6330                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6331 };
6332
6333 static struct drm_framebuffer *
6334 intel_framebuffer_create(struct drm_device *dev,
6335                          struct drm_mode_fb_cmd *mode_cmd,
6336                          struct drm_i915_gem_object *obj)
6337 {
6338         struct intel_framebuffer *intel_fb;
6339         int ret;
6340
6341         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6342         if (!intel_fb) {
6343                 drm_gem_object_unreference_unlocked(&obj->base);
6344                 return ERR_PTR(-ENOMEM);
6345         }
6346
6347         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6348         if (ret) {
6349                 drm_gem_object_unreference_unlocked(&obj->base);
6350                 kfree(intel_fb);
6351                 return ERR_PTR(ret);
6352         }
6353
6354         return &intel_fb->base;
6355 }
6356
6357 static u32
6358 intel_framebuffer_pitch_for_width(int width, int bpp)
6359 {
6360         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6361         return ALIGN(pitch, 64);
6362 }
6363
6364 static u32
6365 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6366 {
6367         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6368         return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6369 }
6370
6371 static struct drm_framebuffer *
6372 intel_framebuffer_create_for_mode(struct drm_device *dev,
6373                                   struct drm_display_mode *mode,
6374                                   int depth, int bpp)
6375 {
6376         struct drm_i915_gem_object *obj;
6377         struct drm_mode_fb_cmd mode_cmd;
6378
6379         obj = i915_gem_alloc_object(dev,
6380                                     intel_framebuffer_size_for_mode(mode, bpp));
6381         if (obj == NULL)
6382                 return ERR_PTR(-ENOMEM);
6383
6384         mode_cmd.width = mode->hdisplay;
6385         mode_cmd.height = mode->vdisplay;
6386         mode_cmd.depth = depth;
6387         mode_cmd.bpp = bpp;
6388         mode_cmd.pitch = intel_framebuffer_pitch_for_width(mode_cmd.width, bpp);
6389
6390         return intel_framebuffer_create(dev, &mode_cmd, obj);
6391 }
6392
6393 static struct drm_framebuffer *
6394 mode_fits_in_fbdev(struct drm_device *dev,
6395                    struct drm_display_mode *mode)
6396 {
6397         struct drm_i915_private *dev_priv = dev->dev_private;
6398         struct drm_i915_gem_object *obj;
6399         struct drm_framebuffer *fb;
6400
6401         if (dev_priv->fbdev == NULL)
6402                 return NULL;
6403
6404         obj = dev_priv->fbdev->ifb.obj;
6405         if (obj == NULL)
6406                 return NULL;
6407
6408         fb = &dev_priv->fbdev->ifb.base;
6409         if (fb->pitch < intel_framebuffer_pitch_for_width(mode->hdisplay,
6410                                                           fb->bits_per_pixel))
6411                 return NULL;
6412
6413         if (obj->base.size < mode->vdisplay * fb->pitch)
6414                 return NULL;
6415
6416         return fb;
6417 }
6418
6419 bool intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
6420                                 struct drm_connector *connector,
6421                                 struct drm_display_mode *mode,
6422                                 struct intel_load_detect_pipe *old)
6423 {
6424         struct intel_crtc *intel_crtc;
6425         struct drm_crtc *possible_crtc;
6426         struct drm_encoder *encoder = &intel_encoder->base;
6427         struct drm_crtc *crtc = NULL;
6428         struct drm_device *dev = encoder->dev;
6429         struct drm_framebuffer *old_fb;
6430         int i = -1;
6431
6432         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6433                       connector->base.id, drm_get_connector_name(connector),
6434                       encoder->base.id, drm_get_encoder_name(encoder));
6435
6436         /*
6437          * Algorithm gets a little messy:
6438          *
6439          *   - if the connector already has an assigned crtc, use it (but make
6440          *     sure it's on first)
6441          *
6442          *   - try to find the first unused crtc that can drive this connector,
6443          *     and use that if we find one
6444          */
6445
6446         /* See if we already have a CRTC for this connector */
6447         if (encoder->crtc) {
6448                 crtc = encoder->crtc;
6449
6450                 intel_crtc = to_intel_crtc(crtc);
6451                 old->dpms_mode = intel_crtc->dpms_mode;
6452                 old->load_detect_temp = false;
6453
6454                 /* Make sure the crtc and connector are running */
6455                 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
6456                         struct drm_encoder_helper_funcs *encoder_funcs;
6457                         struct drm_crtc_helper_funcs *crtc_funcs;
6458
6459                         crtc_funcs = crtc->helper_private;
6460                         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
6461
6462                         encoder_funcs = encoder->helper_private;
6463                         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
6464                 }
6465
6466                 return true;
6467         }
6468
6469         /* Find an unused one (if possible) */
6470         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6471                 i++;
6472                 if (!(encoder->possible_crtcs & (1 << i)))
6473                         continue;
6474                 if (!possible_crtc->enabled) {
6475                         crtc = possible_crtc;
6476                         break;
6477                 }
6478         }
6479
6480         /*
6481          * If we didn't find an unused CRTC, don't use any.
6482          */
6483         if (!crtc) {
6484                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6485                 return false;
6486         }
6487
6488         encoder->crtc = crtc;
6489         connector->encoder = encoder;
6490
6491         intel_crtc = to_intel_crtc(crtc);
6492         old->dpms_mode = intel_crtc->dpms_mode;
6493         old->load_detect_temp = true;
6494         old->release_fb = NULL;
6495
6496         if (!mode)
6497                 mode = &load_detect_mode;
6498
6499         old_fb = crtc->fb;
6500
6501         /* We need a framebuffer large enough to accommodate all accesses
6502          * that the plane may generate whilst we perform load detection.
6503          * We can not rely on the fbcon either being present (we get called
6504          * during its initialisation to detect all boot displays, or it may
6505          * not even exist) or that it is large enough to satisfy the
6506          * requested mode.
6507          */
6508         crtc->fb = mode_fits_in_fbdev(dev, mode);
6509         if (crtc->fb == NULL) {
6510                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
6511                 crtc->fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6512                 old->release_fb = crtc->fb;
6513         } else
6514                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
6515         if (IS_ERR(crtc->fb)) {
6516                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
6517                 crtc->fb = old_fb;
6518                 return false;
6519         }
6520
6521         if (!drm_crtc_helper_set_mode(crtc, mode, 0, 0, old_fb)) {
6522                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
6523                 if (old->release_fb)
6524                         old->release_fb->funcs->destroy(old->release_fb);
6525                 crtc->fb = old_fb;
6526                 return false;
6527         }
6528
6529         /* let the connector get through one full cycle before testing */
6530         intel_wait_for_vblank(dev, intel_crtc->pipe);
6531
6532         return true;
6533 }
6534
6535 void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
6536                                     struct drm_connector *connector,
6537                                     struct intel_load_detect_pipe *old)
6538 {
6539         struct drm_encoder *encoder = &intel_encoder->base;
6540         struct drm_device *dev = encoder->dev;
6541         struct drm_crtc *crtc = encoder->crtc;
6542         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
6543         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
6544
6545         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6546                       connector->base.id, drm_get_connector_name(connector),
6547                       encoder->base.id, drm_get_encoder_name(encoder));
6548
6549         if (old->load_detect_temp) {
6550                 connector->encoder = NULL;
6551                 drm_helper_disable_unused_functions(dev);
6552
6553                 if (old->release_fb)
6554                         old->release_fb->funcs->destroy(old->release_fb);
6555
6556                 return;
6557         }
6558
6559         /* Switch crtc and encoder back off if necessary */
6560         if (old->dpms_mode != DRM_MODE_DPMS_ON) {
6561                 encoder_funcs->dpms(encoder, old->dpms_mode);
6562                 crtc_funcs->dpms(crtc, old->dpms_mode);
6563         }
6564 }
6565
6566 /* Returns the clock of the currently programmed mode of the given pipe. */
6567 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6568 {
6569         struct drm_i915_private *dev_priv = dev->dev_private;
6570         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6571         int pipe = intel_crtc->pipe;
6572         u32 dpll = I915_READ(DPLL(pipe));
6573         u32 fp;
6574         intel_clock_t clock;
6575
6576         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
6577                 fp = I915_READ(FP0(pipe));
6578         else
6579                 fp = I915_READ(FP1(pipe));
6580
6581         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
6582         if (IS_PINEVIEW(dev)) {
6583                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6584                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
6585         } else {
6586                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6587                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6588         }
6589
6590         if (!IS_GEN2(dev)) {
6591                 if (IS_PINEVIEW(dev))
6592                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6593                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
6594                 else
6595                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
6596                                DPLL_FPA01_P1_POST_DIV_SHIFT);
6597
6598                 switch (dpll & DPLL_MODE_MASK) {
6599                 case DPLLB_MODE_DAC_SERIAL:
6600                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6601                                 5 : 10;
6602                         break;
6603                 case DPLLB_MODE_LVDS:
6604                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6605                                 7 : 14;
6606                         break;
6607                 default:
6608                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
6609                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
6610                         return 0;
6611                 }
6612
6613                 /* XXX: Handle the 100Mhz refclk */
6614                 intel_clock(dev, 96000, &clock);
6615         } else {
6616                 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6617
6618                 if (is_lvds) {
6619                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6620                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
6621                         clock.p2 = 14;
6622
6623                         if ((dpll & PLL_REF_INPUT_MASK) ==
6624                             PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6625                                 /* XXX: might not be 66MHz */
6626                                 intel_clock(dev, 66000, &clock);
6627                         } else
6628                                 intel_clock(dev, 48000, &clock);
6629                 } else {
6630                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
6631                                 clock.p1 = 2;
6632                         else {
6633                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6634                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6635                         }
6636                         if (dpll & PLL_P2_DIVIDE_BY_4)
6637                                 clock.p2 = 4;
6638                         else
6639                                 clock.p2 = 2;
6640
6641                         intel_clock(dev, 48000, &clock);
6642                 }
6643         }
6644
6645         /* XXX: It would be nice to validate the clocks, but we can't reuse
6646          * i830PllIsValid() because it relies on the xf86_config connector
6647          * configuration being accurate, which it isn't necessarily.
6648          */
6649
6650         return clock.dot;
6651 }
6652
6653 /** Returns the currently programmed mode of the given pipe. */
6654 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6655                                              struct drm_crtc *crtc)
6656 {
6657         struct drm_i915_private *dev_priv = dev->dev_private;
6658         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6659         int pipe = intel_crtc->pipe;
6660         struct drm_display_mode *mode;
6661         int htot = I915_READ(HTOTAL(pipe));
6662         int hsync = I915_READ(HSYNC(pipe));
6663         int vtot = I915_READ(VTOTAL(pipe));
6664         int vsync = I915_READ(VSYNC(pipe));
6665
6666         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6667         if (!mode)
6668                 return NULL;
6669
6670         mode->clock = intel_crtc_clock_get(dev, crtc);
6671         mode->hdisplay = (htot & 0xffff) + 1;
6672         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6673         mode->hsync_start = (hsync & 0xffff) + 1;
6674         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6675         mode->vdisplay = (vtot & 0xffff) + 1;
6676         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6677         mode->vsync_start = (vsync & 0xffff) + 1;
6678         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6679
6680         drm_mode_set_name(mode);
6681         drm_mode_set_crtcinfo(mode, 0);
6682
6683         return mode;
6684 }
6685
6686 #define GPU_IDLE_TIMEOUT 500 /* ms */
6687
6688 /* When this timer fires, we've been idle for awhile */
6689 static void intel_gpu_idle_timer(unsigned long arg)
6690 {
6691         struct drm_device *dev = (struct drm_device *)arg;
6692         drm_i915_private_t *dev_priv = dev->dev_private;
6693
6694         if (!list_empty(&dev_priv->mm.active_list)) {
6695                 /* Still processing requests, so just re-arm the timer. */
6696                 mod_timer(&dev_priv->idle_timer, jiffies +
6697                           msecs_to_jiffies(GPU_IDLE_TIMEOUT));
6698                 return;
6699         }
6700
6701         dev_priv->busy = false;
6702         queue_work(dev_priv->wq, &dev_priv->idle_work);
6703 }
6704
6705 #define CRTC_IDLE_TIMEOUT 1000 /* ms */
6706
6707 static void intel_crtc_idle_timer(unsigned long arg)
6708 {
6709         struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
6710         struct drm_crtc *crtc = &intel_crtc->base;
6711         drm_i915_private_t *dev_priv = crtc->dev->dev_private;
6712         struct intel_framebuffer *intel_fb;
6713
6714         intel_fb = to_intel_framebuffer(crtc->fb);
6715         if (intel_fb && intel_fb->obj->active) {
6716                 /* The framebuffer is still being accessed by the GPU. */
6717                 mod_timer(&intel_crtc->idle_timer, jiffies +
6718                           msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
6719                 return;
6720         }
6721
6722         intel_crtc->busy = false;
6723         queue_work(dev_priv->wq, &dev_priv->idle_work);
6724 }
6725
6726 static void intel_increase_pllclock(struct drm_crtc *crtc)
6727 {
6728         struct drm_device *dev = crtc->dev;
6729         drm_i915_private_t *dev_priv = dev->dev_private;
6730         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6731         int pipe = intel_crtc->pipe;
6732         int dpll_reg = DPLL(pipe);
6733         int dpll;
6734
6735         if (HAS_PCH_SPLIT(dev))
6736                 return;
6737
6738         if (!dev_priv->lvds_downclock_avail)
6739                 return;
6740
6741         dpll = I915_READ(dpll_reg);
6742         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
6743                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
6744
6745                 /* Unlock panel regs */
6746                 I915_WRITE(PP_CONTROL,
6747                            I915_READ(PP_CONTROL) | PANEL_UNLOCK_REGS);
6748
6749                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
6750                 I915_WRITE(dpll_reg, dpll);
6751                 intel_wait_for_vblank(dev, pipe);
6752
6753                 dpll = I915_READ(dpll_reg);
6754                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
6755                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
6756
6757                 /* ...and lock them again */
6758                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
6759         }
6760
6761         /* Schedule downclock */
6762         mod_timer(&intel_crtc->idle_timer, jiffies +
6763                   msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
6764 }
6765
6766 static void intel_decrease_pllclock(struct drm_crtc *crtc)
6767 {
6768         struct drm_device *dev = crtc->dev;
6769         drm_i915_private_t *dev_priv = dev->dev_private;
6770         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6771         int pipe = intel_crtc->pipe;
6772         int dpll_reg = DPLL(pipe);
6773         int dpll = I915_READ(dpll_reg);
6774
6775         if (HAS_PCH_SPLIT(dev))
6776                 return;
6777
6778         if (!dev_priv->lvds_downclock_avail)
6779                 return;
6780
6781         /*
6782          * Since this is called by a timer, we should never get here in
6783          * the manual case.
6784          */
6785         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
6786                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
6787
6788                 /* Unlock panel regs */
6789                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) |
6790                            PANEL_UNLOCK_REGS);
6791
6792                 dpll |= DISPLAY_RATE_SELECT_FPA1;
6793                 I915_WRITE(dpll_reg, dpll);
6794                 intel_wait_for_vblank(dev, pipe);
6795                 dpll = I915_READ(dpll_reg);
6796                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
6797                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
6798
6799                 /* ...and lock them again */
6800                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
6801         }
6802
6803 }
6804
6805 /**
6806  * intel_idle_update - adjust clocks for idleness
6807  * @work: work struct
6808  *
6809  * Either the GPU or display (or both) went idle.  Check the busy status
6810  * here and adjust the CRTC and GPU clocks as necessary.
6811  */
6812 static void intel_idle_update(struct work_struct *work)
6813 {
6814         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
6815                                                     idle_work);
6816         struct drm_device *dev = dev_priv->dev;
6817         struct drm_crtc *crtc;
6818         struct intel_crtc *intel_crtc;
6819
6820         if (!i915_powersave)
6821                 return;
6822
6823         mutex_lock(&dev->struct_mutex);
6824
6825         i915_update_gfx_val(dev_priv);
6826
6827         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6828                 /* Skip inactive CRTCs */
6829                 if (!crtc->fb)
6830                         continue;
6831
6832                 intel_crtc = to_intel_crtc(crtc);
6833                 if (!intel_crtc->busy)
6834                         intel_decrease_pllclock(crtc);
6835         }
6836
6837
6838         mutex_unlock(&dev->struct_mutex);
6839 }
6840
6841 /**
6842  * intel_mark_busy - mark the GPU and possibly the display busy
6843  * @dev: drm device
6844  * @obj: object we're operating on
6845  *
6846  * Callers can use this function to indicate that the GPU is busy processing
6847  * commands.  If @obj matches one of the CRTC objects (i.e. it's a scanout
6848  * buffer), we'll also mark the display as busy, so we know to increase its
6849  * clock frequency.
6850  */
6851 void intel_mark_busy(struct drm_device *dev, struct drm_i915_gem_object *obj)
6852 {
6853         drm_i915_private_t *dev_priv = dev->dev_private;
6854         struct drm_crtc *crtc = NULL;
6855         struct intel_framebuffer *intel_fb;
6856         struct intel_crtc *intel_crtc;
6857
6858         if (!drm_core_check_feature(dev, DRIVER_MODESET))
6859                 return;
6860
6861         if (!dev_priv->busy)
6862                 dev_priv->busy = true;
6863         else
6864                 mod_timer(&dev_priv->idle_timer, jiffies +
6865                           msecs_to_jiffies(GPU_IDLE_TIMEOUT));
6866
6867         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6868                 if (!crtc->fb)
6869                         continue;
6870
6871                 intel_crtc = to_intel_crtc(crtc);
6872                 intel_fb = to_intel_framebuffer(crtc->fb);
6873                 if (intel_fb->obj == obj) {
6874                         if (!intel_crtc->busy) {
6875                                 /* Non-busy -> busy, upclock */
6876                                 intel_increase_pllclock(crtc);
6877                                 intel_crtc->busy = true;
6878                         } else {
6879                                 /* Busy -> busy, put off timer */
6880                                 mod_timer(&intel_crtc->idle_timer, jiffies +
6881                                           msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
6882                         }
6883                 }
6884         }
6885 }
6886
6887 static void intel_crtc_destroy(struct drm_crtc *crtc)
6888 {
6889         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6890         struct drm_device *dev = crtc->dev;
6891         struct intel_unpin_work *work;
6892         unsigned long flags;
6893
6894         spin_lock_irqsave(&dev->event_lock, flags);
6895         work = intel_crtc->unpin_work;
6896         intel_crtc->unpin_work = NULL;
6897         spin_unlock_irqrestore(&dev->event_lock, flags);
6898
6899         if (work) {
6900                 cancel_work_sync(&work->work);
6901                 kfree(work);
6902         }
6903
6904         drm_crtc_cleanup(crtc);
6905
6906         kfree(intel_crtc);
6907 }
6908
6909 static void intel_unpin_work_fn(struct work_struct *__work)
6910 {
6911         struct intel_unpin_work *work =
6912                 container_of(__work, struct intel_unpin_work, work);
6913
6914         mutex_lock(&work->dev->struct_mutex);
6915         i915_gem_object_unpin(work->old_fb_obj);
6916         drm_gem_object_unreference(&work->pending_flip_obj->base);
6917         drm_gem_object_unreference(&work->old_fb_obj->base);
6918
6919         intel_update_fbc(work->dev);
6920         mutex_unlock(&work->dev->struct_mutex);
6921         kfree(work);
6922 }
6923
6924 static void do_intel_finish_page_flip(struct drm_device *dev,
6925                                       struct drm_crtc *crtc)
6926 {
6927         drm_i915_private_t *dev_priv = dev->dev_private;
6928         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6929         struct intel_unpin_work *work;
6930         struct drm_i915_gem_object *obj;
6931         struct drm_pending_vblank_event *e;
6932         struct timeval tnow, tvbl;
6933         unsigned long flags;
6934
6935         /* Ignore early vblank irqs */
6936         if (intel_crtc == NULL)
6937                 return;
6938
6939         do_gettimeofday(&tnow);
6940
6941         spin_lock_irqsave(&dev->event_lock, flags);
6942         work = intel_crtc->unpin_work;
6943
6944         /* Ensure we don't miss a work->pending update ... */
6945         smp_rmb();
6946
6947         if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
6948                 spin_unlock_irqrestore(&dev->event_lock, flags);
6949                 return;
6950         }
6951
6952         /* and that the unpin work is consistent wrt ->pending. */
6953         smp_rmb();
6954
6955         intel_crtc->unpin_work = NULL;
6956
6957         if (work->event) {
6958                 e = work->event;
6959                 e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
6960
6961                 /* Called before vblank count and timestamps have
6962                  * been updated for the vblank interval of flip
6963                  * completion? Need to increment vblank count and
6964                  * add one videorefresh duration to returned timestamp
6965                  * to account for this. We assume this happened if we
6966                  * get called over 0.9 frame durations after the last
6967                  * timestamped vblank.
6968                  *
6969                  * This calculation can not be used with vrefresh rates
6970                  * below 5Hz (10Hz to be on the safe side) without
6971                  * promoting to 64 integers.
6972                  */
6973                 if (10 * (timeval_to_ns(&tnow) - timeval_to_ns(&tvbl)) >
6974                     9 * crtc->framedur_ns) {
6975                         e->event.sequence++;
6976                         tvbl = ns_to_timeval(timeval_to_ns(&tvbl) +
6977                                              crtc->framedur_ns);
6978                 }
6979
6980                 e->event.tv_sec = tvbl.tv_sec;
6981                 e->event.tv_usec = tvbl.tv_usec;
6982
6983                 list_add_tail(&e->base.link,
6984                               &e->base.file_priv->event_list);
6985                 wake_up_interruptible(&e->base.file_priv->event_wait);
6986         }
6987
6988         drm_vblank_put(dev, intel_crtc->pipe);
6989
6990         spin_unlock_irqrestore(&dev->event_lock, flags);
6991
6992         obj = work->old_fb_obj;
6993
6994         atomic_clear_mask(1 << intel_crtc->plane,
6995                           &obj->pending_flip.counter);
6996
6997         wake_up(&dev_priv->pending_flip_queue);
6998         schedule_work(&work->work);
6999
7000         trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
7001 }
7002
7003 void intel_finish_page_flip(struct drm_device *dev, int pipe)
7004 {
7005         drm_i915_private_t *dev_priv = dev->dev_private;
7006         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7007
7008         do_intel_finish_page_flip(dev, crtc);
7009 }
7010
7011 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7012 {
7013         drm_i915_private_t *dev_priv = dev->dev_private;
7014         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7015
7016         do_intel_finish_page_flip(dev, crtc);
7017 }
7018
7019 void intel_prepare_page_flip(struct drm_device *dev, int plane)
7020 {
7021         drm_i915_private_t *dev_priv = dev->dev_private;
7022         struct intel_crtc *intel_crtc =
7023                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7024         unsigned long flags;
7025
7026         /* NB: An MMIO update of the plane base pointer will also
7027          * generate a page-flip completion irq, i.e. every modeset
7028          * is also accompanied by a spurious intel_prepare_page_flip().
7029          */
7030         spin_lock_irqsave(&dev->event_lock, flags);
7031         if (intel_crtc->unpin_work)
7032                 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
7033         spin_unlock_irqrestore(&dev->event_lock, flags);
7034 }
7035
7036 inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
7037 {
7038         /* Ensure that the work item is consistent when activating it ... */
7039         smp_wmb();
7040         atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
7041         /* and that it is marked active as soon as the irq could fire. */
7042         smp_wmb();
7043 }
7044
7045 static int intel_gen2_queue_flip(struct drm_device *dev,
7046                                  struct drm_crtc *crtc,
7047                                  struct drm_framebuffer *fb,
7048                                  struct drm_i915_gem_object *obj)
7049 {
7050         struct drm_i915_private *dev_priv = dev->dev_private;
7051         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7052         unsigned long offset;
7053         u32 flip_mask;
7054         int ret;
7055
7056         ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
7057         if (ret)
7058                 goto err;
7059
7060         /* Offset into the new buffer for cases of shared fbs between CRTCs */
7061         offset = crtc->y * fb->pitch + crtc->x * fb->bits_per_pixel/8;
7062
7063         ret = BEGIN_LP_RING(6);
7064         if (ret)
7065                 goto err_unpin;
7066
7067         /* Can't queue multiple flips, so wait for the previous
7068          * one to finish before executing the next.
7069          */
7070         if (intel_crtc->plane)
7071                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7072         else
7073                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7074         OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
7075         OUT_RING(MI_NOOP);
7076         OUT_RING(MI_DISPLAY_FLIP |
7077                  MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7078         OUT_RING(fb->pitch);
7079         OUT_RING(obj->gtt_offset + offset);
7080         OUT_RING(MI_NOOP);
7081
7082         intel_mark_page_flip_active(intel_crtc);
7083         ADVANCE_LP_RING();
7084         return 0;
7085
7086 err_unpin:
7087         i915_gem_object_unpin(obj);
7088 err:
7089         return ret;
7090 }
7091
7092 static int intel_gen3_queue_flip(struct drm_device *dev,
7093                                  struct drm_crtc *crtc,
7094                                  struct drm_framebuffer *fb,
7095                                  struct drm_i915_gem_object *obj)
7096 {
7097         struct drm_i915_private *dev_priv = dev->dev_private;
7098         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7099         unsigned long offset;
7100         u32 flip_mask;
7101         int ret;
7102
7103         ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
7104         if (ret)
7105                 goto err;
7106
7107         /* Offset into the new buffer for cases of shared fbs between CRTCs */
7108         offset = crtc->y * fb->pitch + crtc->x * fb->bits_per_pixel/8;
7109
7110         ret = BEGIN_LP_RING(6);
7111         if (ret)
7112                 goto err_unpin;
7113
7114         if (intel_crtc->plane)
7115                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7116         else
7117                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7118         OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
7119         OUT_RING(MI_NOOP);
7120         OUT_RING(MI_DISPLAY_FLIP_I915 |
7121                  MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7122         OUT_RING(fb->pitch);
7123         OUT_RING(obj->gtt_offset + offset);
7124         OUT_RING(MI_NOOP);
7125
7126         intel_mark_page_flip_active(intel_crtc);
7127         ADVANCE_LP_RING();
7128         return 0;
7129
7130 err_unpin:
7131         i915_gem_object_unpin(obj);
7132 err:
7133         return ret;
7134 }
7135
7136 static int intel_gen4_queue_flip(struct drm_device *dev,
7137                                  struct drm_crtc *crtc,
7138                                  struct drm_framebuffer *fb,
7139                                  struct drm_i915_gem_object *obj)
7140 {
7141         struct drm_i915_private *dev_priv = dev->dev_private;
7142         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7143         uint32_t pf, pipesrc;
7144         int ret;
7145
7146         ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
7147         if (ret)
7148                 goto err;
7149
7150         ret = BEGIN_LP_RING(4);
7151         if (ret)
7152                 goto err_unpin;
7153
7154         /* i965+ uses the linear or tiled offsets from the
7155          * Display Registers (which do not change across a page-flip)
7156          * so we need only reprogram the base address.
7157          */
7158         OUT_RING(MI_DISPLAY_FLIP |
7159                  MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7160         OUT_RING(fb->pitch);
7161         OUT_RING(obj->gtt_offset | obj->tiling_mode);
7162
7163         /* XXX Enabling the panel-fitter across page-flip is so far
7164          * untested on non-native modes, so ignore it for now.
7165          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7166          */
7167         pf = 0;
7168         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7169         OUT_RING(pf | pipesrc);
7170
7171         intel_mark_page_flip_active(intel_crtc);
7172         ADVANCE_LP_RING();
7173         return 0;
7174
7175 err_unpin:
7176         i915_gem_object_unpin(obj);
7177 err:
7178         return ret;
7179 }
7180
7181 static int intel_gen6_queue_flip(struct drm_device *dev,
7182                                  struct drm_crtc *crtc,
7183                                  struct drm_framebuffer *fb,
7184                                  struct drm_i915_gem_object *obj)
7185 {
7186         struct drm_i915_private *dev_priv = dev->dev_private;
7187         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7188         uint32_t pf, pipesrc;
7189         int ret;
7190
7191         ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
7192         if (ret)
7193                 goto err;
7194
7195         ret = BEGIN_LP_RING(4);
7196         if (ret)
7197                 goto err_unpin;
7198
7199         OUT_RING(MI_DISPLAY_FLIP |
7200                  MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7201         OUT_RING(fb->pitch | obj->tiling_mode);
7202         OUT_RING(obj->gtt_offset);
7203
7204         pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7205         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7206         OUT_RING(pf | pipesrc);
7207
7208         intel_mark_page_flip_active(intel_crtc);
7209         ADVANCE_LP_RING();
7210         return 0;
7211
7212 err_unpin:
7213         i915_gem_object_unpin(obj);
7214 err:
7215         return ret;
7216 }
7217
7218 /*
7219  * On gen7 we currently use the blit ring because (in early silicon at least)
7220  * the render ring doesn't give us interrpts for page flip completion, which
7221  * means clients will hang after the first flip is queued.  Fortunately the
7222  * blit ring generates interrupts properly, so use it instead.
7223  */
7224 static int intel_gen7_queue_flip(struct drm_device *dev,
7225                                  struct drm_crtc *crtc,
7226                                  struct drm_framebuffer *fb,
7227                                  struct drm_i915_gem_object *obj)
7228 {
7229         struct drm_i915_private *dev_priv = dev->dev_private;
7230         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7231         struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
7232         uint32_t plane_bit = 0;
7233         int ret;
7234
7235         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7236         if (ret)
7237                 goto err;
7238
7239         switch(intel_crtc->plane) {
7240         case PLANE_A:
7241                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7242                 break;
7243         case PLANE_B:
7244                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7245                 break;
7246         case PLANE_C:
7247                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7248                 break;
7249         default:
7250                 WARN_ONCE(1, "unknown plane in flip command\n");
7251                 ret = -ENODEV;
7252                 goto err_unpin;
7253         }
7254
7255         /*
7256          * BSpec MI_DISPLAY_FLIP for IVB:
7257          * "The full packet must be contained within the same cache line."
7258          *
7259          * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
7260          * cacheline, if we ever start emitting more commands before
7261          * the MI_DISPLAY_FLIP we may need to first emit everything else,
7262          * then do the cacheline alignment, and finally emit the
7263          * MI_DISPLAY_FLIP.
7264          */
7265         ret = intel_ring_cacheline_align(ring);
7266         if (ret)
7267                 goto err_unpin;
7268
7269         ret = intel_ring_begin(ring, 4);
7270         if (ret)
7271                 goto err_unpin;
7272
7273         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
7274         intel_ring_emit(ring, (fb->pitch | obj->tiling_mode));
7275         intel_ring_emit(ring, (obj->gtt_offset));
7276         intel_ring_emit(ring, (MI_NOOP));
7277
7278         intel_mark_page_flip_active(intel_crtc);
7279         intel_ring_advance(ring);
7280         return 0;
7281
7282 err_unpin:
7283         i915_gem_object_unpin(obj);
7284 err:
7285         return ret;
7286 }
7287
7288 static int intel_default_queue_flip(struct drm_device *dev,
7289                                     struct drm_crtc *crtc,
7290                                     struct drm_framebuffer *fb,
7291                                     struct drm_i915_gem_object *obj)
7292 {
7293         return -ENODEV;
7294 }
7295
7296 static int intel_crtc_page_flip(struct drm_crtc *crtc,
7297                                 struct drm_framebuffer *fb,
7298                                 struct drm_pending_vblank_event *event)
7299 {
7300         struct drm_device *dev = crtc->dev;
7301         struct drm_i915_private *dev_priv = dev->dev_private;
7302         struct drm_framebuffer *old_fb = crtc->fb;
7303         struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
7304         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7305         struct intel_unpin_work *work;
7306         unsigned long flags;
7307         int ret;
7308
7309         work = kzalloc(sizeof *work, GFP_KERNEL);
7310         if (work == NULL)
7311                 return -ENOMEM;
7312
7313         work->event = event;
7314         work->dev = crtc->dev;
7315         work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
7316         INIT_WORK(&work->work, intel_unpin_work_fn);
7317
7318         ret = drm_vblank_get(dev, intel_crtc->pipe);
7319         if (ret)
7320                 goto free_work;
7321
7322         /* We borrow the event spin lock for protecting unpin_work */
7323         spin_lock_irqsave(&dev->event_lock, flags);
7324         if (intel_crtc->unpin_work) {
7325                 spin_unlock_irqrestore(&dev->event_lock, flags);
7326                 kfree(work);
7327                 drm_vblank_put(dev, intel_crtc->pipe);
7328
7329                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
7330                 return -EBUSY;
7331         }
7332         intel_crtc->unpin_work = work;
7333         spin_unlock_irqrestore(&dev->event_lock, flags);
7334
7335         mutex_lock(&dev->struct_mutex);
7336
7337         /* Reference the objects for the scheduled work. */
7338         drm_gem_object_reference(&work->old_fb_obj->base);
7339         drm_gem_object_reference(&obj->base);
7340
7341         crtc->fb = fb;
7342
7343         work->pending_flip_obj = obj;
7344
7345         work->enable_stall_check = true;
7346
7347         /* Block clients from rendering to the new back buffer until
7348          * the flip occurs and the object is no longer visible.
7349          */
7350         atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
7351
7352         ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7353         if (ret)
7354                 goto cleanup_pending;
7355
7356         intel_disable_fbc(dev);
7357         mutex_unlock(&dev->struct_mutex);
7358
7359         trace_i915_flip_request(intel_crtc->plane, obj);
7360
7361         return 0;
7362
7363 cleanup_pending:
7364         atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
7365         crtc->fb = old_fb;
7366         drm_gem_object_unreference(&work->old_fb_obj->base);
7367         drm_gem_object_unreference(&obj->base);
7368         mutex_unlock(&dev->struct_mutex);
7369
7370         spin_lock_irqsave(&dev->event_lock, flags);
7371         intel_crtc->unpin_work = NULL;
7372         spin_unlock_irqrestore(&dev->event_lock, flags);
7373
7374         drm_vblank_put(dev, intel_crtc->pipe);
7375 free_work:
7376         kfree(work);
7377
7378         return ret;
7379 }
7380
7381 static void intel_sanitize_modesetting(struct drm_device *dev,
7382                                        int pipe, int plane)
7383 {
7384         struct drm_i915_private *dev_priv = dev->dev_private;
7385         u32 reg, val;
7386         int i;
7387
7388         /* Clear any frame start delays used for debugging left by the BIOS */
7389         for_each_pipe(i) {
7390                 reg = PIPECONF(i);
7391                 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
7392         }
7393
7394         if (HAS_PCH_SPLIT(dev))
7395                 return;
7396
7397         /* Who knows what state these registers were left in by the BIOS or
7398          * grub?
7399          *
7400          * If we leave the registers in a conflicting state (e.g. with the
7401          * display plane reading from the other pipe than the one we intend
7402          * to use) then when we attempt to teardown the active mode, we will
7403          * not disable the pipes and planes in the correct order -- leaving
7404          * a plane reading from a disabled pipe and possibly leading to
7405          * undefined behaviour.
7406          */
7407
7408         reg = DSPCNTR(plane);
7409         val = I915_READ(reg);
7410
7411         if ((val & DISPLAY_PLANE_ENABLE) == 0)
7412                 return;
7413         if (!!(val & DISPPLANE_SEL_PIPE_MASK) == pipe)
7414                 return;
7415
7416         /* This display plane is active and attached to the other CPU pipe. */
7417         pipe = !pipe;
7418
7419         /* Disable the plane and wait for it to stop reading from the pipe. */
7420         intel_disable_plane(dev_priv, plane, pipe);
7421         intel_disable_pipe(dev_priv, pipe);
7422 }
7423
7424 static void intel_crtc_reset(struct drm_crtc *crtc)
7425 {
7426         struct drm_device *dev = crtc->dev;
7427         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7428
7429         /* Reset flags back to the 'unknown' status so that they
7430          * will be correctly set on the initial modeset.
7431          */
7432         intel_crtc->dpms_mode = -1;
7433
7434         /* We need to fix up any BIOS configuration that conflicts with
7435          * our expectations.
7436          */
7437         intel_sanitize_modesetting(dev, intel_crtc->pipe, intel_crtc->plane);
7438 }
7439
7440 static struct drm_crtc_helper_funcs intel_helper_funcs = {
7441         .dpms = intel_crtc_dpms,
7442         .mode_fixup = intel_crtc_mode_fixup,
7443         .mode_set = intel_crtc_mode_set,
7444         .mode_set_base = intel_pipe_set_base,
7445         .mode_set_base_atomic = intel_pipe_set_base_atomic,
7446         .load_lut = intel_crtc_load_lut,
7447         .disable = intel_crtc_disable,
7448 };
7449
7450 static const struct drm_crtc_funcs intel_crtc_funcs = {
7451         .reset = intel_crtc_reset,
7452         .cursor_set = intel_crtc_cursor_set,
7453         .cursor_move = intel_crtc_cursor_move,
7454         .gamma_set = intel_crtc_gamma_set,
7455         .set_config = drm_crtc_helper_set_config,
7456         .destroy = intel_crtc_destroy,
7457         .page_flip = intel_crtc_page_flip,
7458 };
7459
7460 static void intel_crtc_init(struct drm_device *dev, int pipe)
7461 {
7462         drm_i915_private_t *dev_priv = dev->dev_private;
7463         struct intel_crtc *intel_crtc;
7464         int i;
7465
7466         intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
7467         if (intel_crtc == NULL)
7468                 return;
7469
7470         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
7471
7472         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
7473         for (i = 0; i < 256; i++) {
7474                 intel_crtc->lut_r[i] = i;
7475                 intel_crtc->lut_g[i] = i;
7476                 intel_crtc->lut_b[i] = i;
7477         }
7478
7479         /* Swap pipes & planes for FBC on pre-965 */
7480         intel_crtc->pipe = pipe;
7481         intel_crtc->plane = pipe;
7482         if (IS_MOBILE(dev) && IS_GEN3(dev)) {
7483                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
7484                 intel_crtc->plane = !pipe;
7485         }
7486
7487         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
7488                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
7489         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
7490         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
7491
7492         intel_crtc_reset(&intel_crtc->base);
7493         intel_crtc->active = true; /* force the pipe off on setup_init_config */
7494         intel_crtc->bpp = 24; /* default for pre-Ironlake */
7495
7496         if (HAS_PCH_SPLIT(dev)) {
7497                 if (pipe == 2 && IS_IVYBRIDGE(dev))
7498                         intel_crtc->no_pll = true;
7499                 intel_helper_funcs.prepare = ironlake_crtc_prepare;
7500                 intel_helper_funcs.commit = ironlake_crtc_commit;
7501         } else {
7502                 intel_helper_funcs.prepare = i9xx_crtc_prepare;
7503                 intel_helper_funcs.commit = i9xx_crtc_commit;
7504         }
7505
7506         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
7507
7508         intel_crtc->busy = false;
7509
7510         setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
7511                     (unsigned long)intel_crtc);
7512 }
7513
7514 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
7515                                 struct drm_file *file)
7516 {
7517         drm_i915_private_t *dev_priv = dev->dev_private;
7518         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
7519         struct drm_mode_object *drmmode_obj;
7520         struct intel_crtc *crtc;
7521
7522         if (!dev_priv) {
7523                 DRM_ERROR("called with no initialization\n");
7524                 return -EINVAL;
7525         }
7526
7527         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
7528                         DRM_MODE_OBJECT_CRTC);
7529
7530         if (!drmmode_obj) {
7531                 DRM_ERROR("no such CRTC id\n");
7532                 return -EINVAL;
7533         }
7534
7535         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
7536         pipe_from_crtc_id->pipe = crtc->pipe;
7537
7538         return 0;
7539 }
7540
7541 static int intel_encoder_clones(struct drm_device *dev, int type_mask)
7542 {
7543         struct intel_encoder *encoder;
7544         int index_mask = 0;
7545         int entry = 0;
7546
7547         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7548                 if (type_mask & encoder->clone_mask)
7549                         index_mask |= (1 << entry);
7550                 entry++;
7551         }
7552
7553         return index_mask;
7554 }
7555
7556 static bool has_edp_a(struct drm_device *dev)
7557 {
7558         struct drm_i915_private *dev_priv = dev->dev_private;
7559
7560         if (!IS_MOBILE(dev))
7561                 return false;
7562
7563         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
7564                 return false;
7565
7566         if (IS_GEN5(dev) &&
7567             (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
7568                 return false;
7569
7570         return true;
7571 }
7572
7573 static void intel_setup_outputs(struct drm_device *dev)
7574 {
7575         struct drm_i915_private *dev_priv = dev->dev_private;
7576         struct intel_encoder *encoder;
7577         bool dpd_is_edp = false;
7578         bool has_lvds = false;
7579
7580         if (IS_MOBILE(dev) && !IS_I830(dev))
7581                 has_lvds = intel_lvds_init(dev);
7582         if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
7583                 /* disable the panel fitter on everything but LVDS */
7584                 I915_WRITE(PFIT_CONTROL, 0);
7585         }
7586
7587         if (HAS_PCH_SPLIT(dev)) {
7588                 dpd_is_edp = intel_dpd_is_edp(dev);
7589
7590                 if (has_edp_a(dev))
7591                         intel_dp_init(dev, DP_A);
7592
7593                 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
7594                         intel_dp_init(dev, PCH_DP_D);
7595         }
7596
7597         intel_crt_init(dev);
7598
7599         if (HAS_PCH_SPLIT(dev)) {
7600                 int found;
7601
7602                 if (I915_READ(HDMIB) & PORT_DETECTED) {
7603                         /* PCH SDVOB multiplex with HDMIB */
7604                         found = intel_sdvo_init(dev, PCH_SDVOB);
7605                         if (!found)
7606                                 intel_hdmi_init(dev, HDMIB);
7607                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
7608                                 intel_dp_init(dev, PCH_DP_B);
7609                 }
7610
7611                 if (I915_READ(HDMIC) & PORT_DETECTED)
7612                         intel_hdmi_init(dev, HDMIC);
7613
7614                 if (I915_READ(HDMID) & PORT_DETECTED)
7615                         intel_hdmi_init(dev, HDMID);
7616
7617                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
7618                         intel_dp_init(dev, PCH_DP_C);
7619
7620                 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
7621                         intel_dp_init(dev, PCH_DP_D);
7622
7623         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
7624                 bool found = false;
7625
7626                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
7627                         DRM_DEBUG_KMS("probing SDVOB\n");
7628                         found = intel_sdvo_init(dev, SDVOB);
7629                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
7630                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
7631                                 intel_hdmi_init(dev, SDVOB);
7632                         }
7633
7634                         if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
7635                                 DRM_DEBUG_KMS("probing DP_B\n");
7636                                 intel_dp_init(dev, DP_B);
7637                         }
7638                 }
7639
7640                 /* Before G4X SDVOC doesn't have its own detect register */
7641
7642                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
7643                         DRM_DEBUG_KMS("probing SDVOC\n");
7644                         found = intel_sdvo_init(dev, SDVOC);
7645                 }
7646
7647                 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
7648
7649                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
7650                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
7651                                 intel_hdmi_init(dev, SDVOC);
7652                         }
7653                         if (SUPPORTS_INTEGRATED_DP(dev)) {
7654                                 DRM_DEBUG_KMS("probing DP_C\n");
7655                                 intel_dp_init(dev, DP_C);
7656                         }
7657                 }
7658
7659                 if (SUPPORTS_INTEGRATED_DP(dev) &&
7660                     (I915_READ(DP_D) & DP_DETECTED)) {
7661                         DRM_DEBUG_KMS("probing DP_D\n");
7662                         intel_dp_init(dev, DP_D);
7663                 }
7664         } else if (IS_GEN2(dev))
7665                 intel_dvo_init(dev);
7666
7667         if (SUPPORTS_TV(dev))
7668                 intel_tv_init(dev);
7669
7670         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7671                 encoder->base.possible_crtcs = encoder->crtc_mask;
7672                 encoder->base.possible_clones =
7673                         intel_encoder_clones(dev, encoder->clone_mask);
7674         }
7675
7676         /* disable all the possible outputs/crtcs before entering KMS mode */
7677         drm_helper_disable_unused_functions(dev);
7678
7679         if (HAS_PCH_SPLIT(dev))
7680                 ironlake_init_pch_refclk(dev);
7681 }
7682
7683 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
7684 {
7685         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
7686
7687         drm_framebuffer_cleanup(fb);
7688         drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
7689
7690         kfree(intel_fb);
7691 }
7692
7693 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
7694                                                 struct drm_file *file,
7695                                                 unsigned int *handle)
7696 {
7697         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
7698         struct drm_i915_gem_object *obj = intel_fb->obj;
7699
7700         return drm_gem_handle_create(file, &obj->base, handle);
7701 }
7702
7703 static const struct drm_framebuffer_funcs intel_fb_funcs = {
7704         .destroy = intel_user_framebuffer_destroy,
7705         .create_handle = intel_user_framebuffer_create_handle,
7706 };
7707
7708 int intel_framebuffer_init(struct drm_device *dev,
7709                            struct intel_framebuffer *intel_fb,
7710                            struct drm_mode_fb_cmd *mode_cmd,
7711                            struct drm_i915_gem_object *obj)
7712 {
7713         int ret;
7714
7715         if (obj->tiling_mode == I915_TILING_Y)
7716                 return -EINVAL;
7717
7718         if (mode_cmd->pitch & 63)
7719                 return -EINVAL;
7720
7721         switch (mode_cmd->bpp) {
7722         case 8:
7723         case 16:
7724                 /* Only pre-ILK can handle 5:5:5 */
7725                 if (mode_cmd->depth == 15 && !HAS_PCH_SPLIT(dev))
7726                         return -EINVAL;
7727                 break;
7728
7729         case 24:
7730         case 32:
7731                 break;
7732         default:
7733                 return -EINVAL;
7734         }
7735
7736         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
7737         if (ret) {
7738                 DRM_ERROR("framebuffer init failed %d\n", ret);
7739                 return ret;
7740         }
7741
7742         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
7743         intel_fb->obj = obj;
7744         return 0;
7745 }
7746
7747 static struct drm_framebuffer *
7748 intel_user_framebuffer_create(struct drm_device *dev,
7749                               struct drm_file *filp,
7750                               struct drm_mode_fb_cmd *mode_cmd)
7751 {
7752         struct drm_i915_gem_object *obj;
7753
7754         obj = to_intel_bo(drm_gem_object_lookup(dev, filp, mode_cmd->handle));
7755         if (&obj->base == NULL)
7756                 return ERR_PTR(-ENOENT);
7757
7758         return intel_framebuffer_create(dev, mode_cmd, obj);
7759 }
7760
7761 static const struct drm_mode_config_funcs intel_mode_funcs = {
7762         .fb_create = intel_user_framebuffer_create,
7763         .output_poll_changed = intel_fb_output_poll_changed,
7764 };
7765
7766 static struct drm_i915_gem_object *
7767 intel_alloc_context_page(struct drm_device *dev)
7768 {
7769         struct drm_i915_gem_object *ctx;
7770         int ret;
7771
7772         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
7773
7774         ctx = i915_gem_alloc_object(dev, 4096);
7775         if (!ctx) {
7776                 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
7777                 return NULL;
7778         }
7779
7780         ret = i915_gem_object_pin(ctx, 4096, true);
7781         if (ret) {
7782                 DRM_ERROR("failed to pin power context: %d\n", ret);
7783                 goto err_unref;
7784         }
7785
7786         ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
7787         if (ret) {
7788                 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
7789                 goto err_unpin;
7790         }
7791
7792         return ctx;
7793
7794 err_unpin:
7795         i915_gem_object_unpin(ctx);
7796 err_unref:
7797         drm_gem_object_unreference(&ctx->base);
7798         mutex_unlock(&dev->struct_mutex);
7799         return NULL;
7800 }
7801
7802 bool ironlake_set_drps(struct drm_device *dev, u8 val)
7803 {
7804         struct drm_i915_private *dev_priv = dev->dev_private;
7805         u16 rgvswctl;
7806
7807         rgvswctl = I915_READ16(MEMSWCTL);
7808         if (rgvswctl & MEMCTL_CMD_STS) {
7809                 DRM_DEBUG("gpu busy, RCS change rejected\n");
7810                 return false; /* still busy with another command */
7811         }
7812
7813         rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
7814                 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
7815         I915_WRITE16(MEMSWCTL, rgvswctl);
7816         POSTING_READ16(MEMSWCTL);
7817
7818         rgvswctl |= MEMCTL_CMD_STS;
7819         I915_WRITE16(MEMSWCTL, rgvswctl);
7820
7821         return true;
7822 }
7823
7824 void ironlake_enable_drps(struct drm_device *dev)
7825 {
7826         struct drm_i915_private *dev_priv = dev->dev_private;
7827         u32 rgvmodectl = I915_READ(MEMMODECTL);
7828         u8 fmax, fmin, fstart, vstart;
7829
7830         /* Enable temp reporting */
7831         I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
7832         I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
7833
7834         /* 100ms RC evaluation intervals */
7835         I915_WRITE(RCUPEI, 100000);
7836         I915_WRITE(RCDNEI, 100000);
7837
7838         /* Set max/min thresholds to 90ms and 80ms respectively */
7839         I915_WRITE(RCBMAXAVG, 90000);
7840         I915_WRITE(RCBMINAVG, 80000);
7841
7842         I915_WRITE(MEMIHYST, 1);
7843
7844         /* Set up min, max, and cur for interrupt handling */
7845         fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
7846         fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
7847         fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
7848                 MEMMODE_FSTART_SHIFT;
7849
7850         vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
7851                 PXVFREQ_PX_SHIFT;
7852
7853         dev_priv->fmax = fmax; /* IPS callback will increase this */
7854         dev_priv->fstart = fstart;
7855
7856         dev_priv->max_delay = fstart;
7857         dev_priv->min_delay = fmin;
7858         dev_priv->cur_delay = fstart;
7859
7860         DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
7861                          fmax, fmin, fstart);
7862
7863         I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
7864
7865         /*
7866          * Interrupts will be enabled in ironlake_irq_postinstall
7867          */
7868
7869         I915_WRITE(VIDSTART, vstart);
7870         POSTING_READ(VIDSTART);
7871
7872         rgvmodectl |= MEMMODE_SWMODE_EN;
7873         I915_WRITE(MEMMODECTL, rgvmodectl);
7874
7875         if (wait_for((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
7876                 DRM_ERROR("stuck trying to change perf mode\n");
7877         msleep(1);
7878
7879         ironlake_set_drps(dev, fstart);
7880
7881         dev_priv->last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
7882                 I915_READ(0x112e0);
7883         dev_priv->last_time1 = jiffies_to_msecs(jiffies);
7884         dev_priv->last_count2 = I915_READ(0x112f4);
7885         getrawmonotonic(&dev_priv->last_time2);
7886 }
7887
7888 void ironlake_disable_drps(struct drm_device *dev)
7889 {
7890         struct drm_i915_private *dev_priv = dev->dev_private;
7891         u16 rgvswctl = I915_READ16(MEMSWCTL);
7892
7893         /* Ack interrupts, disable EFC interrupt */
7894         I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
7895         I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
7896         I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
7897         I915_WRITE(DEIIR, DE_PCU_EVENT);
7898         I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
7899
7900         /* Go back to the starting frequency */
7901         ironlake_set_drps(dev, dev_priv->fstart);
7902         msleep(1);
7903         rgvswctl |= MEMCTL_CMD_STS;
7904         I915_WRITE(MEMSWCTL, rgvswctl);
7905         msleep(1);
7906
7907 }
7908
7909 void gen6_set_rps(struct drm_device *dev, u8 val)
7910 {
7911         struct drm_i915_private *dev_priv = dev->dev_private;
7912         u32 swreq;
7913
7914         swreq = (val & 0x3ff) << 25;
7915         I915_WRITE(GEN6_RPNSWREQ, swreq);
7916 }
7917
7918 void gen6_disable_rps(struct drm_device *dev)
7919 {
7920         struct drm_i915_private *dev_priv = dev->dev_private;
7921
7922         I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
7923         I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
7924         I915_WRITE(GEN6_PMIER, 0);
7925         /* Complete PM interrupt masking here doesn't race with the rps work
7926          * item again unmasking PM interrupts because that is using a different
7927          * register (PMIMR) to mask PM interrupts. The only risk is in leaving
7928          * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */
7929
7930         spin_lock_irq(&dev_priv->rps_lock);
7931         dev_priv->pm_iir = 0;
7932         spin_unlock_irq(&dev_priv->rps_lock);
7933
7934         I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
7935 }
7936
7937 static unsigned long intel_pxfreq(u32 vidfreq)
7938 {
7939         unsigned long freq;
7940         int div = (vidfreq & 0x3f0000) >> 16;
7941         int post = (vidfreq & 0x3000) >> 12;
7942         int pre = (vidfreq & 0x7);
7943
7944         if (!pre)
7945                 return 0;
7946
7947         freq = ((div * 133333) / ((1<<post) * pre));
7948
7949         return freq;
7950 }
7951
7952 void intel_init_emon(struct drm_device *dev)
7953 {
7954         struct drm_i915_private *dev_priv = dev->dev_private;
7955         u32 lcfuse;
7956         u8 pxw[16];
7957         int i;
7958
7959         /* Disable to program */
7960         I915_WRITE(ECR, 0);
7961         POSTING_READ(ECR);
7962
7963         /* Program energy weights for various events */
7964         I915_WRITE(SDEW, 0x15040d00);
7965         I915_WRITE(CSIEW0, 0x007f0000);
7966         I915_WRITE(CSIEW1, 0x1e220004);
7967         I915_WRITE(CSIEW2, 0x04000004);
7968
7969         for (i = 0; i < 5; i++)
7970                 I915_WRITE(PEW + (i * 4), 0);
7971         for (i = 0; i < 3; i++)
7972                 I915_WRITE(DEW + (i * 4), 0);
7973
7974         /* Program P-state weights to account for frequency power adjustment */
7975         for (i = 0; i < 16; i++) {
7976                 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
7977                 unsigned long freq = intel_pxfreq(pxvidfreq);
7978                 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
7979                         PXVFREQ_PX_SHIFT;
7980                 unsigned long val;
7981
7982                 val = vid * vid;
7983                 val *= (freq / 1000);
7984                 val *= 255;
7985                 val /= (127*127*900);
7986                 if (val > 0xff)
7987                         DRM_ERROR("bad pxval: %ld\n", val);
7988                 pxw[i] = val;
7989         }
7990         /* Render standby states get 0 weight */
7991         pxw[14] = 0;
7992         pxw[15] = 0;
7993
7994         for (i = 0; i < 4; i++) {
7995                 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
7996                         (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
7997                 I915_WRITE(PXW + (i * 4), val);
7998         }
7999
8000         /* Adjust magic regs to magic values (more experimental results) */
8001         I915_WRITE(OGW0, 0);
8002         I915_WRITE(OGW1, 0);
8003         I915_WRITE(EG0, 0x00007f00);
8004         I915_WRITE(EG1, 0x0000000e);
8005         I915_WRITE(EG2, 0x000e0000);
8006         I915_WRITE(EG3, 0x68000300);
8007         I915_WRITE(EG4, 0x42000000);
8008         I915_WRITE(EG5, 0x00140031);
8009         I915_WRITE(EG6, 0);
8010         I915_WRITE(EG7, 0);
8011
8012         for (i = 0; i < 8; i++)
8013                 I915_WRITE(PXWL + (i * 4), 0);
8014
8015         /* Enable PMON + select events */
8016         I915_WRITE(ECR, 0x80000019);
8017
8018         lcfuse = I915_READ(LCFUSE02);
8019
8020         dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK);
8021 }
8022
8023 static bool intel_enable_rc6(struct drm_device *dev)
8024 {
8025         /*
8026          * Respect the kernel parameter if it is set
8027          */
8028         if (i915_enable_rc6 >= 0)
8029                 return i915_enable_rc6;
8030
8031         /*
8032          * Disable RC6 on Ironlake
8033          */
8034         if (INTEL_INFO(dev)->gen == 5)
8035                 return 0;
8036
8037         /*
8038          * Disable rc6 on Sandybridge
8039          */
8040         if (INTEL_INFO(dev)->gen == 6) {
8041                 DRM_DEBUG_DRIVER("Sandybridge: RC6 disabled\n");
8042                 return 0;
8043         }
8044         DRM_DEBUG_DRIVER("RC6 enabled\n");
8045         return 1;
8046 }
8047
8048 void gen6_enable_rps(struct drm_i915_private *dev_priv)
8049 {
8050         u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
8051         u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
8052         u32 pcu_mbox, rc6_mask = 0;
8053         int cur_freq, min_freq, max_freq;
8054         int i;
8055
8056         /* Here begins a magic sequence of register writes to enable
8057          * auto-downclocking.
8058          *
8059          * Perhaps there might be some value in exposing these to
8060          * userspace...
8061          */
8062         I915_WRITE(GEN6_RC_STATE, 0);
8063         mutex_lock(&dev_priv->dev->struct_mutex);
8064         gen6_gt_force_wake_get(dev_priv);
8065
8066         /* disable the counters and set deterministic thresholds */
8067         I915_WRITE(GEN6_RC_CONTROL, 0);
8068
8069         I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
8070         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
8071         I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
8072         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
8073         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
8074
8075         for (i = 0; i < I915_NUM_RINGS; i++)
8076                 I915_WRITE(RING_MAX_IDLE(dev_priv->ring[i].mmio_base), 10);
8077
8078         I915_WRITE(GEN6_RC_SLEEP, 0);
8079         I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
8080         I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
8081         I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
8082         I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
8083
8084         if (intel_enable_rc6(dev_priv->dev))
8085                 rc6_mask = GEN6_RC_CTL_RC6_ENABLE |
8086                         ((IS_GEN7(dev_priv->dev)) ? GEN6_RC_CTL_RC6p_ENABLE : 0);
8087
8088         I915_WRITE(GEN6_RC_CONTROL,
8089                    rc6_mask |
8090                    GEN6_RC_CTL_EI_MODE(1) |
8091                    GEN6_RC_CTL_HW_ENABLE);
8092
8093         I915_WRITE(GEN6_RPNSWREQ,
8094                    GEN6_FREQUENCY(10) |
8095                    GEN6_OFFSET(0) |
8096                    GEN6_AGGRESSIVE_TURBO);
8097         I915_WRITE(GEN6_RC_VIDEO_FREQ,
8098                    GEN6_FREQUENCY(12));
8099
8100         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
8101         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
8102                    18 << 24 |
8103                    6 << 16);
8104         I915_WRITE(GEN6_RP_UP_THRESHOLD, 10000);
8105         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 1000000);
8106         I915_WRITE(GEN6_RP_UP_EI, 100000);
8107         I915_WRITE(GEN6_RP_DOWN_EI, 5000000);
8108         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
8109         I915_WRITE(GEN6_RP_CONTROL,
8110                    GEN6_RP_MEDIA_TURBO |
8111                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
8112                    GEN6_RP_MEDIA_IS_GFX |
8113                    GEN6_RP_ENABLE |
8114                    GEN6_RP_UP_BUSY_AVG |
8115                    GEN6_RP_DOWN_IDLE_CONT);
8116
8117         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
8118                      500))
8119                 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
8120
8121         I915_WRITE(GEN6_PCODE_DATA, 0);
8122         I915_WRITE(GEN6_PCODE_MAILBOX,
8123                    GEN6_PCODE_READY |
8124                    GEN6_PCODE_WRITE_MIN_FREQ_TABLE);
8125         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
8126                      500))
8127                 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
8128
8129         min_freq = (rp_state_cap & 0xff0000) >> 16;
8130         max_freq = rp_state_cap & 0xff;
8131         cur_freq = (gt_perf_status & 0xff00) >> 8;
8132
8133         /* Check for overclock support */
8134         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
8135                      500))
8136                 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
8137         I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_READ_OC_PARAMS);
8138         pcu_mbox = I915_READ(GEN6_PCODE_DATA);
8139         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
8140                      500))
8141                 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
8142         if (pcu_mbox & (1<<31)) { /* OC supported */
8143                 max_freq = pcu_mbox & 0xff;
8144                 DRM_DEBUG_DRIVER("overclocking supported, adjusting frequency max to %dMHz\n", pcu_mbox * 50);
8145         }
8146
8147         /* In units of 100MHz */
8148         dev_priv->max_delay = max_freq;
8149         dev_priv->min_delay = min_freq;
8150         dev_priv->cur_delay = cur_freq;
8151
8152         /* requires MSI enabled */
8153         I915_WRITE(GEN6_PMIER,
8154                    GEN6_PM_MBOX_EVENT |
8155                    GEN6_PM_THERMAL_EVENT |
8156                    GEN6_PM_RP_DOWN_TIMEOUT |
8157                    GEN6_PM_RP_UP_THRESHOLD |
8158                    GEN6_PM_RP_DOWN_THRESHOLD |
8159                    GEN6_PM_RP_UP_EI_EXPIRED |
8160                    GEN6_PM_RP_DOWN_EI_EXPIRED);
8161         spin_lock_irq(&dev_priv->rps_lock);
8162         WARN_ON(dev_priv->pm_iir != 0);
8163         I915_WRITE(GEN6_PMIMR, 0);
8164         spin_unlock_irq(&dev_priv->rps_lock);
8165         /* enable all PM interrupts */
8166         I915_WRITE(GEN6_PMINTRMSK, 0);
8167
8168         gen6_gt_force_wake_put(dev_priv);
8169         mutex_unlock(&dev_priv->dev->struct_mutex);
8170 }
8171
8172 void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
8173 {
8174         int min_freq = 15;
8175         int gpu_freq, ia_freq, max_ia_freq;
8176         int scaling_factor = 180;
8177
8178         max_ia_freq = cpufreq_quick_get_max(0);
8179         /*
8180          * Default to measured freq if none found, PCU will ensure we don't go
8181          * over
8182          */
8183         if (!max_ia_freq)
8184                 max_ia_freq = tsc_khz;
8185
8186         /* Convert from kHz to MHz */
8187         max_ia_freq /= 1000;
8188
8189         mutex_lock(&dev_priv->dev->struct_mutex);
8190
8191         /*
8192          * For each potential GPU frequency, load a ring frequency we'd like
8193          * to use for memory access.  We do this by specifying the IA frequency
8194          * the PCU should use as a reference to determine the ring frequency.
8195          */
8196         for (gpu_freq = dev_priv->max_delay; gpu_freq >= dev_priv->min_delay;
8197              gpu_freq--) {
8198                 int diff = dev_priv->max_delay - gpu_freq;
8199
8200                 /*
8201                  * For GPU frequencies less than 750MHz, just use the lowest
8202                  * ring freq.
8203                  */
8204                 if (gpu_freq < min_freq)
8205                         ia_freq = 800;
8206                 else
8207                         ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
8208                 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
8209
8210                 I915_WRITE(GEN6_PCODE_DATA,
8211                            (ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT) |
8212                            gpu_freq);
8213                 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY |
8214                            GEN6_PCODE_WRITE_MIN_FREQ_TABLE);
8215                 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) &
8216                               GEN6_PCODE_READY) == 0, 10)) {
8217                         DRM_ERROR("pcode write of freq table timed out\n");
8218                         continue;
8219                 }
8220         }
8221
8222         mutex_unlock(&dev_priv->dev->struct_mutex);
8223 }
8224
8225 static void ironlake_init_clock_gating(struct drm_device *dev)
8226 {
8227         struct drm_i915_private *dev_priv = dev->dev_private;
8228         uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
8229
8230         /* Required for FBC */
8231         dspclk_gate |= DPFCUNIT_CLOCK_GATE_DISABLE |
8232                 DPFCRUNIT_CLOCK_GATE_DISABLE |
8233                 DPFDUNIT_CLOCK_GATE_DISABLE;
8234         /* Required for CxSR */
8235         dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE;
8236
8237         I915_WRITE(PCH_3DCGDIS0,
8238                    MARIUNIT_CLOCK_GATE_DISABLE |
8239                    SVSMUNIT_CLOCK_GATE_DISABLE);
8240         I915_WRITE(PCH_3DCGDIS1,
8241                    VFMUNIT_CLOCK_GATE_DISABLE);
8242
8243         I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
8244
8245         /*
8246          * According to the spec the following bits should be set in
8247          * order to enable memory self-refresh
8248          * The bit 22/21 of 0x42004
8249          * The bit 5 of 0x42020
8250          * The bit 15 of 0x45000
8251          */
8252         I915_WRITE(ILK_DISPLAY_CHICKEN2,
8253                    (I915_READ(ILK_DISPLAY_CHICKEN2) |
8254                     ILK_DPARB_GATE | ILK_VSDPFD_FULL));
8255         I915_WRITE(ILK_DSPCLK_GATE,
8256                    (I915_READ(ILK_DSPCLK_GATE) |
8257                     ILK_DPARB_CLK_GATE));
8258         I915_WRITE(DISP_ARB_CTL,
8259                    (I915_READ(DISP_ARB_CTL) |
8260                     DISP_FBC_WM_DIS));
8261         I915_WRITE(WM3_LP_ILK, 0);
8262         I915_WRITE(WM2_LP_ILK, 0);
8263         I915_WRITE(WM1_LP_ILK, 0);
8264
8265         /*
8266          * Based on the document from hardware guys the following bits
8267          * should be set unconditionally in order to enable FBC.
8268          * The bit 22 of 0x42000
8269          * The bit 22 of 0x42004
8270          * The bit 7,8,9 of 0x42020.
8271          */
8272         if (IS_IRONLAKE_M(dev)) {
8273                 I915_WRITE(ILK_DISPLAY_CHICKEN1,
8274                            I915_READ(ILK_DISPLAY_CHICKEN1) |
8275                            ILK_FBCQ_DIS);
8276                 I915_WRITE(ILK_DISPLAY_CHICKEN2,
8277                            I915_READ(ILK_DISPLAY_CHICKEN2) |
8278                            ILK_DPARB_GATE);
8279                 I915_WRITE(ILK_DSPCLK_GATE,
8280                            I915_READ(ILK_DSPCLK_GATE) |
8281                            ILK_DPFC_DIS1 |
8282                            ILK_DPFC_DIS2 |
8283                            ILK_CLK_FBC);
8284         }
8285
8286         I915_WRITE(ILK_DISPLAY_CHICKEN2,
8287                    I915_READ(ILK_DISPLAY_CHICKEN2) |
8288                    ILK_ELPIN_409_SELECT);
8289         I915_WRITE(_3D_CHICKEN2,
8290                    _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
8291                    _3D_CHICKEN2_WM_READ_PIPELINED);
8292 }
8293
8294 static void gen6_init_clock_gating(struct drm_device *dev)
8295 {
8296         struct drm_i915_private *dev_priv = dev->dev_private;
8297         int pipe;
8298         uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
8299
8300         I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
8301
8302         I915_WRITE(ILK_DISPLAY_CHICKEN2,
8303                    I915_READ(ILK_DISPLAY_CHICKEN2) |
8304                    ILK_ELPIN_409_SELECT);
8305
8306         /* WaDisableHiZPlanesWhenMSAAEnabled */
8307         I915_WRITE(_3D_CHICKEN,
8308                    _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
8309
8310         I915_WRITE(WM3_LP_ILK, 0);
8311         I915_WRITE(WM2_LP_ILK, 0);
8312         I915_WRITE(WM1_LP_ILK, 0);
8313
8314         /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
8315          * gating disable must be set.  Failure to set it results in
8316          * flickering pixels due to Z write ordering failures after
8317          * some amount of runtime in the Mesa "fire" demo, and Unigine
8318          * Sanctuary and Tropics, and apparently anything else with
8319          * alpha test or pixel discard.
8320          *
8321          * According to the spec, bit 11 (RCCUNIT) must also be set,
8322          * but we didn't debug actual testcases to find it out.
8323          */
8324         I915_WRITE(GEN6_UCGCTL2,
8325                    GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
8326                    GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
8327
8328         /*
8329          * According to the spec the following bits should be
8330          * set in order to enable memory self-refresh and fbc:
8331          * The bit21 and bit22 of 0x42000
8332          * The bit21 and bit22 of 0x42004
8333          * The bit5 and bit7 of 0x42020
8334          * The bit14 of 0x70180
8335          * The bit14 of 0x71180
8336          */
8337         I915_WRITE(ILK_DISPLAY_CHICKEN1,
8338                    I915_READ(ILK_DISPLAY_CHICKEN1) |
8339                    ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
8340         I915_WRITE(ILK_DISPLAY_CHICKEN2,
8341                    I915_READ(ILK_DISPLAY_CHICKEN2) |
8342                    ILK_DPARB_GATE | ILK_VSDPFD_FULL);
8343         I915_WRITE(ILK_DSPCLK_GATE,
8344                    I915_READ(ILK_DSPCLK_GATE) |
8345                    ILK_DPARB_CLK_GATE  |
8346                    ILK_DPFD_CLK_GATE);
8347
8348         for_each_pipe(pipe) {
8349                 I915_WRITE(DSPCNTR(pipe),
8350                            I915_READ(DSPCNTR(pipe)) |
8351                            DISPPLANE_TRICKLE_FEED_DISABLE);
8352                 intel_flush_display_plane(dev_priv, pipe);
8353         }
8354
8355         /* The default value should be 0x200 according to docs, but the two
8356          * platforms I checked have a 0 for this. (Maybe BIOS overrides?) */
8357         I915_WRITE(GEN6_GT_MODE, 0xffff << 16);
8358         I915_WRITE(GEN6_GT_MODE, GEN6_GT_MODE_HI << 16 | GEN6_GT_MODE_HI);
8359 }
8360
8361 static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
8362 {
8363         uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
8364
8365         reg &= ~GEN7_FF_SCHED_MASK;
8366         reg |= GEN7_FF_TS_SCHED_HW;
8367         reg |= GEN7_FF_VS_SCHED_HW;
8368         reg |= GEN7_FF_DS_SCHED_HW;
8369
8370         I915_WRITE(GEN7_FF_THREAD_MODE, reg);
8371 }
8372
8373 static void ivybridge_init_clock_gating(struct drm_device *dev)
8374 {
8375         struct drm_i915_private *dev_priv = dev->dev_private;
8376         int pipe;
8377         uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
8378
8379         I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
8380
8381         I915_WRITE(WM3_LP_ILK, 0);
8382         I915_WRITE(WM2_LP_ILK, 0);
8383         I915_WRITE(WM1_LP_ILK, 0);
8384
8385         /* According to the spec, bit 13 (RCZUNIT) must be set on IVB.
8386          * This implements the WaDisableRCZUnitClockGating workaround.
8387          */
8388         I915_WRITE(GEN6_UCGCTL2, GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
8389
8390         I915_WRITE(ILK_DSPCLK_GATE, IVB_VRHUNIT_CLK_GATE);
8391
8392         /* Apply the WaDisableRHWOOptimizationForRenderHang workaround. */
8393         I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
8394                    GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
8395
8396         /* WaApplyL3ControlAndL3ChickenMode requires those two on Ivy Bridge */
8397         I915_WRITE(GEN7_L3CNTLREG1,
8398                         GEN7_WA_FOR_GEN7_L3_CONTROL);
8399         I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
8400                         GEN7_WA_L3_CHICKEN_MODE);
8401
8402         /* This is required by WaCatErrorRejectionIssue */
8403         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
8404                         I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
8405                         GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
8406
8407         for_each_pipe(pipe) {
8408                 I915_WRITE(DSPCNTR(pipe),
8409                            I915_READ(DSPCNTR(pipe)) |
8410                            DISPPLANE_TRICKLE_FEED_DISABLE);
8411                 intel_flush_display_plane(dev_priv, pipe);
8412         }
8413
8414         gen7_setup_fixed_func_scheduler(dev_priv);
8415 }
8416
8417 static void g4x_init_clock_gating(struct drm_device *dev)
8418 {
8419         struct drm_i915_private *dev_priv = dev->dev_private;
8420         uint32_t dspclk_gate;
8421
8422         I915_WRITE(RENCLK_GATE_D1, 0);
8423         I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
8424                    GS_UNIT_CLOCK_GATE_DISABLE |
8425                    CL_UNIT_CLOCK_GATE_DISABLE);
8426         I915_WRITE(RAMCLK_GATE_D, 0);
8427         dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
8428                 OVRUNIT_CLOCK_GATE_DISABLE |
8429                 OVCUNIT_CLOCK_GATE_DISABLE;
8430         if (IS_GM45(dev))
8431                 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
8432         I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
8433 }
8434
8435 static void crestline_init_clock_gating(struct drm_device *dev)
8436 {
8437         struct drm_i915_private *dev_priv = dev->dev_private;
8438
8439         I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
8440         I915_WRITE(RENCLK_GATE_D2, 0);
8441         I915_WRITE(DSPCLK_GATE_D, 0);
8442         I915_WRITE(RAMCLK_GATE_D, 0);
8443         I915_WRITE16(DEUC, 0);
8444 }
8445
8446 static void broadwater_init_clock_gating(struct drm_device *dev)
8447 {
8448         struct drm_i915_private *dev_priv = dev->dev_private;
8449
8450         I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
8451                    I965_RCC_CLOCK_GATE_DISABLE |
8452                    I965_RCPB_CLOCK_GATE_DISABLE |
8453                    I965_ISC_CLOCK_GATE_DISABLE |
8454                    I965_FBC_CLOCK_GATE_DISABLE);
8455         I915_WRITE(RENCLK_GATE_D2, 0);
8456 }
8457
8458 static void gen3_init_clock_gating(struct drm_device *dev)
8459 {
8460         struct drm_i915_private *dev_priv = dev->dev_private;
8461         u32 dstate = I915_READ(D_STATE);
8462
8463         dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
8464                 DSTATE_DOT_CLOCK_GATING;
8465         I915_WRITE(D_STATE, dstate);
8466 }
8467
8468 static void i85x_init_clock_gating(struct drm_device *dev)
8469 {
8470         struct drm_i915_private *dev_priv = dev->dev_private;
8471
8472         I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
8473 }
8474
8475 static void i830_init_clock_gating(struct drm_device *dev)
8476 {
8477         struct drm_i915_private *dev_priv = dev->dev_private;
8478
8479         I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
8480 }
8481
8482 static void ibx_init_clock_gating(struct drm_device *dev)
8483 {
8484         struct drm_i915_private *dev_priv = dev->dev_private;
8485
8486         /*
8487          * On Ibex Peak and Cougar Point, we need to disable clock
8488          * gating for the panel power sequencer or it will fail to
8489          * start up when no ports are active.
8490          */
8491         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
8492 }
8493
8494 static void cpt_init_clock_gating(struct drm_device *dev)
8495 {
8496         struct drm_i915_private *dev_priv = dev->dev_private;
8497         int pipe;
8498
8499         /*
8500          * On Ibex Peak and Cougar Point, we need to disable clock
8501          * gating for the panel power sequencer or it will fail to
8502          * start up when no ports are active.
8503          */
8504         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
8505         I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
8506                    DPLS_EDP_PPS_FIX_DIS);
8507         /* Without this, mode sets may fail silently on FDI */
8508         for_each_pipe(pipe)
8509                 I915_WRITE(TRANS_CHICKEN2(pipe), TRANS_AUTOTRAIN_GEN_STALL_DIS);
8510 }
8511
8512 static void ironlake_teardown_rc6(struct drm_device *dev)
8513 {
8514         struct drm_i915_private *dev_priv = dev->dev_private;
8515
8516         if (dev_priv->renderctx) {
8517                 i915_gem_object_unpin(dev_priv->renderctx);
8518                 drm_gem_object_unreference(&dev_priv->renderctx->base);
8519                 dev_priv->renderctx = NULL;
8520         }
8521
8522         if (dev_priv->pwrctx) {
8523                 i915_gem_object_unpin(dev_priv->pwrctx);
8524                 drm_gem_object_unreference(&dev_priv->pwrctx->base);
8525                 dev_priv->pwrctx = NULL;
8526         }
8527 }
8528
8529 static void ironlake_disable_rc6(struct drm_device *dev)
8530 {
8531         struct drm_i915_private *dev_priv = dev->dev_private;
8532
8533         if (I915_READ(PWRCTXA)) {
8534                 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
8535                 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
8536                 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
8537                          50);
8538
8539                 I915_WRITE(PWRCTXA, 0);
8540                 POSTING_READ(PWRCTXA);
8541
8542                 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
8543                 POSTING_READ(RSTDBYCTL);
8544         }
8545
8546         ironlake_teardown_rc6(dev);
8547 }
8548
8549 static int ironlake_setup_rc6(struct drm_device *dev)
8550 {
8551         struct drm_i915_private *dev_priv = dev->dev_private;
8552
8553         if (dev_priv->renderctx == NULL)
8554                 dev_priv->renderctx = intel_alloc_context_page(dev);
8555         if (!dev_priv->renderctx)
8556                 return -ENOMEM;
8557
8558         if (dev_priv->pwrctx == NULL)
8559                 dev_priv->pwrctx = intel_alloc_context_page(dev);
8560         if (!dev_priv->pwrctx) {
8561                 ironlake_teardown_rc6(dev);
8562                 return -ENOMEM;
8563         }
8564
8565         return 0;
8566 }
8567
8568 void ironlake_enable_rc6(struct drm_device *dev)
8569 {
8570         struct drm_i915_private *dev_priv = dev->dev_private;
8571         int ret;
8572
8573         /* rc6 disabled by default due to repeated reports of hanging during
8574          * boot and resume.
8575          */
8576         if (!intel_enable_rc6(dev))
8577                 return;
8578
8579         mutex_lock(&dev->struct_mutex);
8580         ret = ironlake_setup_rc6(dev);
8581         if (ret) {
8582                 mutex_unlock(&dev->struct_mutex);
8583                 return;
8584         }
8585
8586         /*
8587          * GPU can automatically power down the render unit if given a page
8588          * to save state.
8589          */
8590         ret = BEGIN_LP_RING(6);
8591         if (ret) {
8592                 ironlake_teardown_rc6(dev);
8593                 mutex_unlock(&dev->struct_mutex);
8594                 return;
8595         }
8596
8597         OUT_RING(MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
8598         OUT_RING(MI_SET_CONTEXT);
8599         OUT_RING(dev_priv->renderctx->gtt_offset |
8600                  MI_MM_SPACE_GTT |
8601                  MI_SAVE_EXT_STATE_EN |
8602                  MI_RESTORE_EXT_STATE_EN |
8603                  MI_RESTORE_INHIBIT);
8604         OUT_RING(MI_SUSPEND_FLUSH);
8605         OUT_RING(MI_NOOP);
8606         OUT_RING(MI_FLUSH);
8607         ADVANCE_LP_RING();
8608
8609         /*
8610          * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
8611          * does an implicit flush, combined with MI_FLUSH above, it should be
8612          * safe to assume that renderctx is valid
8613          */
8614         ret = intel_wait_ring_idle(LP_RING(dev_priv));
8615         if (ret) {
8616                 DRM_ERROR("failed to enable ironlake power power savings\n");
8617                 ironlake_teardown_rc6(dev);
8618                 mutex_unlock(&dev->struct_mutex);
8619                 return;
8620         }
8621
8622         I915_WRITE(PWRCTXA, dev_priv->pwrctx->gtt_offset | PWRCTX_EN);
8623         I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
8624         mutex_unlock(&dev->struct_mutex);
8625 }
8626
8627 void intel_init_clock_gating(struct drm_device *dev)
8628 {
8629         struct drm_i915_private *dev_priv = dev->dev_private;
8630
8631         dev_priv->display.init_clock_gating(dev);
8632
8633         if (dev_priv->display.init_pch_clock_gating)
8634                 dev_priv->display.init_pch_clock_gating(dev);
8635 }
8636
8637 /* Set up chip specific display functions */
8638 static void intel_init_display(struct drm_device *dev)
8639 {
8640         struct drm_i915_private *dev_priv = dev->dev_private;
8641
8642         /* We always want a DPMS function */
8643         if (HAS_PCH_SPLIT(dev)) {
8644                 dev_priv->display.dpms = ironlake_crtc_dpms;
8645                 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
8646                 dev_priv->display.update_plane = ironlake_update_plane;
8647         } else {
8648                 dev_priv->display.dpms = i9xx_crtc_dpms;
8649                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
8650                 dev_priv->display.update_plane = i9xx_update_plane;
8651         }
8652
8653         if (I915_HAS_FBC(dev)) {
8654                 if (HAS_PCH_SPLIT(dev)) {
8655                         dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
8656                         dev_priv->display.enable_fbc = ironlake_enable_fbc;
8657                         dev_priv->display.disable_fbc = ironlake_disable_fbc;
8658                 } else if (IS_GM45(dev)) {
8659                         dev_priv->display.fbc_enabled = g4x_fbc_enabled;
8660                         dev_priv->display.enable_fbc = g4x_enable_fbc;
8661                         dev_priv->display.disable_fbc = g4x_disable_fbc;
8662                 } else if (IS_CRESTLINE(dev)) {
8663                         dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
8664                         dev_priv->display.enable_fbc = i8xx_enable_fbc;
8665                         dev_priv->display.disable_fbc = i8xx_disable_fbc;
8666                 }
8667                 /* 855GM needs testing */
8668         }
8669
8670         /* Returns the core display clock speed */
8671         if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
8672                 dev_priv->display.get_display_clock_speed =
8673                         i945_get_display_clock_speed;
8674         else if (IS_I915G(dev))
8675                 dev_priv->display.get_display_clock_speed =
8676                         i915_get_display_clock_speed;
8677         else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
8678                 dev_priv->display.get_display_clock_speed =
8679                         i9xx_misc_get_display_clock_speed;
8680         else if (IS_I915GM(dev))
8681                 dev_priv->display.get_display_clock_speed =
8682                         i915gm_get_display_clock_speed;
8683         else if (IS_I865G(dev))
8684                 dev_priv->display.get_display_clock_speed =
8685                         i865_get_display_clock_speed;
8686         else if (IS_I85X(dev))
8687                 dev_priv->display.get_display_clock_speed =
8688                         i855_get_display_clock_speed;
8689         else /* 852, 830 */
8690                 dev_priv->display.get_display_clock_speed =
8691                         i830_get_display_clock_speed;
8692
8693         /* For FIFO watermark updates */
8694         if (HAS_PCH_SPLIT(dev)) {
8695                 dev_priv->display.force_wake_get = __gen6_gt_force_wake_get;
8696                 dev_priv->display.force_wake_put = __gen6_gt_force_wake_put;
8697
8698                 /* IVB configs may use multi-threaded forcewake */
8699                 if (IS_IVYBRIDGE(dev)) {
8700                         u32     ecobus;
8701
8702                         mutex_lock(&dev->struct_mutex);
8703                         __gen6_gt_force_wake_mt_get(dev_priv);
8704                         ecobus = I915_READ(ECOBUS);
8705                         __gen6_gt_force_wake_mt_put(dev_priv);
8706                         mutex_unlock(&dev->struct_mutex);
8707
8708                         if (ecobus & FORCEWAKE_MT_ENABLE) {
8709                                 DRM_DEBUG_KMS("Using MT version of forcewake\n");
8710                                 dev_priv->display.force_wake_get =
8711                                         __gen6_gt_force_wake_mt_get;
8712                                 dev_priv->display.force_wake_put =
8713                                         __gen6_gt_force_wake_mt_put;
8714                         }
8715                 }
8716
8717                 if (HAS_PCH_IBX(dev))
8718                         dev_priv->display.init_pch_clock_gating = ibx_init_clock_gating;
8719                 else if (HAS_PCH_CPT(dev))
8720                         dev_priv->display.init_pch_clock_gating = cpt_init_clock_gating;
8721
8722                 if (IS_GEN5(dev)) {
8723                         if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
8724                                 dev_priv->display.update_wm = ironlake_update_wm;
8725                         else {
8726                                 DRM_DEBUG_KMS("Failed to get proper latency. "
8727                                               "Disable CxSR\n");
8728                                 dev_priv->display.update_wm = NULL;
8729                         }
8730                         dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
8731                         dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
8732                         dev_priv->display.write_eld = ironlake_write_eld;
8733                 } else if (IS_GEN6(dev)) {
8734                         if (SNB_READ_WM0_LATENCY()) {
8735                                 dev_priv->display.update_wm = sandybridge_update_wm;
8736                         } else {
8737                                 DRM_DEBUG_KMS("Failed to read display plane latency. "
8738                                               "Disable CxSR\n");
8739                                 dev_priv->display.update_wm = NULL;
8740                         }
8741                         dev_priv->display.fdi_link_train = gen6_fdi_link_train;
8742                         dev_priv->display.init_clock_gating = gen6_init_clock_gating;
8743                         dev_priv->display.write_eld = ironlake_write_eld;
8744                 } else if (IS_IVYBRIDGE(dev)) {
8745                         /* FIXME: detect B0+ stepping and use auto training */
8746                         dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
8747                         if (SNB_READ_WM0_LATENCY()) {
8748                                 dev_priv->display.update_wm = sandybridge_update_wm;
8749                         } else {
8750                                 DRM_DEBUG_KMS("Failed to read display plane latency. "
8751                                               "Disable CxSR\n");
8752                                 dev_priv->display.update_wm = NULL;
8753                         }
8754                         dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
8755                         dev_priv->display.write_eld = ironlake_write_eld;
8756                 } else
8757                         dev_priv->display.update_wm = NULL;
8758         } else if (IS_PINEVIEW(dev)) {
8759                 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
8760                                             dev_priv->is_ddr3,
8761                                             dev_priv->fsb_freq,
8762                                             dev_priv->mem_freq)) {
8763                         DRM_INFO("failed to find known CxSR latency "
8764                                  "(found ddr%s fsb freq %d, mem freq %d), "
8765                                  "disabling CxSR\n",
8766                                  (dev_priv->is_ddr3 == 1) ? "3" : "2",
8767                                  dev_priv->fsb_freq, dev_priv->mem_freq);
8768                         /* Disable CxSR and never update its watermark again */
8769                         pineview_disable_cxsr(dev);
8770                         dev_priv->display.update_wm = NULL;
8771                 } else
8772                         dev_priv->display.update_wm = pineview_update_wm;
8773                 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
8774         } else if (IS_G4X(dev)) {
8775                 dev_priv->display.write_eld = g4x_write_eld;
8776                 dev_priv->display.update_wm = g4x_update_wm;
8777                 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
8778         } else if (IS_GEN4(dev)) {
8779                 dev_priv->display.update_wm = i965_update_wm;
8780                 if (IS_CRESTLINE(dev))
8781                         dev_priv->display.init_clock_gating = crestline_init_clock_gating;
8782                 else if (IS_BROADWATER(dev))
8783                         dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
8784         } else if (IS_GEN3(dev)) {
8785                 dev_priv->display.update_wm = i9xx_update_wm;
8786                 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
8787                 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
8788         } else if (IS_I865G(dev)) {
8789                 dev_priv->display.update_wm = i830_update_wm;
8790                 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
8791                 dev_priv->display.get_fifo_size = i830_get_fifo_size;
8792         } else if (IS_I85X(dev)) {
8793                 dev_priv->display.update_wm = i9xx_update_wm;
8794                 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
8795                 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
8796         } else {
8797                 dev_priv->display.update_wm = i830_update_wm;
8798                 dev_priv->display.init_clock_gating = i830_init_clock_gating;
8799                 if (IS_845G(dev))
8800                         dev_priv->display.get_fifo_size = i845_get_fifo_size;
8801                 else
8802                         dev_priv->display.get_fifo_size = i830_get_fifo_size;
8803         }
8804
8805         /* Default just returns -ENODEV to indicate unsupported */
8806         dev_priv->display.queue_flip = intel_default_queue_flip;
8807
8808         switch (INTEL_INFO(dev)->gen) {
8809         case 2:
8810                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
8811                 break;
8812
8813         case 3:
8814                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
8815                 break;
8816
8817         case 4:
8818         case 5:
8819                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
8820                 break;
8821
8822         case 6:
8823                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
8824                 break;
8825         case 7:
8826                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
8827                 break;
8828         }
8829 }
8830
8831 /*
8832  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
8833  * resume, or other times.  This quirk makes sure that's the case for
8834  * affected systems.
8835  */
8836 static void quirk_pipea_force(struct drm_device *dev)
8837 {
8838         struct drm_i915_private *dev_priv = dev->dev_private;
8839
8840         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
8841         DRM_DEBUG_DRIVER("applying pipe a force quirk\n");
8842 }
8843
8844 /*
8845  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
8846  */
8847 static void quirk_ssc_force_disable(struct drm_device *dev)
8848 {
8849         struct drm_i915_private *dev_priv = dev->dev_private;
8850         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
8851 }
8852
8853 /*
8854  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
8855  * brightness value
8856  */
8857 static void quirk_invert_brightness(struct drm_device *dev)
8858 {
8859         struct drm_i915_private *dev_priv = dev->dev_private;
8860         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
8861 }
8862
8863 /*
8864  * Some machines (Dell XPS13) suffer broken backlight controls if
8865  * BLM_PCH_PWM_ENABLE is set.
8866  */
8867 static void quirk_no_pcm_pwm_enable(struct drm_device *dev)
8868 {
8869         struct drm_i915_private *dev_priv = dev->dev_private;
8870         dev_priv->quirks |= QUIRK_NO_PCH_PWM_ENABLE;
8871         DRM_INFO("applying no-PCH_PWM_ENABLE quirk\n");
8872 }
8873
8874 struct intel_quirk {
8875         int device;
8876         int subsystem_vendor;
8877         int subsystem_device;
8878         void (*hook)(struct drm_device *dev);
8879 };
8880
8881 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
8882 struct intel_dmi_quirk {
8883         void (*hook)(struct drm_device *dev);
8884         const struct dmi_system_id (*dmi_id_list)[];
8885 };
8886
8887 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
8888 {
8889         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
8890         return 1;
8891 }
8892
8893 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
8894         {
8895                 .dmi_id_list = &(const struct dmi_system_id[]) {
8896                         {
8897                                 .callback = intel_dmi_reverse_brightness,
8898                                 .ident = "NCR Corporation",
8899                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
8900                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
8901                                 },
8902                         },
8903                         { }  /* terminating entry */
8904                 },
8905                 .hook = quirk_invert_brightness,
8906         },
8907 };
8908
8909 struct intel_quirk intel_quirks[] = {
8910         /* HP Compaq 2730p needs pipe A force quirk (LP: #291555) */
8911         { 0x2a42, 0x103c, 0x30eb, quirk_pipea_force },
8912         /* HP Mini needs pipe A force quirk (LP: #322104) */
8913         { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
8914
8915         /* Thinkpad R31 needs pipe A force quirk */
8916         { 0x3577, 0x1014, 0x0505, quirk_pipea_force },
8917         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
8918         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
8919
8920         /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
8921         { 0x3577,  0x1014, 0x0513, quirk_pipea_force },
8922         /* ThinkPad X40 needs pipe A force quirk */
8923
8924         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
8925         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
8926
8927         /* 855 & before need to leave pipe A & dpll A up */
8928         { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
8929         { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
8930
8931         /* Lenovo U160 cannot use SSC on LVDS */
8932         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
8933
8934         /* Sony Vaio Y cannot use SSC on LVDS */
8935         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
8936
8937         /* Acer Aspire 5734Z must invert backlight brightness */
8938         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
8939
8940         /* Acer/eMachines G725 */
8941         { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
8942
8943         /* Acer/eMachines e725 */
8944         { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
8945
8946         /* Acer/Packard Bell NCL20 */
8947         { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
8948
8949         /* Dell XPS13 HD Sandy Bridge */
8950         { 0x0116, 0x1028, 0x052e, quirk_no_pcm_pwm_enable },
8951         /* Dell XPS13 HD and XPS13 FHD Ivy Bridge */
8952         { 0x0166, 0x1028, 0x058b, quirk_no_pcm_pwm_enable },
8953 };
8954
8955 static void intel_init_quirks(struct drm_device *dev)
8956 {
8957         struct pci_dev *d = dev->pdev;
8958         int i;
8959
8960         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
8961                 struct intel_quirk *q = &intel_quirks[i];
8962
8963                 if (d->device == q->device &&
8964                     (d->subsystem_vendor == q->subsystem_vendor ||
8965                      q->subsystem_vendor == PCI_ANY_ID) &&
8966                     (d->subsystem_device == q->subsystem_device ||
8967                      q->subsystem_device == PCI_ANY_ID))
8968                         q->hook(dev);
8969         }
8970         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
8971                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
8972                         intel_dmi_quirks[i].hook(dev);
8973         }
8974 }
8975
8976 /* Disable the VGA plane that we never use */
8977 static void i915_disable_vga(struct drm_device *dev)
8978 {
8979         struct drm_i915_private *dev_priv = dev->dev_private;
8980         u8 sr1;
8981         u32 vga_reg;
8982
8983         if (HAS_PCH_SPLIT(dev))
8984                 vga_reg = CPU_VGACNTRL;
8985         else
8986                 vga_reg = VGACNTRL;
8987
8988         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
8989         outb(1, VGA_SR_INDEX);
8990         sr1 = inb(VGA_SR_DATA);
8991         outb(sr1 | 1<<5, VGA_SR_DATA);
8992         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
8993         udelay(300);
8994
8995         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
8996         POSTING_READ(vga_reg);
8997 }
8998
8999 void i915_redisable_vga(struct drm_device *dev)
9000 {
9001         struct drm_i915_private *dev_priv = dev->dev_private;
9002         u32 vga_reg;
9003
9004         if (HAS_PCH_SPLIT(dev))
9005                 vga_reg = CPU_VGACNTRL;
9006         else
9007                 vga_reg = VGACNTRL;
9008
9009         if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
9010                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
9011                 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
9012                 POSTING_READ(vga_reg);
9013         }
9014 }
9015
9016 void intel_modeset_init(struct drm_device *dev)
9017 {
9018         struct drm_i915_private *dev_priv = dev->dev_private;
9019         int i;
9020
9021         drm_mode_config_init(dev);
9022
9023         dev->mode_config.min_width = 0;
9024         dev->mode_config.min_height = 0;
9025
9026         dev->mode_config.funcs = (void *)&intel_mode_funcs;
9027
9028         intel_init_quirks(dev);
9029
9030         intel_init_display(dev);
9031
9032         if (IS_GEN2(dev)) {
9033                 dev->mode_config.max_width = 2048;
9034                 dev->mode_config.max_height = 2048;
9035         } else if (IS_GEN3(dev)) {
9036                 dev->mode_config.max_width = 4096;
9037                 dev->mode_config.max_height = 4096;
9038         } else {
9039                 dev->mode_config.max_width = 8192;
9040                 dev->mode_config.max_height = 8192;
9041         }
9042         dev->mode_config.fb_base = dev->agp->base;
9043
9044         DRM_DEBUG_KMS("%d display pipe%s available.\n",
9045                       dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
9046
9047         for (i = 0; i < dev_priv->num_pipe; i++) {
9048                 intel_crtc_init(dev, i);
9049         }
9050
9051         /* Just disable it once at startup */
9052         i915_disable_vga(dev);
9053         intel_setup_outputs(dev);
9054
9055         intel_init_clock_gating(dev);
9056
9057         if (IS_IRONLAKE_M(dev)) {
9058                 ironlake_enable_drps(dev);
9059                 intel_init_emon(dev);
9060         }
9061
9062         if (IS_GEN6(dev) || IS_GEN7(dev)) {
9063                 gen6_enable_rps(dev_priv);
9064                 gen6_update_ring_freq(dev_priv);
9065         }
9066
9067         INIT_WORK(&dev_priv->idle_work, intel_idle_update);
9068         setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
9069                     (unsigned long)dev);
9070 }
9071
9072 void intel_modeset_gem_init(struct drm_device *dev)
9073 {
9074         if (IS_IRONLAKE_M(dev))
9075                 ironlake_enable_rc6(dev);
9076
9077         intel_setup_overlay(dev);
9078 }
9079
9080 void intel_modeset_cleanup(struct drm_device *dev)
9081 {
9082         struct drm_i915_private *dev_priv = dev->dev_private;
9083         struct drm_crtc *crtc;
9084         struct intel_crtc *intel_crtc;
9085
9086         drm_kms_helper_poll_fini(dev);
9087         mutex_lock(&dev->struct_mutex);
9088
9089         intel_unregister_dsm_handler();
9090
9091
9092         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9093                 /* Skip inactive CRTCs */
9094                 if (!crtc->fb)
9095                         continue;
9096
9097                 intel_crtc = to_intel_crtc(crtc);
9098                 intel_increase_pllclock(crtc);
9099         }
9100
9101         intel_disable_fbc(dev);
9102
9103         if (IS_IRONLAKE_M(dev))
9104                 ironlake_disable_drps(dev);
9105         if (IS_GEN6(dev) || IS_GEN7(dev))
9106                 gen6_disable_rps(dev);
9107
9108         if (IS_IRONLAKE_M(dev))
9109                 ironlake_disable_rc6(dev);
9110
9111         mutex_unlock(&dev->struct_mutex);
9112
9113         /* Disable the irq before mode object teardown, for the irq might
9114          * enqueue unpin/hotplug work. */
9115         drm_irq_uninstall(dev);
9116         cancel_work_sync(&dev_priv->hotplug_work);
9117         cancel_work_sync(&dev_priv->rps_work);
9118
9119         /* flush any delayed tasks or pending work */
9120         flush_scheduled_work();
9121
9122         /* Shut off idle work before the crtcs get freed. */
9123         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9124                 intel_crtc = to_intel_crtc(crtc);
9125                 del_timer_sync(&intel_crtc->idle_timer);
9126         }
9127         del_timer_sync(&dev_priv->idle_timer);
9128         cancel_work_sync(&dev_priv->idle_work);
9129
9130         /* destroy backlight, if any, before the connectors */
9131         intel_panel_destroy_backlight(dev);
9132
9133         drm_mode_config_cleanup(dev);
9134 }
9135
9136 /*
9137  * Return which encoder is currently attached for connector.
9138  */
9139 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
9140 {
9141         return &intel_attached_encoder(connector)->base;
9142 }
9143
9144 void intel_connector_attach_encoder(struct intel_connector *connector,
9145                                     struct intel_encoder *encoder)
9146 {
9147         connector->encoder = encoder;
9148         drm_mode_connector_attach_encoder(&connector->base,
9149                                           &encoder->base);
9150 }
9151
9152 /*
9153  * set vga decode state - true == enable VGA decode
9154  */
9155 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
9156 {
9157         struct drm_i915_private *dev_priv = dev->dev_private;
9158         unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
9159         u16 gmch_ctrl;
9160
9161         pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl);
9162         if (state)
9163                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
9164         else
9165                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
9166         pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl);
9167         return 0;
9168 }
9169
9170 #ifdef CONFIG_DEBUG_FS
9171 #include <linux/seq_file.h>
9172
9173 struct intel_display_error_state {
9174         struct intel_cursor_error_state {
9175                 u32 control;
9176                 u32 position;
9177                 u32 base;
9178                 u32 size;
9179         } cursor[2];
9180
9181         struct intel_pipe_error_state {
9182                 u32 conf;
9183                 u32 source;
9184
9185                 u32 htotal;
9186                 u32 hblank;
9187                 u32 hsync;
9188                 u32 vtotal;
9189                 u32 vblank;
9190                 u32 vsync;
9191         } pipe[2];
9192
9193         struct intel_plane_error_state {
9194                 u32 control;
9195                 u32 stride;
9196                 u32 size;
9197                 u32 pos;
9198                 u32 addr;
9199                 u32 surface;
9200                 u32 tile_offset;
9201         } plane[2];
9202 };
9203
9204 struct intel_display_error_state *
9205 intel_display_capture_error_state(struct drm_device *dev)
9206 {
9207         drm_i915_private_t *dev_priv = dev->dev_private;
9208         struct intel_display_error_state *error;
9209         int i;
9210
9211         error = kmalloc(sizeof(*error), GFP_ATOMIC);
9212         if (error == NULL)
9213                 return NULL;
9214
9215         for (i = 0; i < 2; i++) {
9216                 error->cursor[i].control = I915_READ(CURCNTR(i));
9217                 error->cursor[i].position = I915_READ(CURPOS(i));
9218                 error->cursor[i].base = I915_READ(CURBASE(i));
9219
9220                 error->plane[i].control = I915_READ(DSPCNTR(i));
9221                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
9222                 error->plane[i].size = I915_READ(DSPSIZE(i));
9223                 error->plane[i].pos = I915_READ(DSPPOS(i));
9224                 error->plane[i].addr = I915_READ(DSPADDR(i));
9225                 if (INTEL_INFO(dev)->gen >= 4) {
9226                         error->plane[i].surface = I915_READ(DSPSURF(i));
9227                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
9228                 }
9229
9230                 error->pipe[i].conf = I915_READ(PIPECONF(i));
9231                 error->pipe[i].source = I915_READ(PIPESRC(i));
9232                 error->pipe[i].htotal = I915_READ(HTOTAL(i));
9233                 error->pipe[i].hblank = I915_READ(HBLANK(i));
9234                 error->pipe[i].hsync = I915_READ(HSYNC(i));
9235                 error->pipe[i].vtotal = I915_READ(VTOTAL(i));
9236                 error->pipe[i].vblank = I915_READ(VBLANK(i));
9237                 error->pipe[i].vsync = I915_READ(VSYNC(i));
9238         }
9239
9240         return error;
9241 }
9242
9243 void
9244 intel_display_print_error_state(struct seq_file *m,
9245                                 struct drm_device *dev,
9246                                 struct intel_display_error_state *error)
9247 {
9248         int i;
9249
9250         for (i = 0; i < 2; i++) {
9251                 seq_printf(m, "Pipe [%d]:\n", i);
9252                 seq_printf(m, "  CONF: %08x\n", error->pipe[i].conf);
9253                 seq_printf(m, "  SRC: %08x\n", error->pipe[i].source);
9254                 seq_printf(m, "  HTOTAL: %08x\n", error->pipe[i].htotal);
9255                 seq_printf(m, "  HBLANK: %08x\n", error->pipe[i].hblank);
9256                 seq_printf(m, "  HSYNC: %08x\n", error->pipe[i].hsync);
9257                 seq_printf(m, "  VTOTAL: %08x\n", error->pipe[i].vtotal);
9258                 seq_printf(m, "  VBLANK: %08x\n", error->pipe[i].vblank);
9259                 seq_printf(m, "  VSYNC: %08x\n", error->pipe[i].vsync);
9260
9261                 seq_printf(m, "Plane [%d]:\n", i);
9262                 seq_printf(m, "  CNTR: %08x\n", error->plane[i].control);
9263                 seq_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
9264                 seq_printf(m, "  SIZE: %08x\n", error->plane[i].size);
9265                 seq_printf(m, "  POS: %08x\n", error->plane[i].pos);
9266                 seq_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
9267                 if (INTEL_INFO(dev)->gen >= 4) {
9268                         seq_printf(m, "  SURF: %08x\n", error->plane[i].surface);
9269                         seq_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
9270                 }
9271
9272                 seq_printf(m, "Cursor [%d]:\n", i);
9273                 seq_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
9274                 seq_printf(m, "  POS: %08x\n", error->cursor[i].position);
9275                 seq_printf(m, "  BASE: %08x\n", error->cursor[i].base);
9276         }
9277 }
9278 #endif