drivers/dma/imx-sdma.c

   1 /*
   2  * drivers/dma/imx-sdma.c
   3  *
   4  * This file contains a driver for the Freescale Smart DMA engine
   5  *
   6  * Copyright 2010 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
   7  *
   8  * Based on code from Freescale:
   9  *
  10  * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved.
  11  *
  12  * The code contained herein is licensed under the GNU General Public
  13  * License. You may obtain a copy of the GNU General Public License
  14  * Version 2 or later at the following locations:
  15  *
  16  * http://www.opensource.org/licenses/gpl-license.html
  17  * http://www.gnu.org/copyleft/gpl.html
  18  */
  19
  20 #include <linux/init.h>
  21 #include <linux/types.h>
  22 #include <linux/mm.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/clk.h>
  25 #include <linux/wait.h>
  26 #include <linux/sched.h>
  27 #include <linux/semaphore.h>
  28 #include <linux/spinlock.h>
  29 #include <linux/device.h>
  30 #include <linux/dma-mapping.h>
  31 #include <linux/firmware.h>
  32 #include <linux/slab.h>
  33 #include <linux/platform_device.h>
  34 #include <linux/dmaengine.h>
  35 #include <linux/of.h>
  36 #include <linux/of_device.h>
  37
  38 #include <asm/irq.h>
  39 #include <mach/sdma.h>
  40 #include <mach/dma.h>
  41 #include <mach/hardware.h>
  42
  43 /* SDMA registers */
  44 #define SDMA_H_C0PTR            0x000
  45 #define SDMA_H_INTR             0x004
  46 #define SDMA_H_STATSTOP         0x008
  47 #define SDMA_H_START            0x00c
  48 #define SDMA_H_EVTOVR           0x010
  49 #define SDMA_H_DSPOVR           0x014
  50 #define SDMA_H_HOSTOVR          0x018
  51 #define SDMA_H_EVTPEND          0x01c
  52 #define SDMA_H_DSPENBL          0x020
  53 #define SDMA_H_RESET            0x024
  54 #define SDMA_H_EVTERR           0x028
  55 #define SDMA_H_INTRMSK          0x02c
  56 #define SDMA_H_PSW              0x030
  57 #define SDMA_H_EVTERRDBG        0x034
  58 #define SDMA_H_CONFIG           0x038
  59 #define SDMA_ONCE_ENB           0x040
  60 #define SDMA_ONCE_DATA          0x044
  61 #define SDMA_ONCE_INSTR         0x048
  62 #define SDMA_ONCE_STAT          0x04c
  63 #define SDMA_ONCE_CMD           0x050
  64 #define SDMA_EVT_MIRROR         0x054
  65 #define SDMA_ILLINSTADDR        0x058
  66 #define SDMA_CHN0ADDR           0x05c
  67 #define SDMA_ONCE_RTB           0x060
  68 #define SDMA_XTRIG_CONF1        0x070
  69 #define SDMA_XTRIG_CONF2        0x074
  70 #define SDMA_CHNENBL0_IMX35     0x200
  71 #define SDMA_CHNENBL0_IMX31     0x080
  72 #define SDMA_CHNPRI_0           0x100
  73
  74 /*
  75  * Buffer descriptor status values.
  76  */
  77 #define BD_DONE  0x01
  78 #define BD_WRAP  0x02
  79 #define BD_CONT  0x04
  80 #define BD_INTR  0x08
  81 #define BD_RROR  0x10
  82 #define BD_LAST  0x20
  83 #define BD_EXTD  0x80
  84
  85 /*
  86  * Data Node descriptor status values.
  87  */
  88 #define DND_END_OF_FRAME  0x80
  89 #define DND_END_OF_XFER   0x40
  90 #define DND_DONE          0x20
  91 #define DND_UNUSED        0x01
  92
  93 /*
  94  * IPCV2 descriptor status values.
  95  */
  96 #define BD_IPCV2_END_OF_FRAME  0x40
  97
  98 #define IPCV2_MAX_NODES        50
  99 /*
 100  * Error bit set in the CCB status field by the SDMA,
 101  * in setbd routine, in case of a transfer error
 102  */
 103 #define DATA_ERROR  0x10000000
 104
 105 /*
 106  * Buffer descriptor commands.
 107  */
 108 #define C0_ADDR             0x01
 109 #define C0_LOAD             0x02
 110 #define C0_DUMP             0x03
 111 #define C0_SETCTX           0x07
 112 #define C0_GETCTX           0x03
 113 #define C0_SETDM            0x01
 114 #define C0_SETPM            0x04
 115 #define C0_GETDM            0x02
 116 #define C0_GETPM            0x08
 117 /*
 118  * Change endianness indicator in the BD command field
 119  */
 120 #define CHANGE_ENDIANNESS   0x80
 121
 122 /*
 123  * Mode/Count of data node descriptors - IPCv2
 124  */
 125 struct sdma_mode_count {
 126         u32 count   : 16; /* size of the buffer pointed by this BD */
 127         u32 status  :  8; /* E,R,I,C,W,D status bits stored here */
 128         u32 command :  8; /* command mostlky used for channel 0 */
 129 };
 130
 131 /*
 132  * Buffer descriptor
 133  */
 134 struct sdma_buffer_descriptor {
 135         struct sdma_mode_count  mode;
 136         u32 buffer_addr;        /* address of the buffer described */
 137         u32 ext_buffer_addr;    /* extended buffer address */
 138 } __attribute__ ((packed));
 139
 140 /**
 141  * struct sdma_channel_control - Channel control Block
 142  *
 143  * @current_bd_ptr      current buffer descriptor processed
 144  * @base_bd_ptr         first element of buffer descriptor array
 145  * @unused              padding. The SDMA engine expects an array of 128 byte
 146  *                      control blocks
 147  */
 148 struct sdma_channel_control {
 149         u32 current_bd_ptr;
 150         u32 base_bd_ptr;
 151         u32 unused[2];
 152 } __attribute__ ((packed));
 153
 154 /**
 155  * struct sdma_state_registers - SDMA context for a channel
 156  *
 157  * @pc:         program counter
 158  * @t:          test bit: status of arithmetic & test instruction
 159  * @rpc:        return program counter
 160  * @sf:         source fault while loading data
 161  * @spc:        loop start program counter
 162  * @df:         destination fault while storing data
 163  * @epc:        loop end program counter
 164  * @lm:         loop mode
 165  */
 166 struct sdma_state_registers {
 167         u32 pc     :14;
 168         u32 unused1: 1;
 169         u32 t      : 1;
 170         u32 rpc    :14;
 171         u32 unused0: 1;
 172         u32 sf     : 1;
 173         u32 spc    :14;
 174         u32 unused2: 1;
 175         u32 df     : 1;
 176         u32 epc    :14;
 177         u32 lm     : 2;
 178 } __attribute__ ((packed));
 179
 180 /**
 181  * struct sdma_context_data - sdma context specific to a channel
 182  *
 183  * @channel_state:      channel state bits
 184  * @gReg:               general registers
 185  * @mda:                burst dma destination address register
 186  * @msa:                burst dma source address register
 187  * @ms:                 burst dma status register
 188  * @md:                 burst dma data register
 189  * @pda:                peripheral dma destination address register
 190  * @psa:                peripheral dma source address register
 191  * @ps:                 peripheral dma status register
 192  * @pd:                 peripheral dma data register
 193  * @ca:                 CRC polynomial register
 194  * @cs:                 CRC accumulator register
 195  * @dda:                dedicated core destination address register
 196  * @dsa:                dedicated core source address register
 197  * @ds:                 dedicated core status register
 198  * @dd:                 dedicated core data register
 199  */
 200 struct sdma_context_data {
 201         struct sdma_state_registers  channel_state;
 202         u32  gReg[8];
 203         u32  mda;
 204         u32  msa;
 205         u32  ms;
 206         u32  md;
 207         u32  pda;
 208         u32  psa;
 209         u32  ps;
 210         u32  pd;
 211         u32  ca;
 212         u32  cs;
 213         u32  dda;
 214         u32  dsa;
 215         u32  ds;
 216         u32  dd;
 217         u32  scratch0;
 218         u32  scratch1;
 219         u32  scratch2;
 220         u32  scratch3;
 221         u32  scratch4;
 222         u32  scratch5;
 223         u32  scratch6;
 224         u32  scratch7;
 225 } __attribute__ ((packed));
 226
 227 #define NUM_BD (int)(PAGE_SIZE / sizeof(struct sdma_buffer_descriptor))
 228
 229 struct sdma_engine;
 230
 231 /**
 232  * struct sdma_channel - housekeeping for a SDMA channel
 233  *
 234  * @sdma                pointer to the SDMA engine for this channel
 235  * @channel             the channel number, matches dmaengine chan_id + 1
 236  * @direction           transfer type. Needed for setting SDMA script
 237  * @peripheral_type     Peripheral type. Needed for setting SDMA script
 238  * @event_id0           aka dma request line
 239  * @event_id1           for channels that use 2 events
 240  * @word_size           peripheral access size
 241  * @buf_tail            ID of the buffer that was processed
 242  * @done                channel completion
 243  * @num_bd              max NUM_BD. number of descriptors currently handling
 244  */
 245 struct sdma_channel {
 246         struct sdma_engine              *sdma;
 247         unsigned int                    channel;
 248         enum dma_data_direction         direction;
 249         enum sdma_peripheral_type       peripheral_type;
 250         unsigned int                    event_id0;
 251         unsigned int                    event_id1;
 252         enum dma_slave_buswidth         word_size;
 253         unsigned int                    buf_tail;
 254         struct completion               done;
 255         unsigned int                    num_bd;
 256         struct sdma_buffer_descriptor   *bd;
 257         dma_addr_t                      bd_phys;
 258         unsigned int                    pc_from_device, pc_to_device;
 259         unsigned long                   flags;
 260         dma_addr_t                      per_address;
 261         u32                             event_mask0, event_mask1;
 262         u32                             watermark_level;
 263         u32                             shp_addr, per_addr;
 264         struct dma_chan                 chan;
 265         spinlock_t                      lock;
 266         struct dma_async_tx_descriptor  desc;
 267         dma_cookie_t                    last_completed;
 268         enum dma_status                 status;
 269 };
 270
 271 #define IMX_DMA_SG_LOOP         (1 << 0)
 272
 273 #define MAX_DMA_CHANNELS 32
 274 #define MXC_SDMA_DEFAULT_PRIORITY 1
 275 #define MXC_SDMA_MIN_PRIORITY 1
 276 #define MXC_SDMA_MAX_PRIORITY 7
 277
 278 #define SDMA_FIRMWARE_MAGIC 0x414d4453
 279
 280 /**
 281  * struct sdma_firmware_header - Layout of the firmware image
 282  *
 283  * @magic               "SDMA"
 284  * @version_major       increased whenever layout of struct sdma_script_start_addrs
 285  *                      changes.
 286  * @version_minor       firmware minor version (for binary compatible changes)
 287  * @script_addrs_start  offset of struct sdma_script_start_addrs in this image
 288  * @num_script_addrs    Number of script addresses in this image
 289  * @ram_code_start      offset of SDMA ram image in this firmware image
 290  * @ram_code_size       size of SDMA ram image
 291  * @script_addrs        Stores the start address of the SDMA scripts
 292  *                      (in SDMA memory space)
 293  */
 294 struct sdma_firmware_header {
 295         u32     magic;
 296         u32     version_major;
 297         u32     version_minor;
 298         u32     script_addrs_start;
 299         u32     num_script_addrs;
 300         u32     ram_code_start;
 301         u32     ram_code_size;
 302 };
 303
 304 enum sdma_devtype {
 305         IMX31_SDMA,     /* runs on i.mx31 */
 306         IMX35_SDMA,     /* runs on i.mx35 and later */
 307 };
 308
 309 struct sdma_engine {
 310         struct device                   *dev;
 311         struct device_dma_parameters    dma_parms;
 312         struct sdma_channel             channel[MAX_DMA_CHANNELS];
 313         struct sdma_channel_control     *channel_control;
 314         void __iomem                    *regs;
 315         enum sdma_devtype               devtype;
 316         unsigned int                    num_events;
 317         struct sdma_context_data        *context;
 318         dma_addr_t                      context_phys;
 319         struct dma_device               dma_device;
 320         struct clk                      *clk;
 321         struct mutex                    channel_0_lock;
 322         struct sdma_script_start_addrs  *script_addrs;
 323 };
 324
 325 static struct platform_device_id sdma_devtypes[] = {
 326         {
 327                 .name = "imx31-sdma",
 328                 .driver_data = IMX31_SDMA,
 329         }, {
 330                 .name = "imx35-sdma",
 331                 .driver_data = IMX35_SDMA,
 332         }, {
 333                 /* sentinel */
 334         }
 335 };
 336 MODULE_DEVICE_TABLE(platform, sdma_devtypes);
 337
 338 static const struct of_device_id sdma_dt_ids[] = {
 339         { .compatible = "fsl,imx31-sdma", .data = &sdma_devtypes[IMX31_SDMA], },
 340         { .compatible = "fsl,imx35-sdma", .data = &sdma_devtypes[IMX35_SDMA], },
 341         { /* sentinel */ }
 342 };
 343 MODULE_DEVICE_TABLE(of, sdma_dt_ids);
 344
 345 #define SDMA_H_CONFIG_DSPDMA    (1 << 12) /* indicates if the DSPDMA is used */
 346 #define SDMA_H_CONFIG_RTD_PINS  (1 << 11) /* indicates if Real-Time Debug pins are enabled */
 347 #define SDMA_H_CONFIG_ACR       (1 << 4)  /* indicates if AHB freq /core freq = 2 or 1 */
 348 #define SDMA_H_CONFIG_CSM       (3)       /* indicates which context switch mode is selected*/
 349
 350 static inline u32 chnenbl_ofs(struct sdma_engine *sdma, unsigned int event)
 351 {
 352         u32 chnenbl0 = (sdma->devtype == IMX31_SDMA ? SDMA_CHNENBL0_IMX31 :
 353                                                       SDMA_CHNENBL0_IMX35);
 354         return chnenbl0 + event * 4;
 355 }
 356
 357 static int sdma_config_ownership(struct sdma_channel *sdmac,
 358                 bool event_override, bool mcu_override, bool dsp_override)
 359 {
 360         struct sdma_engine *sdma = sdmac->sdma;
 361         int channel = sdmac->channel;
 362         u32 evt, mcu, dsp;
 363
 364         if (event_override && mcu_override && dsp_override)
 365                 return -EINVAL;
 366
 367         evt = __raw_readl(sdma->regs + SDMA_H_EVTOVR);
 368         mcu = __raw_readl(sdma->regs + SDMA_H_HOSTOVR);
 369         dsp = __raw_readl(sdma->regs + SDMA_H_DSPOVR);
 370
 371         if (dsp_override)
 372                 dsp &= ~(1 << channel);
 373         else
 374                 dsp |= (1 << channel);
 375
 376         if (event_override)
 377                 evt &= ~(1 << channel);
 378         else
 379                 evt |= (1 << channel);
 380
 381         if (mcu_override)
 382                 mcu &= ~(1 << channel);
 383         else
 384                 mcu |= (1 << channel);
 385
 386         __raw_writel(evt, sdma->regs + SDMA_H_EVTOVR);
 387         __raw_writel(mcu, sdma->regs + SDMA_H_HOSTOVR);
 388         __raw_writel(dsp, sdma->regs + SDMA_H_DSPOVR);
 389
 390         return 0;
 391 }
 392
 393 /*
 394  * sdma_run_channel - run a channel and wait till it's done
 395  */
 396 static int sdma_run_channel(struct sdma_channel *sdmac)
 397 {
 398         struct sdma_engine *sdma = sdmac->sdma;
 399         int channel = sdmac->channel;
 400         int ret;
 401
 402         init_completion(&sdmac->done);
 403
 404         __raw_writel(1 << channel, sdma->regs + SDMA_H_START);
 405
 406         ret = wait_for_completion_timeout(&sdmac->done, HZ);
 407
 408         return ret ? 0 : -ETIMEDOUT;
 409 }
 410
 411 static int sdma_load_script(struct sdma_engine *sdma, void *buf, int size,
 412                 u32 address)
 413 {
 414         struct sdma_buffer_descriptor *bd0 = sdma->channel[0].bd;
 415         void *buf_virt;
 416         dma_addr_t buf_phys;
 417         int ret;
 418
 419         mutex_lock(&sdma->channel_0_lock);
 420
 421         buf_virt = dma_alloc_coherent(NULL,
 422                         size,
 423                         &buf_phys, GFP_KERNEL);
 424         if (!buf_virt) {
 425                 ret = -ENOMEM;
 426                 goto err_out;
 427         }
 428
 429         bd0->mode.command = C0_SETPM;
 430         bd0->mode.status = BD_DONE | BD_INTR | BD_WRAP | BD_EXTD;
 431         bd0->mode.count = size / 2;
 432         bd0->buffer_addr = buf_phys;
 433         bd0->ext_buffer_addr = address;
 434
 435         memcpy(buf_virt, buf, size);
 436
 437         ret = sdma_run_channel(&sdma->channel[0]);
 438
 439         dma_free_coherent(NULL, size, buf_virt, buf_phys);
 440
 441 err_out:
 442         mutex_unlock(&sdma->channel_0_lock);
 443
 444         return ret;
 445 }
 446
 447 static void sdma_event_enable(struct sdma_channel *sdmac, unsigned int event)
 448 {
 449         struct sdma_engine *sdma = sdmac->sdma;
 450         int channel = sdmac->channel;
 451         u32 val;
 452         u32 chnenbl = chnenbl_ofs(sdma, event);
 453
 454         val = __raw_readl(sdma->regs + chnenbl);
 455         val |= (1 << channel);
 456         __raw_writel(val, sdma->regs + chnenbl);
 457 }
 458
 459 static void sdma_event_disable(struct sdma_channel *sdmac, unsigned int event)
 460 {
 461         struct sdma_engine *sdma = sdmac->sdma;
 462         int channel = sdmac->channel;
 463         u32 chnenbl = chnenbl_ofs(sdma, event);
 464         u32 val;
 465
 466         val = __raw_readl(sdma->regs + chnenbl);
 467         val &= ~(1 << channel);
 468         __raw_writel(val, sdma->regs + chnenbl);
 469 }
 470
 471 static void sdma_handle_channel_loop(struct sdma_channel *sdmac)
 472 {
 473         struct sdma_buffer_descriptor *bd;
 474
 475         /*
 476          * loop mode. Iterate over descriptors, re-setup them and
 477          * call callback function.
 478          */
 479         while (1) {
 480                 bd = &sdmac->bd[sdmac->buf_tail];
 481
 482                 if (bd->mode.status & BD_DONE)
 483                         break;
 484
 485                 if (bd->mode.status & BD_RROR)
 486                         sdmac->status = DMA_ERROR;
 487                 else
 488                         sdmac->status = DMA_IN_PROGRESS;
 489
 490                 bd->mode.status |= BD_DONE;
 491                 sdmac->buf_tail++;
 492                 sdmac->buf_tail %= sdmac->num_bd;
 493
 494                 if (sdmac->desc.callback)
 495                         sdmac->desc.callback(sdmac->desc.callback_param);
 496         }
 497 }
 498
 499 static void mxc_sdma_handle_channel_normal(struct sdma_channel *sdmac)
 500 {
 501         struct sdma_buffer_descriptor *bd;
 502         int i, error = 0;
 503
 504         /*
 505          * non loop mode. Iterate over all descriptors, collect
 506          * errors and call callback function
 507          */
 508         for (i = 0; i < sdmac->num_bd; i++) {
 509                 bd = &sdmac->bd[i];
 510
 511                  if (bd->mode.status & (BD_DONE | BD_RROR))
 512                         error = -EIO;
 513         }
 514
 515         if (error)
 516                 sdmac->status = DMA_ERROR;
 517         else
 518                 sdmac->status = DMA_SUCCESS;
 519
 520         if (sdmac->desc.callback)
 521                 sdmac->desc.callback(sdmac->desc.callback_param);
 522         sdmac->last_completed = sdmac->desc.cookie;
 523 }
 524
 525 static void mxc_sdma_handle_channel(struct sdma_channel *sdmac)
 526 {
 527         complete(&sdmac->done);
 528
 529         /* not interested in channel 0 interrupts */
 530         if (sdmac->channel == 0)
 531                 return;
 532
 533         if (sdmac->flags & IMX_DMA_SG_LOOP)
 534                 sdma_handle_channel_loop(sdmac);
 535         else
 536                 mxc_sdma_handle_channel_normal(sdmac);
 537 }
 538
 539 static irqreturn_t sdma_int_handler(int irq, void *dev_id)
 540 {
 541         struct sdma_engine *sdma = dev_id;
 542         u32 stat;
 543
 544         stat = __raw_readl(sdma->regs + SDMA_H_INTR);
 545         __raw_writel(stat, sdma->regs + SDMA_H_INTR);
 546
 547         while (stat) {
 548                 int channel = fls(stat) - 1;
 549                 struct sdma_channel *sdmac = &sdma->channel[channel];
 550
 551                 mxc_sdma_handle_channel(sdmac);
 552
 553                 stat &= ~(1 << channel);
 554         }
 555
 556         return IRQ_HANDLED;
 557 }
 558
 559 /*
 560  * sets the pc of SDMA script according to the peripheral type
 561  */
 562 static void sdma_get_pc(struct sdma_channel *sdmac,
 563                 enum sdma_peripheral_type peripheral_type)
 564 {
 565         struct sdma_engine *sdma = sdmac->sdma;
 566         int per_2_emi = 0, emi_2_per = 0;
 567         /*
 568          * These are needed once we start to support transfers between
 569          * two peripherals or memory-to-memory transfers
 570          */
 571         int per_2_per = 0, emi_2_emi = 0;
 572
 573         sdmac->pc_from_device = 0;
 574         sdmac->pc_to_device = 0;
 575
 576         switch (peripheral_type) {
 577         case IMX_DMATYPE_MEMORY:
 578                 emi_2_emi = sdma->script_addrs->ap_2_ap_addr;
 579                 break;
 580         case IMX_DMATYPE_DSP:
 581                 emi_2_per = sdma->script_addrs->bp_2_ap_addr;
 582                 per_2_emi = sdma->script_addrs->ap_2_bp_addr;
 583                 break;
 584         case IMX_DMATYPE_FIRI:
 585                 per_2_emi = sdma->script_addrs->firi_2_mcu_addr;
 586                 emi_2_per = sdma->script_addrs->mcu_2_firi_addr;
 587                 break;
 588         case IMX_DMATYPE_UART:
 589                 per_2_emi = sdma->script_addrs->uart_2_mcu_addr;
 590                 emi_2_per = sdma->script_addrs->mcu_2_app_addr;
 591                 break;
 592         case IMX_DMATYPE_UART_SP:
 593                 per_2_emi = sdma->script_addrs->uartsh_2_mcu_addr;
 594                 emi_2_per = sdma->script_addrs->mcu_2_shp_addr;
 595                 break;
 596         case IMX_DMATYPE_ATA:
 597                 per_2_emi = sdma->script_addrs->ata_2_mcu_addr;
 598                 emi_2_per = sdma->script_addrs->mcu_2_ata_addr;
 599                 break;
 600         case IMX_DMATYPE_CSPI:
 601         case IMX_DMATYPE_EXT:
 602         case IMX_DMATYPE_SSI:
 603                 per_2_emi = sdma->script_addrs->app_2_mcu_addr;
 604                 emi_2_per = sdma->script_addrs->mcu_2_app_addr;
 605                 break;
 606         case IMX_DMATYPE_SSI_SP:
 607         case IMX_DMATYPE_MMC:
 608         case IMX_DMATYPE_SDHC:
 609         case IMX_DMATYPE_CSPI_SP:
 610         case IMX_DMATYPE_ESAI:
 611         case IMX_DMATYPE_MSHC_SP:
 612                 per_2_emi = sdma->script_addrs->shp_2_mcu_addr;
 613                 emi_2_per = sdma->script_addrs->mcu_2_shp_addr;
 614                 break;
 615         case IMX_DMATYPE_ASRC:
 616                 per_2_emi = sdma->script_addrs->asrc_2_mcu_addr;
 617                 emi_2_per = sdma->script_addrs->asrc_2_mcu_addr;
 618                 per_2_per = sdma->script_addrs->per_2_per_addr;
 619                 break;
 620         case IMX_DMATYPE_MSHC:
 621                 per_2_emi = sdma->script_addrs->mshc_2_mcu_addr;
 622                 emi_2_per = sdma->script_addrs->mcu_2_mshc_addr;
 623                 break;
 624         case IMX_DMATYPE_CCM:
 625                 per_2_emi = sdma->script_addrs->dptc_dvfs_addr;
 626                 break;
 627         case IMX_DMATYPE_SPDIF:
 628                 per_2_emi = sdma->script_addrs->spdif_2_mcu_addr;
 629                 emi_2_per = sdma->script_addrs->mcu_2_spdif_addr;
 630                 break;
 631         case IMX_DMATYPE_IPU_MEMORY:
 632                 emi_2_per = sdma->script_addrs->ext_mem_2_ipu_addr;
 633                 break;
 634         default:
 635                 break;
 636         }
 637
 638         sdmac->pc_from_device = per_2_emi;
 639         sdmac->pc_to_device = emi_2_per;
 640 }
 641
 642 static int sdma_load_context(struct sdma_channel *sdmac)
 643 {
 644         struct sdma_engine *sdma = sdmac->sdma;
 645         int channel = sdmac->channel;
 646         int load_address;
 647         struct sdma_context_data *context = sdma->context;
 648         struct sdma_buffer_descriptor *bd0 = sdma->channel[0].bd;
 649         int ret;
 650
 651         if (sdmac->direction == DMA_FROM_DEVICE) {
 652                 load_address = sdmac->pc_from_device;
 653         } else {
 654                 load_address = sdmac->pc_to_device;
 655         }
 656
 657         if (load_address < 0)
 658                 return load_address;
 659
 660         dev_dbg(sdma->dev, "load_address = %d\n", load_address);
 661         dev_dbg(sdma->dev, "wml = 0x%08x\n", sdmac->watermark_level);
 662         dev_dbg(sdma->dev, "shp_addr = 0x%08x\n", sdmac->shp_addr);
 663         dev_dbg(sdma->dev, "per_addr = 0x%08x\n", sdmac->per_addr);
 664         dev_dbg(sdma->dev, "event_mask0 = 0x%08x\n", sdmac->event_mask0);
 665         dev_dbg(sdma->dev, "event_mask1 = 0x%08x\n", sdmac->event_mask1);
 666
 667         mutex_lock(&sdma->channel_0_lock);
 668
 669         memset(context, 0, sizeof(*context));
 670         context->channel_state.pc = load_address;
 671
 672         /* Send by context the event mask,base address for peripheral
 673          * and watermark level
 674          */
 675         context->gReg[0] = sdmac->event_mask1;
 676         context->gReg[1] = sdmac->event_mask0;
 677         context->gReg[2] = sdmac->per_addr;
 678         context->gReg[6] = sdmac->shp_addr;
 679         context->gReg[7] = sdmac->watermark_level;
 680
 681         bd0->mode.command = C0_SETDM;
 682         bd0->mode.status = BD_DONE | BD_INTR | BD_WRAP | BD_EXTD;
 683         bd0->mode.count = sizeof(*context) / 4;
 684         bd0->buffer_addr = sdma->context_phys;
 685         bd0->ext_buffer_addr = 2048 + (sizeof(*context) / 4) * channel;
 686
 687         ret = sdma_run_channel(&sdma->channel[0]);
 688
 689         mutex_unlock(&sdma->channel_0_lock);
 690
 691         return ret;
 692 }
 693
 694 static void sdma_disable_channel(struct sdma_channel *sdmac)
 695 {
 696         struct sdma_engine *sdma = sdmac->sdma;
 697         int channel = sdmac->channel;
 698
 699         __raw_writel(1 << channel, sdma->regs + SDMA_H_STATSTOP);
 700         sdmac->status = DMA_ERROR;
 701 }
 702
 703 static int sdma_config_channel(struct sdma_channel *sdmac)
 704 {
 705         int ret;
 706
 707         sdma_disable_channel(sdmac);
 708
 709         sdmac->event_mask0 = 0;
 710         sdmac->event_mask1 = 0;
 711         sdmac->shp_addr = 0;
 712         sdmac->per_addr = 0;
 713
 714         if (sdmac->event_id0) {
 715                 if (sdmac->event_id0 > 32)
 716                         return -EINVAL;
 717                 sdma_event_enable(sdmac, sdmac->event_id0);
 718         }
 719
 720         switch (sdmac->peripheral_type) {
 721         case IMX_DMATYPE_DSP:
 722                 sdma_config_ownership(sdmac, false, true, true);
 723                 break;
 724         case IMX_DMATYPE_MEMORY:
 725                 sdma_config_ownership(sdmac, false, true, false);
 726                 break;
 727         default:
 728                 sdma_config_ownership(sdmac, true, true, false);
 729                 break;
 730         }
 731
 732         sdma_get_pc(sdmac, sdmac->peripheral_type);
 733
 734         if ((sdmac->peripheral_type != IMX_DMATYPE_MEMORY) &&
 735                         (sdmac->peripheral_type != IMX_DMATYPE_DSP)) {
 736                 /* Handle multiple event channels differently */
 737                 if (sdmac->event_id1) {
 738                         sdmac->event_mask1 = 1 << (sdmac->event_id1 % 32);
 739                         if (sdmac->event_id1 > 31)
 740                                 sdmac->watermark_level |= 1 << 31;
 741                         sdmac->event_mask0 = 1 << (sdmac->event_id0 % 32);
 742                         if (sdmac->event_id0 > 31)
 743                                 sdmac->watermark_level |= 1 << 30;
 744                 } else {
 745                         sdmac->event_mask0 = 1 << sdmac->event_id0;
 746                         sdmac->event_mask1 = 1 << (sdmac->event_id0 - 32);
 747                 }
 748                 /* Watermark Level */
 749                 sdmac->watermark_level |= sdmac->watermark_level;
 750                 /* Address */
 751                 sdmac->shp_addr = sdmac->per_address;
 752         } else {
 753                 sdmac->watermark_level = 0; /* FIXME: M3_BASE_ADDRESS */
 754         }
 755
 756         ret = sdma_load_context(sdmac);
 757
 758         return ret;
 759 }
 760
 761 static int sdma_set_channel_priority(struct sdma_channel *sdmac,
 762                 unsigned int priority)
 763 {
 764         struct sdma_engine *sdma = sdmac->sdma;
 765         int channel = sdmac->channel;
 766
 767         if (priority < MXC_SDMA_MIN_PRIORITY
 768             || priority > MXC_SDMA_MAX_PRIORITY) {
 769                 return -EINVAL;
 770         }
 771
 772         __raw_writel(priority, sdma->regs + SDMA_CHNPRI_0 + 4 * channel);
 773
 774         return 0;
 775 }
 776
 777 static int sdma_request_channel(struct sdma_channel *sdmac)
 778 {
 779         struct sdma_engine *sdma = sdmac->sdma;
 780         int channel = sdmac->channel;
 781         int ret = -EBUSY;
 782
 783         sdmac->bd = dma_alloc_coherent(NULL, PAGE_SIZE, &sdmac->bd_phys, GFP_KERNEL);
 784         if (!sdmac->bd) {
 785                 ret = -ENOMEM;
 786                 goto out;
 787         }
 788
 789         memset(sdmac->bd, 0, PAGE_SIZE);
 790
 791         sdma->channel_control[channel].base_bd_ptr = sdmac->bd_phys;
 792         sdma->channel_control[channel].current_bd_ptr = sdmac->bd_phys;
 793
 794         clk_enable(sdma->clk);
 795
 796         sdma_set_channel_priority(sdmac, MXC_SDMA_DEFAULT_PRIORITY);
 797
 798         init_completion(&sdmac->done);
 799
 800         sdmac->buf_tail = 0;
 801
 802         return 0;
 803 out:
 804
 805         return ret;
 806 }
 807
 808 static void sdma_enable_channel(struct sdma_engine *sdma, int channel)
 809 {
 810         __raw_writel(1 << channel, sdma->regs + SDMA_H_START);
 811 }
 812
 813 static dma_cookie_t sdma_assign_cookie(struct sdma_channel *sdmac)
 814 {
 815         dma_cookie_t cookie = sdmac->chan.cookie;
 816
 817         if (++cookie < 0)
 818                 cookie = 1;
 819
 820         sdmac->chan.cookie = cookie;
 821         sdmac->desc.cookie = cookie;
 822
 823         return cookie;
 824 }
 825
 826 static struct sdma_channel *to_sdma_chan(struct dma_chan *chan)
 827 {
 828         return container_of(chan, struct sdma_channel, chan);
 829 }
 830
 831 static dma_cookie_t sdma_tx_submit(struct dma_async_tx_descriptor *tx)
 832 {
 833         struct sdma_channel *sdmac = to_sdma_chan(tx->chan);
 834         struct sdma_engine *sdma = sdmac->sdma;
 835         dma_cookie_t cookie;
 836
 837         spin_lock_irq(&sdmac->lock);
 838
 839         cookie = sdma_assign_cookie(sdmac);
 840
 841         sdma_enable_channel(sdma, sdmac->channel);
 842
 843         spin_unlock_irq(&sdmac->lock);
 844
 845         return cookie;
 846 }
 847
 848 static int sdma_alloc_chan_resources(struct dma_chan *chan)
 849 {
 850         struct sdma_channel *sdmac = to_sdma_chan(chan);
 851         struct imx_dma_data *data = chan->private;
 852         int prio, ret;
 853
 854         if (!data)
 855                 return -EINVAL;
 856
 857         switch (data->priority) {
 858         case DMA_PRIO_HIGH:
 859                 prio = 3;
 860                 break;
 861         case DMA_PRIO_MEDIUM:
 862                 prio = 2;
 863                 break;
 864         case DMA_PRIO_LOW:
 865         default:
 866                 prio = 1;
 867                 break;
 868         }
 869
 870         sdmac->peripheral_type = data->peripheral_type;
 871         sdmac->event_id0 = data->dma_request;
 872         ret = sdma_set_channel_priority(sdmac, prio);
 873         if (ret)
 874                 return ret;
 875
 876         ret = sdma_request_channel(sdmac);
 877         if (ret)
 878                 return ret;
 879
 880         dma_async_tx_descriptor_init(&sdmac->desc, chan);
 881         sdmac->desc.tx_submit = sdma_tx_submit;
 882         /* txd.flags will be overwritten in prep funcs */
 883         sdmac->desc.flags = DMA_CTRL_ACK;
 884
 885         return 0;
 886 }
 887
 888 static void sdma_free_chan_resources(struct dma_chan *chan)
 889 {
 890         struct sdma_channel *sdmac = to_sdma_chan(chan);
 891         struct sdma_engine *sdma = sdmac->sdma;
 892
 893         sdma_disable_channel(sdmac);
 894
 895         if (sdmac->event_id0)
 896                 sdma_event_disable(sdmac, sdmac->event_id0);
 897         if (sdmac->event_id1)
 898                 sdma_event_disable(sdmac, sdmac->event_id1);
 899
 900         sdmac->event_id0 = 0;
 901         sdmac->event_id1 = 0;
 902
 903         sdma_set_channel_priority(sdmac, 0);
 904
 905         dma_free_coherent(NULL, PAGE_SIZE, sdmac->bd, sdmac->bd_phys);
 906
 907         clk_disable(sdma->clk);
 908 }
 909
 910 static struct dma_async_tx_descriptor *sdma_prep_slave_sg(
 911                 struct dma_chan *chan, struct scatterlist *sgl,
 912                 unsigned int sg_len, enum dma_data_direction direction,
 913                 unsigned long flags)
 914 {
 915         struct sdma_channel *sdmac = to_sdma_chan(chan);
 916         struct sdma_engine *sdma = sdmac->sdma;
 917         int ret, i, count;
 918         int channel = sdmac->channel;
 919         struct scatterlist *sg;
 920
 921         if (sdmac->status == DMA_IN_PROGRESS)
 922                 return NULL;
 923         sdmac->status = DMA_IN_PROGRESS;
 924
 925         sdmac->flags = 0;
 926
 927         dev_dbg(sdma->dev, "setting up %d entries for channel %d.\n",
 928                         sg_len, channel);
 929
 930         sdmac->direction = direction;
 931         ret = sdma_load_context(sdmac);
 932         if (ret)
 933                 goto err_out;
 934
 935         if (sg_len > NUM_BD) {
 936                 dev_err(sdma->dev, "SDMA channel %d: maximum number of sg exceeded: %d > %d\n",
 937                                 channel, sg_len, NUM_BD);
 938                 ret = -EINVAL;
 939                 goto err_out;
 940         }
 941
 942         for_each_sg(sgl, sg, sg_len, i) {
 943                 struct sdma_buffer_descriptor *bd = &sdmac->bd[i];
 944                 int param;
 945
 946                 bd->buffer_addr = sg->dma_address;
 947
 948                 count = sg->length;
 949
 950                 if (count > 0xffff) {
 951                         dev_err(sdma->dev, "SDMA channel %d: maximum bytes for sg entry exceeded: %d > %d\n",
 952                                         channel, count, 0xffff);
 953                         ret = -EINVAL;
 954                         goto err_out;
 955                 }
 956
 957                 bd->mode.count = count;
 958
 959                 if (sdmac->word_size > DMA_SLAVE_BUSWIDTH_4_BYTES) {
 960                         ret =  -EINVAL;
 961                         goto err_out;
 962                 }
 963
 964                 switch (sdmac->word_size) {
 965                 case DMA_SLAVE_BUSWIDTH_4_BYTES:
 966                         bd->mode.command = 0;
 967                         if (count & 3 || sg->dma_address & 3)
 968                                 return NULL;
 969                         break;
 970                 case DMA_SLAVE_BUSWIDTH_2_BYTES:
 971                         bd->mode.command = 2;
 972                         if (count & 1 || sg->dma_address & 1)
 973                                 return NULL;
 974                         break;
 975                 case DMA_SLAVE_BUSWIDTH_1_BYTE:
 976                         bd->mode.command = 1;
 977                         break;
 978                 default:
 979                         return NULL;
 980                 }
 981
 982                 param = BD_DONE | BD_EXTD | BD_CONT;
 983
 984                 if (i + 1 == sg_len) {
 985                         param |= BD_INTR;
 986                         param |= BD_LAST;
 987                         param &= ~BD_CONT;
 988                 }
 989
 990                 dev_dbg(sdma->dev, "entry %d: count: %d dma: 0x%08x %s%s\n",
 991                                 i, count, sg->dma_address,
 992                                 param & BD_WRAP ? "wrap" : "",
 993                                 param & BD_INTR ? " intr" : "");
 994
 995                 bd->mode.status = param;
 996         }
 997
 998         sdmac->num_bd = sg_len;
 999         sdma->channel_control[channel].current_bd_ptr = sdmac->bd_phys;
1000
1001         return &sdmac->desc;
1002 err_out:
1003         sdmac->status = DMA_ERROR;
1004         return NULL;
1005 }
1006
1007 static struct dma_async_tx_descriptor *sdma_prep_dma_cyclic(
1008                 struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len,
1009                 size_t period_len, enum dma_data_direction direction)
1010 {
1011         struct sdma_channel *sdmac = to_sdma_chan(chan);
1012         struct sdma_engine *sdma = sdmac->sdma;
1013         int num_periods = buf_len / period_len;
1014         int channel = sdmac->channel;
1015         int ret, i = 0, buf = 0;
1016
1017         dev_dbg(sdma->dev, "%s channel: %d\n", __func__, channel);
1018
1019         if (sdmac->status == DMA_IN_PROGRESS)
1020                 return NULL;
1021
1022         sdmac->status = DMA_IN_PROGRESS;
1023
1024         sdmac->flags |= IMX_DMA_SG_LOOP;
1025         sdmac->direction = direction;
1026         ret = sdma_load_context(sdmac);
1027         if (ret)
1028                 goto err_out;
1029
1030         if (num_periods > NUM_BD) {
1031                 dev_err(sdma->dev, "SDMA channel %d: maximum number of sg exceeded: %d > %d\n",
1032                                 channel, num_periods, NUM_BD);
1033                 goto err_out;
1034         }
1035
1036         if (period_len > 0xffff) {
1037                 dev_err(sdma->dev, "SDMA channel %d: maximum period size exceeded: %d > %d\n",
1038                                 channel, period_len, 0xffff);
1039                 goto err_out;
1040         }
1041
1042         while (buf < buf_len) {
1043                 struct sdma_buffer_descriptor *bd = &sdmac->bd[i];
1044                 int param;
1045
1046                 bd->buffer_addr = dma_addr;
1047
1048                 bd->mode.count = period_len;
1049
1050                 if (sdmac->word_size > DMA_SLAVE_BUSWIDTH_4_BYTES)
1051                         goto err_out;
1052                 if (sdmac->word_size == DMA_SLAVE_BUSWIDTH_4_BYTES)
1053                         bd->mode.command = 0;
1054                 else
1055                         bd->mode.command = sdmac->word_size;
1056
1057                 param = BD_DONE | BD_EXTD | BD_CONT | BD_INTR;
1058                 if (i + 1 == num_periods)
1059                         param |= BD_WRAP;
1060
1061                 dev_dbg(sdma->dev, "entry %d: count: %d dma: 0x%08x %s%s\n",
1062                                 i, period_len, dma_addr,
1063                                 param & BD_WRAP ? "wrap" : "",
1064                                 param & BD_INTR ? " intr" : "");
1065
1066                 bd->mode.status = param;
1067
1068                 dma_addr += period_len;
1069                 buf += period_len;
1070
1071                 i++;
1072         }
1073
1074         sdmac->num_bd = num_periods;
1075         sdma->channel_control[channel].current_bd_ptr = sdmac->bd_phys;
1076
1077         return &sdmac->desc;
1078 err_out:
1079         sdmac->status = DMA_ERROR;
1080         return NULL;
1081 }
1082
1083 static int sdma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
1084                 unsigned long arg)
1085 {
1086         struct sdma_channel *sdmac = to_sdma_chan(chan);
1087         struct dma_slave_config *dmaengine_cfg = (void *)arg;
1088
1089         switch (cmd) {
1090         case DMA_TERMINATE_ALL:
1091                 sdma_disable_channel(sdmac);
1092                 return 0;
1093         case DMA_SLAVE_CONFIG:
1094                 if (dmaengine_cfg->direction == DMA_FROM_DEVICE) {
1095                         sdmac->per_address = dmaengine_cfg->src_addr;
1096                         sdmac->watermark_level = dmaengine_cfg->src_maxburst;
1097                         sdmac->word_size = dmaengine_cfg->src_addr_width;
1098                 } else {
1099                         sdmac->per_address = dmaengine_cfg->dst_addr;
1100                         sdmac->watermark_level = dmaengine_cfg->dst_maxburst;
1101                         sdmac->word_size = dmaengine_cfg->dst_addr_width;
1102                 }
1103                 return sdma_config_channel(sdmac);
1104         default:
1105                 return -ENOSYS;
1106         }
1107
1108         return -EINVAL;
1109 }
1110
1111 static enum dma_status sdma_tx_status(struct dma_chan *chan,
1112                                             dma_cookie_t cookie,
1113                                             struct dma_tx_state *txstate)
1114 {
1115         struct sdma_channel *sdmac = to_sdma_chan(chan);
1116         dma_cookie_t last_used;
1117
1118         last_used = chan->cookie;
1119
1120         dma_set_tx_state(txstate, sdmac->last_completed, last_used, 0);
1121
1122         return sdmac->status;
1123 }
1124
1125 static void sdma_issue_pending(struct dma_chan *chan)
1126 {
1127         /*
1128          * Nothing to do. We only have a single descriptor
1129          */
1130 }
1131
1132 #define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1 34
1133
1134 static void sdma_add_scripts(struct sdma_engine *sdma,
1135                 const struct sdma_script_start_addrs *addr)
1136 {
1137         s32 *addr_arr = (u32 *)addr;
1138         s32 *saddr_arr = (u32 *)sdma->script_addrs;
1139         int i;
1140
1141         for (i = 0; i < SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1; i++)
1142                 if (addr_arr[i] > 0)
1143                         saddr_arr[i] = addr_arr[i];
1144 }
1145
1146 static void sdma_load_firmware(const struct firmware *fw, void *context)
1147 {
1148         struct sdma_engine *sdma = context;
1149         const struct sdma_firmware_header *header;
1150         const struct sdma_script_start_addrs *addr;
1151         unsigned short *ram_code;
1152
1153         if (!fw) {
1154                 dev_err(sdma->dev, "firmware not found\n");
1155                 return;
1156         }
1157
1158         if (fw->size < sizeof(*header))
1159                 goto err_firmware;
1160
1161         header = (struct sdma_firmware_header *)fw->data;
1162
1163         if (header->magic != SDMA_FIRMWARE_MAGIC)
1164                 goto err_firmware;
1165         if (header->ram_code_start + header->ram_code_size > fw->size)
1166                 goto err_firmware;
1167
1168         addr = (void *)header + header->script_addrs_start;
1169         ram_code = (void *)header + header->ram_code_start;
1170
1171         clk_enable(sdma->clk);
1172         /* download the RAM image for SDMA */
1173         sdma_load_script(sdma, ram_code,
1174                         header->ram_code_size,
1175                         addr->ram_code_start_addr);
1176         clk_disable(sdma->clk);
1177
1178         sdma_add_scripts(sdma, addr);
1179
1180         dev_info(sdma->dev, "loaded firmware %d.%d\n",
1181                         header->version_major,
1182                         header->version_minor);
1183
1184 err_firmware:
1185         release_firmware(fw);
1186 }
1187
1188 static int __init sdma_get_firmware(struct sdma_engine *sdma,
1189                 const char *fw_name)
1190 {
1191         int ret;
1192
1193         ret = request_firmware_nowait(THIS_MODULE,
1194                         FW_ACTION_HOTPLUG, fw_name, sdma->dev,
1195                         GFP_KERNEL, sdma, sdma_load_firmware);
1196
1197         return ret;
1198 }
1199
1200 static int __init sdma_init(struct sdma_engine *sdma)
1201 {
1202         int i, ret;
1203         dma_addr_t ccb_phys;
1204
1205         switch (sdma->devtype) {
1206         case IMX31_SDMA:
1207                 sdma->num_events = 32;
1208                 break;
1209         case IMX35_SDMA:
1210                 sdma->num_events = 48;
1211                 break;
1212         default:
1213                 dev_err(sdma->dev, "Unknown sdma type %d. aborting\n",
1214                         sdma->devtype);
1215                 return -ENODEV;
1216         }
1217
1218         clk_enable(sdma->clk);
1219
1220         /* Be sure SDMA has not started yet */
1221         __raw_writel(0, sdma->regs + SDMA_H_C0PTR);
1222
1223         sdma->channel_control = dma_alloc_coherent(NULL,
1224                         MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control) +
1225                         sizeof(struct sdma_context_data),
1226                         &ccb_phys, GFP_KERNEL);
1227
1228         if (!sdma->channel_control) {
1229                 ret = -ENOMEM;
1230                 goto err_dma_alloc;
1231         }
1232
1233         sdma->context = (void *)sdma->channel_control +
1234                 MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control);
1235         sdma->context_phys = ccb_phys +
1236                 MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control);
1237
1238         /* Zero-out the CCB structures array just allocated */
1239         memset(sdma->channel_control, 0,
1240                         MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control));
1241
1242         /* disable all channels */
1243         for (i = 0; i < sdma->num_events; i++)
1244                 __raw_writel(0, sdma->regs + chnenbl_ofs(sdma, i));
1245
1246         /* All channels have priority 0 */
1247         for (i = 0; i < MAX_DMA_CHANNELS; i++)
1248                 __raw_writel(0, sdma->regs + SDMA_CHNPRI_0 + i * 4);
1249
1250         ret = sdma_request_channel(&sdma->channel[0]);
1251         if (ret)
1252                 goto err_dma_alloc;
1253
1254         sdma_config_ownership(&sdma->channel[0], false, true, false);
1255
1256         /* Set Command Channel (Channel Zero) */
1257         __raw_writel(0x4050, sdma->regs + SDMA_CHN0ADDR);
1258
1259         /* Set bits of CONFIG register but with static context switching */
1260         /* FIXME: Check whether to set ACR bit depending on clock ratios */
1261         __raw_writel(0, sdma->regs + SDMA_H_CONFIG);
1262
1263         __raw_writel(ccb_phys, sdma->regs + SDMA_H_C0PTR);
1264
1265         /* Set bits of CONFIG register with given context switching mode */
1266         __raw_writel(SDMA_H_CONFIG_CSM, sdma->regs + SDMA_H_CONFIG);
1267
1268         /* Initializes channel's priorities */
1269         sdma_set_channel_priority(&sdma->channel[0], 7);
1270
1271         clk_disable(sdma->clk);
1272
1273         return 0;
1274
1275 err_dma_alloc:
1276         clk_disable(sdma->clk);
1277         dev_err(sdma->dev, "initialisation failed with %d\n", ret);
1278         return ret;
1279 }
1280
1281 static int __init sdma_probe(struct platform_device *pdev)
1282 {
1283         const struct of_device_id *of_id =
1284                         of_match_device(sdma_dt_ids, &pdev->dev);
1285         struct device_node *np = pdev->dev.of_node;
1286         const char *fw_name;
1287         int ret;
1288         int irq;
1289         struct resource *iores;
1290         struct sdma_platform_data *pdata = pdev->dev.platform_data;
1291         int i;
1292         struct sdma_engine *sdma;
1293         s32 *saddr_arr;
1294
1295         sdma = kzalloc(sizeof(*sdma), GFP_KERNEL);
1296         if (!sdma)
1297                 return -ENOMEM;
1298
1299         mutex_init(&sdma->channel_0_lock);
1300
1301         sdma->dev = &pdev->dev;
1302
1303         iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1304         irq = platform_get_irq(pdev, 0);
1305         if (!iores || irq < 0) {
1306                 ret = -EINVAL;
1307                 goto err_irq;
1308         }
1309
1310         if (!request_mem_region(iores->start, resource_size(iores), pdev->name)) {
1311                 ret = -EBUSY;
1312                 goto err_request_region;
1313         }
1314
1315         sdma->clk = clk_get(&pdev->dev, NULL);
1316         if (IS_ERR(sdma->clk)) {
1317                 ret = PTR_ERR(sdma->clk);
1318                 goto err_clk;
1319         }
1320
1321         sdma->regs = ioremap(iores->start, resource_size(iores));
1322         if (!sdma->regs) {
1323                 ret = -ENOMEM;
1324                 goto err_ioremap;
1325         }
1326
1327         ret = request_irq(irq, sdma_int_handler, 0, "sdma", sdma);
1328         if (ret)
1329                 goto err_request_irq;
1330
1331         sdma->script_addrs = kzalloc(sizeof(*sdma->script_addrs), GFP_KERNEL);
1332         if (!sdma->script_addrs) {
1333                 ret = -ENOMEM;
1334                 goto err_alloc;
1335         }
1336
1337         /* initially no scripts available */
1338         saddr_arr = (s32 *)sdma->script_addrs;
1339         for (i = 0; i < SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1; i++)
1340                 saddr_arr[i] = -EINVAL;
1341
1342         if (of_id)
1343                 pdev->id_entry = of_id->data;
1344         sdma->devtype = pdev->id_entry->driver_data;
1345
1346         dma_cap_set(DMA_SLAVE, sdma->dma_device.cap_mask);
1347         dma_cap_set(DMA_CYCLIC, sdma->dma_device.cap_mask);
1348
1349         INIT_LIST_HEAD(&sdma->dma_device.channels);
1350         /* Initialize channel parameters */
1351         for (i = 0; i < MAX_DMA_CHANNELS; i++) {
1352                 struct sdma_channel *sdmac = &sdma->channel[i];
1353
1354                 sdmac->sdma = sdma;
1355                 spin_lock_init(&sdmac->lock);
1356
1357                 sdmac->chan.device = &sdma->dma_device;
1358                 sdmac->channel = i;
1359
1360                 /*
1361                  * Add the channel to the DMAC list. Do not add channel 0 though
1362                  * because we need it internally in the SDMA driver. This also means
1363                  * that channel 0 in dmaengine counting matches sdma channel 1.
1364                  */
1365                 if (i)
1366                         list_add_tail(&sdmac->chan.device_node,
1367                                         &sdma->dma_device.channels);
1368         }
1369
1370         ret = sdma_init(sdma);
1371         if (ret)
1372                 goto err_init;
1373
1374         if (pdata && pdata->script_addrs)
1375                 sdma_add_scripts(sdma, pdata->script_addrs);
1376
1377         if (pdata) {
1378                 sdma_get_firmware(sdma, pdata->fw_name);
1379         } else {
1380                 /*
1381                  * Because that device tree does not encode ROM script address,
1382                  * the RAM script in firmware is mandatory for device tree
1383                  * probe, otherwise it fails.
1384                  */
1385                 ret = of_property_read_string(np, "fsl,sdma-ram-script-name",
1386                                               &fw_name);
1387                 if (ret) {
1388                         dev_err(&pdev->dev, "failed to get firmware name\n");
1389                         goto err_init;
1390                 }
1391
1392                 ret = sdma_get_firmware(sdma, fw_name);
1393                 if (ret) {
1394                         dev_err(&pdev->dev, "failed to get firmware\n");
1395                         goto err_init;
1396                 }
1397         }
1398
1399         sdma->dma_device.dev = &pdev->dev;
1400
1401         sdma->dma_device.device_alloc_chan_resources = sdma_alloc_chan_resources;
1402         sdma->dma_device.device_free_chan_resources = sdma_free_chan_resources;
1403         sdma->dma_device.device_tx_status = sdma_tx_status;
1404         sdma->dma_device.device_prep_slave_sg = sdma_prep_slave_sg;
1405         sdma->dma_device.device_prep_dma_cyclic = sdma_prep_dma_cyclic;
1406         sdma->dma_device.device_control = sdma_control;
1407         sdma->dma_device.device_issue_pending = sdma_issue_pending;
1408         sdma->dma_device.dev->dma_parms = &sdma->dma_parms;
1409         dma_set_max_seg_size(sdma->dma_device.dev, 65535);
1410
1411         ret = dma_async_device_register(&sdma->dma_device);
1412         if (ret) {
1413                 dev_err(&pdev->dev, "unable to register\n");
1414                 goto err_init;
1415         }
1416
1417         dev_info(sdma->dev, "initialized\n");
1418
1419         return 0;
1420
1421 err_init:
1422         kfree(sdma->script_addrs);
1423 err_alloc:
1424         free_irq(irq, sdma);
1425 err_request_irq:
1426         iounmap(sdma->regs);
1427 err_ioremap:
1428         clk_put(sdma->clk);
1429 err_clk:
1430         release_mem_region(iores->start, resource_size(iores));
1431 err_request_region:
1432 err_irq:
1433         kfree(sdma);
1434         return ret;
1435 }
1436
1437 static int __exit sdma_remove(struct platform_device *pdev)
1438 {
1439         return -EBUSY;
1440 }
1441
1442 static struct platform_driver sdma_driver = {
1443         .driver         = {
1444                 .name   = "imx-sdma",
1445                 .of_match_table = sdma_dt_ids,
1446         },
1447         .id_table       = sdma_devtypes,
1448         .remove         = __exit_p(sdma_remove),
1449 };
1450
1451 static int __init sdma_module_init(void)
1452 {
1453         return platform_driver_probe(&sdma_driver, sdma_probe);
1454 }
1455 module_init(sdma_module_init);
1456
1457 MODULE_AUTHOR("Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>");
1458 MODULE_DESCRIPTION("i.MX SDMA driver");
1459 MODULE_LICENSE("GPL");