1 // SPDX-License-Identifier: GPL-2.0
3 * (C) Copyright 2015 Google, Inc
4 * (C) 2017 Theobroma Systems Design und Consulting GmbH
8 #include <clk-uclass.h>
10 #include <dt-structs.h>
17 #include <asm/arch-rockchip/clock.h>
18 #include <asm/arch-rockchip/cru.h>
19 #include <asm/arch-rockchip/hardware.h>
20 #include <asm/global_data.h>
21 #include <dm/device-internal.h>
23 #include <dt-bindings/clock/rk3399-cru.h>
24 #include <linux/bitops.h>
25 #include <linux/delay.h>
26 #include <linux/printk.h>
28 DECLARE_GLOBAL_DATA_PTR;
30 #if CONFIG_IS_ENABLED(OF_PLATDATA)
31 struct rk3399_clk_plat {
32 struct dtd_rockchip_rk3399_cru dtd;
35 struct rk3399_pmuclk_plat {
36 struct dtd_rockchip_rk3399_pmucru dtd;
48 #define RATE_TO_DIV(input_rate, output_rate) \
49 ((input_rate) / (output_rate) - 1)
50 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1))
52 #define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\
54 .fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ),\
55 .postdiv1 = _postdiv1, .postdiv2 = _postdiv2};
57 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1);
58 static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2, 2);
59 #if !defined(CONFIG_SPL_BUILD)
60 static const struct pll_div ppll_init_cfg = PLL_DIVISORS(PPLL_HZ, 2, 2, 1);
63 static const struct pll_div apll_l_1600_cfg = PLL_DIVISORS(1600 * MHz, 3, 1, 1);
64 static const struct pll_div apll_l_600_cfg = PLL_DIVISORS(600 * MHz, 1, 2, 1);
66 static const struct pll_div *apll_l_cfgs[] = {
67 [APLL_L_1600_MHZ] = &apll_l_1600_cfg,
68 [APLL_L_600_MHZ] = &apll_l_600_cfg,
71 static const struct pll_div apll_b_600_cfg = PLL_DIVISORS(600 * MHz, 1, 2, 1);
72 static const struct pll_div *apll_b_cfgs[] = {
73 [APLL_B_600_MHZ] = &apll_b_600_cfg,
78 PLL_FBDIV_MASK = 0xfff,
82 PLL_POSTDIV2_SHIFT = 12,
83 PLL_POSTDIV2_MASK = 0x7 << PLL_POSTDIV2_SHIFT,
84 PLL_POSTDIV1_SHIFT = 8,
85 PLL_POSTDIV1_MASK = 0x7 << PLL_POSTDIV1_SHIFT,
86 PLL_REFDIV_MASK = 0x3f,
90 PLL_LOCK_STATUS_SHIFT = 31,
91 PLL_LOCK_STATUS_MASK = 1 << PLL_LOCK_STATUS_SHIFT,
92 PLL_FRACDIV_MASK = 0xffffff,
93 PLL_FRACDIV_SHIFT = 0,
97 PLL_MODE_MASK = 3 << PLL_MODE_SHIFT,
102 PLL_DSMPD_MASK = 1 << PLL_DSMPD_SHIFT,
103 PLL_INTEGER_MODE = 1,
105 /* PMUCRU_CLKSEL_CON0 */
106 PMU_PCLK_DIV_CON_MASK = 0x1f,
107 PMU_PCLK_DIV_CON_SHIFT = 0,
109 /* PMUCRU_CLKSEL_CON1 */
110 SPI3_PLL_SEL_SHIFT = 7,
111 SPI3_PLL_SEL_MASK = 1 << SPI3_PLL_SEL_SHIFT,
112 SPI3_PLL_SEL_24M = 0,
113 SPI3_PLL_SEL_PPLL = 1,
114 SPI3_DIV_CON_SHIFT = 0x0,
115 SPI3_DIV_CON_MASK = 0x7f,
117 /* PMUCRU_CLKSEL_CON2 */
118 I2C_DIV_CON_MASK = 0x7f,
119 CLK_I2C8_DIV_CON_SHIFT = 8,
120 CLK_I2C0_DIV_CON_SHIFT = 0,
122 /* PMUCRU_CLKSEL_CON3 */
123 CLK_I2C4_DIV_CON_SHIFT = 0,
126 ACLKM_CORE_L_DIV_CON_SHIFT = 8,
127 ACLKM_CORE_L_DIV_CON_MASK = 0x1f << ACLKM_CORE_L_DIV_CON_SHIFT,
128 CLK_CORE_L_PLL_SEL_SHIFT = 6,
129 CLK_CORE_L_PLL_SEL_MASK = 3 << CLK_CORE_L_PLL_SEL_SHIFT,
130 CLK_CORE_L_PLL_SEL_ALPLL = 0x0,
131 CLK_CORE_L_PLL_SEL_ABPLL = 0x1,
132 CLK_CORE_L_PLL_SEL_DPLL = 0x10,
133 CLK_CORE_L_PLL_SEL_GPLL = 0x11,
134 CLK_CORE_L_DIV_MASK = 0x1f,
135 CLK_CORE_L_DIV_SHIFT = 0,
138 PCLK_DBG_L_DIV_SHIFT = 0x8,
139 PCLK_DBG_L_DIV_MASK = 0x1f << PCLK_DBG_L_DIV_SHIFT,
140 ATCLK_CORE_L_DIV_SHIFT = 0,
141 ATCLK_CORE_L_DIV_MASK = 0x1f << ATCLK_CORE_L_DIV_SHIFT,
144 ACLKM_CORE_B_DIV_CON_SHIFT = 8,
145 ACLKM_CORE_B_DIV_CON_MASK = 0x1f << ACLKM_CORE_B_DIV_CON_SHIFT,
146 CLK_CORE_B_PLL_SEL_SHIFT = 6,
147 CLK_CORE_B_PLL_SEL_MASK = 3 << CLK_CORE_B_PLL_SEL_SHIFT,
148 CLK_CORE_B_PLL_SEL_ALPLL = 0x0,
149 CLK_CORE_B_PLL_SEL_ABPLL = 0x1,
150 CLK_CORE_B_PLL_SEL_DPLL = 0x10,
151 CLK_CORE_B_PLL_SEL_GPLL = 0x11,
152 CLK_CORE_B_DIV_MASK = 0x1f,
153 CLK_CORE_B_DIV_SHIFT = 0,
156 PCLK_DBG_B_DIV_SHIFT = 0x8,
157 PCLK_DBG_B_DIV_MASK = 0x1f << PCLK_DBG_B_DIV_SHIFT,
158 ATCLK_CORE_B_DIV_SHIFT = 0,
159 ATCLK_CORE_B_DIV_MASK = 0x1f << ATCLK_CORE_B_DIV_SHIFT,
162 PCLK_PERIHP_DIV_CON_SHIFT = 12,
163 PCLK_PERIHP_DIV_CON_MASK = 0x7 << PCLK_PERIHP_DIV_CON_SHIFT,
164 HCLK_PERIHP_DIV_CON_SHIFT = 8,
165 HCLK_PERIHP_DIV_CON_MASK = 3 << HCLK_PERIHP_DIV_CON_SHIFT,
166 ACLK_PERIHP_PLL_SEL_SHIFT = 7,
167 ACLK_PERIHP_PLL_SEL_MASK = 1 << ACLK_PERIHP_PLL_SEL_SHIFT,
168 ACLK_PERIHP_PLL_SEL_CPLL = 0,
169 ACLK_PERIHP_PLL_SEL_GPLL = 1,
170 ACLK_PERIHP_DIV_CON_SHIFT = 0,
171 ACLK_PERIHP_DIV_CON_MASK = 0x1f,
174 ACLK_EMMC_PLL_SEL_SHIFT = 7,
175 ACLK_EMMC_PLL_SEL_MASK = 0x1 << ACLK_EMMC_PLL_SEL_SHIFT,
176 ACLK_EMMC_PLL_SEL_GPLL = 0x1,
177 ACLK_EMMC_DIV_CON_SHIFT = 0,
178 ACLK_EMMC_DIV_CON_MASK = 0x1f,
181 CLK_EMMC_PLL_SHIFT = 8,
182 CLK_EMMC_PLL_MASK = 0x7 << CLK_EMMC_PLL_SHIFT,
183 CLK_EMMC_PLL_SEL_GPLL = 0x1,
184 CLK_EMMC_PLL_SEL_24M = 0x5,
185 CLK_EMMC_DIV_CON_SHIFT = 0,
186 CLK_EMMC_DIV_CON_MASK = 0x7f << CLK_EMMC_DIV_CON_SHIFT,
189 PCLK_PERILP0_DIV_CON_SHIFT = 12,
190 PCLK_PERILP0_DIV_CON_MASK = 0x7 << PCLK_PERILP0_DIV_CON_SHIFT,
191 HCLK_PERILP0_DIV_CON_SHIFT = 8,
192 HCLK_PERILP0_DIV_CON_MASK = 3 << HCLK_PERILP0_DIV_CON_SHIFT,
193 ACLK_PERILP0_PLL_SEL_SHIFT = 7,
194 ACLK_PERILP0_PLL_SEL_MASK = 1 << ACLK_PERILP0_PLL_SEL_SHIFT,
195 ACLK_PERILP0_PLL_SEL_CPLL = 0,
196 ACLK_PERILP0_PLL_SEL_GPLL = 1,
197 ACLK_PERILP0_DIV_CON_SHIFT = 0,
198 ACLK_PERILP0_DIV_CON_MASK = 0x1f,
201 PCLK_PERILP1_DIV_CON_SHIFT = 8,
202 PCLK_PERILP1_DIV_CON_MASK = 0x7 << PCLK_PERILP1_DIV_CON_SHIFT,
203 HCLK_PERILP1_PLL_SEL_SHIFT = 7,
204 HCLK_PERILP1_PLL_SEL_MASK = 1 << HCLK_PERILP1_PLL_SEL_SHIFT,
205 HCLK_PERILP1_PLL_SEL_CPLL = 0,
206 HCLK_PERILP1_PLL_SEL_GPLL = 1,
207 HCLK_PERILP1_DIV_CON_SHIFT = 0,
208 HCLK_PERILP1_DIV_CON_MASK = 0x1f,
211 CLK_SARADC_DIV_CON_SHIFT = 8,
212 CLK_SARADC_DIV_CON_MASK = GENMASK(15, 8),
213 CLK_SARADC_DIV_CON_WIDTH = 8,
216 CLK_TSADC_SEL_X24M = 0x0,
217 CLK_TSADC_SEL_SHIFT = 15,
218 CLK_TSADC_SEL_MASK = 1 << CLK_TSADC_SEL_SHIFT,
219 CLK_TSADC_DIV_CON_SHIFT = 0,
220 CLK_TSADC_DIV_CON_MASK = 0x3ff,
222 /* CLKSEL_CON47 & CLKSEL_CON48 */
223 ACLK_VOP_PLL_SEL_SHIFT = 6,
224 ACLK_VOP_PLL_SEL_MASK = 0x3 << ACLK_VOP_PLL_SEL_SHIFT,
225 ACLK_VOP_PLL_SEL_CPLL = 0x1,
226 ACLK_VOP_DIV_CON_SHIFT = 0,
227 ACLK_VOP_DIV_CON_MASK = 0x1f << ACLK_VOP_DIV_CON_SHIFT,
229 /* CLKSEL_CON49 & CLKSEL_CON50 */
230 DCLK_VOP_DCLK_SEL_SHIFT = 11,
231 DCLK_VOP_DCLK_SEL_MASK = 1 << DCLK_VOP_DCLK_SEL_SHIFT,
232 DCLK_VOP_DCLK_SEL_DIVOUT = 0,
233 DCLK_VOP_PLL_SEL_SHIFT = 8,
234 DCLK_VOP_PLL_SEL_MASK = 3 << DCLK_VOP_PLL_SEL_SHIFT,
235 DCLK_VOP_PLL_SEL_VPLL = 0,
236 DCLK_VOP_DIV_CON_MASK = 0xff,
237 DCLK_VOP_DIV_CON_SHIFT = 0,
240 PCLK_ALIVE_DIV_CON_SHIFT = 0,
241 PCLK_ALIVE_DIV_CON_MASK = 0x1f << PCLK_ALIVE_DIV_CON_SHIFT,
244 CLK_SPI_PLL_SEL_WIDTH = 1,
245 CLK_SPI_PLL_SEL_MASK = ((1 < CLK_SPI_PLL_SEL_WIDTH) - 1),
246 CLK_SPI_PLL_SEL_CPLL = 0,
247 CLK_SPI_PLL_SEL_GPLL = 1,
248 CLK_SPI_PLL_DIV_CON_WIDTH = 7,
249 CLK_SPI_PLL_DIV_CON_MASK = ((1 << CLK_SPI_PLL_DIV_CON_WIDTH) - 1),
251 CLK_SPI5_PLL_DIV_CON_SHIFT = 8,
252 CLK_SPI5_PLL_SEL_SHIFT = 15,
255 CLK_SPI1_PLL_SEL_SHIFT = 15,
256 CLK_SPI1_PLL_DIV_CON_SHIFT = 8,
257 CLK_SPI0_PLL_SEL_SHIFT = 7,
258 CLK_SPI0_PLL_DIV_CON_SHIFT = 0,
261 CLK_SPI4_PLL_SEL_SHIFT = 15,
262 CLK_SPI4_PLL_DIV_CON_SHIFT = 8,
263 CLK_SPI2_PLL_SEL_SHIFT = 7,
264 CLK_SPI2_PLL_DIV_CON_SHIFT = 0,
267 CLK_I2C_PLL_SEL_MASK = 1,
268 CLK_I2C_PLL_SEL_CPLL = 0,
269 CLK_I2C_PLL_SEL_GPLL = 1,
270 CLK_I2C5_PLL_SEL_SHIFT = 15,
271 CLK_I2C5_DIV_CON_SHIFT = 8,
272 CLK_I2C1_PLL_SEL_SHIFT = 7,
273 CLK_I2C1_DIV_CON_SHIFT = 0,
276 CLK_I2C6_PLL_SEL_SHIFT = 15,
277 CLK_I2C6_DIV_CON_SHIFT = 8,
278 CLK_I2C2_PLL_SEL_SHIFT = 7,
279 CLK_I2C2_DIV_CON_SHIFT = 0,
282 CLK_I2C7_PLL_SEL_SHIFT = 15,
283 CLK_I2C7_DIV_CON_SHIFT = 8,
284 CLK_I2C3_PLL_SEL_SHIFT = 7,
285 CLK_I2C3_DIV_CON_SHIFT = 0,
287 /* CRU_SOFTRST_CON4 */
288 RESETN_DDR0_REQ_SHIFT = 8,
289 RESETN_DDR0_REQ_MASK = 1 << RESETN_DDR0_REQ_SHIFT,
290 RESETN_DDRPHY0_REQ_SHIFT = 9,
291 RESETN_DDRPHY0_REQ_MASK = 1 << RESETN_DDRPHY0_REQ_SHIFT,
292 RESETN_DDR1_REQ_SHIFT = 12,
293 RESETN_DDR1_REQ_MASK = 1 << RESETN_DDR1_REQ_SHIFT,
294 RESETN_DDRPHY1_REQ_SHIFT = 13,
295 RESETN_DDRPHY1_REQ_MASK = 1 << RESETN_DDRPHY1_REQ_SHIFT,
298 #define VCO_MAX_KHZ (3200 * (MHz / KHz))
299 #define VCO_MIN_KHZ (800 * (MHz / KHz))
300 #define OUTPUT_MAX_KHZ (3200 * (MHz / KHz))
301 #define OUTPUT_MIN_KHZ (16 * (MHz / KHz))
304 * the div restructions of pll in integer mode, these are defined in
305 * * CRU_*PLL_CON0 or PMUCRU_*PLL_CON0
307 #define PLL_DIV_MIN 16
308 #define PLL_DIV_MAX 3200
311 * How to calculate the PLL(from TRM V0.3 Part 1 Page 63):
312 * Formulas also embedded within the Fractional PLL Verilog model:
313 * If DSMPD = 1 (DSM is disabled, "integer mode")
314 * FOUTVCO = FREF / REFDIV * FBDIV
315 * FOUTPOSTDIV = FOUTVCO / POSTDIV1 / POSTDIV2
317 * FOUTVCO = Fractional PLL non-divided output frequency
318 * FOUTPOSTDIV = Fractional PLL divided output frequency
319 * (output of second post divider)
320 * FREF = Fractional PLL input reference frequency, (the OSC_HZ 24MHz input)
321 * REFDIV = Fractional PLL input reference clock divider
322 * FBDIV = Integer value programmed into feedback divide
325 static void rkclk_set_pll(u32 *pll_con, const struct pll_div *div)
327 /* All 8 PLLs have same VCO and output frequency range restrictions. */
328 u32 vco_khz = OSC_HZ / 1000 * div->fbdiv / div->refdiv;
329 u32 output_khz = vco_khz / div->postdiv1 / div->postdiv2;
331 debug("PLL at %p: fbdiv=%d, refdiv=%d, postdiv1=%d, "
332 "postdiv2=%d, vco=%u khz, output=%u khz\n",
333 pll_con, div->fbdiv, div->refdiv, div->postdiv1,
334 div->postdiv2, vco_khz, output_khz);
335 assert(vco_khz >= VCO_MIN_KHZ && vco_khz <= VCO_MAX_KHZ &&
336 output_khz >= OUTPUT_MIN_KHZ && output_khz <= OUTPUT_MAX_KHZ &&
337 div->fbdiv >= PLL_DIV_MIN && div->fbdiv <= PLL_DIV_MAX);
340 * When power on or changing PLL setting,
341 * we must force PLL into slow mode to ensure output stable clock.
343 rk_clrsetreg(&pll_con[3], PLL_MODE_MASK,
344 PLL_MODE_SLOW << PLL_MODE_SHIFT);
346 /* use integer mode */
347 rk_clrsetreg(&pll_con[3], PLL_DSMPD_MASK,
348 PLL_INTEGER_MODE << PLL_DSMPD_SHIFT);
350 rk_clrsetreg(&pll_con[0], PLL_FBDIV_MASK,
351 div->fbdiv << PLL_FBDIV_SHIFT);
352 rk_clrsetreg(&pll_con[1],
353 PLL_POSTDIV2_MASK | PLL_POSTDIV1_MASK |
354 PLL_REFDIV_MASK | PLL_REFDIV_SHIFT,
355 (div->postdiv2 << PLL_POSTDIV2_SHIFT) |
356 (div->postdiv1 << PLL_POSTDIV1_SHIFT) |
357 (div->refdiv << PLL_REFDIV_SHIFT));
359 /* waiting for pll lock */
360 while (!(readl(&pll_con[2]) & (1 << PLL_LOCK_STATUS_SHIFT)))
363 /* pll enter normal mode */
364 rk_clrsetreg(&pll_con[3], PLL_MODE_MASK,
365 PLL_MODE_NORM << PLL_MODE_SHIFT);
368 static int pll_para_config(u32 freq_hz, struct pll_div *div)
370 u32 ref_khz = OSC_HZ / KHz, refdiv, fbdiv = 0;
371 u32 postdiv1, postdiv2 = 1;
373 u32 diff_khz, best_diff_khz;
374 const u32 max_refdiv = 63, max_fbdiv = 3200, min_fbdiv = 16;
375 const u32 max_postdiv1 = 7, max_postdiv2 = 7;
377 u32 freq_khz = freq_hz / KHz;
380 printf("%s: the frequency can't be 0 Hz\n", __func__);
384 postdiv1 = DIV_ROUND_UP(VCO_MIN_KHZ, freq_khz);
385 if (postdiv1 > max_postdiv1) {
386 postdiv2 = DIV_ROUND_UP(postdiv1, max_postdiv1);
387 postdiv1 = DIV_ROUND_UP(postdiv1, postdiv2);
390 vco_khz = freq_khz * postdiv1 * postdiv2;
392 if (vco_khz < VCO_MIN_KHZ || vco_khz > VCO_MAX_KHZ ||
393 postdiv2 > max_postdiv2) {
394 printf("%s: Cannot find out a supported VCO"
395 " for Frequency (%uHz).\n", __func__, freq_hz);
399 div->postdiv1 = postdiv1;
400 div->postdiv2 = postdiv2;
402 best_diff_khz = vco_khz;
403 for (refdiv = 1; refdiv < max_refdiv && best_diff_khz; refdiv++) {
404 fref_khz = ref_khz / refdiv;
406 fbdiv = vco_khz / fref_khz;
407 if (fbdiv >= max_fbdiv || fbdiv <= min_fbdiv)
409 diff_khz = vco_khz - fbdiv * fref_khz;
410 if (fbdiv + 1 < max_fbdiv && diff_khz > fref_khz / 2) {
412 diff_khz = fref_khz - diff_khz;
415 if (diff_khz >= best_diff_khz)
418 best_diff_khz = diff_khz;
419 div->refdiv = refdiv;
423 if (best_diff_khz > 4 * (MHz / KHz)) {
424 printf("%s: Failed to match output frequency %u, "
425 "difference is %u Hz,exceed 4MHZ\n", __func__, freq_hz,
426 best_diff_khz * KHz);
432 void rk3399_configure_cpu_l(struct rockchip_cru *cru,
433 enum apll_l_frequencies apll_l_freq)
439 /* Setup cluster L */
440 rkclk_set_pll(&cru->apll_l_con[0], apll_l_cfgs[apll_l_freq]);
442 aclkm_div = LPLL_HZ / ACLKM_CORE_L_HZ - 1;
443 assert((aclkm_div + 1) * ACLKM_CORE_L_HZ == LPLL_HZ &&
446 pclk_dbg_div = LPLL_HZ / PCLK_DBG_L_HZ - 1;
447 assert((pclk_dbg_div + 1) * PCLK_DBG_L_HZ == LPLL_HZ &&
448 pclk_dbg_div < 0x1f);
450 atclk_div = LPLL_HZ / ATCLK_CORE_L_HZ - 1;
451 assert((atclk_div + 1) * ATCLK_CORE_L_HZ == LPLL_HZ &&
454 rk_clrsetreg(&cru->clksel_con[0],
455 ACLKM_CORE_L_DIV_CON_MASK | CLK_CORE_L_PLL_SEL_MASK |
457 aclkm_div << ACLKM_CORE_L_DIV_CON_SHIFT |
458 CLK_CORE_L_PLL_SEL_ALPLL << CLK_CORE_L_PLL_SEL_SHIFT |
459 0 << CLK_CORE_L_DIV_SHIFT);
461 rk_clrsetreg(&cru->clksel_con[1],
462 PCLK_DBG_L_DIV_MASK | ATCLK_CORE_L_DIV_MASK,
463 pclk_dbg_div << PCLK_DBG_L_DIV_SHIFT |
464 atclk_div << ATCLK_CORE_L_DIV_SHIFT);
467 void rk3399_configure_cpu_b(struct rockchip_cru *cru,
468 enum apll_b_frequencies apll_b_freq)
474 /* Setup cluster B */
475 rkclk_set_pll(&cru->apll_b_con[0], apll_b_cfgs[apll_b_freq]);
477 aclkm_div = BPLL_HZ / ACLKM_CORE_B_HZ - 1;
478 assert((aclkm_div + 1) * ACLKM_CORE_B_HZ == BPLL_HZ &&
481 pclk_dbg_div = BPLL_HZ / PCLK_DBG_B_HZ - 1;
482 assert((pclk_dbg_div + 1) * PCLK_DBG_B_HZ == BPLL_HZ &&
483 pclk_dbg_div < 0x1f);
485 atclk_div = BPLL_HZ / ATCLK_CORE_B_HZ - 1;
486 assert((atclk_div + 1) * ATCLK_CORE_B_HZ == BPLL_HZ &&
489 rk_clrsetreg(&cru->clksel_con[2],
490 ACLKM_CORE_B_DIV_CON_MASK | CLK_CORE_B_PLL_SEL_MASK |
492 aclkm_div << ACLKM_CORE_B_DIV_CON_SHIFT |
493 CLK_CORE_B_PLL_SEL_ABPLL << CLK_CORE_B_PLL_SEL_SHIFT |
494 0 << CLK_CORE_B_DIV_SHIFT);
496 rk_clrsetreg(&cru->clksel_con[3],
497 PCLK_DBG_B_DIV_MASK | ATCLK_CORE_B_DIV_MASK,
498 pclk_dbg_div << PCLK_DBG_B_DIV_SHIFT |
499 atclk_div << ATCLK_CORE_B_DIV_SHIFT);
502 #define I2C_CLK_REG_MASK(bus) \
503 (I2C_DIV_CON_MASK << CLK_I2C ##bus## _DIV_CON_SHIFT | \
504 CLK_I2C_PLL_SEL_MASK << CLK_I2C ##bus## _PLL_SEL_SHIFT)
506 #define I2C_CLK_REG_VALUE(bus, clk_div) \
507 ((clk_div - 1) << CLK_I2C ##bus## _DIV_CON_SHIFT | \
508 CLK_I2C_PLL_SEL_GPLL << CLK_I2C ##bus## _PLL_SEL_SHIFT)
510 #define I2C_CLK_DIV_VALUE(con, bus) \
511 ((con >> CLK_I2C ##bus## _DIV_CON_SHIFT) & I2C_DIV_CON_MASK)
513 #define I2C_PMUCLK_REG_MASK(bus) \
514 (I2C_DIV_CON_MASK << CLK_I2C ##bus## _DIV_CON_SHIFT)
516 #define I2C_PMUCLK_REG_VALUE(bus, clk_div) \
517 ((clk_div - 1) << CLK_I2C ##bus## _DIV_CON_SHIFT)
519 static ulong rk3399_i2c_get_clk(struct rockchip_cru *cru, ulong clk_id)
525 con = readl(&cru->clksel_con[61]);
526 div = I2C_CLK_DIV_VALUE(con, 1);
529 con = readl(&cru->clksel_con[62]);
530 div = I2C_CLK_DIV_VALUE(con, 2);
533 con = readl(&cru->clksel_con[63]);
534 div = I2C_CLK_DIV_VALUE(con, 3);
537 con = readl(&cru->clksel_con[61]);
538 div = I2C_CLK_DIV_VALUE(con, 5);
541 con = readl(&cru->clksel_con[62]);
542 div = I2C_CLK_DIV_VALUE(con, 6);
545 con = readl(&cru->clksel_con[63]);
546 div = I2C_CLK_DIV_VALUE(con, 7);
549 printf("do not support this i2c bus\n");
553 return DIV_TO_RATE(GPLL_HZ, div);
556 static ulong rk3399_i2c_set_clk(struct rockchip_cru *cru, ulong clk_id, uint hz)
560 /* i2c0,4,8 src clock from ppll, i2c1,2,3,5,6,7 src clock from gpll*/
561 src_clk_div = GPLL_HZ / hz;
562 assert(src_clk_div - 1 < 127);
566 rk_clrsetreg(&cru->clksel_con[61], I2C_CLK_REG_MASK(1),
567 I2C_CLK_REG_VALUE(1, src_clk_div));
570 rk_clrsetreg(&cru->clksel_con[62], I2C_CLK_REG_MASK(2),
571 I2C_CLK_REG_VALUE(2, src_clk_div));
574 rk_clrsetreg(&cru->clksel_con[63], I2C_CLK_REG_MASK(3),
575 I2C_CLK_REG_VALUE(3, src_clk_div));
578 rk_clrsetreg(&cru->clksel_con[61], I2C_CLK_REG_MASK(5),
579 I2C_CLK_REG_VALUE(5, src_clk_div));
582 rk_clrsetreg(&cru->clksel_con[62], I2C_CLK_REG_MASK(6),
583 I2C_CLK_REG_VALUE(6, src_clk_div));
586 rk_clrsetreg(&cru->clksel_con[63], I2C_CLK_REG_MASK(7),
587 I2C_CLK_REG_VALUE(7, src_clk_div));
590 printf("do not support this i2c bus\n");
594 return rk3399_i2c_get_clk(cru, clk_id);
598 * RK3399 SPI clocks have a common divider-width (7 bits) and a single bit
599 * to select either CPLL or GPLL as the clock-parent. The location within
600 * the enclosing CLKSEL_CON (i.e. div_shift and sel_shift) are variable.
604 u8 reg; /* CLKSEL_CON[reg] register in CRU */
610 * The entries are numbered relative to their offset from SCLK_SPI0.
612 * Note that SCLK_SPI3 (which is configured via PMUCRU and requires different
613 * logic is not supported).
615 static const struct spi_clkreg spi_clkregs[] = {
617 .div_shift = CLK_SPI0_PLL_DIV_CON_SHIFT,
618 .sel_shift = CLK_SPI0_PLL_SEL_SHIFT, },
620 .div_shift = CLK_SPI1_PLL_DIV_CON_SHIFT,
621 .sel_shift = CLK_SPI1_PLL_SEL_SHIFT, },
623 .div_shift = CLK_SPI2_PLL_DIV_CON_SHIFT,
624 .sel_shift = CLK_SPI2_PLL_SEL_SHIFT, },
626 .div_shift = CLK_SPI4_PLL_DIV_CON_SHIFT,
627 .sel_shift = CLK_SPI4_PLL_SEL_SHIFT, },
629 .div_shift = CLK_SPI5_PLL_DIV_CON_SHIFT,
630 .sel_shift = CLK_SPI5_PLL_SEL_SHIFT, },
633 static ulong rk3399_spi_get_clk(struct rockchip_cru *cru, ulong clk_id)
635 const struct spi_clkreg *spiclk = NULL;
639 case SCLK_SPI0 ... SCLK_SPI5:
640 spiclk = &spi_clkregs[clk_id - SCLK_SPI0];
644 pr_err("%s: SPI clk-id %ld not supported\n", __func__, clk_id);
648 val = readl(&cru->clksel_con[spiclk->reg]);
649 div = bitfield_extract(val, spiclk->div_shift,
650 CLK_SPI_PLL_DIV_CON_WIDTH);
652 return DIV_TO_RATE(GPLL_HZ, div);
655 static ulong rk3399_spi_set_clk(struct rockchip_cru *cru, ulong clk_id, uint hz)
657 const struct spi_clkreg *spiclk = NULL;
660 src_clk_div = DIV_ROUND_UP(GPLL_HZ, hz) - 1;
661 assert(src_clk_div < 128);
664 case SCLK_SPI1 ... SCLK_SPI5:
665 spiclk = &spi_clkregs[clk_id - SCLK_SPI0];
669 pr_err("%s: SPI clk-id %ld not supported\n", __func__, clk_id);
673 rk_clrsetreg(&cru->clksel_con[spiclk->reg],
674 ((CLK_SPI_PLL_DIV_CON_MASK << spiclk->div_shift) |
675 (CLK_SPI_PLL_SEL_GPLL << spiclk->sel_shift)),
676 ((src_clk_div << spiclk->div_shift) |
677 (CLK_SPI_PLL_SEL_GPLL << spiclk->sel_shift)));
679 return rk3399_spi_get_clk(cru, clk_id);
682 static ulong rk3399_vop_set_clk(struct rockchip_cru *cru, ulong clk_id, u32 hz)
684 struct pll_div vpll_config = {0};
685 int aclk_vop = 198 * MHz;
686 void *aclkreg_addr, *dclkreg_addr;
691 aclkreg_addr = &cru->clksel_con[47];
692 dclkreg_addr = &cru->clksel_con[49];
695 aclkreg_addr = &cru->clksel_con[48];
696 dclkreg_addr = &cru->clksel_con[50];
701 /* vop aclk source clk: cpll */
702 div = CPLL_HZ / aclk_vop;
703 assert(div - 1 < 32);
705 rk_clrsetreg(aclkreg_addr,
706 ACLK_VOP_PLL_SEL_MASK | ACLK_VOP_DIV_CON_MASK,
707 ACLK_VOP_PLL_SEL_CPLL << ACLK_VOP_PLL_SEL_SHIFT |
708 (div - 1) << ACLK_VOP_DIV_CON_SHIFT);
710 /* vop dclk source from vpll, and equals to vpll(means div == 1) */
711 if (pll_para_config(hz, &vpll_config))
714 rkclk_set_pll(&cru->vpll_con[0], &vpll_config);
716 rk_clrsetreg(dclkreg_addr,
717 DCLK_VOP_DCLK_SEL_MASK | DCLK_VOP_PLL_SEL_MASK |
718 DCLK_VOP_DIV_CON_MASK,
719 DCLK_VOP_DCLK_SEL_DIVOUT << DCLK_VOP_DCLK_SEL_SHIFT |
720 DCLK_VOP_PLL_SEL_VPLL << DCLK_VOP_PLL_SEL_SHIFT |
721 (1 - 1) << DCLK_VOP_DIV_CON_SHIFT);
726 static ulong rk3399_mmc_get_clk(struct rockchip_cru *cru, uint clk_id)
733 con = readl(&cru->clksel_con[15]);
734 /* dwmmc controller have internal div 2 */
739 con = readl(&cru->clksel_con[16]);
740 /* dwmmc controller have internal div 2 */
744 con = readl(&cru->clksel_con[22]);
751 div *= (con & CLK_EMMC_DIV_CON_MASK) >> CLK_EMMC_DIV_CON_SHIFT;
752 if ((con & CLK_EMMC_PLL_MASK) >> CLK_EMMC_PLL_SHIFT
753 == CLK_EMMC_PLL_SEL_24M)
754 return DIV_TO_RATE(OSC_HZ, div);
756 return DIV_TO_RATE(GPLL_HZ, div);
759 static void rk3399_dwmmc_set_clk(struct rockchip_cru *cru,
760 unsigned int con, ulong set_rate)
762 /* Select clk_sdmmc source from GPLL by default */
763 /* mmc clock defaulg div 2 internal, provide double in cru */
764 int src_clk_div = DIV_ROUND_UP(GPLL_HZ / 2, set_rate);
766 if (src_clk_div > 128) {
767 /* use 24MHz source for 400KHz clock */
768 src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, set_rate);
769 assert(src_clk_div - 1 < 128);
770 rk_clrsetreg(&cru->clksel_con[con],
771 CLK_EMMC_PLL_MASK | CLK_EMMC_DIV_CON_MASK,
772 CLK_EMMC_PLL_SEL_24M << CLK_EMMC_PLL_SHIFT |
773 (src_clk_div - 1) << CLK_EMMC_DIV_CON_SHIFT);
775 rk_clrsetreg(&cru->clksel_con[con],
776 CLK_EMMC_PLL_MASK | CLK_EMMC_DIV_CON_MASK,
777 CLK_EMMC_PLL_SEL_GPLL << CLK_EMMC_PLL_SHIFT |
778 (src_clk_div - 1) << CLK_EMMC_DIV_CON_SHIFT);
782 static ulong rk3399_mmc_set_clk(struct rockchip_cru *cru,
783 ulong clk_id, ulong set_rate)
788 rk3399_dwmmc_set_clk(cru, 15, set_rate);
792 rk3399_dwmmc_set_clk(cru, 16, set_rate);
795 int aclk_emmc = 198 * MHz;
796 /* Select aclk_emmc source from GPLL */
797 int src_clk_div = DIV_ROUND_UP(GPLL_HZ, aclk_emmc);
799 assert(src_clk_div - 1 < 32);
801 rk_clrsetreg(&cru->clksel_con[21],
802 ACLK_EMMC_PLL_SEL_MASK | ACLK_EMMC_DIV_CON_MASK,
803 ACLK_EMMC_PLL_SEL_GPLL << ACLK_EMMC_PLL_SEL_SHIFT |
804 (src_clk_div - 1) << ACLK_EMMC_DIV_CON_SHIFT);
806 /* Select clk_emmc source from GPLL too */
807 src_clk_div = DIV_ROUND_UP(GPLL_HZ, set_rate);
808 assert(src_clk_div - 1 < 128);
810 rk_clrsetreg(&cru->clksel_con[22],
811 CLK_EMMC_PLL_MASK | CLK_EMMC_DIV_CON_MASK,
812 CLK_EMMC_PLL_SEL_GPLL << CLK_EMMC_PLL_SHIFT |
813 (src_clk_div - 1) << CLK_EMMC_DIV_CON_SHIFT);
819 return rk3399_mmc_get_clk(cru, clk_id);
822 static ulong rk3399_gmac_set_clk(struct rockchip_cru *cru, ulong rate)
827 * The RGMII CLK can be derived either from an external "clkin"
828 * or can be generated from internally by a divider from SCLK_MAC.
830 if (readl(&cru->clksel_con[19]) & BIT(4)) {
831 /* An external clock will always generate the right rate... */
835 * No platform uses an internal clock to date.
836 * Implement this once it becomes necessary and print an error
837 * if someone tries to use it (while it remains unimplemented).
839 pr_err("%s: internal clock is UNIMPLEMENTED\n", __func__);
846 #define PMUSGRF_DDR_RGN_CON16 0xff330040
847 static ulong rk3399_ddr_set_clk(struct rockchip_cru *cru,
850 struct pll_div dpll_cfg;
852 /* IC ECO bug, need to set this register */
853 writel(0xc000c000, PMUSGRF_DDR_RGN_CON16);
855 /* clk_ddrc == DPLL = 24MHz / refdiv * fbdiv / postdiv1 / postdiv2 */
858 dpll_cfg = (struct pll_div)
859 {.refdiv = 2, .fbdiv = 75, .postdiv1 = 3, .postdiv2 = 6};
862 dpll_cfg = (struct pll_div)
863 {.refdiv = 1, .fbdiv = 50, .postdiv1 = 6, .postdiv2 = 1};
866 dpll_cfg = (struct pll_div)
867 {.refdiv = 2, .fbdiv = 100, .postdiv1 = 4, .postdiv2 = 1};
870 dpll_cfg = (struct pll_div)
871 {.refdiv = 1, .fbdiv = 50, .postdiv1 = 3, .postdiv2 = 1};
874 dpll_cfg = (struct pll_div)
875 {.refdiv = 2, .fbdiv = 111, .postdiv1 = 2, .postdiv2 = 1};
878 dpll_cfg = (struct pll_div)
879 {.refdiv = 1, .fbdiv = 100, .postdiv1 = 3, .postdiv2 = 1};
882 dpll_cfg = (struct pll_div)
883 {.refdiv = 1, .fbdiv = 116, .postdiv1 = 3, .postdiv2 = 1};
886 pr_err("Unsupported SDRAM frequency!,%ld\n", set_rate);
888 rkclk_set_pll(&cru->dpll_con[0], &dpll_cfg);
893 static ulong rk3399_alive_get_clk(struct rockchip_cru *cru)
897 val = readl(&cru->clksel_con[57]);
898 div = (val & PCLK_ALIVE_DIV_CON_MASK) >>
899 PCLK_ALIVE_DIV_CON_SHIFT;
901 return DIV_TO_RATE(GPLL_HZ, div);
904 static ulong rk3399_saradc_get_clk(struct rockchip_cru *cru)
908 val = readl(&cru->clksel_con[26]);
909 div = bitfield_extract(val, CLK_SARADC_DIV_CON_SHIFT,
910 CLK_SARADC_DIV_CON_WIDTH);
912 return DIV_TO_RATE(OSC_HZ, div);
915 static ulong rk3399_saradc_set_clk(struct rockchip_cru *cru, uint hz)
919 src_clk_div = DIV_ROUND_UP(OSC_HZ, hz) - 1;
920 assert(src_clk_div < 128);
922 rk_clrsetreg(&cru->clksel_con[26],
923 CLK_SARADC_DIV_CON_MASK,
924 src_clk_div << CLK_SARADC_DIV_CON_SHIFT);
926 return rk3399_saradc_get_clk(cru);
929 static ulong rk3399_clk_get_rate(struct clk *clk)
931 struct rk3399_clk_priv *priv = dev_get_priv(clk->dev);
942 rate = rk3399_mmc_get_clk(priv->cru, clk->id);
950 rate = rk3399_i2c_get_clk(priv->cru, clk->id);
952 case SCLK_SPI0...SCLK_SPI5:
953 rate = rk3399_spi_get_clk(priv->cru, clk->id);
965 case PCLK_EFUSE1024NS:
968 rate = rk3399_saradc_get_clk(priv->cru);
977 rate = rk3399_alive_get_clk(priv->cru);
980 log_debug("Unknown clock %lu\n", clk->id);
987 static ulong rk3399_clk_set_rate(struct clk *clk, ulong rate)
989 struct rk3399_clk_priv *priv = dev_get_priv(clk->dev);
1018 ret = rk3399_mmc_set_clk(priv->cru, clk->id, rate);
1021 ret = rk3399_gmac_set_clk(priv->cru, rate);
1029 ret = rk3399_i2c_set_clk(priv->cru, clk->id, rate);
1031 case SCLK_SPI0...SCLK_SPI5:
1032 ret = rk3399_spi_set_clk(priv->cru, clk->id, rate);
1034 case PCLK_HDMI_CTRL:
1036 /* the PCLK gates for video are enabled by default */
1040 ret = rk3399_vop_set_clk(priv->cru, clk->id, rate);
1045 case SCLK_UPHY0_TCPDCORE:
1046 case SCLK_UPHY1_TCPDCORE:
1048 * assigned-clocks handling won't require for vopl, so
1049 * return 0 to satisfy clk_set_defaults during device probe.
1053 ret = rk3399_ddr_set_clk(priv->cru, rate);
1055 case PCLK_EFUSE1024NS:
1058 ret = rk3399_saradc_set_clk(priv->cru, rate);
1066 log_debug("Unknown clock %lu\n", clk->id);
1073 static int __maybe_unused rk3399_gmac_set_parent(struct clk *clk,
1076 struct rk3399_clk_priv *priv = dev_get_priv(clk->dev);
1077 const char *clock_output_name;
1081 * If the requested parent is in the same clock-controller and
1082 * the id is SCLK_MAC ("clk_gmac"), switch to the internal clock.
1084 if (parent->dev == clk->dev && parent->id == SCLK_MAC) {
1085 debug("%s: switching RGMII to SCLK_MAC\n", __func__);
1086 rk_clrreg(&priv->cru->clksel_con[19], BIT(4));
1091 * Otherwise, we need to check the clock-output-names of the
1092 * requested parent to see if the requested id is "clkin_gmac".
1094 ret = dev_read_string_index(parent->dev, "clock-output-names",
1095 parent->id, &clock_output_name);
1099 /* If this is "clkin_gmac", switch to the external clock input */
1100 if (!strcmp(clock_output_name, "clkin_gmac")) {
1101 debug("%s: switching RGMII to CLKIN\n", __func__);
1102 rk_setreg(&priv->cru->clksel_con[19], BIT(4));
1109 static int __maybe_unused rk3399_clk_set_parent(struct clk *clk,
1114 return rk3399_gmac_set_parent(clk, parent);
1117 debug("%s: unsupported clk %ld\n", __func__, clk->id);
1121 static int rk3399_clk_enable(struct clk *clk)
1123 struct rk3399_clk_priv *priv = dev_get_priv(clk->dev);
1127 rk_clrreg(&priv->cru->clkgate_con[5], BIT(5));
1130 rk_clrreg(&priv->cru->clkgate_con[5], BIT(8));
1133 rk_clrreg(&priv->cru->clkgate_con[5], BIT(9));
1136 rk_clrreg(&priv->cru->clkgate_con[5], BIT(7));
1138 case SCLK_MACREF_OUT:
1139 rk_clrreg(&priv->cru->clkgate_con[5], BIT(6));
1141 case SCLK_USB2PHY0_REF:
1142 rk_clrreg(&priv->cru->clkgate_con[6], BIT(5));
1144 case SCLK_USB2PHY1_REF:
1145 rk_clrreg(&priv->cru->clkgate_con[6], BIT(6));
1148 rk_clrreg(&priv->cru->clkgate_con[32], BIT(0));
1151 rk_clrreg(&priv->cru->clkgate_con[32], BIT(2));
1153 case SCLK_USB3OTG0_REF:
1154 rk_clrreg(&priv->cru->clkgate_con[12], BIT(1));
1156 case SCLK_USB3OTG1_REF:
1157 rk_clrreg(&priv->cru->clkgate_con[12], BIT(2));
1159 case SCLK_USB3OTG0_SUSPEND:
1160 rk_clrreg(&priv->cru->clkgate_con[12], BIT(3));
1162 case SCLK_USB3OTG1_SUSPEND:
1163 rk_clrreg(&priv->cru->clkgate_con[12], BIT(4));
1166 rk_clrreg(&priv->cru->clkgate_con[30], BIT(1));
1169 rk_clrreg(&priv->cru->clkgate_con[30], BIT(2));
1171 case ACLK_USB3_RKSOC_AXI_PERF:
1172 rk_clrreg(&priv->cru->clkgate_con[30], BIT(3));
1175 rk_clrreg(&priv->cru->clkgate_con[12], BIT(0));
1178 rk_clrreg(&priv->cru->clkgate_con[30], BIT(4));
1181 rk_clrreg(&priv->cru->clksel_con[20], BIT(5));
1183 case HCLK_HOST0_ARB:
1184 rk_clrreg(&priv->cru->clksel_con[20], BIT(6));
1187 rk_clrreg(&priv->cru->clksel_con[20], BIT(7));
1189 case HCLK_HOST1_ARB:
1190 rk_clrreg(&priv->cru->clksel_con[20], BIT(8));
1192 case SCLK_UPHY0_TCPDPHY_REF:
1193 rk_clrreg(&priv->cru->clkgate_con[13], BIT(4));
1195 case SCLK_UPHY0_TCPDCORE:
1196 rk_clrreg(&priv->cru->clkgate_con[13], BIT(5));
1198 case SCLK_UPHY1_TCPDPHY_REF:
1199 rk_clrreg(&priv->cru->clkgate_con[13], BIT(6));
1201 case SCLK_UPHY1_TCPDCORE:
1202 rk_clrreg(&priv->cru->clkgate_con[13], BIT(7));
1204 case SCLK_PCIEPHY_REF:
1205 rk_clrreg(&priv->cru->clksel_con[18], BIT(10));
1208 debug("%s: unsupported clk %ld\n", __func__, clk->id);
1215 static int rk3399_clk_disable(struct clk *clk)
1217 struct rk3399_clk_priv *priv = dev_get_priv(clk->dev);
1221 rk_setreg(&priv->cru->clkgate_con[5], BIT(5));
1224 rk_setreg(&priv->cru->clkgate_con[5], BIT(8));
1227 rk_setreg(&priv->cru->clkgate_con[5], BIT(9));
1230 rk_setreg(&priv->cru->clkgate_con[5], BIT(7));
1232 case SCLK_MACREF_OUT:
1233 rk_setreg(&priv->cru->clkgate_con[5], BIT(6));
1235 case SCLK_USB2PHY0_REF:
1236 rk_setreg(&priv->cru->clkgate_con[6], BIT(5));
1238 case SCLK_USB2PHY1_REF:
1239 rk_setreg(&priv->cru->clkgate_con[6], BIT(6));
1242 rk_setreg(&priv->cru->clkgate_con[32], BIT(0));
1245 rk_setreg(&priv->cru->clkgate_con[32], BIT(2));
1247 case SCLK_USB3OTG0_REF:
1248 rk_setreg(&priv->cru->clkgate_con[12], BIT(1));
1250 case SCLK_USB3OTG1_REF:
1251 rk_setreg(&priv->cru->clkgate_con[12], BIT(2));
1253 case SCLK_USB3OTG0_SUSPEND:
1254 rk_setreg(&priv->cru->clkgate_con[12], BIT(3));
1256 case SCLK_USB3OTG1_SUSPEND:
1257 rk_setreg(&priv->cru->clkgate_con[12], BIT(4));
1260 rk_setreg(&priv->cru->clkgate_con[30], BIT(1));
1263 rk_setreg(&priv->cru->clkgate_con[30], BIT(2));
1265 case ACLK_USB3_RKSOC_AXI_PERF:
1266 rk_setreg(&priv->cru->clkgate_con[30], BIT(3));
1269 rk_setreg(&priv->cru->clkgate_con[12], BIT(0));
1272 rk_setreg(&priv->cru->clkgate_con[30], BIT(4));
1275 rk_setreg(&priv->cru->clksel_con[20], BIT(5));
1277 case HCLK_HOST0_ARB:
1278 rk_setreg(&priv->cru->clksel_con[20], BIT(6));
1281 rk_setreg(&priv->cru->clksel_con[20], BIT(7));
1283 case HCLK_HOST1_ARB:
1284 rk_setreg(&priv->cru->clksel_con[20], BIT(8));
1286 case SCLK_UPHY0_TCPDPHY_REF:
1287 rk_setreg(&priv->cru->clkgate_con[13], BIT(4));
1289 case SCLK_UPHY0_TCPDCORE:
1290 rk_setreg(&priv->cru->clkgate_con[13], BIT(5));
1292 case SCLK_UPHY1_TCPDPHY_REF:
1293 rk_setreg(&priv->cru->clkgate_con[13], BIT(6));
1295 case SCLK_UPHY1_TCPDCORE:
1296 rk_setreg(&priv->cru->clkgate_con[13], BIT(7));
1298 case SCLK_PCIEPHY_REF:
1299 rk_clrreg(&priv->cru->clksel_con[18], BIT(10));
1302 debug("%s: unsupported clk %ld\n", __func__, clk->id);
1309 static struct clk_ops rk3399_clk_ops = {
1310 .get_rate = rk3399_clk_get_rate,
1311 .set_rate = rk3399_clk_set_rate,
1312 #if CONFIG_IS_ENABLED(OF_REAL)
1313 .set_parent = rk3399_clk_set_parent,
1315 .enable = rk3399_clk_enable,
1316 .disable = rk3399_clk_disable,
1319 static void rkclk_init(struct rockchip_cru *cru)
1325 rk3399_configure_cpu_l(cru, APLL_L_600_MHZ);
1326 rk3399_configure_cpu_b(cru, APLL_B_600_MHZ);
1328 * some cru registers changed by bootrom, we'd better reset them to
1329 * reset/default values described in TRM to avoid confusion in kernel.
1330 * Please consider these three lines as a fix of bootrom bug.
1332 rk_clrsetreg(&cru->clksel_con[12], 0xffff, 0x4101);
1333 rk_clrsetreg(&cru->clksel_con[19], 0xffff, 0x033f);
1334 rk_clrsetreg(&cru->clksel_con[56], 0x0003, 0x0003);
1336 /* configure gpll cpll */
1337 rkclk_set_pll(&cru->gpll_con[0], &gpll_init_cfg);
1338 rkclk_set_pll(&cru->cpll_con[0], &cpll_init_cfg);
1340 /* configure perihp aclk, hclk, pclk */
1341 aclk_div = GPLL_HZ / PERIHP_ACLK_HZ - 1;
1342 assert((aclk_div + 1) * PERIHP_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f);
1344 hclk_div = PERIHP_ACLK_HZ / PERIHP_HCLK_HZ - 1;
1345 assert((hclk_div + 1) * PERIHP_HCLK_HZ ==
1346 PERIHP_ACLK_HZ && (hclk_div < 0x4));
1348 pclk_div = PERIHP_ACLK_HZ / PERIHP_PCLK_HZ - 1;
1349 assert((pclk_div + 1) * PERIHP_PCLK_HZ ==
1350 PERIHP_ACLK_HZ && (pclk_div < 0x7));
1352 rk_clrsetreg(&cru->clksel_con[14],
1353 PCLK_PERIHP_DIV_CON_MASK | HCLK_PERIHP_DIV_CON_MASK |
1354 ACLK_PERIHP_PLL_SEL_MASK | ACLK_PERIHP_DIV_CON_MASK,
1355 pclk_div << PCLK_PERIHP_DIV_CON_SHIFT |
1356 hclk_div << HCLK_PERIHP_DIV_CON_SHIFT |
1357 ACLK_PERIHP_PLL_SEL_GPLL << ACLK_PERIHP_PLL_SEL_SHIFT |
1358 aclk_div << ACLK_PERIHP_DIV_CON_SHIFT);
1360 /* configure perilp0 aclk, hclk, pclk */
1361 aclk_div = GPLL_HZ / PERILP0_ACLK_HZ - 1;
1362 assert((aclk_div + 1) * PERILP0_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f);
1364 hclk_div = PERILP0_ACLK_HZ / PERILP0_HCLK_HZ - 1;
1365 assert((hclk_div + 1) * PERILP0_HCLK_HZ ==
1366 PERILP0_ACLK_HZ && (hclk_div < 0x4));
1368 pclk_div = PERILP0_ACLK_HZ / PERILP0_PCLK_HZ - 1;
1369 assert((pclk_div + 1) * PERILP0_PCLK_HZ ==
1370 PERILP0_ACLK_HZ && (pclk_div < 0x7));
1372 rk_clrsetreg(&cru->clksel_con[23],
1373 PCLK_PERILP0_DIV_CON_MASK | HCLK_PERILP0_DIV_CON_MASK |
1374 ACLK_PERILP0_PLL_SEL_MASK | ACLK_PERILP0_DIV_CON_MASK,
1375 pclk_div << PCLK_PERILP0_DIV_CON_SHIFT |
1376 hclk_div << HCLK_PERILP0_DIV_CON_SHIFT |
1377 ACLK_PERILP0_PLL_SEL_GPLL << ACLK_PERILP0_PLL_SEL_SHIFT |
1378 aclk_div << ACLK_PERILP0_DIV_CON_SHIFT);
1380 /* perilp1 hclk select gpll as source */
1381 hclk_div = GPLL_HZ / PERILP1_HCLK_HZ - 1;
1382 assert((hclk_div + 1) * PERILP1_HCLK_HZ ==
1383 GPLL_HZ && (hclk_div < 0x1f));
1385 pclk_div = PERILP1_HCLK_HZ / PERILP1_HCLK_HZ - 1;
1386 assert((pclk_div + 1) * PERILP1_HCLK_HZ ==
1387 PERILP1_HCLK_HZ && (hclk_div < 0x7));
1389 rk_clrsetreg(&cru->clksel_con[25],
1390 PCLK_PERILP1_DIV_CON_MASK | HCLK_PERILP1_DIV_CON_MASK |
1391 HCLK_PERILP1_PLL_SEL_MASK,
1392 pclk_div << PCLK_PERILP1_DIV_CON_SHIFT |
1393 hclk_div << HCLK_PERILP1_DIV_CON_SHIFT |
1394 HCLK_PERILP1_PLL_SEL_GPLL << HCLK_PERILP1_PLL_SEL_SHIFT);
1397 static int rk3399_clk_probe(struct udevice *dev)
1399 struct rk3399_clk_priv *priv = dev_get_priv(dev);
1400 bool init_clocks = false;
1402 #if CONFIG_IS_ENABLED(OF_PLATDATA)
1403 struct rk3399_clk_plat *plat = dev_get_plat(dev);
1405 priv->cru = map_sysmem(plat->dtd.reg[0], plat->dtd.reg[1]);
1408 #if defined(CONFIG_SPL_BUILD)
1410 #elif CONFIG_IS_ENABLED(HANDOFF)
1411 if (!(gd->flags & GD_FLG_RELOC)) {
1412 if (!(gd->spl_handoff))
1418 rkclk_init(priv->cru);
1423 static int rk3399_clk_of_to_plat(struct udevice *dev)
1425 if (CONFIG_IS_ENABLED(OF_REAL)) {
1426 struct rk3399_clk_priv *priv = dev_get_priv(dev);
1428 priv->cru = dev_read_addr_ptr(dev);
1434 static int rk3399_clk_bind(struct udevice *dev)
1437 struct udevice *sys_child;
1438 struct sysreset_reg *priv;
1440 /* The reset driver does not have a device node, so bind it here */
1441 ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset",
1444 debug("Warning: No sysreset driver: ret=%d\n", ret);
1446 priv = malloc(sizeof(struct sysreset_reg));
1447 priv->glb_srst_fst_value = offsetof(struct rockchip_cru,
1448 glb_srst_fst_value);
1449 priv->glb_srst_snd_value = offsetof(struct rockchip_cru,
1450 glb_srst_snd_value);
1451 dev_set_priv(sys_child, priv);
1454 #if CONFIG_IS_ENABLED(RESET_ROCKCHIP)
1455 ret = offsetof(struct rockchip_cru, softrst_con[0]);
1456 ret = rockchip_reset_bind(dev, ret, 21);
1458 debug("Warning: software reset driver bind failed\n");
1464 static const struct udevice_id rk3399_clk_ids[] = {
1465 { .compatible = "rockchip,rk3399-cru" },
1469 U_BOOT_DRIVER(clk_rk3399) = {
1470 .name = "rockchip_rk3399_cru",
1472 .of_match = rk3399_clk_ids,
1473 .priv_auto = sizeof(struct rk3399_clk_priv),
1474 .of_to_plat = rk3399_clk_of_to_plat,
1475 .ops = &rk3399_clk_ops,
1476 .bind = rk3399_clk_bind,
1477 .probe = rk3399_clk_probe,
1478 #if CONFIG_IS_ENABLED(OF_PLATDATA)
1479 .plat_auto = sizeof(struct rk3399_clk_plat),
1483 static ulong rk3399_i2c_get_pmuclk(struct rk3399_pmucru *pmucru, ulong clk_id)
1489 con = readl(&pmucru->pmucru_clksel[2]);
1490 div = I2C_CLK_DIV_VALUE(con, 0);
1493 con = readl(&pmucru->pmucru_clksel[3]);
1494 div = I2C_CLK_DIV_VALUE(con, 4);
1497 con = readl(&pmucru->pmucru_clksel[2]);
1498 div = I2C_CLK_DIV_VALUE(con, 8);
1501 printf("do not support this i2c bus\n");
1505 return DIV_TO_RATE(PPLL_HZ, div);
1508 static ulong rk3399_i2c_set_pmuclk(struct rk3399_pmucru *pmucru, ulong clk_id,
1513 src_clk_div = PPLL_HZ / hz;
1514 assert(src_clk_div - 1 < 127);
1518 rk_clrsetreg(&pmucru->pmucru_clksel[2], I2C_PMUCLK_REG_MASK(0),
1519 I2C_PMUCLK_REG_VALUE(0, src_clk_div));
1522 rk_clrsetreg(&pmucru->pmucru_clksel[3], I2C_PMUCLK_REG_MASK(4),
1523 I2C_PMUCLK_REG_VALUE(4, src_clk_div));
1526 rk_clrsetreg(&pmucru->pmucru_clksel[2], I2C_PMUCLK_REG_MASK(8),
1527 I2C_PMUCLK_REG_VALUE(8, src_clk_div));
1530 printf("do not support this i2c bus\n");
1534 return DIV_TO_RATE(PPLL_HZ, src_clk_div);
1537 static ulong rk3399_pwm_get_clk(struct rk3399_pmucru *pmucru)
1541 /* PWM closk rate is same as pclk_pmu */
1542 con = readl(&pmucru->pmucru_clksel[0]);
1543 div = con & PMU_PCLK_DIV_CON_MASK;
1545 return DIV_TO_RATE(PPLL_HZ, div);
1548 static ulong rk3399_pmuclk_get_rate(struct clk *clk)
1550 struct rk3399_pmuclk_priv *priv = dev_get_priv(clk->dev);
1556 case PCLK_RKPWM_PMU:
1557 case PCLK_WDT_M0_PMU:
1558 rate = rk3399_pwm_get_clk(priv->pmucru);
1563 rate = rk3399_i2c_get_pmuclk(priv->pmucru, clk->id);
1572 static ulong rk3399_pmuclk_set_rate(struct clk *clk, ulong rate)
1574 struct rk3399_pmuclk_priv *priv = dev_get_priv(clk->dev);
1580 * This has already been set up and we don't want/need
1581 * to change it here. Accept the request though, as the
1582 * device-tree has this in an 'assigned-clocks' list.
1588 ret = rk3399_i2c_set_pmuclk(priv->pmucru, clk->id, rate);
1597 static struct clk_ops rk3399_pmuclk_ops = {
1598 .get_rate = rk3399_pmuclk_get_rate,
1599 .set_rate = rk3399_pmuclk_set_rate,
1602 #ifndef CONFIG_SPL_BUILD
1603 static void pmuclk_init(struct rk3399_pmucru *pmucru)
1607 /* configure pmu pll(ppll) */
1608 rkclk_set_pll(&pmucru->ppll_con[0], &ppll_init_cfg);
1610 /* configure pmu pclk */
1611 pclk_div = PPLL_HZ / PMU_PCLK_HZ - 1;
1612 rk_clrsetreg(&pmucru->pmucru_clksel[0],
1613 PMU_PCLK_DIV_CON_MASK,
1614 pclk_div << PMU_PCLK_DIV_CON_SHIFT);
1618 static int rk3399_pmuclk_probe(struct udevice *dev)
1620 #if CONFIG_IS_ENABLED(OF_PLATDATA) || !defined(CONFIG_SPL_BUILD)
1621 struct rk3399_pmuclk_priv *priv = dev_get_priv(dev);
1624 #if CONFIG_IS_ENABLED(OF_PLATDATA)
1625 struct rk3399_pmuclk_plat *plat = dev_get_plat(dev);
1627 priv->pmucru = map_sysmem(plat->dtd.reg[0], plat->dtd.reg[1]);
1630 #ifndef CONFIG_SPL_BUILD
1631 pmuclk_init(priv->pmucru);
1636 static int rk3399_pmuclk_of_to_plat(struct udevice *dev)
1638 if (CONFIG_IS_ENABLED(OF_REAL)) {
1639 struct rk3399_pmuclk_priv *priv = dev_get_priv(dev);
1641 priv->pmucru = dev_read_addr_ptr(dev);
1647 static int rk3399_pmuclk_bind(struct udevice *dev)
1649 #if CONFIG_IS_ENABLED(RESET_ROCKCHIP)
1652 ret = offsetof(struct rk3399_pmucru, pmucru_softrst_con[0]);
1653 ret = rockchip_reset_bind(dev, ret, 2);
1655 debug("Warning: software reset driver bind failed\n");
1660 static const struct udevice_id rk3399_pmuclk_ids[] = {
1661 { .compatible = "rockchip,rk3399-pmucru" },
1665 U_BOOT_DRIVER(rockchip_rk3399_pmuclk) = {
1666 .name = "rockchip_rk3399_pmucru",
1668 .of_match = rk3399_pmuclk_ids,
1669 .priv_auto = sizeof(struct rk3399_pmuclk_priv),
1670 .of_to_plat = rk3399_pmuclk_of_to_plat,
1671 .ops = &rk3399_pmuclk_ops,
1672 .probe = rk3399_pmuclk_probe,
1673 .bind = rk3399_pmuclk_bind,
1674 #if CONFIG_IS_ENABLED(OF_PLATDATA)
1675 .plat_auto = sizeof(struct rk3399_pmuclk_plat),