cpu/omap3/sys_info.c

   1 /*
   2  * See file CREDITS for list of people who contributed to this
   3  * project.
   4  *
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License as
   7  * published by the Free Software Foundation; either version 2 of
   8  * the License, or (at your option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  18  * MA 02111-1307 USA
  19  */
  20
  21 #include <common.h>
  22 #include <asm/io.h>
  23 #include <asm/arch/bits.h>
  24 #include <asm/arch/clocks.h>
  25 #include <asm/arch/sys_proto.h>
  26 #include <asm/arch/sys_info.h>
  27
  28 static char *rev_s[CPU_3XX_MAX_REV] = {
  29                                 "1.0",
  30                                 "2.0",
  31                                 "2.1",
  32                                 "3.0",
  33                                 "3.1",
  34                                 "UNKNOWN",
  35                                 "UNKNOWN",
  36                                 "3.1.2"};
  37
  38 /*
  39  * sr32: clear & set a value in a bit range for a 32 bit address
  40  */
  41 void sr32(u32 addr, u32 start_bit, u32 num_bits, u32 value)
  42 {
  43         u32 tmp, msk = 0;
  44         msk = 1 << num_bits;
  45         --msk;
  46         tmp = __raw_readl(addr) & ~(msk << start_bit);
  47         tmp |= value << start_bit;
  48         __raw_writel(tmp, addr);
  49 }
  50
  51 /*
  52  * wait_on_value(): common routine to allow waiting for changes in
  53  * volatile regs.
  54  */
  55 u32 wait_on_value(u32 read_bit_mask, u32 match_value, u32 read_addr, u32 bound)
  56 {
  57         u32 i = 0, val;
  58         do {
  59                 ++i;
  60                 val = __raw_readl(read_addr) & read_bit_mask;
  61                 if (val == match_value)
  62                         return 1;
  63                 if (i == bound)
  64                         return 0;
  65         } while (1);
  66 }
  67
  68 /*
  69  *  get_device_type(): tell if GP/HS/EMU/TST
  70  */
  71 u32 get_device_type(void)
  72 {
  73         int mode;
  74         mode = __raw_readl(CONTROL_STATUS) & (DEVICE_MASK);
  75         return mode >>= 8;
  76 }
  77
  78 /*
  79  *  get_cpu_type(): extract cpu info
  80  */
  81 u32 get_cpu_type(void)
  82 {
  83         return __raw_readl(CONTROL_OMAP_STATUS);
  84 }
  85
  86 /*
  87  * get_cpu_id(): extract cpu id
  88  * returns 0 for ES1.0, cpuid otherwise
  89  */
  90 u32 get_cpu_id(void)
  91 {
  92         u32 cpuid = 0;
  93
  94         /*
  95          * On ES1.0 the IDCODE register is not exposed on L4
  96          * so using CPU ID to differentiate between ES1.0 and > ES1.0.
  97          */
  98         __asm__ __volatile__("mrc p15, 0, %0, c0, c0, 0":"=r"(cpuid));
  99         if ((cpuid & 0xf) == 0x0) {
 100                 return 0;
 101         } else {
 102                 /* Decode the IDs on > ES1.0 */
 103                 cpuid = __raw_readl(CONTROL_IDCODE);
 104         }
 105
 106         return cpuid;
 107 }
 108
 109 /*
 110  * get_cpu_family(void): extract cpu info
 111  */
 112 u32 get_cpu_family(void)
 113 {
 114         u16 hawkeye;
 115         u32 cpu_family;
 116         u32 cpuid = get_cpu_id();
 117
 118         if (cpuid == 0)
 119                 return CPU_OMAP34XX;
 120
 121         hawkeye = (cpuid >> HAWKEYE_SHIFT) & 0xffff;
 122         switch (hawkeye) {
 123         case HAWKEYE_OMAP34XX:
 124                 cpu_family = CPU_OMAP34XX;
 125                 break;
 126         case HAWKEYE_AM35XX:
 127                 cpu_family = CPU_AM35XX;
 128                 break;
 129         case HAWKEYE_OMAP36XX:
 130                 cpu_family = CPU_OMAP36XX;
 131                 break;
 132         default:
 133                 cpu_family = CPU_OMAP34XX;
 134         }
 135
 136         return cpu_family;
 137 }
 138
 139 /*
 140  * get_cpu_rev(void): extract version info
 141  */
 142 u32 get_cpu_rev(void)
 143 {
 144         u32 cpuid = get_cpu_id();
 145
 146         if (cpuid == 0)
 147                 return CPU_3XX_ES10;
 148         else
 149                 return (cpuid >> CPU_3XX_ID_SHIFT) & 0xf;
 150 }
 151
 152 /*
 153  * print_cpuinfo(void): print CPU information
 154  */
 155 int print_cpuinfo(void)
 156 {
 157         char *cpu_family_s, *cpu_s, *sec_s;
 158
 159         switch (get_cpu_family()) {
 160         case CPU_OMAP34XX:
 161                 cpu_family_s = "OMAP";
 162                 switch (get_cpu_type()) {
 163                 case OMAP3503:
 164                         cpu_s = "3503";
 165                         break;
 166                 case OMAP3515:
 167                         cpu_s = "3515";
 168                         break;
 169                 case OMAP3525:
 170                         cpu_s = "3525";
 171                         break;
 172                 case OMAP3530:
 173                         cpu_s = "3530";
 174                         break;
 175                 default:
 176                         cpu_s = "35XX";
 177                         break;
 178                 }
 179                 break;
 180         case CPU_AM35XX:
 181                 cpu_family_s = "AM";
 182                 switch (get_cpu_type()) {
 183                 case AM3505:
 184                         cpu_s = "3505";
 185                         break;
 186                 case AM3517:
 187                         cpu_s = "3517";
 188                         break;
 189                 default:
 190                         cpu_s = "35XX";
 191                         break;
 192                 }
 193                 break;
 194         case CPU_OMAP36XX:
 195                 cpu_family_s = "OMAP";
 196                 switch (get_cpu_type()) {
 197                 case OMAP3730:
 198                         cpu_s = "3630/3730";
 199                         break;
 200                 default:
 201                         cpu_s = "36XX/37XX";
 202                         break;
 203                 }
 204                 break;
 205         default:
 206                 cpu_family_s = "OMAP";
 207                 cpu_s = "35XX";
 208         }
 209
 210         switch (get_device_type()) {
 211         case TST_DEVICE:
 212                 sec_s = "TST";
 213                 break;
 214         case EMU_DEVICE:
 215                 sec_s = "EMU";
 216                 break;
 217         case HS_DEVICE:
 218                 sec_s = "HS";
 219                 break;
 220         case GP_DEVICE:
 221                 sec_s = "GP";
 222                 break;
 223         default:
 224                 sec_s = "?";
 225         }
 226
 227         printf("%s%s-%s ES%s\n",
 228                         cpu_family_s, cpu_s, sec_s, rev_s[get_cpu_rev()]);
 229
 230         return 0;
 231 }
 232
 233 /*
 234  * get_sysboot_value(void): return SYS_BOOT[4:0]
 235  */
 236 u32 get_sysboot_value(void)
 237 {
 238         int mode;
 239         mode = __raw_readl(CONTROL_STATUS) & (SYSBOOT_MASK);
 240         return mode;
 241 }
 242
 243 /*
 244  * get_sys_clkin_sel(): returns the sys_clkin_sel field value based on
 245  *   input oscillator clock frequency.
 246  */
 247 void get_sys_clkin_sel(u32 osc_clk, u32 *sys_clkin_sel)
 248 {
 249         if (osc_clk == S38_4M)
 250                 *sys_clkin_sel = 4;
 251         else if (osc_clk == S26M)
 252                 *sys_clkin_sel = 3;
 253         else if (osc_clk == S19_2M)
 254                 *sys_clkin_sel = 2;
 255         else if (osc_clk == S13M)
 256                 *sys_clkin_sel = 1;
 257         else if (osc_clk == S12M)
 258                 *sys_clkin_sel = 0;
 259 }
 260
 261 /*
 262  * secure_unlock(void): setup security registers for access
 263  * (GP Device only)
 264  */
 265 void secure_unlock(void)
 266 {
 267         /* Permission values for registers -Full fledged permissions to all */
 268         #define UNLOCK_1 0xFFFFFFFF
 269         #define UNLOCK_2 0x00000000
 270         #define UNLOCK_3 0x0000FFFF
 271         /* Protection Module Register Target APE (PM_RT)*/
 272         __raw_writel(UNLOCK_1, RT_REQ_INFO_PERMISSION_1);
 273         __raw_writel(UNLOCK_1, RT_READ_PERMISSION_0);
 274         __raw_writel(UNLOCK_1, RT_WRITE_PERMISSION_0);
 275         __raw_writel(UNLOCK_2, RT_ADDR_MATCH_1);
 276
 277         __raw_writel(UNLOCK_3, GPMC_REQ_INFO_PERMISSION_0);
 278         __raw_writel(UNLOCK_3, GPMC_READ_PERMISSION_0);
 279         __raw_writel(UNLOCK_3, GPMC_WRITE_PERMISSION_0);
 280
 281         __raw_writel(UNLOCK_3, OCM_REQ_INFO_PERMISSION_0);
 282         __raw_writel(UNLOCK_3, OCM_READ_PERMISSION_0);
 283         __raw_writel(UNLOCK_3, OCM_WRITE_PERMISSION_0);
 284         __raw_writel(UNLOCK_2, OCM_ADDR_MATCH_2);
 285
 286         /* IVA Changes */
 287         __raw_writel(UNLOCK_3, IVA2_REQ_INFO_PERMISSION_0);
 288         __raw_writel(UNLOCK_3, IVA2_READ_PERMISSION_0);
 289         __raw_writel(UNLOCK_3, IVA2_WRITE_PERMISSION_0);
 290
 291         __raw_writel(UNLOCK_1, SMS_RG_ATT0); /* SDRC region 0 public */
 292 }
 293
 294 /*
 295  * try_unlock_memory(void): If chip is GP type, unlock the SRAM for
 296  *  general use.
 297  */
 298 void try_unlock_memory(void)
 299 {
 300         int mode;
 301
 302         /* if GP device unlock device SRAM for general use */
 303         /* secure code breaks for Secure/Emulation device - HS/E/T*/
 304         mode = get_device_type();
 305         if (mode == GP_DEVICE) {
 306                 secure_unlock();
 307         }
 308         return;
 309 }