3 * Texas Instruments, <www.ti.com>
4 * Jian Zhang <jzhang@ti.com>
5 * Richard Woodruff <r-woodruff2@ti.com>
8 * Steve Sakoman <steve@sakoman.com>
10 * See file CREDITS for list of people who contributed to this
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of
16 * the License, or (at your option) any later version.
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
34 #include <asm/arch/cpu.h>
35 #include <asm/arch/bits.h>
36 #include <asm/arch/gpio.h>
37 #include <asm/arch/mux.h>
38 #include <asm/arch/sys_proto.h>
39 #include <asm/arch/sys_info.h>
40 #include <asm/arch/clocks.h>
41 #include <asm/arch/mem.h>
44 #define CORE_DPLL_PARAM_M2 0x09
45 #define CORE_DPLL_PARAM_M 0x360
46 #define CORE_DPLL_PARAM_N 0xC
48 /* Used to index into DPLL parameter tables */
56 typedef struct dpll_param dpll_param;
58 /* Following functions are exported from lowlevel_init.S */
59 extern dpll_param *get_mpu_dpll_param();
60 extern dpll_param *get_iva_dpll_param();
61 extern dpll_param *get_core_dpll_param();
62 extern dpll_param *get_per_dpll_param();
64 #define __raw_readl(a) (*(volatile unsigned int *)(a))
65 #define __raw_writel(v, a) (*(volatile unsigned int *)(a) = (v))
66 #define __raw_readw(a) (*(volatile unsigned short *)(a))
67 #define __raw_writew(v, a) (*(volatile unsigned short *)(a) = (v))
69 /*******************************************************
71 * Description: spinning delay to use before udelay works
72 ******************************************************/
73 static inline void delay(unsigned long loops)
75 __asm__ volatile ("1:\n" "subs %0, %1, #1\n"
76 "bne 1b":"=r" (loops):"0"(loops));
79 void udelay (unsigned long usecs) {
83 /*****************************************
85 * Description: Early hardware init.
86 *****************************************/
92 /*************************************************************
93 * Routine: get_mem_type(void) - returns the kind of memory connected
94 * to GPMC that we are trying to boot form. Uses SYS BOOT settings.
95 *************************************************************/
96 u32 get_mem_type(void)
98 u32 mem_type = get_sysboot_value();
141 /******************************************
142 * cpu_is_3410(void) - returns true for 3410
143 ******************************************/
144 u32 cpu_is_3410(void)
147 if (get_cpu_rev() < CPU_3430_ES2) {
150 /* read scalability status and return 1 for 3410*/
151 status = __raw_readl(CONTROL_SCALABLE_OMAP_STATUS);
152 /* Check whether MPU frequency is set to 266 MHz which
153 * is nominal for 3410. If yes return true else false
155 if (((status >> 8) & 0x3) == 0x2)
162 /*****************************************************************
163 * Routine: get_board_revision
164 * Description: Returns the board revision
165 *****************************************************************/
166 int get_board_revision(void)
171 /* board revisions <= R2410 connect 4030 irq_1 to gpio112 */
172 /* these boards should return a revision number of 0 */
173 /* the code below forces a 4030 RTC irq to ensure that gpio112 is low */
175 i2c_write(0x4B, 0x29, 1, &data, 1);
177 i2c_write(0x4B, 0x2b, 1, &data, 1);
178 i2c_read(0x4B, 0x2a, 1, &data, 1);
180 if (!omap_request_gpio(112) &&
181 !omap_request_gpio(113) &&
182 !omap_request_gpio(115)) {
184 omap_set_gpio_direction(112, 1);
185 omap_set_gpio_direction(113, 1);
186 omap_set_gpio_direction(115, 1);
188 revision = omap_get_gpio_datain(115) << 2 |
189 omap_get_gpio_datain(113) << 1 |
190 omap_get_gpio_datain(112);
196 printf("Error: unable to acquire board revision GPIOs\n");
203 #ifdef CFG_3430SDRAM_DDR
204 /*********************************************************************
205 * config_3430sdram_ddr() - Init DDR on 3430SDP dev board.
206 *********************************************************************/
207 void config_3430sdram_ddr(void)
209 /* reset sdrc controller */
210 __raw_writel(SOFTRESET, SDRC_SYSCONFIG);
211 wait_on_value(BIT0, BIT0, SDRC_STATUS, 12000000);
212 __raw_writel(0, SDRC_SYSCONFIG);
214 /* setup sdrc to ball mux */
215 __raw_writel(SDP_SDRC_SHARING, SDRC_SHARING);
217 switch (get_board_revision()) {
218 case 0: /* Micron 1286MB/256MB, 1/2 banks of 128MB */
219 __raw_writel(0x1, SDRC_CS_CFG); /* 128MB/bank */
220 __raw_writel(SDP_SDRC_MDCFG_0_DDR, SDRC_MCFG_0);
221 __raw_writel(SDP_SDRC_MDCFG_0_DDR, SDRC_MCFG_1);
222 __raw_writel(MICRON_V_ACTIMA_165, SDRC_ACTIM_CTRLA_0);
223 __raw_writel(MICRON_V_ACTIMB_165, SDRC_ACTIM_CTRLB_0);
224 __raw_writel(MICRON_V_ACTIMA_165, SDRC_ACTIM_CTRLA_1);
225 __raw_writel(MICRON_V_ACTIMB_165, SDRC_ACTIM_CTRLB_1);
226 __raw_writel(SDP_3430_SDRC_RFR_CTRL_165MHz, SDRC_RFR_CTRL_0);
227 __raw_writel(SDP_3430_SDRC_RFR_CTRL_165MHz, SDRC_RFR_CTRL_1);
229 case 1: /* Micron 256MB/512MB, 1/2 banks of 256MB */
230 __raw_writel(0x2, SDRC_CS_CFG); /* 256MB/bank */
231 __raw_writel(SDP_SDRC_MDCFG_0_DDR_MICRON_XM, SDRC_MCFG_0);
232 __raw_writel(SDP_SDRC_MDCFG_0_DDR_MICRON_XM, SDRC_MCFG_1);
233 __raw_writel(MICRON_V_ACTIMA_165, SDRC_ACTIM_CTRLA_0);
234 __raw_writel(MICRON_V_ACTIMB_165, SDRC_ACTIM_CTRLB_0);
235 __raw_writel(MICRON_V_ACTIMA_165, SDRC_ACTIM_CTRLA_1);
236 __raw_writel(MICRON_V_ACTIMB_165, SDRC_ACTIM_CTRLB_1);
237 __raw_writel(SDP_3430_SDRC_RFR_CTRL_165MHz, SDRC_RFR_CTRL_0);
238 __raw_writel(SDP_3430_SDRC_RFR_CTRL_165MHz, SDRC_RFR_CTRL_1);
240 case 2: /* Hynix 256MB/512MB, 1/2 banks of 256MB */
241 __raw_writel(0x2, SDRC_CS_CFG); /* 256MB/bank */
242 __raw_writel(SDP_SDRC_MDCFG_0_DDR_HYNIX, SDRC_MCFG_0);
243 __raw_writel(SDP_SDRC_MDCFG_0_DDR_HYNIX, SDRC_MCFG_1);
244 __raw_writel(HYNIX_V_ACTIMA_165, SDRC_ACTIM_CTRLA_0);
245 __raw_writel(HYNIX_V_ACTIMB_165, SDRC_ACTIM_CTRLB_0);
246 __raw_writel(HYNIX_V_ACTIMA_165, SDRC_ACTIM_CTRLA_1);
247 __raw_writel(HYNIX_V_ACTIMB_165, SDRC_ACTIM_CTRLB_1);
248 __raw_writel(SDP_3430_SDRC_RFR_CTRL_165MHz, SDRC_RFR_CTRL_0);
249 __raw_writel(SDP_3430_SDRC_RFR_CTRL_165MHz, SDRC_RFR_CTRL_1);
252 __raw_writel(0x1, SDRC_CS_CFG); /* 128MB/bank */
253 __raw_writel(SDP_SDRC_MDCFG_0_DDR, SDRC_MCFG_0);
254 __raw_writel(SDP_SDRC_MDCFG_0_DDR, SDRC_MCFG_1);
255 __raw_writel(MICRON_V_ACTIMA_165, SDRC_ACTIM_CTRLA_0);
256 __raw_writel(MICRON_V_ACTIMB_165, SDRC_ACTIM_CTRLB_0);
257 __raw_writel(MICRON_V_ACTIMA_165, SDRC_ACTIM_CTRLA_1);
258 __raw_writel(MICRON_V_ACTIMB_165, SDRC_ACTIM_CTRLB_1);
259 __raw_writel(SDP_3430_SDRC_RFR_CTRL_165MHz, SDRC_RFR_CTRL_0);
260 __raw_writel(SDP_3430_SDRC_RFR_CTRL_165MHz, SDRC_RFR_CTRL_1);
263 __raw_writel(SDP_SDRC_POWER_POP, SDRC_POWER);
265 /* init sequence for mDDR/mSDR using manual commands (DDR is different) */
266 __raw_writel(CMD_NOP, SDRC_MANUAL_0);
267 __raw_writel(CMD_NOP, SDRC_MANUAL_1);
271 __raw_writel(CMD_PRECHARGE, SDRC_MANUAL_0);
272 __raw_writel(CMD_PRECHARGE, SDRC_MANUAL_1);
274 __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0);
275 __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_1);
277 __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0);
278 __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_1);
281 __raw_writel(SDP_SDRC_MR_0_DDR, SDRC_MR_0);
282 __raw_writel(SDP_SDRC_MR_0_DDR, SDRC_MR_1);
285 __raw_writel(SDP_SDRC_DLLAB_CTRL, SDRC_DLLA_CTRL);
286 delay(0x2000); /* give time to lock */
288 #endif /* CFG_3430SDRAM_DDR */
290 /*************************************************************
291 * get_sys_clk_speed - determine reference oscillator speed
292 * based on known 32kHz clock and gptimer.
293 *************************************************************/
294 u32 get_osc_clk_speed(void)
296 u32 start, cstart, cend, cdiff, cdiv, val;
298 val = __raw_readl(PRM_CLKSRC_CTRL);
300 if (val & SYSCLKDIV_2)
306 val = __raw_readl(CM_CLKSEL_WKUP) | BIT0;
307 __raw_writel(val, CM_CLKSEL_WKUP); /* select sys_clk for GPT1 */
309 /* Enable I and F Clocks for GPT1 */
310 val = __raw_readl(CM_ICLKEN_WKUP) | BIT0 | BIT2;
311 __raw_writel(val, CM_ICLKEN_WKUP);
312 val = __raw_readl(CM_FCLKEN_WKUP) | BIT0;
313 __raw_writel(val, CM_FCLKEN_WKUP);
315 __raw_writel(0, OMAP34XX_GPT1 + TLDR); /* start counting at 0 */
316 __raw_writel(GPT_EN, OMAP34XX_GPT1 + TCLR); /* enable clock */
317 /* enable 32kHz source */
318 /* enabled out of reset */
319 /* determine sys_clk via gauging */
321 start = 20 + __raw_readl(S32K_CR); /* start time in 20 cycles */
322 while (__raw_readl(S32K_CR) < start); /* dead loop till start time */
323 cstart = __raw_readl(OMAP34XX_GPT1 + TCRR); /* get start sys_clk count */
324 while (__raw_readl(S32K_CR) < (start + 20)); /* wait for 40 cycles */
325 cend = __raw_readl(OMAP34XX_GPT1 + TCRR); /* get end sys_clk count */
326 cdiff = cend - cstart; /* get elapsed ticks */
329 /* based on number of ticks assign speed */
332 else if (cdiff > 15200)
334 else if (cdiff > 13000)
336 else if (cdiff > 9000)
338 else if (cdiff > 7600)
344 /******************************************************************************
345 * prcm_init() - inits clocks for PRCM as defined in clocks.h
346 * -- called from SRAM, or Flash (using temp SRAM stack).
347 *****************************************************************************/
350 u32 osc_clk = 0, sys_clkin_sel;
351 dpll_param *dpll_param_p;
352 u32 clk_index, sil_index;
354 /* Gauge the input clock speed and find out the sys_clkin_sel
355 * value corresponding to the input clock.
357 osc_clk = get_osc_clk_speed();
358 get_sys_clkin_sel(osc_clk, &sys_clkin_sel);
360 sr32(PRM_CLKSEL, 0, 3, sys_clkin_sel); /* set input crystal speed */
362 /* If the input clock is greater than 19.2M always divide/2 */
363 if (sys_clkin_sel > 2) {
364 sr32(PRM_CLKSRC_CTRL, 6, 2, 2); /* input clock divider */
365 clk_index = sys_clkin_sel / 2;
367 sr32(PRM_CLKSRC_CTRL, 6, 2, 1); /* input clock divider */
368 clk_index = sys_clkin_sel;
371 sr32(PRM_CLKSRC_CTRL, 0, 2, 0);/* Bypass mode: T2 inputs a square clock */
373 /* The DPLL tables are defined according to sysclk value and
374 * silicon revision. The clk_index value will be used to get
375 * the values for that input sysclk from the DPLL param table
376 * and sil_index will get the values for that SysClk for the
377 * appropriate silicon rev.
379 sil_index = (get_cpu_rev() == CPU_3XX_ES10) ? 0 : 1;
381 /* Unlock MPU DPLL (slows things down, and needed later) */
382 sr32(CM_CLKEN_PLL_MPU, 0, 3, PLL_LOW_POWER_BYPASS);
383 wait_on_value(BIT0, 0, CM_IDLEST_PLL_MPU, LDELAY);
385 /* Getting the base address of Core DPLL param table */
386 dpll_param_p = (dpll_param *) get_core_dpll_param();
387 /* Moving it to the right sysclk and ES rev base */
388 dpll_param_p = dpll_param_p + 3 * clk_index + sil_index;
390 /* sr32(CM_CLKSEL2_EMU) set override to work when asleep */
391 sr32(CM_CLKEN_PLL, 0, 3, PLL_FAST_RELOCK_BYPASS);
392 wait_on_value(BIT0, 0, CM_IDLEST_CKGEN, LDELAY);
394 /* For 3430 ES1.0 Errata 1.50, default value directly doesnt
395 work. write another value and then default value. */
396 sr32(CM_CLKSEL1_EMU, 16, 5, CORE_M3X2 + 1); /* m3x2 */
397 sr32(CM_CLKSEL1_EMU, 16, 5, CORE_M3X2); /* m3x2 */
398 sr32(CM_CLKSEL1_PLL, 27, 2, dpll_param_p->m2); /* Set M2 */
399 sr32(CM_CLKSEL1_PLL, 16, 11, dpll_param_p->m); /* Set M */
400 sr32(CM_CLKSEL1_PLL, 8, 7, dpll_param_p->n); /* Set N */
401 sr32(CM_CLKSEL1_PLL, 6, 1, 0); /* 96M Src */
402 sr32(CM_CLKSEL_CORE, 8, 4, CORE_SSI_DIV); /* ssi */
403 sr32(CM_CLKSEL_CORE, 4, 2, CORE_FUSB_DIV); /* fsusb */
404 sr32(CM_CLKSEL_CORE, 2, 2, CORE_L4_DIV); /* l4 */
405 sr32(CM_CLKSEL_CORE, 0, 2, CORE_L3_DIV); /* l3 */
406 sr32(CM_CLKSEL_GFX, 0, 3, GFX_DIV); /* gfx */
407 sr32(CM_CLKSEL_WKUP, 1, 2, WKUP_RSM); /* reset mgr */
408 sr32(CM_CLKEN_PLL, 4, 4, dpll_param_p->fsel); /* FREQSEL */
409 sr32(CM_CLKEN_PLL, 0, 3, PLL_LOCK); /* lock mode */
410 wait_on_value(BIT0, 1, CM_IDLEST_CKGEN, LDELAY);
412 /* Getting the base address to PER DPLL param table */
413 dpll_param_p = (dpll_param *) get_per_dpll_param();
414 /* Moving it to the right sysclk base */
415 dpll_param_p = dpll_param_p + clk_index;
417 sr32(CM_CLKEN_PLL, 16, 3, PLL_STOP);
418 wait_on_value(BIT1, 0, CM_IDLEST_CKGEN, LDELAY);
419 sr32(CM_CLKSEL1_EMU, 24, 5, PER_M6X2); /* set M6 */
420 sr32(CM_CLKSEL_CAM, 0, 5, PER_M5X2); /* set M5 */
421 sr32(CM_CLKSEL_DSS, 0, 5, PER_M4X2); /* set M4 */
422 sr32(CM_CLKSEL_DSS, 8, 5, PER_M3X2); /* set M3 */
424 if (get_cpu_family() == CPU_OMAP36XX) {
425 sr32(CM_CLKSEL3_PLL, 0, 5, CORE_DPLL_PARAM_M2); /* set M2 */
426 sr32(CM_CLKSEL2_PLL, 8, 11, CORE_DPLL_PARAM_M); /* set m */
427 sr32(CM_CLKSEL2_PLL, 0, 7, CORE_DPLL_PARAM_N); /* set n */
429 sr32(CM_CLKSEL3_PLL, 0, 5, dpll_param_p->m2); /* set M2 */
430 sr32(CM_CLKSEL2_PLL, 8, 11, dpll_param_p->m); /* set m */
431 sr32(CM_CLKSEL2_PLL, 0, 7, dpll_param_p->n); /* set n */
434 sr32(CM_CLKEN_PLL, 20, 4, dpll_param_p->fsel); /* FREQSEL */
435 sr32(CM_CLKEN_PLL, 16, 3, PLL_LOCK); /* lock mode */
436 wait_on_value(BIT1, 2, CM_IDLEST_CKGEN, LDELAY);
438 /* Getting the base address to MPU DPLL param table */
439 dpll_param_p = (dpll_param *) get_mpu_dpll_param();
441 /* Moving it to the right sysclk and ES rev base */
442 dpll_param_p = dpll_param_p + 3 * clk_index + sil_index;
444 /* MPU DPLL (unlocked already) */
445 sr32(CM_CLKSEL2_PLL_MPU, 0, 5, dpll_param_p->m2); /* Set M2 */
446 sr32(CM_CLKSEL1_PLL_MPU, 8, 11, dpll_param_p->m); /* Set M */
447 sr32(CM_CLKSEL1_PLL_MPU, 0, 7, dpll_param_p->n); /* Set N */
448 sr32(CM_CLKEN_PLL_MPU, 4, 4, dpll_param_p->fsel); /* FREQSEL */
449 sr32(CM_CLKEN_PLL_MPU, 0, 3, PLL_LOCK); /* lock mode */
450 wait_on_value(BIT0, 1, CM_IDLEST_PLL_MPU, LDELAY);
452 /* Getting the base address to IVA DPLL param table */
453 dpll_param_p = (dpll_param *) get_iva_dpll_param();
454 /* Moving it to the right sysclk and ES rev base */
455 dpll_param_p = dpll_param_p + 3 * clk_index + sil_index;
456 /* IVA DPLL (set to 12*20=240MHz) */
457 sr32(CM_CLKEN_PLL_IVA2, 0, 3, PLL_STOP);
458 wait_on_value(BIT0, 0, CM_IDLEST_PLL_IVA2, LDELAY);
459 sr32(CM_CLKSEL2_PLL_IVA2, 0, 5, dpll_param_p->m2); /* set M2 */
460 sr32(CM_CLKSEL1_PLL_IVA2, 8, 11, dpll_param_p->m); /* set M */
461 sr32(CM_CLKSEL1_PLL_IVA2, 0, 7, dpll_param_p->n); /* set N */
462 sr32(CM_CLKEN_PLL_IVA2, 4, 4, dpll_param_p->fsel); /* FREQSEL */
463 sr32(CM_CLKEN_PLL_IVA2, 0, 3, PLL_LOCK); /* lock mode */
464 wait_on_value(BIT0, 1, CM_IDLEST_PLL_IVA2, LDELAY);
466 /* Set up GPTimers to sys_clk source only */
467 sr32(CM_CLKSEL_PER, 0, 8, 0xff);
468 sr32(CM_CLKSEL_WKUP, 0, 1, 1);
473 /*****************************************
474 * Routine: secure_unlock
475 * Description: Setup security registers for access
477 *****************************************/
478 void secure_unlock(void)
480 /* Permission values for registers -Full fledged permissions to all */
481 #define UNLOCK_1 0xFFFFFFFF
482 #define UNLOCK_2 0x00000000
483 #define UNLOCK_3 0x0000FFFF
484 /* Protection Module Register Target APE (PM_RT)*/
485 __raw_writel(UNLOCK_1, RT_REQ_INFO_PERMISSION_1);
486 __raw_writel(UNLOCK_1, RT_READ_PERMISSION_0);
487 __raw_writel(UNLOCK_1, RT_WRITE_PERMISSION_0);
488 __raw_writel(UNLOCK_2, RT_ADDR_MATCH_1);
490 __raw_writel(UNLOCK_3, GPMC_REQ_INFO_PERMISSION_0);
491 __raw_writel(UNLOCK_3, GPMC_READ_PERMISSION_0);
492 __raw_writel(UNLOCK_3, GPMC_WRITE_PERMISSION_0);
494 __raw_writel(UNLOCK_3, OCM_REQ_INFO_PERMISSION_0);
495 __raw_writel(UNLOCK_3, OCM_READ_PERMISSION_0);
496 __raw_writel(UNLOCK_3, OCM_WRITE_PERMISSION_0);
497 __raw_writel(UNLOCK_2, OCM_ADDR_MATCH_2);
500 __raw_writel(UNLOCK_3, IVA2_REQ_INFO_PERMISSION_0);
501 __raw_writel(UNLOCK_3, IVA2_READ_PERMISSION_0);
502 __raw_writel(UNLOCK_3, IVA2_WRITE_PERMISSION_0);
504 __raw_writel(UNLOCK_1, SMS_RG_ATT0); /* SDRC region 0 public */
507 /**********************************************************
508 * Routine: try_unlock_sram()
509 * Description: If chip is GP type, unlock the SRAM for
511 ***********************************************************/
512 void try_unlock_memory(void)
516 /* if GP device unlock device SRAM for general use */
517 /* secure code breaks for Secure/Emulation device - HS/E/T*/
518 mode = get_device_type();
519 if (mode == GP_DEVICE)
524 /**********************************************************
526 * Description: Does early system init of muxing and clocks.
527 * - Called at time when only stack is available.
528 **********************************************************/
533 #ifdef CONFIG_3430_AS_3410
534 /* setup the scalability control register for
535 * 3430 to work in 3410 mode
537 __raw_writel(0x5ABF, CONTROL_SCALABLE_OMAP_OCP);
544 config_3430sdram_ddr();
547 /*******************************************************
548 * Routine: misc_init_r
549 ********************************************************/
550 int misc_init_r(void)
553 printf("Board revision: %d\n", get_board_revision());
557 /******************************************************
558 * Routine: wait_for_command_complete
559 * Description: Wait for posting to finish on watchdog
560 ******************************************************/
561 void wait_for_command_complete(unsigned int wd_base)
565 pending = __raw_readl(wd_base + WWPS);
569 /****************************************
570 * Routine: watchdog_init
571 * Description: Shut down watch dogs
572 *****************************************/
573 void watchdog_init(void)
575 /* There are 3 watch dogs WD1=Secure, WD2=MPU, WD3=IVA. WD1 is
576 * either taken care of by ROM (HS/EMU) or not accessible (GP).
577 * We need to take care of WD2-MPU or take a PRCM reset. WD3
578 * should not be running and does not generate a PRCM reset.
580 sr32(CM_FCLKEN_WKUP, 5, 1, 1);
581 sr32(CM_ICLKEN_WKUP, 5, 1, 1);
582 wait_on_value(BIT5, 0x20, CM_IDLEST_WKUP, 5); /* some issue here */
584 __raw_writel(WD_UNLOCK1, WD2_BASE + WSPR);
585 wait_for_command_complete(WD2_BASE);
586 __raw_writel(WD_UNLOCK2, WD2_BASE + WSPR);
589 /**********************************************
591 * Description: sets uboots idea of sdram size
592 **********************************************/
598 /*****************************************************************
599 * Routine: peripheral_enable
600 * Description: Enable the clks & power for perifs (GPT2, UART1,...)
601 ******************************************************************/
602 void per_clocks_enable(void)
604 /* Enable GP2 timer. */
605 sr32(CM_CLKSEL_PER, 0, 1, 0x1); /* GPT2 = sys clk */
606 sr32(CM_ICLKEN_PER, 3, 1, 0x1); /* ICKen GPT2 */
607 sr32(CM_FCLKEN_PER, 3, 1, 0x1); /* FCKen GPT2 */
611 sr32(CM_FCLKEN1_CORE, 13, 1, 0x1);
612 sr32(CM_ICLKEN1_CORE, 13, 1, 0x1);
615 sr32(CM_FCLKEN_PER, 11, 1, 0x1);
616 sr32(CM_ICLKEN_PER, 11, 1, 0x1);
620 /* Enable GPIO 4, 5, & 6 clocks */
621 sr32(CM_FCLKEN_PER, 17, 3, 0x7);
622 sr32(CM_ICLKEN_PER, 17, 3, 0x7);
624 #ifdef CONFIG_DRIVER_OMAP34XX_I2C
625 /* Turn on all 3 I2C clocks */
626 sr32(CM_FCLKEN1_CORE, 15, 3, 0x7);
627 sr32(CM_ICLKEN1_CORE, 15, 3, 0x7); /* I2C1,2,3 = on */
630 /* Enable the ICLK for 32K Sync Timer as its used in udelay */
631 sr32(CM_ICLKEN_WKUP, 2, 1, 0x1);
633 sr32(CM_FCLKEN_IVA2, 0, 32, FCK_IVA2_ON);
634 sr32(CM_FCLKEN1_CORE, 0, 32, FCK_CORE1_ON);
635 sr32(CM_ICLKEN1_CORE, 0, 32, ICK_CORE1_ON);
636 sr32(CM_ICLKEN2_CORE, 0, 32, ICK_CORE2_ON);
637 sr32(CM_FCLKEN_WKUP, 0, 32, FCK_WKUP_ON);
638 sr32(CM_ICLKEN_WKUP, 0, 32, ICK_WKUP_ON);
639 sr32(CM_FCLKEN_DSS, 0, 32, FCK_DSS_ON);
640 sr32(CM_ICLKEN_DSS, 0, 32, ICK_DSS_ON);
641 sr32(CM_FCLKEN_CAM, 0, 32, FCK_CAM_ON);
642 sr32(CM_ICLKEN_CAM, 0, 32, ICK_CAM_ON);
643 sr32(CM_FCLKEN_PER, 0, 32, FCK_PER_ON);
644 sr32(CM_ICLKEN_PER, 0, 32, ICK_PER_ON);
649 /* Set MUX for UART, GPMC, SDRC, GPIO */
651 #define MUX_VAL(OFFSET,VALUE)\
652 __raw_writew((VALUE), OMAP34XX_CTRL_BASE + (OFFSET));
654 #define CP(x) (CONTROL_PADCONF_##x)
657 * IDIS - Input Disable
658 * PTD - Pull type Down
660 * DIS - Pull type selection is inactive
661 * EN - Pull type selection is active
663 * The commented string gives the final mux configuration for that pin
665 #define MUX_DEFAULT()\
666 MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) /*SDRC_D0*/\
667 MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) /*SDRC_D1*/\
668 MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) /*SDRC_D2*/\
669 MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) /*SDRC_D3*/\
670 MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) /*SDRC_D4*/\
671 MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) /*SDRC_D5*/\
672 MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) /*SDRC_D6*/\
673 MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) /*SDRC_D7*/\
674 MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) /*SDRC_D8*/\
675 MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) /*SDRC_D9*/\
676 MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) /*SDRC_D10*/\
677 MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) /*SDRC_D11*/\
678 MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) /*SDRC_D12*/\
679 MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) /*SDRC_D13*/\
680 MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) /*SDRC_D14*/\
681 MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) /*SDRC_D15*/\
682 MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) /*SDRC_D16*/\
683 MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) /*SDRC_D17*/\
684 MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) /*SDRC_D18*/\
685 MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) /*SDRC_D19*/\
686 MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) /*SDRC_D20*/\
687 MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) /*SDRC_D21*/\
688 MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) /*SDRC_D22*/\
689 MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) /*SDRC_D23*/\
690 MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) /*SDRC_D24*/\
691 MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) /*SDRC_D25*/\
692 MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) /*SDRC_D26*/\
693 MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) /*SDRC_D27*/\
694 MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) /*SDRC_D28*/\
695 MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) /*SDRC_D29*/\
696 MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) /*SDRC_D30*/\
697 MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) /*SDRC_D31*/\
698 MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) /*SDRC_CLK*/\
699 MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) /*SDRC_DQS0*/\
700 MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) /*SDRC_DQS1*/\
701 MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) /*SDRC_DQS2*/\
702 MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) /*SDRC_DQS3*/\
703 MUX_VAL(CP(GPMC_A1), (IDIS | PTD | DIS | M0)) /*GPMC_A1*/\
704 MUX_VAL(CP(GPMC_A2), (IDIS | PTD | DIS | M0)) /*GPMC_A2*/\
705 MUX_VAL(CP(GPMC_A3), (IDIS | PTD | DIS | M0)) /*GPMC_A3*/\
706 MUX_VAL(CP(GPMC_A4), (IDIS | PTD | DIS | M0)) /*GPMC_A4*/\
707 MUX_VAL(CP(GPMC_A5), (IDIS | PTD | DIS | M0)) /*GPMC_A5*/\
708 MUX_VAL(CP(GPMC_A6), (IDIS | PTD | DIS | M0)) /*GPMC_A6*/\
709 MUX_VAL(CP(GPMC_A7), (IDIS | PTD | DIS | M0)) /*GPMC_A7*/\
710 MUX_VAL(CP(GPMC_A8), (IDIS | PTD | DIS | M0)) /*GPMC_A8*/\
711 MUX_VAL(CP(GPMC_A9), (IDIS | PTD | DIS | M0)) /*GPMC_A9*/\
712 MUX_VAL(CP(GPMC_A10), (IDIS | PTD | DIS | M0)) /*GPMC_A10*/\
713 MUX_VAL(CP(GPMC_D0), (IEN | PTD | DIS | M0)) /*GPMC_D0*/\
714 MUX_VAL(CP(GPMC_D1), (IEN | PTD | DIS | M0)) /*GPMC_D1*/\
715 MUX_VAL(CP(GPMC_D2), (IEN | PTD | DIS | M0)) /*GPMC_D2*/\
716 MUX_VAL(CP(GPMC_D3), (IEN | PTD | DIS | M0)) /*GPMC_D3*/\
717 MUX_VAL(CP(GPMC_D4), (IEN | PTD | DIS | M0)) /*GPMC_D4*/\
718 MUX_VAL(CP(GPMC_D5), (IEN | PTD | DIS | M0)) /*GPMC_D5*/\
719 MUX_VAL(CP(GPMC_D6), (IEN | PTD | DIS | M0)) /*GPMC_D6*/\
720 MUX_VAL(CP(GPMC_D7), (IEN | PTD | DIS | M0)) /*GPMC_D7*/\
721 MUX_VAL(CP(GPMC_D8), (IEN | PTD | DIS | M0)) /*GPMC_D8*/\
722 MUX_VAL(CP(GPMC_D9), (IEN | PTD | DIS | M0)) /*GPMC_D9*/\
723 MUX_VAL(CP(GPMC_D10), (IEN | PTD | DIS | M0)) /*GPMC_D10*/\
724 MUX_VAL(CP(GPMC_D11), (IEN | PTD | DIS | M0)) /*GPMC_D11*/\
725 MUX_VAL(CP(GPMC_D12), (IEN | PTD | DIS | M0)) /*GPMC_D12*/\
726 MUX_VAL(CP(GPMC_D13), (IEN | PTD | DIS | M0)) /*GPMC_D13*/\
727 MUX_VAL(CP(GPMC_D14), (IEN | PTD | DIS | M0)) /*GPMC_D14*/\
728 MUX_VAL(CP(GPMC_D15), (IEN | PTD | DIS | M0)) /*GPMC_D15*/\
729 MUX_VAL(CP(GPMC_nCS0), (IDIS | PTU | EN | M0)) /*GPMC_nCS0*/\
730 MUX_VAL(CP(GPMC_nCS1), (IDIS | PTU | EN | M0)) /*GPMC_nCS1*/\
731 MUX_VAL(CP(GPMC_nCS2), (IDIS | PTU | EN | M0)) /*GPMC_nCS2*/\
732 MUX_VAL(CP(GPMC_nCS3), (IDIS | PTU | EN | M0)) /*GPMC_nCS3*/\
733 MUX_VAL(CP(GPMC_nCS4), (IDIS | PTU | EN | M0)) /*GPMC_nCS4*/\
734 MUX_VAL(CP(GPMC_nCS5), (IDIS | PTU | EN | M0)) /*GPMC_nCS5*/\
735 MUX_VAL(CP(GPMC_nCS6), (IDIS | PTU | EN | M0)) /*GPMC_nCS6*/\
736 MUX_VAL(CP(GPMC_nCS7), (IDIS | PTU | EN | M0)) /*GPMC_nCS7*/\
737 MUX_VAL(CP(GPMC_CLK), (IDIS | PTD | DIS | M0)) /*GPMC_CLK*/\
738 MUX_VAL(CP(GPMC_nADV_ALE), (IDIS | PTD | DIS | M0)) /*GPMC_nADV_ALE*/\
739 MUX_VAL(CP(GPMC_nOE), (IDIS | PTD | DIS | M0)) /*GPMC_nOE*/\
740 MUX_VAL(CP(GPMC_nWE), (IDIS | PTD | DIS | M0)) /*GPMC_nWE*/\
741 MUX_VAL(CP(GPMC_nBE0_CLE), (IDIS | PTD | DIS | M0)) /*GPMC_nBE0_CLE*/\
742 MUX_VAL(CP(GPMC_nBE1), (IDIS | PTD | DIS | M4)) /*GPIO_61*/\
743 MUX_VAL(CP(GPMC_nWP), (IEN | PTD | DIS | M0)) /*GPMC_nWP*/\
744 MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) /*GPMC_WAIT0*/\
745 MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0)) /*GPMC_WAIT1*/\
746 MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M4)) /*GPIO_64*/\
747 MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M4)) /*GPIO_65*/\
748 MUX_VAL(CP(DSS_DATA18), (IEN | PTD | DIS | M4)) /*GPIO_88*/\
749 MUX_VAL(CP(DSS_DATA19), (IEN | PTD | DIS | M4)) /*GPIO_89*/\
750 MUX_VAL(CP(DSS_DATA20), (IEN | PTD | DIS | M4)) /*GPIO_90*/\
751 MUX_VAL(CP(DSS_DATA21), (IEN | PTD | DIS | M4)) /*GPIO_91*/\
752 MUX_VAL(CP(CSI2_DX0), (IEN | PTD | EN | M4)) /*GPIO_112*/\
753 MUX_VAL(CP(CSI2_DY0), (IEN | PTD | EN | M4)) /*GPIO_113*/\
754 MUX_VAL(CP(CSI2_DX1), (IEN | PTD | EN | M4)) /*GPIO_114*/\
756 MUX_VAL(CP(CSI2_DY1), (IEN | PTD | EN | M4)) /*GPIO_115*/\
757 MUX_VAL(CP(CAM_WEN), (IEN | PTD | DIS | M4)) /*GPIO_167*/\
758 MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0)) /*MMC1_CLK*/\
759 MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)) /*MMC1_CMD*/\
760 MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)) /*MMC1_DAT0*/\
761 MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)) /*MMC1_DAT1*/\
762 MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)) /*MMC1_DAT2*/\
763 MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)) /*MMC1_DAT3*/\
764 MUX_VAL(CP(MMC1_DAT4), (IEN | PTD | EN | M4)) /*GPIO_126*/\
765 MUX_VAL(CP(MMC1_DAT5), (IEN | PTD | EN | M4)) /*GPIO_127*/\
766 MUX_VAL(CP(MMC1_DAT6), (IEN | PTD | EN | M4)) /*GPIO_128*/\
767 MUX_VAL(CP(MMC1_DAT7), (IEN | PTD | EN | M4)) /*GPIO_129*/\
768 MUX_VAL(CP(MMC2_CLK), (IEN | PTU | EN | M4)) /*GPIO_130*/\
769 MUX_VAL(CP(MMC2_DAT7), (IEN | PTU | EN | M4)) /*GPIO_139*/\
770 MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) /*UART1_TX*/\
771 MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M0)) /*UART1_RTS*/\
772 MUX_VAL(CP(UART1_CTS), (IEN | PTU | DIS | M0)) /*UART1_CTS*/\
773 MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) /*UART1_RX*/\
774 MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTD | EN | M0)) /*UART3_CTS_RCTX */\
775 MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTD | DIS | M0)) /*UART3_RTS_SD */\
776 MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)) /*UART3_RX_IRRX*/\
777 MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) /*UART3_TX_IRTX*/\
778 MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) /*I2C1_SCL*/\
779 MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) /*I2C1_SDA*/\
780 MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0)) /*I2C2_SCL*/\
781 MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0)) /*I2C2_SDA*/\
782 MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)) /*I2C3_SCL*/\
783 MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)) /*I2C3_SDA*/\
784 MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) /*I2C4_SCL*/\
785 MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) /*I2C4_SDA*/\
786 MUX_VAL(CP(McBSP1_DX), (IEN | PTD | DIS | M4)) /*GPIO_158*/\
787 MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) /*SYS_32K*/\
788 MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) /*GPIO_2 */\
789 MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) /*GPIO_3 */\
790 MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) /*GPIO_4 */\
791 MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)) /*GPIO_5 */\
792 MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) /*GPIO_6 */\
793 MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)) /*GPIO_7 */\
794 MUX_VAL(CP(SYS_BOOT6), (IEN | PTD | DIS | M4)) /*GPIO_8 */\
795 MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M4)) /*GPIO_186*/\
796 MUX_VAL(CP(JTAG_nTRST), (IEN | PTD | DIS | M0)) /*JTAG_nTRST*/\
797 MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)) /*JTAG_TCK*/\
798 MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)) /*JTAG_TMS*/\
799 MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)) /*JTAG_TDI*/\
800 MUX_VAL(CP(JTAG_EMU0), (IEN | PTD | DIS | M0)) /*JTAG_EMU0*/\
801 MUX_VAL(CP(JTAG_EMU1), (IEN | PTD | DIS | M0)) /*JTAG_EMU1*/\
802 MUX_VAL(CP(ETK_CLK), (IEN | PTD | DIS | M4)) /*GPIO_12*/\
803 MUX_VAL(CP(ETK_CTL), (IEN | PTD | DIS | M4)) /*GPIO_13*/\
804 MUX_VAL(CP(ETK_D0), (IEN | PTD | DIS | M4)) /*GPIO_14*/\
805 MUX_VAL(CP(ETK_D1), (IEN | PTD | DIS | M4)) /*GPIO_15*/\
806 MUX_VAL(CP(ETK_D2), (IEN | PTD | DIS | M4)) /*GPIO_16*/\
807 MUX_VAL(CP(ETK_D10), (IEN | PTD | DIS | M4)) /*GPIO_24*/\
808 MUX_VAL(CP(ETK_D11), (IEN | PTD | DIS | M4)) /*GPIO_25*/\
809 MUX_VAL(CP(ETK_D12), (IEN | PTD | DIS | M4)) /*GPIO_26*/\
810 MUX_VAL(CP(ETK_D13), (IEN | PTD | DIS | M4)) /*GPIO_27*/\
811 MUX_VAL(CP(ETK_D14), (IEN | PTD | DIS | M4)) /*GPIO_28*/\
812 MUX_VAL(CP(ETK_D15), (IEN | PTD | DIS | M4)) /*GPIO_29*/
814 /**********************************************************
815 * Routine: set_muxconf_regs
816 * Description: Setting up the configuration Mux registers
817 * specific to the hardware. Many pins need
818 * to be moved from protect to primary mode.
819 *********************************************************/
820 void set_muxconf_regs(void)
825 /**********************************************************
826 * Routine: nand+_init
827 * Description: Set up nand for nand and jffs2 commands
828 *********************************************************/
832 /* global settings */
833 __raw_writel(0x10, GPMC_SYSCONFIG); /* smart idle */
834 __raw_writel(0x0, GPMC_IRQENABLE); /* isr's sources masked */
835 __raw_writel(0, GPMC_TIMEOUT_CONTROL);/* timeout disable */
837 /* Set the GPMC Vals, NAND is mapped at CS0, oneNAND at CS0.
838 * We configure only GPMC CS0 with required values. Configiring other devices
839 * at other CS is done in u-boot. So we don't have to bother doing it here.
841 __raw_writel(0 , GPMC_CONFIG7 + GPMC_CONFIG_CS0);
844 #ifdef CFG_NAND_K9F1G08R0A
845 if ((get_mem_type() == GPMC_NAND) || (get_mem_type() == MMC_NAND)) {
846 __raw_writel(M_NAND_GPMC_CONFIG1, GPMC_CONFIG1 + GPMC_CONFIG_CS0);
847 __raw_writel(M_NAND_GPMC_CONFIG2, GPMC_CONFIG2 + GPMC_CONFIG_CS0);
848 __raw_writel(M_NAND_GPMC_CONFIG3, GPMC_CONFIG3 + GPMC_CONFIG_CS0);
849 __raw_writel(M_NAND_GPMC_CONFIG4, GPMC_CONFIG4 + GPMC_CONFIG_CS0);
850 __raw_writel(M_NAND_GPMC_CONFIG5, GPMC_CONFIG5 + GPMC_CONFIG_CS0);
851 __raw_writel(M_NAND_GPMC_CONFIG6, GPMC_CONFIG6 + GPMC_CONFIG_CS0);
853 /* Enable the GPMC Mapping */
854 __raw_writel((((OMAP34XX_GPMC_CS0_SIZE & 0xF)<<8) |
855 ((NAND_BASE_ADR>>24) & 0x3F) |
856 (1<<6)), (GPMC_CONFIG7 + GPMC_CONFIG_CS0));
861 printf("Unsupported Chip!\n");
869 if ((get_mem_type() == GPMC_ONENAND) || (get_mem_type() == MMC_ONENAND)) {
870 __raw_writel(ONENAND_GPMC_CONFIG1, GPMC_CONFIG1 + GPMC_CONFIG_CS0);
871 __raw_writel(ONENAND_GPMC_CONFIG2, GPMC_CONFIG2 + GPMC_CONFIG_CS0);
872 __raw_writel(ONENAND_GPMC_CONFIG3, GPMC_CONFIG3 + GPMC_CONFIG_CS0);
873 __raw_writel(ONENAND_GPMC_CONFIG4, GPMC_CONFIG4 + GPMC_CONFIG_CS0);
874 __raw_writel(ONENAND_GPMC_CONFIG5, GPMC_CONFIG5 + GPMC_CONFIG_CS0);
875 __raw_writel(ONENAND_GPMC_CONFIG6, GPMC_CONFIG6 + GPMC_CONFIG_CS0);
877 /* Enable the GPMC Mapping */
878 __raw_writel((((OMAP34XX_GPMC_CS0_SIZE & 0xF)<<8) |
879 ((ONENAND_BASE>>24) & 0x3F) |
880 (1<<6)), (GPMC_CONFIG7 + GPMC_CONFIG_CS0));
883 if (onenand_chip()) {
885 printf("OneNAND Unsupported !\n");
895 /* optionally do something like blinking LED */
896 void board_hang(void)
902 /******************************************************************************
903 * Dummy function to handle errors for EABI incompatibility
904 *****************************************************************************/
909 /******************************************************************************
910 * Dummy function to handle errors for EABI incompatibility
911 *****************************************************************************/