3 * Texas Instruments, <www.ti.com>
4 * Jian Zhang <jzhang@ti.com>
5 * Richard Woodruff <r-woodruff2@ti.com>
8 * Steve Sakoman <steve@sakoman.com>
10 * See file CREDITS for list of people who contributed to this
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of
16 * the License, or (at your option) any later version.
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
33 #include <asm/arch/cpu.h>
34 #include <asm/arch/bits.h>
35 #include <asm/arch/mux.h>
36 #include <asm/arch/sys_proto.h>
37 #include <asm/arch/sys_info.h>
38 #include <asm/arch/clocks.h>
39 #include <asm/arch/mem.h>
41 /* Used to index into DPLL parameter tables */
49 typedef struct dpll_param dpll_param;
51 /* Following functions are exported from lowlevel_init.S */
52 extern dpll_param *get_mpu_dpll_param();
53 extern dpll_param *get_iva_dpll_param();
54 extern dpll_param *get_core_dpll_param();
55 extern dpll_param *get_per_dpll_param();
57 #define __raw_readl(a) (*(volatile unsigned int *)(a))
58 #define __raw_writel(v, a) (*(volatile unsigned int *)(a) = (v))
59 #define __raw_readw(a) (*(volatile unsigned short *)(a))
60 #define __raw_writew(v, a) (*(volatile unsigned short *)(a) = (v))
62 /*******************************************************
64 * Description: spinning delay to use before udelay works
65 ******************************************************/
66 static inline void delay(unsigned long loops)
68 __asm__ volatile ("1:\n" "subs %0, %1, #1\n"
69 "bne 1b":"=r" (loops):"0"(loops));
72 /*****************************************
74 * Description: Early hardware init.
75 *****************************************/
81 /*************************************************************
82 * get_device_type(): tell if GP/HS/EMU/TST
83 *************************************************************/
84 u32 get_device_type(void)
87 mode = __raw_readl(CONTROL_STATUS) & (DEVICE_MASK);
91 /************************************************
92 * get_sysboot_value(void) - return SYS_BOOT[4:0]
93 ************************************************/
94 u32 get_sysboot_value(void)
97 mode = __raw_readl(CONTROL_STATUS) & (SYSBOOT_MASK);
101 /*************************************************************
102 * Routine: get_mem_type(void) - returns the kind of memory connected
103 * to GPMC that we are trying to boot form. Uses SYS BOOT settings.
104 *************************************************************/
105 u32 get_mem_type(void)
107 u32 mem_type = get_sysboot_value();
149 /******************************************
150 * get_cpu_rev(void) - extract version info
151 ******************************************/
152 u32 get_cpu_rev(void)
155 /* On ES1.0 the IDCODE register is not exposed on L4
156 * so using CPU ID to differentiate
157 * between ES2.0 and ES1.0.
159 __asm__ __volatile__("mrc p15, 0, %0, c0, c0, 0":"=r" (cpuid));
160 if ((cpuid & 0xf) == 0x0)
167 /******************************************
168 * cpu_is_3410(void) - returns true for 3410
169 ******************************************/
170 u32 cpu_is_3410(void)
173 if (get_cpu_rev() < CPU_3430_ES2) {
176 /* read scalability status and return 1 for 3410*/
177 status = __raw_readl(CONTROL_SCALABLE_OMAP_STATUS);
178 /* Check whether MPU frequency is set to 266 MHz which
179 * is nominal for 3410. If yes return true else false
181 if (((status >> 8) & 0x3) == 0x2)
188 /*****************************************************************
189 * sr32 - clear & set a value in a bit range for a 32 bit address
190 *****************************************************************/
191 void sr32(u32 addr, u32 start_bit, u32 num_bits, u32 value)
196 tmp = __raw_readl(addr) & ~(msk << start_bit);
197 tmp |= value << start_bit;
198 __raw_writel(tmp, addr);
201 /*********************************************************************
202 * wait_on_value() - common routine to allow waiting for changes in
204 *********************************************************************/
205 u32 wait_on_value(u32 read_bit_mask, u32 match_value, u32 read_addr, u32 bound)
210 val = __raw_readl(read_addr) & read_bit_mask;
211 if (val == match_value)
218 #ifdef CFG_3430SDRAM_DDR
219 /*********************************************************************
220 * config_3430sdram_ddr() - Init DDR on 3430SDP dev board.
221 *********************************************************************/
222 void config_3430sdram_ddr(void)
224 /* reset sdrc controller */
225 __raw_writel(SOFTRESET, SDRC_SYSCONFIG);
226 wait_on_value(BIT0, BIT0, SDRC_STATUS, 12000000);
227 __raw_writel(0, SDRC_SYSCONFIG);
229 /* setup sdrc to ball mux */
230 __raw_writel(SDP_SDRC_SHARING, SDRC_SHARING);
233 __raw_writel(SDP_SDRC_MDCFG_0_DDR, SDRC_MCFG_0);
236 if ((get_mem_type() == GPMC_ONENAND) || (get_mem_type() == MMC_ONENAND)) {
237 __raw_writel(INFINEON_SDRC_ACTIM_CTRLA_0, SDRC_ACTIM_CTRLA_0);
238 __raw_writel(INFINEON_SDRC_ACTIM_CTRLB_0, SDRC_ACTIM_CTRLB_0);
240 if ((get_mem_type() == GPMC_NAND) || (get_mem_type() == MMC_NAND)) {
241 __raw_writel(MICRON_SDRC_ACTIM_CTRLA_0, SDRC_ACTIM_CTRLA_0);
242 __raw_writel(MICRON_SDRC_ACTIM_CTRLB_0, SDRC_ACTIM_CTRLB_0);
245 __raw_writel(SDP_SDRC_RFR_CTRL, SDRC_RFR_CTRL);
246 __raw_writel(SDP_SDRC_POWER_POP, SDRC_POWER);
248 /* init sequence for mDDR/mSDR using manual commands (DDR is different) */
249 __raw_writel(CMD_NOP, SDRC_MANUAL_0);
251 __raw_writel(CMD_PRECHARGE, SDRC_MANUAL_0);
252 __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0);
253 __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0);
256 __raw_writel(SDP_SDRC_MR_0_DDR, SDRC_MR_0);
259 __raw_writel(SDP_SDRC_DLLAB_CTRL, SDRC_DLLA_CTRL);
260 delay(0x2000); /* give time to lock */
263 #endif /* CFG_3430SDRAM_DDR */
265 /*************************************************************
266 * get_sys_clk_speed - determine reference oscillator speed
267 * based on known 32kHz clock and gptimer.
268 *************************************************************/
269 u32 get_osc_clk_speed(void)
271 u32 start, cstart, cend, cdiff, val;
273 val = __raw_readl(PRM_CLKSRC_CTRL);
274 /* If SYS_CLK is being divided by 2, remove for now */
275 val = (val & (~BIT7)) | BIT6;
276 __raw_writel(val, PRM_CLKSRC_CTRL);
279 val = __raw_readl(CM_CLKSEL_WKUP) | BIT0;
280 __raw_writel(val, CM_CLKSEL_WKUP); /* select sys_clk for GPT1 */
282 /* Enable I and F Clocks for GPT1 */
283 val = __raw_readl(CM_ICLKEN_WKUP) | BIT0 | BIT2;
284 __raw_writel(val, CM_ICLKEN_WKUP);
285 val = __raw_readl(CM_FCLKEN_WKUP) | BIT0;
286 __raw_writel(val, CM_FCLKEN_WKUP);
288 __raw_writel(0, OMAP34XX_GPT1 + TLDR); /* start counting at 0 */
289 __raw_writel(GPT_EN, OMAP34XX_GPT1 + TCLR); /* enable clock */
290 /* enable 32kHz source */
291 /* enabled out of reset */
292 /* determine sys_clk via gauging */
294 start = 20 + __raw_readl(S32K_CR); /* start time in 20 cycles */
295 while (__raw_readl(S32K_CR) < start); /* dead loop till start time */
296 cstart = __raw_readl(OMAP34XX_GPT1 + TCRR); /* get start sys_clk count */
297 while (__raw_readl(S32K_CR) < (start + 20)); /* wait for 40 cycles */
298 cend = __raw_readl(OMAP34XX_GPT1 + TCRR); /* get end sys_clk count */
299 cdiff = cend - cstart; /* get elapsed ticks */
301 /* based on number of ticks assign speed */
304 else if (cdiff > 15200)
306 else if (cdiff > 13000)
308 else if (cdiff > 9000)
310 else if (cdiff > 7600)
316 /******************************************************************************
317 * get_sys_clkin_sel() - returns the sys_clkin_sel field value based on
318 * -- input oscillator clock frequency.
320 *****************************************************************************/
321 void get_sys_clkin_sel(u32 osc_clk, u32 *sys_clkin_sel)
323 if (osc_clk == S38_4M)
325 else if (osc_clk == S26M)
327 else if (osc_clk == S19_2M)
329 else if (osc_clk == S13M)
331 else if (osc_clk == S12M)
335 /******************************************************************************
336 * prcm_init() - inits clocks for PRCM as defined in clocks.h
337 * -- called from SRAM, or Flash (using temp SRAM stack).
338 *****************************************************************************/
341 u32 osc_clk = 0, sys_clkin_sel;
342 dpll_param *dpll_param_p;
343 u32 clk_index, sil_index;
345 /* Gauge the input clock speed and find out the sys_clkin_sel
346 * value corresponding to the input clock.
348 osc_clk = get_osc_clk_speed();
349 get_sys_clkin_sel(osc_clk, &sys_clkin_sel);
351 sr32(PRM_CLKSEL, 0, 3, sys_clkin_sel); /* set input crystal speed */
353 /* If the input clock is greater than 19.2M always divide/2 */
354 if (sys_clkin_sel > 2) {
355 sr32(PRM_CLKSRC_CTRL, 6, 2, 2);/* input clock divider */
356 clk_index = sys_clkin_sel/2;
358 sr32(PRM_CLKSRC_CTRL, 6, 2, 1);/* input clock divider */
359 clk_index = sys_clkin_sel;
362 /* The DPLL tables are defined according to sysclk value and
363 * silicon revision. The clk_index value will be used to get
364 * the values for that input sysclk from the DPLL param table
365 * and sil_index will get the values for that SysClk for the
366 * appropriate silicon rev.
368 sil_index = get_cpu_rev() - 1;
370 /* Unlock MPU DPLL (slows things down, and needed later) */
371 sr32(CM_CLKEN_PLL_MPU, 0, 3, PLL_LOW_POWER_BYPASS);
372 wait_on_value(BIT0, 0, CM_IDLEST_PLL_MPU, LDELAY);
374 /* Getting the base address of Core DPLL param table*/
375 dpll_param_p = (dpll_param *)get_core_dpll_param();
376 /* Moving it to the right sysclk and ES rev base */
377 dpll_param_p = dpll_param_p + 2*clk_index + sil_index;
379 /* sr32(CM_CLKSEL2_EMU) set override to work when asleep */
380 sr32(CM_CLKEN_PLL, 0, 3, PLL_FAST_RELOCK_BYPASS);
381 wait_on_value(BIT0, 0, CM_IDLEST_CKGEN, LDELAY);
382 sr32(CM_CLKSEL1_EMU, 16, 5, CORE_M3X2); /* m3x2 */
383 sr32(CM_CLKSEL1_PLL, 27, 2, dpll_param_p->m2); /* Set M2 */
384 sr32(CM_CLKSEL1_PLL, 16, 11, dpll_param_p->m); /* Set M */
385 sr32(CM_CLKSEL1_PLL, 8, 7, dpll_param_p->n); /* Set N */
386 sr32(CM_CLKSEL1_PLL, 6, 1, 0); /* 96M Src */
387 sr32(CM_CLKSEL_CORE, 8, 4, CORE_SSI_DIV); /* ssi */
388 sr32(CM_CLKSEL_CORE, 4, 2, CORE_FUSB_DIV); /* fsusb */
389 sr32(CM_CLKSEL_CORE, 2, 2, CORE_L4_DIV); /* l4 */
390 sr32(CM_CLKSEL_CORE, 0, 2, CORE_L3_DIV); /* l3 */
391 sr32(CM_CLKSEL_GFX, 0, 3, GFX_DIV); /* gfx */
392 sr32(CM_CLKSEL_WKUP, 1, 2, WKUP_RSM); /* reset mgr */
393 sr32(CM_CLKEN_PLL, 4, 4, dpll_param_p->fsel); /* FREQSEL */
394 sr32(CM_CLKEN_PLL, 0, 3, PLL_LOCK); /* lock mode */
395 wait_on_value(BIT0, 1, CM_IDLEST_CKGEN, LDELAY);
397 /* Getting the base address to PER DPLL param table*/
398 dpll_param_p = (dpll_param *)get_per_dpll_param();
399 /* Moving it to the right sysclk base */
400 dpll_param_p = dpll_param_p + clk_index;
402 sr32(CM_CLKEN_PLL, 16, 3, PLL_STOP);
403 wait_on_value(BIT1, 0, CM_IDLEST_CKGEN, LDELAY);
404 sr32(CM_CLKSEL1_EMU, 24, 5, PER_M6X2); /* set M6 */
405 sr32(CM_CLKSEL_CAM, 0, 5, PER_M5X2); /* set M5 */
406 sr32(CM_CLKSEL_DSS, 0, 5, PER_M4X2); /* set M4 */
407 sr32(CM_CLKSEL_DSS, 8, 5, PER_M3X2); /* set M3 */
408 sr32(CM_CLKSEL3_PLL, 0, 5, dpll_param_p->m2); /* set M2 */
409 sr32(CM_CLKSEL2_PLL, 8, 11, dpll_param_p->m); /* set m */
410 sr32(CM_CLKSEL2_PLL, 0, 7, dpll_param_p->n); /* set n */
411 sr32(CM_CLKEN_PLL, 20, 4, dpll_param_p->fsel);/* FREQSEL */
412 sr32(CM_CLKEN_PLL, 16, 3, PLL_LOCK); /* lock mode */
413 wait_on_value(BIT1, 2, CM_IDLEST_CKGEN, LDELAY);
415 /* Getting the base address to MPU DPLL param table*/
416 dpll_param_p = (dpll_param *)get_mpu_dpll_param();
417 /* Moving it to the right sysclk and ES rev base */
418 dpll_param_p = dpll_param_p + 2*clk_index + sil_index;
419 /* MPU DPLL (unlocked already) */
420 sr32(CM_CLKSEL2_PLL_MPU, 0, 5, dpll_param_p->m2); /* Set M2 */
421 sr32(CM_CLKSEL1_PLL_MPU, 8, 11, dpll_param_p->m); /* Set M */
422 sr32(CM_CLKSEL1_PLL_MPU, 0, 7, dpll_param_p->n); /* Set N */
423 sr32(CM_CLKEN_PLL_MPU, 4, 4, dpll_param_p->fsel); /* FREQSEL */
424 sr32(CM_CLKEN_PLL_MPU, 0, 3, PLL_LOCK); /* lock mode */
425 wait_on_value(BIT0, 1, CM_IDLEST_PLL_MPU, LDELAY);
427 /* Getting the base address to IVA DPLL param table*/
428 dpll_param_p = (dpll_param *)get_iva_dpll_param();
429 /* Moving it to the right sysclk and ES rev base */
430 dpll_param_p = dpll_param_p + 2*clk_index + sil_index;
431 /* IVA DPLL (set to 12*20=240MHz) */
432 sr32(CM_CLKEN_PLL_IVA2, 0, 3, PLL_STOP);
433 wait_on_value(BIT0, 0, CM_IDLEST_PLL_IVA2, LDELAY);
434 sr32(CM_CLKSEL2_PLL_IVA2, 0, 5, dpll_param_p->m2); /* set M2 */
435 sr32(CM_CLKSEL1_PLL_IVA2, 8, 11, dpll_param_p->m); /* set M */
436 sr32(CM_CLKSEL1_PLL_IVA2, 0, 7, dpll_param_p->n); /* set N */
437 sr32(CM_CLKEN_PLL_IVA2, 4, 4, dpll_param_p->fsel); /* FREQSEL */
438 sr32(CM_CLKEN_PLL_IVA2, 0, 3, PLL_LOCK); /* lock mode */
439 wait_on_value(BIT0, 1, CM_IDLEST_PLL_IVA2, LDELAY);
441 /* Set up GPTimers to sys_clk source only */
442 sr32(CM_CLKSEL_PER, 0, 8, 0xff);
443 sr32(CM_CLKSEL_WKUP, 0, 1, 1);
448 /*****************************************
449 * Routine: secure_unlock
450 * Description: Setup security registers for access
452 *****************************************/
453 void secure_unlock(void)
455 /* Permission values for registers -Full fledged permissions to all */
456 #define UNLOCK_1 0xFFFFFFFF
457 #define UNLOCK_2 0x00000000
458 #define UNLOCK_3 0x0000FFFF
459 /* Protection Module Register Target APE (PM_RT)*/
460 __raw_writel(UNLOCK_1, RT_REQ_INFO_PERMISSION_1);
461 __raw_writel(UNLOCK_1, RT_READ_PERMISSION_0);
462 __raw_writel(UNLOCK_1, RT_WRITE_PERMISSION_0);
463 __raw_writel(UNLOCK_2, RT_ADDR_MATCH_1);
465 __raw_writel(UNLOCK_3, GPMC_REQ_INFO_PERMISSION_0);
466 __raw_writel(UNLOCK_3, GPMC_READ_PERMISSION_0);
467 __raw_writel(UNLOCK_3, GPMC_WRITE_PERMISSION_0);
469 __raw_writel(UNLOCK_3, OCM_REQ_INFO_PERMISSION_0);
470 __raw_writel(UNLOCK_3, OCM_READ_PERMISSION_0);
471 __raw_writel(UNLOCK_3, OCM_WRITE_PERMISSION_0);
472 __raw_writel(UNLOCK_2, OCM_ADDR_MATCH_2);
475 __raw_writel(UNLOCK_3, IVA2_REQ_INFO_PERMISSION_0);
476 __raw_writel(UNLOCK_3, IVA2_READ_PERMISSION_0);
477 __raw_writel(UNLOCK_3, IVA2_WRITE_PERMISSION_0);
479 __raw_writel(UNLOCK_1, SMS_RG_ATT0); /* SDRC region 0 public */
482 /**********************************************************
483 * Routine: try_unlock_sram()
484 * Description: If chip is GP type, unlock the SRAM for
486 ***********************************************************/
487 void try_unlock_memory(void)
491 /* if GP device unlock device SRAM for general use */
492 /* secure code breaks for Secure/Emulation device - HS/E/T*/
493 mode = get_device_type();
494 if (mode == GP_DEVICE)
499 /**********************************************************
501 * Description: Does early system init of muxing and clocks.
502 * - Called at time when only stack is available.
503 **********************************************************/
508 #ifdef CONFIG_3430_AS_3410
509 /* setup the scalability control register for
510 * 3430 to work in 3410 mode
512 __raw_writel(0x5ABF, CONTROL_SCALABLE_OMAP_OCP);
519 config_3430sdram_ddr();
522 /*******************************************************
523 * Routine: misc_init_r
524 * Description: Init ethernet (done here so udelay works)
525 ********************************************************/
526 int misc_init_r(void)
531 /******************************************************
532 * Routine: wait_for_command_complete
533 * Description: Wait for posting to finish on watchdog
534 ******************************************************/
535 void wait_for_command_complete(unsigned int wd_base)
539 pending = __raw_readl(wd_base + WWPS);
543 /****************************************
544 * Routine: watchdog_init
545 * Description: Shut down watch dogs
546 *****************************************/
547 void watchdog_init(void)
549 /* There are 3 watch dogs WD1=Secure, WD2=MPU, WD3=IVA. WD1 is
550 * either taken care of by ROM (HS/EMU) or not accessible (GP).
551 * We need to take care of WD2-MPU or take a PRCM reset. WD3
552 * should not be running and does not generate a PRCM reset.
554 sr32(CM_FCLKEN_WKUP, 5, 1, 1);
555 sr32(CM_ICLKEN_WKUP, 5, 1, 1);
556 wait_on_value(BIT5, 0x20, CM_IDLEST_WKUP, 5); /* some issue here */
558 __raw_writel(WD_UNLOCK1, WD2_BASE + WSPR);
559 wait_for_command_complete(WD2_BASE);
560 __raw_writel(WD_UNLOCK2, WD2_BASE + WSPR);
563 /**********************************************
565 * Description: sets uboots idea of sdram size
566 **********************************************/
572 /*****************************************************************
573 * Routine: peripheral_enable
574 * Description: Enable the clks & power for perifs (GPT2, UART1,...)
575 ******************************************************************/
576 void per_clocks_enable(void)
578 /* Enable GP2 timer. */
579 sr32(CM_CLKSEL_PER, 0, 1, 0x1); /* GPT2 = sys clk */
580 sr32(CM_ICLKEN_PER, 3, 1, 0x1); /* ICKen GPT2 */
581 sr32(CM_FCLKEN_PER, 3, 1, 0x1); /* FCKen GPT2 */
585 sr32(CM_FCLKEN1_CORE, 13, 1, 0x1);
586 sr32(CM_ICLKEN1_CORE, 13, 1, 0x1);
589 sr32(CM_FCLKEN_PER, 11, 1, 0x1);
590 sr32(CM_ICLKEN_PER, 11, 1, 0x1);
596 /* Set MUX for UART, GPMC, SDRC, GPIO */
598 #define MUX_VAL(OFFSET,VALUE)\
599 __raw_writew((VALUE), OMAP34XX_CTRL_BASE + (OFFSET));
601 #define CP(x) (CONTROL_PADCONF_##x)
604 * IDIS - Input Disable
605 * PTD - Pull type Down
607 * DIS - Pull type selection is inactive
608 * EN - Pull type selection is active
610 * The commented string gives the final mux configuration for that pin
612 #define MUX_DEFAULT()\
613 MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) /*SDRC_D0*/\
614 MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) /*SDRC_D1*/\
615 MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) /*SDRC_D2*/\
616 MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) /*SDRC_D3*/\
617 MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) /*SDRC_D4*/\
618 MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) /*SDRC_D5*/\
619 MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) /*SDRC_D6*/\
620 MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) /*SDRC_D7*/\
621 MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) /*SDRC_D8*/\
622 MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) /*SDRC_D9*/\
623 MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) /*SDRC_D10*/\
624 MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) /*SDRC_D11*/\
625 MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) /*SDRC_D12*/\
626 MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) /*SDRC_D13*/\
627 MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) /*SDRC_D14*/\
628 MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) /*SDRC_D15*/\
629 MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) /*SDRC_D16*/\
630 MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) /*SDRC_D17*/\
631 MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) /*SDRC_D18*/\
632 MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) /*SDRC_D19*/\
633 MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) /*SDRC_D20*/\
634 MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) /*SDRC_D21*/\
635 MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) /*SDRC_D22*/\
636 MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) /*SDRC_D23*/\
637 MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) /*SDRC_D24*/\
638 MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) /*SDRC_D25*/\
639 MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) /*SDRC_D26*/\
640 MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) /*SDRC_D27*/\
641 MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) /*SDRC_D28*/\
642 MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) /*SDRC_D29*/\
643 MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) /*SDRC_D30*/\
644 MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) /*SDRC_D31*/\
645 MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) /*SDRC_CLK*/\
646 MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) /*SDRC_DQS0*/\
647 MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) /*SDRC_DQS1*/\
648 MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) /*SDRC_DQS2*/\
649 MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) /*SDRC_DQS3*/\
650 MUX_VAL(CP(GPMC_A1), (IDIS | PTD | DIS | M0)) /*GPMC_A1*/\
651 MUX_VAL(CP(GPMC_A2), (IDIS | PTD | DIS | M0)) /*GPMC_A2*/\
652 MUX_VAL(CP(GPMC_A3), (IDIS | PTD | DIS | M0)) /*GPMC_A3*/\
653 MUX_VAL(CP(GPMC_A4), (IDIS | PTD | DIS | M0)) /*GPMC_A4*/\
654 MUX_VAL(CP(GPMC_A5), (IDIS | PTD | DIS | M0)) /*GPMC_A5*/\
655 MUX_VAL(CP(GPMC_A6), (IDIS | PTD | DIS | M0)) /*GPMC_A6*/\
656 MUX_VAL(CP(GPMC_A7), (IDIS | PTD | DIS | M0)) /*GPMC_A7*/\
657 MUX_VAL(CP(GPMC_A8), (IDIS | PTD | DIS | M0)) /*GPMC_A8*/\
658 MUX_VAL(CP(GPMC_A9), (IDIS | PTD | DIS | M0)) /*GPMC_A9*/\
659 MUX_VAL(CP(GPMC_A10), (IDIS | PTD | DIS | M0)) /*GPMC_A10*/\
660 MUX_VAL(CP(GPMC_D0), (IEN | PTD | DIS | M0)) /*GPMC_D0*/\
661 MUX_VAL(CP(GPMC_D1), (IEN | PTD | DIS | M0)) /*GPMC_D1*/\
662 MUX_VAL(CP(GPMC_D2), (IEN | PTD | DIS | M0)) /*GPMC_D2*/\
663 MUX_VAL(CP(GPMC_D3), (IEN | PTD | DIS | M0)) /*GPMC_D3*/\
664 MUX_VAL(CP(GPMC_D4), (IEN | PTD | DIS | M0)) /*GPMC_D4*/\
665 MUX_VAL(CP(GPMC_D5), (IEN | PTD | DIS | M0)) /*GPMC_D5*/\
666 MUX_VAL(CP(GPMC_D6), (IEN | PTD | DIS | M0)) /*GPMC_D6*/\
667 MUX_VAL(CP(GPMC_D7), (IEN | PTD | DIS | M0)) /*GPMC_D7*/\
668 MUX_VAL(CP(GPMC_D8), (IEN | PTD | DIS | M0)) /*GPMC_D8*/\
669 MUX_VAL(CP(GPMC_D9), (IEN | PTD | DIS | M0)) /*GPMC_D9*/\
670 MUX_VAL(CP(GPMC_D10), (IEN | PTD | DIS | M0)) /*GPMC_D10*/\
671 MUX_VAL(CP(GPMC_D11), (IEN | PTD | DIS | M0)) /*GPMC_D11*/\
672 MUX_VAL(CP(GPMC_D12), (IEN | PTD | DIS | M0)) /*GPMC_D12*/\
673 MUX_VAL(CP(GPMC_D13), (IEN | PTD | DIS | M0)) /*GPMC_D13*/\
674 MUX_VAL(CP(GPMC_D14), (IEN | PTD | DIS | M0)) /*GPMC_D14*/\
675 MUX_VAL(CP(GPMC_D15), (IEN | PTD | DIS | M0)) /*GPMC_D15*/\
676 MUX_VAL(CP(GPMC_nCS0), (IDIS | PTU | EN | M0)) /*GPMC_nCS0*/\
677 MUX_VAL(CP(GPMC_nCS1), (IDIS | PTU | EN | M0)) /*GPMC_nCS1*/\
678 MUX_VAL(CP(GPMC_nCS2), (IDIS | PTU | EN | M0)) /*GPMC_nCS2*/\
679 MUX_VAL(CP(GPMC_nCS3), (IDIS | PTU | EN | M0)) /*GPMC_nCS3*/\
680 MUX_VAL(CP(GPMC_nCS4), (IDIS | PTU | EN | M0)) /*GPMC_nCS4*/\
681 MUX_VAL(CP(GPMC_nCS5), (IDIS | PTU | EN | M0)) /*GPMC_nCS5*/\
682 MUX_VAL(CP(GPMC_nCS6), (IDIS | PTU | EN | M0)) /*GPMC_nCS6*/\
683 MUX_VAL(CP(GPMC_nCS7), (IDIS | PTU | EN | M0)) /*GPMC_nCS7*/\
684 MUX_VAL(CP(GPMC_CLK), (IDIS | PTD | DIS | M0)) /*GPMC_CLK*/\
685 MUX_VAL(CP(GPMC_nADV_ALE), (IDIS | PTD | DIS | M0)) /*GPMC_nADV_ALE*/\
686 MUX_VAL(CP(GPMC_nOE), (IDIS | PTD | DIS | M0)) /*GPMC_nOE*/\
687 MUX_VAL(CP(GPMC_nWE), (IDIS | PTD | DIS | M0)) /*GPMC_nWE*/\
688 MUX_VAL(CP(GPMC_nBE0_CLE), (IDIS | PTD | DIS | M0)) /*GPMC_nBE0_CLE*/\
689 MUX_VAL(CP(GPMC_nBE1), (IDIS | PTD | DIS | M4)) /*GPIO_61*/\
690 MUX_VAL(CP(GPMC_nWP), (IEN | PTD | DIS | M0)) /*GPMC_nWP*/\
691 MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) /*GPMC_WAIT0*/\
692 MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0)) /*GPMC_WAIT1*/\
693 MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M4)) /*GPIO_64*/\
694 MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M4)) /*GPIO_65*/\
695 MUX_VAL(CP(DSS_DATA18), (IEN | PTD | DIS | M4)) /*GPIO_88*/\
696 MUX_VAL(CP(DSS_DATA19), (IEN | PTD | DIS | M4)) /*GPIO_89*/\
697 MUX_VAL(CP(DSS_DATA20), (IEN | PTD | DIS | M4)) /*GPIO_90*/\
698 MUX_VAL(CP(DSS_DATA21), (IEN | PTD | DIS | M4)) /*GPIO_91*/\
699 MUX_VAL(CP(CAM_WEN), (IEN | PTD | DIS | M4)) /*GPIO_167*/\
700 MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) /*UART1_TX*/\
701 MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M0)) /*UART1_RTS*/\
702 MUX_VAL(CP(UART1_CTS), (IEN | PTU | DIS | M0)) /*UART1_CTS*/\
703 MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) /*UART1_RX*/\
704 MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTD | EN | M0)) /*UART3_CTS_RCTX */\
705 MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTD | DIS | M0)) /*UART3_RTS_SD */\
706 MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)) /*UART3_RX_IRRX*/\
707 MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) /*UART3_TX_IRTX*/\
708 MUX_VAL(CP(McBSP1_DX), (IEN | PTD | DIS | M4)) /*GPIO_158*/\
709 MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) /*SYS_32K*/\
710 MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) /*GPIO_2 */\
711 MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) /*GPIO_3 */\
712 MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) /*GPIO_4 */\
713 MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)) /*GPIO_5 */\
714 MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) /*GPIO_6 */\
715 MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)) /*GPIO_7 */\
716 MUX_VAL(CP(SYS_BOOT6), (IEN | PTD | DIS | M4)) /*GPIO_8 */\
717 MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M4)) /*GPIO_186*/\
718 MUX_VAL(CP(JTAG_nTRST), (IEN | PTD | DIS | M0)) /*JTAG_nTRST*/\
719 MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)) /*JTAG_TCK*/\
720 MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)) /*JTAG_TMS*/\
721 MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)) /*JTAG_TDI*/\
722 MUX_VAL(CP(JTAG_EMU0), (IEN | PTD | DIS | M0)) /*JTAG_EMU0*/\
723 MUX_VAL(CP(JTAG_EMU1), (IEN | PTD | DIS | M0)) /*JTAG_EMU1*/\
724 MUX_VAL(CP(ETK_CLK), (IEN | PTD | DIS | M4)) /*GPIO_12*/\
725 MUX_VAL(CP(ETK_CTL), (IEN | PTD | DIS | M4)) /*GPIO_13*/\
726 MUX_VAL(CP(ETK_D0), (IEN | PTD | DIS | M4)) /*GPIO_14*/\
727 MUX_VAL(CP(ETK_D1), (IEN | PTD | DIS | M4)) /*GPIO_15*/\
728 MUX_VAL(CP(ETK_D2), (IEN | PTD | DIS | M4)) /*GPIO_16*/\
729 MUX_VAL(CP(ETK_D10), (IEN | PTD | DIS | M4)) /*GPIO_24*/\
730 MUX_VAL(CP(ETK_D11), (IEN | PTD | DIS | M4)) /*GPIO_25*/\
731 MUX_VAL(CP(ETK_D12), (IEN | PTD | DIS | M4)) /*GPIO_26*/\
732 MUX_VAL(CP(ETK_D13), (IEN | PTD | DIS | M4)) /*GPIO_27*/\
733 MUX_VAL(CP(ETK_D14), (IEN | PTD | DIS | M4)) /*GPIO_28*/\
734 MUX_VAL(CP(ETK_D15), (IEN | PTD | DIS | M4)) /*GPIO_29*/
736 /**********************************************************
737 * Routine: set_muxconf_regs
738 * Description: Setting up the configuration Mux registers
739 * specific to the hardware. Many pins need
740 * to be moved from protect to primary mode.
741 *********************************************************/
742 void set_muxconf_regs(void)
747 /**********************************************************
748 * Routine: nand+_init
749 * Description: Set up nand for nand and jffs2 commands
750 *********************************************************/
754 /* global settings */
755 __raw_writel(0x10, GPMC_SYSCONFIG); /* smart idle */
756 __raw_writel(0x0, GPMC_IRQENABLE); /* isr's sources masked */
757 __raw_writel(0, GPMC_TIMEOUT_CONTROL);/* timeout disable */
759 /* Set the GPMC Vals, NAND is mapped at CS0, oneNAND at CS0.
760 * We configure only GPMC CS0 with required values. Configiring other devices
761 * at other CS is done in u-boot. So we don't have to bother doing it here.
763 __raw_writel(0 , GPMC_CONFIG7 + GPMC_CONFIG_CS0);
766 if ((get_mem_type() == GPMC_NAND) || (get_mem_type() == MMC_NAND)) {
767 __raw_writel(M_NAND_GPMC_CONFIG1, GPMC_CONFIG1 + GPMC_CONFIG_CS0);
768 __raw_writel(M_NAND_GPMC_CONFIG2, GPMC_CONFIG2 + GPMC_CONFIG_CS0);
769 __raw_writel(M_NAND_GPMC_CONFIG3, GPMC_CONFIG3 + GPMC_CONFIG_CS0);
770 __raw_writel(M_NAND_GPMC_CONFIG4, GPMC_CONFIG4 + GPMC_CONFIG_CS0);
771 __raw_writel(M_NAND_GPMC_CONFIG5, GPMC_CONFIG5 + GPMC_CONFIG_CS0);
772 __raw_writel(M_NAND_GPMC_CONFIG6, GPMC_CONFIG6 + GPMC_CONFIG_CS0);
774 /* Enable the GPMC Mapping */
775 __raw_writel((((OMAP34XX_GPMC_CS0_SIZE & 0xF)<<8) |
776 ((NAND_BASE_ADR>>24) & 0x3F) |
777 (1<<6)), (GPMC_CONFIG7 + GPMC_CONFIG_CS0));
782 printf("Unsupported Chip!\n");
789 if ((get_mem_type() == GPMC_ONENAND) || (get_mem_type() == MMC_ONENAND)) {
790 __raw_writel(ONENAND_GPMC_CONFIG1, GPMC_CONFIG1 + GPMC_CONFIG_CS0);
791 __raw_writel(ONENAND_GPMC_CONFIG2, GPMC_CONFIG2 + GPMC_CONFIG_CS0);
792 __raw_writel(ONENAND_GPMC_CONFIG3, GPMC_CONFIG3 + GPMC_CONFIG_CS0);
793 __raw_writel(ONENAND_GPMC_CONFIG4, GPMC_CONFIG4 + GPMC_CONFIG_CS0);
794 __raw_writel(ONENAND_GPMC_CONFIG5, GPMC_CONFIG5 + GPMC_CONFIG_CS0);
795 __raw_writel(ONENAND_GPMC_CONFIG6, GPMC_CONFIG6 + GPMC_CONFIG_CS0);
797 /* Enable the GPMC Mapping */
798 __raw_writel((((OMAP34XX_GPMC_CS0_SIZE & 0xF)<<8) |
799 ((ONENAND_BASE>>24) & 0x3F) |
800 (1<<6)), (GPMC_CONFIG7 + GPMC_CONFIG_CS0));
803 if (onenand_chip()) {
805 printf("OneNAND Unsupported !\n");
814 typedef int (mmc_boot_addr) (void);
815 int mmc_boot(unsigned char *buf)
820 block_dev_desc_t *dev_desc = NULL;
821 unsigned char ret = 0;
823 printf("Starting X-loader on MMC \n");
827 printf("\n MMC init failed \n");
831 dev_desc = mmc_get_dev(0);
832 fat_register_device(dev_desc, 1);
833 size = file_fat_read("u-boot.bin", buf, 0);
837 printf("\n%ld Bytes Read from MMC \n", size);
839 printf("Starting OS Bootloader from MMC...\n");
844 /* optionally do something like blinking LED */
845 void board_hang(void)