3 * Texas Instruments, <www.ti.com>
4 * Richard Woodruff <r-woodruff2@ti.com>
5 * Rajendra Nayak <rnayak@ti.com>
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 #include <asm/arch/cpu.h>
26 #include <asm/arch/bits.h>
27 #include <asm/arch/clocks.h>
28 #include <asm/arch/mem.h>
29 #include <asm/arch/sys_proto.h>
30 #include <asm/arch/sys_info.h>
31 #include <asm/arch/clocks443x.h>
34 #define CONFIG_OMAP4_SDC 1
36 /* Used to index into DPLL parameter tables */
48 /* Tables having M,N,M2 et al values for different sys_clk speeds
49 * This table is generated only for OPP100
50 * The tables are organized as follows:
51 * Rows : 1 - 12M, 2 - 13M, 3 - 16.8M, 4 - 19.2M, 5 - 26M, 6 - 27M, 7 - 38.4M
55 struct dpll_param mpu_dpll_param[7] = {
57 {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
59 {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
61 {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
63 {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
65 {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
67 {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
70 /* RUN MPU @ 600 MHz */
71 {0x7d, 0x07, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00},
73 {0x69, 0x03, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00},
75 {0x1a, 0x02, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00},
80 struct dpll_param iva_dpll_param[7] = {
82 {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
84 {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
86 {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
88 {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
90 {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
92 {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
94 #ifdef CONFIG_OMAP4_SDC
95 {0x61, 0x03, 0x00, 0x00, 0x04, 0x07, 0x00, 0x00},
97 {0x61, 0x03, 0x00, 0x00, 0x04, 0x07, 0x00, 0x00},
101 /* CORE parameters */
102 struct dpll_param core_dpll_param[7] = {
104 {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
106 {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
108 {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
110 {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
112 {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
114 {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
115 /* 38.4M values - DDR@200MHz*/
116 {0x7d, 0x05, 0x02, 0x05, 0x08, 0x04, 0x06, 0x05},
119 /* CORE parameters - ES2.1 */
120 struct dpll_param core_dpll_param_ddr400[7] = {
122 {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
124 {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
126 {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
128 {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
130 {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
132 {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
133 /* 38.4M values - DDR@400MHz*/
134 {0x7d, 0x05, 0x01, 0x05, 0x08, 0x04, 0x06, 0x05},
137 /* CORE parameters for L3 at 190 MHz - For ES1 only*/
138 struct dpll_param core_dpll_param_l3_190[7] = {
140 {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
142 {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
144 {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
146 {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
148 {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
150 {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
152 #ifdef CONFIG_OMAP4_SDC
154 {0x1f0, 0x18, 0x01, 0x05, 0x08, 0x04, 0x06, 0x05},
155 #else /* Default CORE @166MHz */
156 {0x1b0, 0x18, 0x01, 0x05, 0x08, 0x04, 0x06, 0x05},
159 {0x7d, 0x05, 0x01, 0x05, 0x08, 0x04, 0x06, 0x08},
164 struct dpll_param per_dpll_param[7] = {
166 {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
168 {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
170 {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
172 {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
174 {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
176 {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
180 {0x0a, 0x00, 0x04, 0x03, 0x06, 0x05, 0x02, 0x03},
182 {0x14, 0x00, 0x08, 0x06, 0x0c, 0x09, 0x04, 0x05},
186 struct dpll_param abe_dpll_param[7] = {
188 {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
190 {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
192 {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
194 {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
196 {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
198 {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
200 #ifdef CONFIG_OMAP4_SDC
201 {0x40, 0x18, 0x1, 0x1, 0x0, 0x0, 0x0, 0x0},
203 {0x40, 0x18, 0x1, 0x1, 0x0, 0x0, 0x0, 0x0},
208 struct dpll_param usb_dpll_param[7] = {
210 {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
212 {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
214 {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
216 {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
218 {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
220 {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
222 #ifdef CONFIG_OMAP4_SDC
223 {0x32, 0x1, 0x2, 0x0, 0x0, 0x0, 0x0, 0x0},
225 {0x32, 0x1, 0x2, 0x0, 0x0, 0x0, 0x0, 0x0},
229 typedef struct dpll_param dpll_param;
231 static void configure_mpu_dpll(u32 clk_index)
233 dpll_param *dpll_param_p;
235 /* Unlock the MPU dpll */
236 sr32(CM_CLKMODE_DPLL_MPU, 0, 3, PLL_MN_POWER_BYPASS);
237 wait_on_value(BIT0, 0, CM_IDLEST_DPLL_MPU, LDELAY);
239 /* Program MPU DPLL */
240 dpll_param_p = &mpu_dpll_param[clk_index];
242 sr32(CM_AUTOIDLE_DPLL_MPU, 0, 3, 0x0); /* Disable DPLL autoidle */
244 /* Set M,N,M2 values */
245 sr32(CM_CLKSEL_DPLL_MPU, 8, 11, dpll_param_p->m);
246 sr32(CM_CLKSEL_DPLL_MPU, 0, 6, dpll_param_p->n);
247 sr32(CM_DIV_M2_DPLL_MPU, 0, 5, dpll_param_p->m2);
248 sr32(CM_DIV_M2_DPLL_MPU, 8, 1, 0x1);
250 /* Lock the mpu dpll */
251 sr32(CM_CLKMODE_DPLL_MPU, 0, 3, PLL_LOCK | 0x10);
252 wait_on_value(BIT0, 1, CM_IDLEST_DPLL_MPU, LDELAY);
257 static void configure_iva_dpll(u32 clk_index)
259 dpll_param *dpll_param_p;
261 /* Unlock the IVA dpll */
262 sr32(CM_CLKMODE_DPLL_IVA, 0, 3, PLL_MN_POWER_BYPASS);
263 wait_on_value(BIT0, 0, CM_IDLEST_DPLL_IVA, LDELAY);
265 /* CM_BYPCLK_DPLL_IVA = CORE_X2_CLK/2 */
266 sr32(CM_BYPCLK_DPLL_IVA, 0, 2, 0x1);
268 /* Program IVA DPLL */
269 dpll_param_p = &iva_dpll_param[clk_index];
271 sr32(CM_AUTOIDLE_DPLL_IVA, 0, 3, 0x0); /* Disable DPLL autoidle */
274 sr32(CM_CLKSEL_DPLL_IVA, 8, 11, dpll_param_p->m);
275 sr32(CM_CLKSEL_DPLL_IVA, 0, 7, dpll_param_p->n);
276 sr32(CM_DIV_M4_DPLL_IVA, 0, 5, dpll_param_p->m4);
277 sr32(CM_DIV_M4_DPLL_IVA, 8, 1, 0x1);
278 sr32(CM_DIV_M5_DPLL_IVA, 0, 5, dpll_param_p->m5);
279 sr32(CM_DIV_M5_DPLL_IVA, 8, 1, 0x1);
281 /* Lock the iva dpll */
282 sr32(CM_CLKMODE_DPLL_IVA, 0, 3, PLL_LOCK);
283 wait_on_value(BIT0, 1, CM_IDLEST_DPLL_IVA, LDELAY);
288 static void configure_per_dpll(u32 clk_index)
290 dpll_param *dpll_param_p;
292 /* Unlock the PER dpll */
293 sr32(CM_CLKMODE_DPLL_PER, 0, 3, PLL_MN_POWER_BYPASS);
294 wait_on_value(BIT0, 0, CM_IDLEST_DPLL_PER, LDELAY);
296 /* Program PER DPLL */
297 dpll_param_p = &per_dpll_param[clk_index];
299 /* Disable autoidle */
300 sr32(CM_AUTOIDLE_DPLL_PER, 0, 3, 0x0);
302 sr32(CM_CLKSEL_DPLL_PER, 8, 11, dpll_param_p->m);
303 sr32(CM_CLKSEL_DPLL_PER, 0, 6, dpll_param_p->n);
304 sr32(CM_DIV_M2_DPLL_PER, 0, 5, dpll_param_p->m2);
305 sr32(CM_DIV_M3_DPLL_PER, 0, 5, dpll_param_p->m3);
306 sr32(CM_DIV_M4_DPLL_PER, 0, 5, dpll_param_p->m4);
307 sr32(CM_DIV_M5_DPLL_PER, 0, 5, dpll_param_p->m5);
308 sr32(CM_DIV_M6_DPLL_PER, 0, 5, dpll_param_p->m6);
309 sr32(CM_DIV_M7_DPLL_PER, 0, 5, dpll_param_p->m7);
311 // if(omap_revision() == OMAP4430_ES1_0)
313 /* Do this only on ES1.0 */
314 sr32(CM_DIV_M2_DPLL_PER, 8, 1, 0x1);
315 sr32(CM_DIV_M3_DPLL_PER, 8, 1, 0x1);
316 sr32(CM_DIV_M4_DPLL_PER, 8, 1, 0x1);
317 sr32(CM_DIV_M5_DPLL_PER, 8, 1, 0x1);
318 sr32(CM_DIV_M6_DPLL_PER, 8, 1, 0x1);
319 sr32(CM_DIV_M7_DPLL_PER, 8, 1, 0x1);
322 /* Lock the per dpll */
323 sr32(CM_CLKMODE_DPLL_PER, 0, 3, PLL_LOCK);
324 wait_on_value(BIT0, 1, CM_IDLEST_DPLL_PER, LDELAY);
329 static void configure_abe_dpll(u32 clk_index)
331 dpll_param *dpll_param_p;
333 /* Select sys_clk as ref clk for ABE dpll */
334 sr32(CM_ABE_PLL_REF_CLKSEL, 0, 32, 0x0);
336 /* Enable slimbus and pad clocks */
337 sr32(CM_CLKSEL_ABE, 0, 32, 0x500);
339 /* Unlock the ABE dpll */
340 sr32(CM_CLKMODE_DPLL_ABE, 0, 3, PLL_MN_POWER_BYPASS);
341 wait_on_value(BIT0, 0, CM_IDLEST_DPLL_ABE, LDELAY);
343 /* Program ABE DPLL */
344 dpll_param_p = &abe_dpll_param[clk_index];
346 /* Disable autoidle */
347 sr32(CM_AUTOIDLE_DPLL_ABE, 0, 3, 0x0);
349 sr32(CM_CLKSEL_DPLL_ABE, 8, 11, dpll_param_p->m);
350 sr32(CM_CLKSEL_DPLL_ABE, 0, 6, dpll_param_p->n);
352 /* Force DPLL CLKOUTHIF to stay enabled */
353 sr32(CM_DIV_M2_DPLL_ABE, 0, 32, 0x500);
354 sr32(CM_DIV_M2_DPLL_ABE, 0, 5, dpll_param_p->m2);
355 sr32(CM_DIV_M2_DPLL_ABE, 8, 1, 0x1);
356 /* Force DPLL CLKOUTHIF to stay enabled */
357 sr32(CM_DIV_M3_DPLL_ABE, 0, 32, 0x100);
358 sr32(CM_DIV_M3_DPLL_ABE, 0, 5, dpll_param_p->m3);
359 sr32(CM_DIV_M3_DPLL_ABE, 8, 1, 0x1);
361 /* Lock the abe dpll */
362 sr32(CM_CLKMODE_DPLL_ABE, 0, 3, PLL_LOCK);
363 wait_on_value(BIT0, 1, CM_IDLEST_DPLL_ABE, LDELAY);
368 static void configure_usb_dpll(u32 clk_index)
370 dpll_param *dpll_param_p;
372 /* Select the 60Mhz clock 480/8 = 60*/
373 sr32(CM_CLKSEL_USB_60MHz, 0, 32, 0x1);
375 /* Unlock the USB dpll */
376 sr32(CM_CLKMODE_DPLL_USB, 0, 3, PLL_MN_POWER_BYPASS);
377 wait_on_value(BIT0, 0, CM_IDLEST_DPLL_USB, LDELAY);
379 /* Program USB DPLL */
380 dpll_param_p = &usb_dpll_param[clk_index];
382 /* Disable autoidle */
383 sr32(CM_AUTOIDLE_DPLL_USB, 0, 3, 0x0);
385 sr32(CM_CLKSEL_DPLL_USB, 8, 11, dpll_param_p->m);
386 sr32(CM_CLKSEL_DPLL_USB, 0, 6, dpll_param_p->n);
388 /* Force DPLL CLKOUT to stay active */
389 sr32(CM_DIV_M2_DPLL_USB, 0, 32, 0x100);
390 sr32(CM_DIV_M2_DPLL_USB, 0, 5, dpll_param_p->m2);
391 sr32(CM_DIV_M2_DPLL_USB, 8, 1, 0x1);
392 sr32(CM_CLKDCOLDO_DPLL_USB, 8, 1, 0x1);
394 /* Lock the usb dpll */
395 sr32(CM_CLKMODE_DPLL_USB, 0, 3, PLL_LOCK);
396 wait_on_value(BIT0, 1, CM_IDLEST_DPLL_USB, LDELAY);
398 /* force enable the CLKDCOLDO clock */
399 sr32(CM_CLKDCOLDO_DPLL_USB, 0, 32, 0x100);
404 static void configure_core_dpll(clk_index)
406 dpll_param *dpll_param_p;
408 /* Get the sysclk speed from cm_sys_clksel
409 * Set it to 38.4 MHz, in case ROM code is bypassed
414 /* CORE_CLK=CORE_X2_CLK/2, L3_CLK=CORE_CLK/2, L4_CLK=L3_CLK/2 */
415 sr32(CM_CLKSEL_CORE, 0, 32, 0x110);
417 /* Unlock the CORE dpll */
418 sr32(CM_CLKMODE_DPLL_CORE, 0, 3, PLL_MN_POWER_BYPASS);
419 wait_on_value(BIT0, 0, CM_IDLEST_DPLL_CORE, LDELAY);
421 /* Program Core DPLL */
422 if(omap_revision() == OMAP4430_ES1_0)
423 dpll_param_p = &core_dpll_param_l3_190[clk_index];
424 else if(omap_revision() == OMAP4430_ES2_0)
425 dpll_param_p = &core_dpll_param[clk_index];
426 else if(omap_revision() == OMAP4430_ES2_1)
427 dpll_param_p = &core_dpll_param_ddr400[clk_index];
429 /* Disable autoidle */
430 sr32(CM_AUTOIDLE_DPLL_CORE, 0, 3, 0x0);
432 sr32(CM_CLKSEL_DPLL_CORE, 8, 11, dpll_param_p->m);
433 sr32(CM_CLKSEL_DPLL_CORE, 0, 6, dpll_param_p->n);
434 sr32(CM_DIV_M2_DPLL_CORE, 0, 5, dpll_param_p->m2);
435 sr32(CM_DIV_M3_DPLL_CORE, 0, 5, dpll_param_p->m3);
436 sr32(CM_DIV_M4_DPLL_CORE, 0, 5, dpll_param_p->m4);
437 sr32(CM_DIV_M5_DPLL_CORE, 0, 5, dpll_param_p->m5);
438 sr32(CM_DIV_M6_DPLL_CORE, 0, 5, dpll_param_p->m6);
439 sr32(CM_DIV_M7_DPLL_CORE, 0, 5, dpll_param_p->m7);
441 if(omap_revision() == OMAP4430_ES1_0)
443 /* Do this only on ES1.0 */
444 sr32(CM_DIV_M2_DPLL_CORE, 8, 1, 0x1);
445 sr32(CM_DIV_M3_DPLL_CORE, 8, 1, 0x1);
446 sr32(CM_DIV_M4_DPLL_CORE, 8, 1, 0x1);
447 sr32(CM_DIV_M5_DPLL_CORE, 8, 1, 0x1);
448 sr32(CM_DIV_M6_DPLL_CORE, 8, 1, 0x1);
449 sr32(CM_DIV_M7_DPLL_CORE, 8, 1, 0x1);
453 /* Lock the core dpll */
454 sr32(CM_CLKMODE_DPLL_CORE, 0, 3, PLL_LOCK);
455 wait_on_value(BIT0, 1, CM_IDLEST_DPLL_CORE, LDELAY);
461 void configure_core_dpll_no_lock(void)
463 dpll_param *dpll_param_p;
466 /* Get the sysclk speed from cm_sys_clksel
467 * Set it to 38.4 MHz, in case ROM code is bypassed
469 __raw_writel(0x7,CM_SYS_CLKSEL);
472 clk_index = clk_index - 1;
473 /* CORE_CLK=CORE_X2_CLK/2, L3_CLK=CORE_CLK/2, L4_CLK=L3_CLK/2 */
474 sr32(CM_CLKSEL_CORE, 0, 32, 0x110);
476 /* Unlock the CORE dpll */
477 sr32(CM_CLKMODE_DPLL_CORE, 0, 3, PLL_MN_POWER_BYPASS);
478 wait_on_value(BIT0, 0, CM_IDLEST_DPLL_CORE, LDELAY);
480 /* Program Core DPLL */
481 if(omap_revision() == OMAP4430_ES1_0)
482 dpll_param_p = &core_dpll_param_l3_190[clk_index];
483 else if(omap_revision() == OMAP4430_ES2_0)
484 dpll_param_p = &core_dpll_param[clk_index];
485 else if(omap_revision() == OMAP4430_ES2_1)
486 dpll_param_p = &core_dpll_param_ddr400[clk_index];
488 /* Disable autoidle */
489 sr32(CM_AUTOIDLE_DPLL_CORE, 0, 3, 0x0);
491 sr32(CM_CLKSEL_DPLL_CORE, 8, 11, dpll_param_p->m);
492 sr32(CM_CLKSEL_DPLL_CORE, 0, 6, dpll_param_p->n);
493 sr32(CM_DIV_M2_DPLL_CORE, 0, 5, dpll_param_p->m2);
494 sr32(CM_DIV_M3_DPLL_CORE, 0, 5, dpll_param_p->m3);
495 sr32(CM_DIV_M4_DPLL_CORE, 0, 5, dpll_param_p->m4);
496 sr32(CM_DIV_M5_DPLL_CORE, 0, 5, dpll_param_p->m5);
497 sr32(CM_DIV_M6_DPLL_CORE, 0, 5, dpll_param_p->m6);
498 sr32(CM_DIV_M7_DPLL_CORE, 0, 5, dpll_param_p->m7);
500 // if(omap_revision() == OMAP4430_ES1_0)
502 /* Do this only on ES1.0 */
503 sr32(CM_DIV_M2_DPLL_CORE, 8, 1, 0x1);
504 sr32(CM_DIV_M3_DPLL_CORE, 8, 1, 0x1);
505 sr32(CM_DIV_M4_DPLL_CORE, 8, 1, 0x1);
506 sr32(CM_DIV_M5_DPLL_CORE, 8, 1, 0x1);
507 sr32(CM_DIV_M6_DPLL_CORE, 8, 1, 0x1);
508 sr32(CM_DIV_M7_DPLL_CORE, 8, 1, 0x1);
514 void lock_core_dpll(void)
516 /* Lock the core dpll */
517 sr32(CM_CLKMODE_DPLL_CORE, 0, 3, PLL_LOCK);
518 wait_on_value(BIT0, 1, CM_IDLEST_DPLL_CORE, LDELAY);
523 void lock_core_dpll_shadow(void)
525 dpll_param *dpll_param_p;
526 /* Lock the core dpll using freq update method */
527 *(volatile int*)0x4A004120 = 10; //(CM_CLKMODE_DPLL_CORE)
529 if(omap_revision() == OMAP4430_ES1_0)
530 dpll_param_p = &core_dpll_param_l3_190[6];
531 else if(omap_revision() == OMAP4430_ES2_0)
532 dpll_param_p = &core_dpll_param[6];
533 else if(omap_revision() == OMAP4430_ES2_1)
534 dpll_param_p = &core_dpll_param_ddr400[6];
536 /* CM_SHADOW_FREQ_CONFIG1: DLL_OVERRIDE = 1(hack), DLL_RESET = 1,
537 * DPLL_CORE_M2_DIV =1, DPLL_CORE_DPLL_EN = 0x7, FREQ_UPDATE = 1
539 *(volatile int*)0x4A004260 = 0x70D | (dpll_param_p->m2 << 11);
541 /* Wait for Freq_Update to get cleared: CM_SHADOW_FREQ_CONFIG1 */
542 while( ( (*(volatile int*)0x4A004260) & 0x1) == 0x1 );
544 /* Wait for DPLL to Lock : CM_IDLEST_DPLL_CORE */
545 wait_on_value(BIT0, 1, CM_IDLEST_DPLL_CORE, LDELAY);
551 static void enable_all_clocks(void)
553 volatile int regvalue = 0;
555 /* Enable Ducati clocks */
556 sr32(CM_DUCATI_DUCATI_CLKCTRL, 0, 32, 0x1);
557 sr32(CM_DUCATI_CLKSTCTRL, 0, 32, 0x2);
559 wait_on_value(BIT8, BIT8, CM_DUCATI_CLKSTCTRL, LDELAY);
560 //wait_on_value(BIT18|BIT17|BIT16, 0, CM_DUCATI_DUCATI_CLKCTRL, LDELAY);
562 /* Enable ivahd and sl2 clocks */
563 sr32(IVAHD_IVAHD_CLKCTRL, 0, 32, 0x1);
564 sr32(IVAHD_SL2_CLKCTRL, 0, 32, 0x1);
565 sr32(IVAHD_CLKSTCTRL, 0, 32, 0x2);
567 wait_on_value(BIT8, BIT8, IVAHD_CLKSTCTRL, LDELAY);
569 /* wait for ivahd to become accessible */
570 //wait_on_value(BIT18|BIT17|BIT16, 0, IVAHD_IVAHD_CLKCTRL, LDELAY);
571 /* wait for sl2 to become accessible */
572 //wait_on_value(BIT17|BIT16, 0, IVAHD_SL2_CLKCTRL, LDELAY);
574 /* Enable Tesla clocks */
575 sr32(DSP_DSP_CLKCTRL, 0, 32, 0x1);
576 sr32(DSP_CLKSTCTRL, 0, 32, 0x2);
578 wait_on_value(BIT8, BIT8, DSP_CLKSTCTRL, LDELAY);
580 /* wait for tesla to become accessible */
581 //wait_on_value(BIT18|BIT17|BIT16, 0, DSP_DSP_CLKCTRL, LDELAY);
583 /* TODO: Some hack needed by MM: Clean this */
584 #if 0 /* Doesn't work on some Zebu */
585 *(volatile int*)0x4a306910 = 0x00000003;
586 *(volatile int*)0x550809a0 = 0x00000001;
587 *(volatile int*)0x55080a20 = 0x00000007;
591 sr32(CM1_ABE_CLKSTCTRL, 0, 32, 0x3);
592 sr32(CM1_ABE_AESS_CLKCTRL, 0, 32, 0x2);
593 //wait_on_value(BIT18|BIT17|BIT16, 0, CM1_ABE_AESS_CLKCTRL, LDELAY);
594 sr32(CM1_ABE_PDM_CLKCTRL, 0, 32, 0x2);
595 //wait_on_value(BIT17|BIT16, 0, CM1_ABE_PDM_CLKCTRL, LDELAY);
596 sr32(CM1_ABE_DMIC_CLKCTRL, 0, 32, 0x2);
597 //wait_on_value(BIT17|BIT16, 0, CM1_ABE_DMIC_CLKCTRL, LDELAY);
598 sr32(CM1_ABE_MCASP_CLKCTRL, 0, 32, 0x2);
599 //wait_on_value(BIT17|BIT16, 0, CM1_ABE_MCASP_CLKCTRL, LDELAY);
600 sr32(CM1_ABE_MCBSP1_CLKCTRL, 0, 32, 0x08000002);
601 //wait_on_value(BIT17|BIT16, 0, CM1_ABE_MCBSP1_CLKCTRL, LDELAY);
602 sr32(CM1_ABE_MCBSP2_CLKCTRL, 0, 32, 0x08000002);
603 //wait_on_value(BIT17|BIT16, 0, CM1_ABE_MCBSP2_CLKCTRL, LDELAY);
604 sr32(CM1_ABE_MCBSP3_CLKCTRL, 0, 32, 0x08000002);
605 //wait_on_value(BIT17|BIT16, 0, CM1_ABE_MCBSP3_CLKCTRL, LDELAY);
606 sr32(CM1_ABE_SLIMBUS_CLKCTRL, 0, 32, 0xf02);
607 //wait_on_value(BIT17|BIT16, 0, CM1_ABE_SLIMBUS_CLKCTRL, LDELAY);
608 sr32(CM1_ABE_TIMER5_CLKCTRL, 0, 32, 0x2);
609 //wait_on_value(BIT17|BIT16, 0, CM1_ABE_TIMER5_CLKCTRL, LDELAY);
610 sr32(CM1_ABE_TIMER6_CLKCTRL, 0, 32, 0x2);
611 //wait_on_value(BIT17|BIT16, 0, CM1_ABE_TIMER6_CLKCTRL, LDELAY);
612 sr32(CM1_ABE_TIMER7_CLKCTRL, 0, 32, 0x2);
613 //wait_on_value(BIT17|BIT16, 0, CM1_ABE_TIMER7_CLKCTRL, LDELAY);
614 sr32(CM1_ABE_TIMER8_CLKCTRL, 0, 32, 0x2);
615 //wait_on_value(BIT17|BIT16, 0, CM1_ABE_TIMER8_CLKCTRL, LDELAY);
616 sr32(CM1_ABE_WDT3_CLKCTRL, 0, 32, 0x2);
617 //wait_on_value(BIT17|BIT16, 0, CM1_ABE_WDT3_CLKCTRL, LDELAY);
618 /* Disable sleep transitions */
619 sr32(CM1_ABE_CLKSTCTRL, 0, 32, 0x0);
622 sr32(CM_L4PER_CLKSTCTRL, 0, 32, 0x2);
623 sr32(CM_L4PER_DMTIMER10_CLKCTRL, 0, 32, 0x2);
624 wait_on_value(BIT17|BIT16, 0, CM_L4PER_DMTIMER10_CLKCTRL, LDELAY);
625 sr32(CM_L4PER_DMTIMER11_CLKCTRL, 0, 32, 0x2);
626 wait_on_value(BIT17|BIT16, 0, CM_L4PER_DMTIMER11_CLKCTRL, LDELAY);
627 sr32(CM_L4PER_DMTIMER2_CLKCTRL, 0, 32, 0x2);
628 wait_on_value(BIT17|BIT16, 0, CM_L4PER_DMTIMER2_CLKCTRL, LDELAY);
629 sr32(CM_L4PER_DMTIMER3_CLKCTRL, 0, 32, 0x2);
630 wait_on_value(BIT17|BIT16, 0, CM_L4PER_DMTIMER3_CLKCTRL, LDELAY);
631 sr32(CM_L4PER_DMTIMER4_CLKCTRL, 0, 32, 0x2);
632 wait_on_value(BIT17|BIT16, 0, CM_L4PER_DMTIMER4_CLKCTRL, LDELAY);
633 sr32(CM_L4PER_DMTIMER9_CLKCTRL, 0, 32, 0x2);
634 wait_on_value(BIT17|BIT16, 0, CM_L4PER_DMTIMER9_CLKCTRL, LDELAY);
637 sr32(CM_L4PER_GPIO2_CLKCTRL, 0 ,32, 0x1);
638 wait_on_value(BIT17|BIT16, 0, CM_L4PER_GPIO2_CLKCTRL, LDELAY);
639 sr32(CM_L4PER_GPIO3_CLKCTRL, 0, 32, 0x1);
640 wait_on_value(BIT17|BIT16, 0, CM_L4PER_GPIO3_CLKCTRL, LDELAY);
641 sr32(CM_L4PER_GPIO4_CLKCTRL, 0, 32, 0x1);
642 wait_on_value(BIT17|BIT16, 0, CM_L4PER_GPIO4_CLKCTRL, LDELAY);
643 sr32(CM_L4PER_GPIO5_CLKCTRL, 0, 32, 0x1);
644 wait_on_value(BIT17|BIT16, 0, CM_L4PER_GPIO5_CLKCTRL, LDELAY);
645 sr32(CM_L4PER_GPIO6_CLKCTRL, 0, 32, 0x1);
646 wait_on_value(BIT17|BIT16, 0, CM_L4PER_GPIO6_CLKCTRL, LDELAY);
648 sr32(CM_L4PER_HDQ1W_CLKCTRL, 0, 32, 0x2);
651 sr32(CM_L4PER_I2C1_CLKCTRL, 0, 32, 0x2);
652 wait_on_value(BIT17|BIT16, 0, CM_L4PER_I2C1_CLKCTRL, LDELAY);
653 sr32(CM_L4PER_I2C2_CLKCTRL, 0, 32, 0x2);
654 wait_on_value(BIT17|BIT16, 0, CM_L4PER_I2C2_CLKCTRL, LDELAY);
655 sr32(CM_L4PER_I2C3_CLKCTRL, 0, 32, 0x2);
656 wait_on_value(BIT17|BIT16, 0, CM_L4PER_I2C3_CLKCTRL, LDELAY);
657 sr32(CM_L4PER_I2C4_CLKCTRL, 0, 32, 0x2);
658 wait_on_value(BIT17|BIT16, 0, CM_L4PER_I2C4_CLKCTRL, LDELAY);
660 sr32(CM_L4PER_MCBSP4_CLKCTRL, 0, 32, 0x2);
661 wait_on_value(BIT17|BIT16, 0, CM_L4PER_MCBSP4_CLKCTRL, LDELAY);
664 sr32(CM_L4PER_MCSPI1_CLKCTRL, 0, 32, 0x2);
665 wait_on_value(BIT17|BIT16, 0, CM_L4PER_MCSPI1_CLKCTRL, LDELAY);
666 sr32(CM_L4PER_MCSPI2_CLKCTRL, 0, 32, 0x2);
667 wait_on_value(BIT17|BIT16, 0, CM_L4PER_MCSPI2_CLKCTRL, LDELAY);
668 sr32(CM_L4PER_MCSPI3_CLKCTRL, 0, 32, 0x2);
669 wait_on_value(BIT17|BIT16, 0, CM_L4PER_MCSPI3_CLKCTRL, LDELAY);
670 sr32(CM_L4PER_MCSPI4_CLKCTRL, 0, 32, 0x2);
671 wait_on_value(BIT17|BIT16, 0, CM_L4PER_MCSPI4_CLKCTRL, LDELAY);
674 sr32(CM_L3INIT_HSMMC1_CLKCTRL, 0, 2, 0x2);
675 sr32(CM_L3INIT_HSMMC1_CLKCTRL, 24, 1, 0x1);
676 //wait_on_value(BIT18|BIT17|BIT16, 0, CM_L3INIT_HSMMC1_CLKCTRL, LDELAY);
677 sr32(CM_L3INIT_HSMMC2_CLKCTRL, 0, 2, 0x2);
678 sr32(CM_L3INIT_HSMMC2_CLKCTRL, 24, 1, 0x1);
679 //wait_on_value(BIT18|BIT17|BIT16, 0, CM_L3INIT_HSMMC2_CLKCTRL, LDELAY);
680 sr32(CM_L4PER_MMCSD3_CLKCTRL, 0, 32, 0x2);
681 wait_on_value(BIT18|BIT17|BIT16, 0, CM_L4PER_MMCSD3_CLKCTRL, LDELAY);
682 sr32(CM_L4PER_MMCSD4_CLKCTRL, 0, 32, 0x2);
683 wait_on_value(BIT18|BIT17|BIT16, 0, CM_L4PER_MMCSD4_CLKCTRL, LDELAY);
684 sr32(CM_L4PER_MMCSD5_CLKCTRL, 0, 32, 0x2);
685 wait_on_value(BIT17|BIT16, 0, CM_L4PER_MMCSD5_CLKCTRL, LDELAY);
688 sr32(CM_L4PER_UART1_CLKCTRL, 0, 32, 0x2);
689 wait_on_value(BIT17|BIT16, 0, CM_L4PER_UART1_CLKCTRL, LDELAY);
690 sr32(CM_L4PER_UART2_CLKCTRL, 0, 32, 0x2);
691 wait_on_value(BIT17|BIT16, 0, CM_L4PER_UART2_CLKCTRL, LDELAY);
692 sr32(CM_L4PER_UART3_CLKCTRL, 0, 32, 0x2);
693 wait_on_value(BIT17|BIT16, 0, CM_L4PER_UART3_CLKCTRL, LDELAY);
694 sr32(CM_L4PER_UART4_CLKCTRL, 0, 32, 0x2);
695 wait_on_value(BIT17|BIT16, 0, CM_L4PER_UART4_CLKCTRL, LDELAY);
698 sr32(CM_WKUP_GPIO1_CLKCTRL, 0, 32, 0x1);
699 wait_on_value(BIT17|BIT16, 0, CM_WKUP_GPIO1_CLKCTRL, LDELAY);
700 sr32(CM_WKUP_TIMER1_CLKCTRL, 0, 32, 0x01000002);
701 wait_on_value(BIT17|BIT16, 0, CM_WKUP_TIMER1_CLKCTRL, LDELAY);
703 sr32(CM_WKUP_KEYBOARD_CLKCTRL, 0, 32, 0x2);
704 wait_on_value(BIT17|BIT16, 0, CM_WKUP_KEYBOARD_CLKCTRL, LDELAY);
706 sr32(CM_SDMA_CLKSTCTRL, 0, 32, 0x0);
707 sr32(CM_MEMIF_CLKSTCTRL, 0, 32, 0x3);
708 sr32(CM_MEMIF_EMIF_1_CLKCTRL, 0, 32, 0x1);
709 wait_on_value(BIT17|BIT16, 0, CM_MEMIF_EMIF_1_CLKCTRL, LDELAY);
710 sr32(CM_MEMIF_EMIF_2_CLKCTRL, 0, 32, 0x1);
711 wait_on_value(BIT17|BIT16, 0, CM_MEMIF_EMIF_2_CLKCTRL, LDELAY);
712 sr32(CM_D2D_CLKSTCTRL, 0, 32, 0x3);
713 sr32(CM_L3_2_GPMC_CLKCTRL, 0, 32, 0x1);
714 wait_on_value(BIT17|BIT16, 0, CM_L3_2_GPMC_CLKCTRL, LDELAY);
715 sr32(CM_L3INSTR_L3_3_CLKCTRL, 0, 32, 0x1);
716 wait_on_value(BIT17|BIT16, 0, CM_L3INSTR_L3_3_CLKCTRL, LDELAY);
717 sr32(CM_L3INSTR_L3_INSTR_CLKCTRL, 0, 32, 0x1);
718 wait_on_value(BIT17|BIT16, 0, CM_L3INSTR_L3_INSTR_CLKCTRL, LDELAY);
719 sr32(CM_L3INSTR_OCP_WP1_CLKCTRL, 0, 32, 0x1);
720 wait_on_value(BIT17|BIT16, 0, CM_L3INSTR_OCP_WP1_CLKCTRL, LDELAY);
723 sr32(CM_WKUP_WDT2_CLKCTRL, 0, 32, 0x2);
724 wait_on_value(BIT17|BIT16, 0, CM_WKUP_WDT2_CLKCTRL, LDELAY);
726 /* Enable Camera clocks */
727 sr32(CM_CAM_CLKSTCTRL, 0, 32, 0x3);
728 sr32(CM_CAM_ISS_CLKCTRL, 0, 32, 0x102);
729 //wait_on_value(BIT18|BIT17|BIT16, 0, CM_CAM_ISS_CLKCTRL, LDELAY);
730 sr32(CM_CAM_FDIF_CLKCTRL, 0, 32, 0x2);
731 //wait_on_value(BIT18|BIT17|BIT16, 0, CM_CAM_FDIF_CLKCTRL, LDELAY);
732 sr32(CM_CAM_CLKSTCTRL, 0, 32, 0x0);
734 /* Enable DSS clocks */
735 /* PM_DSS_PWRSTCTRL ON State and LogicState = 1 (Retention) */
736 *(volatile int*)0x4A307100 = 0x7; //DSS_PRM
737 sr32(CM_DSS_CLKSTCTRL, 0, 32, 0x2);
738 sr32(CM_DSS_DSS_CLKCTRL, 0, 32, 0xf02);
739 //wait_on_value(BIT18|BIT17|BIT16, 0, CM_DSS_DSS_CLKCTRL, LDELAY);
740 sr32(CM_DSS_DEISS_CLKCTRL, 0, 32, 0x2);
741 //wait_on_value(BIT18|BIT17|BIT16, 0, CM_DSS_DEISS_CLKCTRL, LDELAY);
742 /* Check for DSS Clocks */
743 while (((*(volatile int*)0x4A009100) & 0xF00) != 0xE00)
744 /* Set HW_AUTO transition mode */
745 sr32(CM_DSS_CLKSTCTRL, 0, 32, 0x3);
747 /* Enable SGX clocks */
748 sr32(CM_SGX_CLKSTCTRL, 0, 32, 0x2);
749 sr32(CM_SGX_SGX_CLKCTRL, 0, 32, 0x2);
750 //wait_on_value(BIT18|BIT17|BIT16, 0, CM_SGX_SGX_CLKCTRL, LDELAY);
751 /* Check for SGX FCLK and ICLK */
752 while ( (*(volatile int*)0x4A009200) != 0x302 );
753 //sr32(CM_SGX_CLKSTCTRL, 0, 32, 0x0);
754 /* Enable hsi/unipro/usb clocks */
755 sr32(CM_L3INIT_HSI_CLKCTRL, 0, 32, 0x1);
756 //wait_on_value(BIT18|BIT17|BIT16, 0, CM_L3INIT_HSI_CLKCTRL, LDELAY);
757 sr32(CM_L3INIT_UNIPRO1_CLKCTRL, 0, 32, 0x2);
758 //wait_on_value(BIT18|BIT17|BIT16, 0, CM_L3INIT_UNIPRO1_CLKCTRL, LDELAY);
759 sr32(CM_L3INIT_HSUSBHOST_CLKCTRL, 0, 32, 0x2);
760 //wait_on_value(BIT18|BIT17|BIT16, 0, CM_L3INIT_HSUSBHOST_CLKCTRL, LDELAY);
761 sr32(CM_L3INIT_HSUSBOTG_CLKCTRL, 0, 32, 0x1);
762 //wait_on_value(BIT18|BIT17|BIT16, 0, CM_L3INIT_HSUSBOTG_CLKCTRL, LDELAY);
763 sr32(CM_L3INIT_HSUSBTLL_CLKCTRL, 0, 32, 0x1);
764 //wait_on_value(BIT17|BIT16, 0, CM_L3INIT_HSUSBTLL_CLKCTRL, LDELAY);
765 sr32(CM_L3INIT_FSUSB_CLKCTRL, 0, 32, 0x2);
766 //wait_on_value(BIT18|BIT17|BIT16, 0, CM_L3INIT_FSUSB_CLKCTRL, LDELAY);
767 /* enable the 32K, 48M optional clocks and enable the module */
768 sr32(CM_L3INIT_USBPHY_CLKCTRL, 0, 32, 0x301);
769 //wait_on_value(BIT17|BIT16, 0, CM_L3INIT_USBPHY_CLKCTRL, LDELAY);
773 /******************************************************************************
774 * prcm_init() - inits clocks for PRCM as defined in clocks.h
775 * -- called from SRAM, or Flash (using temp SRAM stack).
776 *****************************************************************************/
781 /* Get the sysclk speed from cm_sys_clksel
782 * Set the CM_SYS_CLKSEL in case ROM code has not set
784 __raw_writel(0x7,CM_SYS_CLKSEL);
785 clk_index = readl(CM_SYS_CLKSEL);
787 return; /* Sys clk uninitialized */
788 /* Core DPLL is locked using FREQ update method */
789 /* configure_core_dpll(clk_index - 1); */
791 /* Configure all DPLL's at 100% OPP */
792 configure_mpu_dpll(clk_index - 1);
793 configure_iva_dpll(clk_index - 1);
794 configure_per_dpll(clk_index - 1);
795 configure_abe_dpll(clk_index - 1);
796 configure_usb_dpll(clk_index - 1);
798 #ifdef CONFIG_OMAP4_SDC
799 /* Enable all clocks */