3 * Texas Instruments, <www.ti.com>
4 * Richard Woodruff <r-woodruff2@ti.com>
5 * Rajendra Nayak <rnayak@ti.com>
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 #include <asm/arch/cpu.h>
26 #include <asm/arch/bits.h>
27 #include <asm/arch/clocks.h>
28 #include <asm/arch/mem.h>
29 #include <asm/arch/sys_proto.h>
30 #include <asm/arch/sys_info.h>
31 #include <asm/arch/clocks443x.h>
34 #define CONFIG_OMAP4_SDC 1
36 /* Used to index into DPLL parameter tables */
48 /* Tables having M,N,M2 et al values for different sys_clk speeds
49 * This table is generated only for OPP100
50 * The tables are organized as follows:
51 * Rows : 1 - 12M, 2 - 13M, 3 - 16.8M, 4 - 19.2M, 5 - 26M, 6 - 27M, 7 - 38.4M
55 struct dpll_param mpu_dpll_param[7] = {
57 {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
59 {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
61 {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
63 {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
65 {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
67 {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
70 /* RUN MPU @ 600 MHz */
71 {0x7d, 0x07, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00},
73 {0x69, 0x03, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00},
75 {0x1a, 0x02, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00},
80 struct dpll_param iva_dpll_param[7] = {
82 {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
84 {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
86 {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
88 {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
90 {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
92 {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
94 #ifdef CONFIG_OMAP4_SDC
95 {0x61, 0x03, 0x00, 0x00, 0x04, 0x07, 0x00, 0x00},
97 {0x61, 0x03, 0x00, 0x00, 0x04, 0x07, 0x00, 0x00},
101 /* CORE parameters */
102 struct dpll_param core_dpll_param[7] = {
104 {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
106 {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
108 {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
110 {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
112 {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
114 {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
115 /* 38.4M values - DDR@200MHz*/
116 {0x7d, 0x05, 0x02, 0x05, 0x08, 0x04, 0x06, 0x05},
119 /* CORE parameters - ES2.1 */
120 struct dpll_param core_dpll_param_ddr400[7] = {
122 {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
124 {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
126 {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
128 {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
130 {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
132 {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
133 /* 38.4M values - DDR@400MHz*/
134 {0x7d, 0x05, 0x01, 0x05, 0x08, 0x04, 0x06, 0x05},
137 /* CORE parameters for L3 at 190 MHz - For ES1 only*/
138 struct dpll_param core_dpll_param_l3_190[7] = {
140 {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
142 {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
144 {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
146 {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
148 {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
150 {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
152 #ifdef CONFIG_OMAP4_SDC
154 {0x1f0, 0x18, 0x01, 0x05, 0x08, 0x04, 0x06, 0x05},
155 #else /* Default CORE @166MHz */
156 {0x1b0, 0x18, 0x01, 0x05, 0x08, 0x04, 0x06, 0x05},
159 {0x7d, 0x05, 0x01, 0x05, 0x08, 0x04, 0x06, 0x08},
164 struct dpll_param per_dpll_param[7] = {
166 {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
168 {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
170 {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
172 {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
174 {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
176 {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
180 {0x0a, 0x00, 0x04, 0x03, 0x06, 0x05, 0x02, 0x03},
182 {0x14, 0x00, 0x08, 0x06, 0x0c, 0x09, 0x04, 0x05},
186 struct dpll_param abe_dpll_param[7] = {
188 {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
190 {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
192 {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
194 {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
196 {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
198 {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
200 #ifdef CONFIG_OMAP4_SDC
201 {0x40, 0x18, 0x1, 0x1, 0x0, 0x0, 0x0, 0x0},
203 {0x40, 0x18, 0x1, 0x1, 0x0, 0x0, 0x0, 0x0},
208 struct dpll_param usb_dpll_param[7] = {
210 {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
212 {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
214 {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
216 {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
218 {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
220 {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
222 #ifdef CONFIG_OMAP4_SDC
223 {0x32, 0x1, 0x2, 0x0, 0x0, 0x0, 0x0, 0x0},
225 {0x32, 0x1, 0x2, 0x0, 0x0, 0x0, 0x0, 0x0},
229 static void configure_mpu_dpll(u32 clk_index)
231 struct dpll_param *dpll_param_p;
233 /* Unlock the MPU dpll */
234 sr32(CM_CLKMODE_DPLL_MPU, 0, 3, PLL_MN_POWER_BYPASS);
235 wait_on_value(BIT0, 0, CM_IDLEST_DPLL_MPU, LDELAY);
237 /* Program MPU DPLL */
238 dpll_param_p = &mpu_dpll_param[clk_index];
240 sr32(CM_AUTOIDLE_DPLL_MPU, 0, 3, 0x0); /* Disable DPLL autoidle */
242 /* Set M,N,M2 values */
243 sr32(CM_CLKSEL_DPLL_MPU, 8, 11, dpll_param_p->m);
244 sr32(CM_CLKSEL_DPLL_MPU, 0, 6, dpll_param_p->n);
245 sr32(CM_DIV_M2_DPLL_MPU, 0, 5, dpll_param_p->m2);
246 sr32(CM_DIV_M2_DPLL_MPU, 8, 1, 0x1);
248 /* Lock the mpu dpll */
249 sr32(CM_CLKMODE_DPLL_MPU, 0, 3, PLL_LOCK | 0x10);
250 wait_on_value(BIT0, 1, CM_IDLEST_DPLL_MPU, LDELAY);
253 static void configure_iva_dpll(u32 clk_index)
255 struct dpll_param *dpll_param_p;
257 /* Unlock the IVA dpll */
258 sr32(CM_CLKMODE_DPLL_IVA, 0, 3, PLL_MN_POWER_BYPASS);
259 wait_on_value(BIT0, 0, CM_IDLEST_DPLL_IVA, LDELAY);
261 /* CM_BYPCLK_DPLL_IVA = CORE_X2_CLK/2 */
262 sr32(CM_BYPCLK_DPLL_IVA, 0, 2, 0x1);
264 /* Program IVA DPLL */
265 dpll_param_p = &iva_dpll_param[clk_index];
267 sr32(CM_AUTOIDLE_DPLL_IVA, 0, 3, 0x0); /* Disable DPLL autoidle */
270 sr32(CM_CLKSEL_DPLL_IVA, 8, 11, dpll_param_p->m);
271 sr32(CM_CLKSEL_DPLL_IVA, 0, 7, dpll_param_p->n);
272 sr32(CM_DIV_M4_DPLL_IVA, 0, 5, dpll_param_p->m4);
273 sr32(CM_DIV_M4_DPLL_IVA, 8, 1, 0x1);
274 sr32(CM_DIV_M5_DPLL_IVA, 0, 5, dpll_param_p->m5);
275 sr32(CM_DIV_M5_DPLL_IVA, 8, 1, 0x1);
277 /* Lock the iva dpll */
278 sr32(CM_CLKMODE_DPLL_IVA, 0, 3, PLL_LOCK);
279 wait_on_value(BIT0, 1, CM_IDLEST_DPLL_IVA, LDELAY);
282 static void configure_per_dpll(u32 clk_index)
284 struct dpll_param *dpll_param_p;
286 /* Unlock the PER dpll */
287 sr32(CM_CLKMODE_DPLL_PER, 0, 3, PLL_MN_POWER_BYPASS);
288 wait_on_value(BIT0, 0, CM_IDLEST_DPLL_PER, LDELAY);
290 /* Program PER DPLL */
291 dpll_param_p = &per_dpll_param[clk_index];
293 /* Disable autoidle */
294 sr32(CM_AUTOIDLE_DPLL_PER, 0, 3, 0x0);
296 sr32(CM_CLKSEL_DPLL_PER, 8, 11, dpll_param_p->m);
297 sr32(CM_CLKSEL_DPLL_PER, 0, 6, dpll_param_p->n);
298 sr32(CM_DIV_M2_DPLL_PER, 0, 5, dpll_param_p->m2);
299 sr32(CM_DIV_M3_DPLL_PER, 0, 5, dpll_param_p->m3);
300 sr32(CM_DIV_M4_DPLL_PER, 0, 5, dpll_param_p->m4);
301 sr32(CM_DIV_M5_DPLL_PER, 0, 5, dpll_param_p->m5);
302 sr32(CM_DIV_M6_DPLL_PER, 0, 5, dpll_param_p->m6);
303 sr32(CM_DIV_M7_DPLL_PER, 0, 5, dpll_param_p->m7);
306 sr32(CM_DIV_M2_DPLL_PER, 8, 1, 0x1);
307 sr32(CM_DIV_M3_DPLL_PER, 8, 1, 0x1);
308 sr32(CM_DIV_M4_DPLL_PER, 8, 1, 0x1);
309 sr32(CM_DIV_M5_DPLL_PER, 8, 1, 0x1);
310 sr32(CM_DIV_M6_DPLL_PER, 8, 1, 0x1);
311 sr32(CM_DIV_M7_DPLL_PER, 8, 1, 0x1);
313 /* Lock the per dpll */
314 sr32(CM_CLKMODE_DPLL_PER, 0, 3, PLL_LOCK);
315 wait_on_value(BIT0, 1, CM_IDLEST_DPLL_PER, LDELAY);
318 static void configure_abe_dpll(u32 clk_index)
320 struct dpll_param *dpll_param_p;
322 /* Select sys_clk as ref clk for ABE dpll */
323 sr32(CM_ABE_PLL_REF_CLKSEL, 0, 32, 0x0);
325 /* Enable slimbus and pad clocks */
326 sr32(CM_CLKSEL_ABE, 0, 32, 0x500);
328 /* Unlock the ABE dpll */
329 sr32(CM_CLKMODE_DPLL_ABE, 0, 3, PLL_MN_POWER_BYPASS);
330 wait_on_value(BIT0, 0, CM_IDLEST_DPLL_ABE, LDELAY);
332 /* Program ABE DPLL */
333 dpll_param_p = &abe_dpll_param[clk_index];
335 /* Disable autoidle */
336 sr32(CM_AUTOIDLE_DPLL_ABE, 0, 3, 0x0);
338 sr32(CM_CLKSEL_DPLL_ABE, 8, 11, dpll_param_p->m);
339 sr32(CM_CLKSEL_DPLL_ABE, 0, 6, dpll_param_p->n);
341 /* Force DPLL CLKOUTHIF to stay enabled */
342 sr32(CM_DIV_M2_DPLL_ABE, 0, 32, 0x500);
343 sr32(CM_DIV_M2_DPLL_ABE, 0, 5, dpll_param_p->m2);
344 sr32(CM_DIV_M2_DPLL_ABE, 8, 1, 0x1);
345 /* Force DPLL CLKOUTHIF to stay enabled */
346 sr32(CM_DIV_M3_DPLL_ABE, 0, 32, 0x100);
347 sr32(CM_DIV_M3_DPLL_ABE, 0, 5, dpll_param_p->m3);
348 sr32(CM_DIV_M3_DPLL_ABE, 8, 1, 0x1);
350 /* Lock the abe dpll */
351 sr32(CM_CLKMODE_DPLL_ABE, 0, 3, PLL_LOCK);
352 wait_on_value(BIT0, 1, CM_IDLEST_DPLL_ABE, LDELAY);
355 static void configure_usb_dpll(u32 clk_index)
357 struct dpll_param *dpll_param_p;
359 /* Select the 60Mhz clock 480/8 = 60*/
360 sr32(CM_CLKSEL_USB_60MHz, 0, 32, 0x1);
362 /* Unlock the USB dpll */
363 sr32(CM_CLKMODE_DPLL_USB, 0, 3, PLL_MN_POWER_BYPASS);
364 wait_on_value(BIT0, 0, CM_IDLEST_DPLL_USB, LDELAY);
366 /* Program USB DPLL */
367 dpll_param_p = &usb_dpll_param[clk_index];
369 /* Disable autoidle */
370 sr32(CM_AUTOIDLE_DPLL_USB, 0, 3, 0x0);
372 sr32(CM_CLKSEL_DPLL_USB, 8, 11, dpll_param_p->m);
373 sr32(CM_CLKSEL_DPLL_USB, 0, 6, dpll_param_p->n);
375 /* Force DPLL CLKOUT to stay active */
376 sr32(CM_DIV_M2_DPLL_USB, 0, 32, 0x100);
377 sr32(CM_DIV_M2_DPLL_USB, 0, 5, dpll_param_p->m2);
378 sr32(CM_DIV_M2_DPLL_USB, 8, 1, 0x1);
379 sr32(CM_CLKDCOLDO_DPLL_USB, 8, 1, 0x1);
381 /* Lock the usb dpll */
382 sr32(CM_CLKMODE_DPLL_USB, 0, 3, PLL_LOCK);
383 wait_on_value(BIT0, 1, CM_IDLEST_DPLL_USB, LDELAY);
385 /* force enable the CLKDCOLDO clock */
386 sr32(CM_CLKDCOLDO_DPLL_USB, 0, 32, 0x100);
391 /* to remove warning about unused function; will be deleted in decruft patch */
392 static void configure_core_dpll(int clk_index)
394 struct dpll_param *dpll_param_p;
396 /* Get the sysclk speed from cm_sys_clksel
397 * Set it to 38.4 MHz, in case ROM code is bypassed
402 /* CORE_CLK=CORE_X2_CLK/2, L3_CLK=CORE_CLK/2, L4_CLK=L3_CLK/2 */
403 sr32(CM_CLKSEL_CORE, 0, 32, 0x110);
405 /* Unlock the CORE dpll */
406 sr32(CM_CLKMODE_DPLL_CORE, 0, 3, PLL_MN_POWER_BYPASS);
407 wait_on_value(BIT0, 0, CM_IDLEST_DPLL_CORE, LDELAY);
409 /* Program Core DPLL */
410 switch (omap_revision()) {
412 dpll_param_p = &core_dpll_param_l3_190[clk_index];
415 dpll_param_p = &core_dpll_param[clk_index];
419 dpll_param_p = &core_dpll_param_ddr400[clk_index];
423 /* Disable autoidle */
424 sr32(CM_AUTOIDLE_DPLL_CORE, 0, 3, 0x0);
426 sr32(CM_CLKSEL_DPLL_CORE, 8, 11, dpll_param_p->m);
427 sr32(CM_CLKSEL_DPLL_CORE, 0, 6, dpll_param_p->n);
428 sr32(CM_DIV_M2_DPLL_CORE, 0, 5, dpll_param_p->m2);
429 sr32(CM_DIV_M3_DPLL_CORE, 0, 5, dpll_param_p->m3);
430 sr32(CM_DIV_M4_DPLL_CORE, 0, 5, dpll_param_p->m4);
431 sr32(CM_DIV_M5_DPLL_CORE, 0, 5, dpll_param_p->m5);
432 sr32(CM_DIV_M6_DPLL_CORE, 0, 5, dpll_param_p->m6);
433 sr32(CM_DIV_M7_DPLL_CORE, 0, 5, dpll_param_p->m7);
435 if (omap_revision() == OMAP4430_ES1_0) {
436 /* Do this only on ES1.0 */
437 sr32(CM_DIV_M2_DPLL_CORE, 8, 1, 0x1);
438 sr32(CM_DIV_M3_DPLL_CORE, 8, 1, 0x1);
439 sr32(CM_DIV_M4_DPLL_CORE, 8, 1, 0x1);
440 sr32(CM_DIV_M5_DPLL_CORE, 8, 1, 0x1);
441 sr32(CM_DIV_M6_DPLL_CORE, 8, 1, 0x0);
442 sr32(CM_DIV_M7_DPLL_CORE, 8, 1, 0x1);
445 /* Lock the core dpll */
446 sr32(CM_CLKMODE_DPLL_CORE, 0, 3, PLL_LOCK);
447 wait_on_value(BIT0, 1, CM_IDLEST_DPLL_CORE, LDELAY);
451 void configure_core_dpll_no_lock(void)
453 struct dpll_param *dpll_param_p = NULL;
456 /* Get the sysclk speed from cm_sys_clksel
457 * Set it to 38.4 MHz, in case ROM code is bypassed
459 __raw_writel(0x7, CM_SYS_CLKSEL);
462 clk_index = clk_index - 1;
463 /* CORE_CLK=CORE_X2_CLK/2, L3_CLK=CORE_CLK/2, L4_CLK=L3_CLK/2 */
464 sr32(CM_CLKSEL_CORE, 0, 32, 0x110);
466 /* Unlock the CORE dpll */
467 sr32(CM_CLKMODE_DPLL_CORE, 0, 3, PLL_MN_POWER_BYPASS);
468 wait_on_value(BIT0, 0, CM_IDLEST_DPLL_CORE, LDELAY);
470 /* Program Core DPLL */
471 switch (omap_revision()) {
473 dpll_param_p = &core_dpll_param_l3_190[clk_index];
476 dpll_param_p = &core_dpll_param[clk_index];
480 dpll_param_p = &core_dpll_param_ddr400[clk_index];
484 /* Disable autoidle */
485 sr32(CM_AUTOIDLE_DPLL_CORE, 0, 3, 0x0);
487 sr32(CM_CLKSEL_DPLL_CORE, 8, 11, dpll_param_p->m);
488 sr32(CM_CLKSEL_DPLL_CORE, 0, 6, dpll_param_p->n);
489 sr32(CM_DIV_M2_DPLL_CORE, 0, 5, dpll_param_p->m2);
490 sr32(CM_DIV_M3_DPLL_CORE, 0, 5, dpll_param_p->m3);
491 sr32(CM_DIV_M4_DPLL_CORE, 0, 5, dpll_param_p->m4);
492 sr32(CM_DIV_M5_DPLL_CORE, 0, 5, dpll_param_p->m5);
493 sr32(CM_DIV_M6_DPLL_CORE, 0, 5, dpll_param_p->m6);
494 sr32(CM_DIV_M7_DPLL_CORE, 0, 5, dpll_param_p->m7);
496 sr32(CM_DIV_M2_DPLL_CORE, 8, 1, 0x1);
497 sr32(CM_DIV_M3_DPLL_CORE, 8, 1, 0x1);
498 sr32(CM_DIV_M4_DPLL_CORE, 8, 1, 0x1);
499 sr32(CM_DIV_M5_DPLL_CORE, 8, 1, 0x1);
500 sr32(CM_DIV_M6_DPLL_CORE, 8, 1, 0x0);
501 sr32(CM_DIV_M7_DPLL_CORE, 8, 1, 0x1);
504 void lock_core_dpll(void)
506 /* Lock the core dpll */
507 sr32(CM_CLKMODE_DPLL_CORE, 0, 3, PLL_LOCK);
508 wait_on_value(BIT0, 1, CM_IDLEST_DPLL_CORE, LDELAY);
511 void lock_core_dpll_shadow(void)
513 struct dpll_param *dpll_param_p = NULL;
515 /* Lock the core dpll using freq update method */
516 __raw_writel(10, 0x4A004120); /* CM_CLKMODE_DPLL_CORE */
518 switch (omap_revision()) {
520 dpll_param_p = &core_dpll_param_l3_190[6];
523 dpll_param_p = &core_dpll_param[6];
527 dpll_param_p = &core_dpll_param_ddr400[6];
531 /* CM_SHADOW_FREQ_CONFIG1: DLL_OVERRIDE = 1(hack), DLL_RESET = 1,
532 * DPLL_CORE_M2_DIV =1, DPLL_CORE_DPLL_EN = 0x7, FREQ_UPDATE = 1
534 __raw_writel(0x70D | (dpll_param_p->m2 << 11), 0x4A004260);
537 * if the EMIF never goes idle, and eg, if ROM enabled USB,
538 * we loop for a very very long time here becuse shadow updates wait
542 /* Wait for Freq_Update to get cleared: CM_SHADOW_FREQ_CONFIG1 */
543 while (__raw_readl(0x4A004260) & 1)
546 /* Wait for DPLL to Lock : CM_IDLEST_DPLL_CORE */
547 wait_on_value(BIT0, 1, CM_IDLEST_DPLL_CORE, LDELAY);
548 /* lock_core_dpll(); */
551 static void enable_all_clocks(void)
553 /* Enable Ducati clocks */
554 sr32(CM_DUCATI_DUCATI_CLKCTRL, 0, 32, 0x1);
555 sr32(CM_DUCATI_CLKSTCTRL, 0, 32, 0x2);
557 wait_on_value(BIT8, BIT8, CM_DUCATI_CLKSTCTRL, LDELAY);
559 /* Enable ivahd and sl2 clocks */
560 sr32(IVAHD_IVAHD_CLKCTRL, 0, 32, 0x1);
561 sr32(IVAHD_SL2_CLKCTRL, 0, 32, 0x1);
562 sr32(IVAHD_CLKSTCTRL, 0, 32, 0x2);
564 wait_on_value(BIT8, BIT8, IVAHD_CLKSTCTRL, LDELAY);
566 /* Enable Tesla clocks */
567 sr32(DSP_DSP_CLKCTRL, 0, 32, 0x1);
568 sr32(DSP_CLKSTCTRL, 0, 32, 0x2);
570 wait_on_value(BIT8, BIT8, DSP_CLKSTCTRL, LDELAY);
572 /* wait for tesla to become accessible */
575 sr32(CM1_ABE_CLKSTCTRL, 0, 32, 0x3);
576 sr32(CM1_ABE_AESS_CLKCTRL, 0, 32, 0x2);
577 sr32(CM1_ABE_PDM_CLKCTRL, 0, 32, 0x2);
578 sr32(CM1_ABE_DMIC_CLKCTRL, 0, 32, 0x2);
579 sr32(CM1_ABE_MCASP_CLKCTRL, 0, 32, 0x2);
580 sr32(CM1_ABE_MCBSP1_CLKCTRL, 0, 32, 0x08000002);
581 sr32(CM1_ABE_MCBSP2_CLKCTRL, 0, 32, 0x08000002);
582 sr32(CM1_ABE_MCBSP3_CLKCTRL, 0, 32, 0x08000002);
583 sr32(CM1_ABE_SLIMBUS_CLKCTRL, 0, 32, 0xf02);
584 sr32(CM1_ABE_TIMER5_CLKCTRL, 0, 32, 0x2);
585 sr32(CM1_ABE_TIMER6_CLKCTRL, 0, 32, 0x2);
586 sr32(CM1_ABE_TIMER7_CLKCTRL, 0, 32, 0x2);
587 sr32(CM1_ABE_TIMER8_CLKCTRL, 0, 32, 0x2);
588 sr32(CM1_ABE_WDT3_CLKCTRL, 0, 32, 0x2);
589 /* Disable sleep transitions */
590 sr32(CM1_ABE_CLKSTCTRL, 0, 32, 0x0);
593 sr32(CM_L4PER_CLKSTCTRL, 0, 32, 0x2);
594 sr32(CM_L4PER_DMTIMER10_CLKCTRL, 0, 32, 0x2);
595 wait_on_value(BIT17|BIT16, 0, CM_L4PER_DMTIMER10_CLKCTRL, LDELAY);
596 sr32(CM_L4PER_DMTIMER11_CLKCTRL, 0, 32, 0x2);
597 wait_on_value(BIT17|BIT16, 0, CM_L4PER_DMTIMER11_CLKCTRL, LDELAY);
598 sr32(CM_L4PER_DMTIMER2_CLKCTRL, 0, 32, 0x2);
599 wait_on_value(BIT17|BIT16, 0, CM_L4PER_DMTIMER2_CLKCTRL, LDELAY);
600 sr32(CM_L4PER_DMTIMER3_CLKCTRL, 0, 32, 0x2);
601 wait_on_value(BIT17|BIT16, 0, CM_L4PER_DMTIMER3_CLKCTRL, LDELAY);
602 sr32(CM_L4PER_DMTIMER4_CLKCTRL, 0, 32, 0x2);
603 wait_on_value(BIT17|BIT16, 0, CM_L4PER_DMTIMER4_CLKCTRL, LDELAY);
604 sr32(CM_L4PER_DMTIMER9_CLKCTRL, 0, 32, 0x2);
605 wait_on_value(BIT17|BIT16, 0, CM_L4PER_DMTIMER9_CLKCTRL, LDELAY);
608 sr32(CM_L4PER_GPIO2_CLKCTRL, 0, 32, 0x1);
609 wait_on_value(BIT17|BIT16, 0, CM_L4PER_GPIO2_CLKCTRL, LDELAY);
610 sr32(CM_L4PER_GPIO3_CLKCTRL, 0, 32, 0x1);
611 wait_on_value(BIT17|BIT16, 0, CM_L4PER_GPIO3_CLKCTRL, LDELAY);
612 sr32(CM_L4PER_GPIO4_CLKCTRL, 0, 32, 0x1);
613 wait_on_value(BIT17|BIT16, 0, CM_L4PER_GPIO4_CLKCTRL, LDELAY);
614 sr32(CM_L4PER_GPIO5_CLKCTRL, 0, 32, 0x1);
615 wait_on_value(BIT17|BIT16, 0, CM_L4PER_GPIO5_CLKCTRL, LDELAY);
616 sr32(CM_L4PER_GPIO6_CLKCTRL, 0, 32, 0x1);
617 wait_on_value(BIT17|BIT16, 0, CM_L4PER_GPIO6_CLKCTRL, LDELAY);
619 sr32(CM_L4PER_HDQ1W_CLKCTRL, 0, 32, 0x2);
622 sr32(CM_L4PER_I2C1_CLKCTRL, 0, 32, 0x2);
623 wait_on_value(BIT17|BIT16, 0, CM_L4PER_I2C1_CLKCTRL, LDELAY);
624 sr32(CM_L4PER_I2C2_CLKCTRL, 0, 32, 0x2);
625 wait_on_value(BIT17|BIT16, 0, CM_L4PER_I2C2_CLKCTRL, LDELAY);
626 sr32(CM_L4PER_I2C3_CLKCTRL, 0, 32, 0x2);
627 wait_on_value(BIT17|BIT16, 0, CM_L4PER_I2C3_CLKCTRL, LDELAY);
628 sr32(CM_L4PER_I2C4_CLKCTRL, 0, 32, 0x2);
629 wait_on_value(BIT17|BIT16, 0, CM_L4PER_I2C4_CLKCTRL, LDELAY);
631 sr32(CM_L4PER_MCBSP4_CLKCTRL, 0, 32, 0x2);
632 wait_on_value(BIT17|BIT16, 0, CM_L4PER_MCBSP4_CLKCTRL, LDELAY);
635 sr32(CM_L4PER_MCSPI1_CLKCTRL, 0, 32, 0x2);
636 wait_on_value(BIT17|BIT16, 0, CM_L4PER_MCSPI1_CLKCTRL, LDELAY);
637 sr32(CM_L4PER_MCSPI2_CLKCTRL, 0, 32, 0x2);
638 wait_on_value(BIT17|BIT16, 0, CM_L4PER_MCSPI2_CLKCTRL, LDELAY);
639 sr32(CM_L4PER_MCSPI3_CLKCTRL, 0, 32, 0x2);
640 wait_on_value(BIT17|BIT16, 0, CM_L4PER_MCSPI3_CLKCTRL, LDELAY);
641 sr32(CM_L4PER_MCSPI4_CLKCTRL, 0, 32, 0x2);
642 wait_on_value(BIT17|BIT16, 0, CM_L4PER_MCSPI4_CLKCTRL, LDELAY);
645 sr32(CM_L3INIT_HSMMC1_CLKCTRL, 0, 2, 0x2);
646 sr32(CM_L3INIT_HSMMC1_CLKCTRL, 24, 1, 0x1);
647 sr32(CM_L3INIT_HSMMC2_CLKCTRL, 0, 2, 0x2);
648 sr32(CM_L3INIT_HSMMC2_CLKCTRL, 24, 1, 0x1);
649 sr32(CM_L4PER_MMCSD3_CLKCTRL, 0, 32, 0x2);
650 wait_on_value(BIT18|BIT17|BIT16, 0, CM_L4PER_MMCSD3_CLKCTRL, LDELAY);
651 sr32(CM_L4PER_MMCSD4_CLKCTRL, 0, 32, 0x2);
652 wait_on_value(BIT18|BIT17|BIT16, 0, CM_L4PER_MMCSD4_CLKCTRL, LDELAY);
653 sr32(CM_L4PER_MMCSD5_CLKCTRL, 0, 32, 0x2);
654 wait_on_value(BIT17|BIT16, 0, CM_L4PER_MMCSD5_CLKCTRL, LDELAY);
657 sr32(CM_L4PER_UART1_CLKCTRL, 0, 32, 0x2);
658 wait_on_value(BIT17|BIT16, 0, CM_L4PER_UART1_CLKCTRL, LDELAY);
659 sr32(CM_L4PER_UART2_CLKCTRL, 0, 32, 0x2);
660 wait_on_value(BIT17|BIT16, 0, CM_L4PER_UART2_CLKCTRL, LDELAY);
661 sr32(CM_L4PER_UART3_CLKCTRL, 0, 32, 0x2);
662 wait_on_value(BIT17|BIT16, 0, CM_L4PER_UART3_CLKCTRL, LDELAY);
663 sr32(CM_L4PER_UART4_CLKCTRL, 0, 32, 0x2);
664 wait_on_value(BIT17|BIT16, 0, CM_L4PER_UART4_CLKCTRL, LDELAY);
667 sr32(CM_WKUP_GPIO1_CLKCTRL, 0, 32, 0x1);
668 wait_on_value(BIT17|BIT16, 0, CM_WKUP_GPIO1_CLKCTRL, LDELAY);
669 sr32(CM_WKUP_TIMER1_CLKCTRL, 0, 32, 0x01000002);
670 wait_on_value(BIT17|BIT16, 0, CM_WKUP_TIMER1_CLKCTRL, LDELAY);
672 sr32(CM_WKUP_KEYBOARD_CLKCTRL, 0, 32, 0x2);
673 wait_on_value(BIT17|BIT16, 0, CM_WKUP_KEYBOARD_CLKCTRL, LDELAY);
675 sr32(CM_SDMA_CLKSTCTRL, 0, 32, 0x0);
676 sr32(CM_MEMIF_CLKSTCTRL, 0, 32, 0x3);
677 sr32(CM_MEMIF_EMIF_1_CLKCTRL, 0, 32, 0x1);
678 wait_on_value(BIT17|BIT16, 0, CM_MEMIF_EMIF_1_CLKCTRL, LDELAY);
679 sr32(CM_MEMIF_EMIF_2_CLKCTRL, 0, 32, 0x1);
680 wait_on_value(BIT17|BIT16, 0, CM_MEMIF_EMIF_2_CLKCTRL, LDELAY);
681 sr32(CM_D2D_CLKSTCTRL, 0, 32, 0x3);
682 sr32(CM_L3_2_GPMC_CLKCTRL, 0, 32, 0x1);
683 wait_on_value(BIT17|BIT16, 0, CM_L3_2_GPMC_CLKCTRL, LDELAY);
684 sr32(CM_L3INSTR_L3_3_CLKCTRL, 0, 32, 0x1);
685 wait_on_value(BIT17|BIT16, 0, CM_L3INSTR_L3_3_CLKCTRL, LDELAY);
686 sr32(CM_L3INSTR_L3_INSTR_CLKCTRL, 0, 32, 0x1);
687 wait_on_value(BIT17|BIT16, 0, CM_L3INSTR_L3_INSTR_CLKCTRL, LDELAY);
688 sr32(CM_L3INSTR_OCP_WP1_CLKCTRL, 0, 32, 0x1);
689 wait_on_value(BIT17|BIT16, 0, CM_L3INSTR_OCP_WP1_CLKCTRL, LDELAY);
692 sr32(CM_WKUP_WDT2_CLKCTRL, 0, 32, 0x2);
693 wait_on_value(BIT17|BIT16, 0, CM_WKUP_WDT2_CLKCTRL, LDELAY);
695 /* Enable Camera clocks */
696 sr32(CM_CAM_CLKSTCTRL, 0, 32, 0x3);
697 sr32(CM_CAM_ISS_CLKCTRL, 0, 32, 0x102);
698 sr32(CM_CAM_FDIF_CLKCTRL, 0, 32, 0x2);
699 sr32(CM_CAM_CLKSTCTRL, 0, 32, 0x0);
701 /* Enable DSS clocks */
702 /* PM_DSS_PWRSTCTRL ON State and LogicState = 1 (Retention) */
703 __raw_writel(7, 0x4A307100); /* DSS_PRM */
705 sr32(CM_DSS_CLKSTCTRL, 0, 32, 0x2);
706 sr32(CM_DSS_DSS_CLKCTRL, 0, 32, 0xf02);
707 sr32(CM_DSS_DEISS_CLKCTRL, 0, 32, 0x2);
709 /* Check for DSS Clocks */
710 while ((__raw_readl(0x4A009100) & 0xF00) != 0xE00)
712 /* Set HW_AUTO transition mode */
713 sr32(CM_DSS_CLKSTCTRL, 0, 32, 0x3);
715 /* Enable SGX clocks */
716 sr32(CM_SGX_CLKSTCTRL, 0, 32, 0x2);
717 sr32(CM_SGX_SGX_CLKCTRL, 0, 32, 0x2);
718 /* Check for SGX FCLK and ICLK */
719 while (__raw_readl(0x4A009200) != 0x302)
721 /* Enable hsi/unipro/usb clocks */
722 sr32(CM_L3INIT_HSI_CLKCTRL, 0, 32, 0x1);
723 sr32(CM_L3INIT_UNIPRO1_CLKCTRL, 0, 32, 0x2);
724 sr32(CM_L3INIT_HSUSBHOST_CLKCTRL, 0, 32, 0x2);
725 sr32(CM_L3INIT_HSUSBOTG_CLKCTRL, 0, 32, 0x1);
726 sr32(CM_L3INIT_HSUSBTLL_CLKCTRL, 0, 32, 0x1);
727 sr32(CM_L3INIT_FSUSB_CLKCTRL, 0, 32, 0x2);
728 /* enable the 32K, 48M optional clocks and enable the module */
729 sr32(CM_L3INIT_USBPHY_CLKCTRL, 0, 32, 0x301);
732 /******************************************************************************
733 * prcm_init() - inits clocks for PRCM as defined in clocks.h
734 * -- called from SRAM, or Flash (using temp SRAM stack).
735 *****************************************************************************/
740 /* Get the sysclk speed from cm_sys_clksel
741 * Set the CM_SYS_CLKSEL in case ROM code has not set
743 __raw_writel(0x7, CM_SYS_CLKSEL);
744 clk_index = readl(CM_SYS_CLKSEL);
746 return; /* Sys clk uninitialized */
747 /* Core DPLL is locked using FREQ update method */
748 /* configure_core_dpll(clk_index - 1); */
750 /* Configure all DPLL's at 100% OPP */
751 configure_mpu_dpll(clk_index - 1);
752 configure_iva_dpll(clk_index - 1);
753 configure_per_dpll(clk_index - 1);
754 configure_abe_dpll(clk_index - 1);
755 configure_usb_dpll(clk_index - 1);
757 #ifdef CONFIG_OMAP4_SDC
758 /* Enable all clocks */