3 * Texas Instruments, <www.ti.com>
4 * Jian Zhang <jzhang@ti.com>
5 * Richard Woodruff <r-woodruff2@ti.com>
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
30 #include <asm/arch/cpu.h>
31 #include <asm/arch/bits.h>
32 #include <asm/arch/mux.h>
33 #include <asm/arch/gpio.h>
34 #include <asm/arch/sys_proto.h>
35 #include <asm/arch/sys_info.h>
36 #include <asm/arch/clocks.h>
37 #include <asm/arch/mem.h>
40 #define CORE_DPLL_PARAM_M2 0x09
41 #define CORE_DPLL_PARAM_M 0x360
42 #define CORE_DPLL_PARAM_N 0xC
44 /* BeagleBoard revisions */
45 #define REVISION_AXBX 0x7
46 #define REVISION_CX 0x6
47 #define REVISION_C4 0x5
48 #define REVISION_XM 0x0
50 /* Used to index into DPLL parameter tables */
58 typedef struct dpll_param dpll_param;
60 /* Following functions are exported from lowlevel_init.S */
61 extern dpll_param *get_mpu_dpll_param();
62 extern dpll_param *get_iva_dpll_param();
63 extern dpll_param *get_core_dpll_param();
64 extern dpll_param *get_per_dpll_param();
66 #define __raw_readl(a) (*(volatile unsigned int *)(a))
67 #define __raw_writel(v, a) (*(volatile unsigned int *)(a) = (v))
68 #define __raw_readw(a) (*(volatile unsigned short *)(a))
69 #define __raw_writew(v, a) (*(volatile unsigned short *)(a) = (v))
71 /*******************************************************
73 * Description: spinning delay to use before udelay works
74 ******************************************************/
75 static inline void delay(unsigned long loops)
77 __asm__ volatile ("1:\n" "subs %0, %1, #1\n"
78 "bne 1b":"=r" (loops):"0"(loops));
81 void udelay (unsigned long usecs) {
85 /*****************************************
87 * Description: Early hardware init.
88 *****************************************/
94 /*************************************************************
95 * get_device_type(): tell if GP/HS/EMU/TST
96 *************************************************************/
97 u32 get_device_type(void)
100 mode = __raw_readl(CONTROL_STATUS) & (DEVICE_MASK);
104 /************************************************
105 * get_sysboot_value(void) - return SYS_BOOT[4:0]
106 ************************************************/
107 u32 get_sysboot_value(void)
110 mode = __raw_readl(CONTROL_STATUS) & (SYSBOOT_MASK);
114 /*************************************************************
115 * Routine: get_mem_type(void) - returns the kind of memory connected
116 * to GPMC that we are trying to boot form. Uses SYS BOOT settings.
117 *************************************************************/
118 u32 get_mem_type(void)
121 if (beagle_revision() == REVISION_XM)
124 u32 mem_type = get_sysboot_value();
166 /******************************************
167 * get_cpu_rev(void) - extract version info
168 ******************************************/
169 u32 get_cpu_rev(void)
172 /* On ES1.0 the IDCODE register is not exposed on L4
173 * so using CPU ID to differentiate
174 * between ES2.0 and ES1.0.
176 __asm__ __volatile__("mrc p15, 0, %0, c0, c0, 0":"=r" (cpuid));
177 if ((cpuid & 0xf) == 0x0)
184 /******************************************
185 * cpu_is_3410(void) - returns true for 3410
186 ******************************************/
187 u32 cpu_is_3410(void)
190 if (get_cpu_rev() < CPU_3430_ES2) {
193 /* read scalability status and return 1 for 3410*/
194 status = __raw_readl(CONTROL_SCALABLE_OMAP_STATUS);
195 /* Check whether MPU frequency is set to 266 MHz which
196 * is nominal for 3410. If yes return true else false
198 if (((status >> 8) & 0x3) == 0x2)
205 /******************************************
207 * Description: Detect if we are running on a Beagle revision Ax/Bx,
208 * C1/2/3, C4 or D. This can be done by reading
209 * the level of GPIO173, GPIO172 and GPIO171. This should
211 * GPIO173, GPIO172, GPIO171: 1 1 1 => Ax/Bx
212 * GPIO173, GPIO172, GPIO171: 1 1 0 => C1/2/3
213 * GPIO173, GPIO172, GPIO171: 1 0 1 => C4
214 * GPIO173, GPIO172, GPIO171: 0 0 0 => XM
215 ******************************************/
216 int beagle_revision(void)
220 omap_request_gpio(171);
221 omap_request_gpio(172);
222 omap_request_gpio(173);
223 omap_set_gpio_direction(171, 1);
224 omap_set_gpio_direction(172, 1);
225 omap_set_gpio_direction(173, 1);
227 rev = omap_get_gpio_datain(173) << 2 |
228 omap_get_gpio_datain(172) << 1 |
229 omap_get_gpio_datain(171);
237 /*****************************************************************
238 * sr32 - clear & set a value in a bit range for a 32 bit address
239 *****************************************************************/
240 void sr32(u32 addr, u32 start_bit, u32 num_bits, u32 value)
245 tmp = __raw_readl(addr) & ~(msk << start_bit);
246 tmp |= value << start_bit;
247 __raw_writel(tmp, addr);
250 /*********************************************************************
251 * wait_on_value() - common routine to allow waiting for changes in
253 *********************************************************************/
254 u32 wait_on_value(u32 read_bit_mask, u32 match_value, u32 read_addr, u32 bound)
259 val = __raw_readl(read_addr) & read_bit_mask;
260 if (val == match_value)
267 #ifdef CFG_3430SDRAM_DDR
270 #define NUMONYX_MCP 1
271 int identify_xm_ddr()
275 __raw_writel(M_NAND_GPMC_CONFIG1, GPMC_CONFIG1 + GPMC_CONFIG_CS0);
276 __raw_writel(M_NAND_GPMC_CONFIG2, GPMC_CONFIG2 + GPMC_CONFIG_CS0);
277 __raw_writel(M_NAND_GPMC_CONFIG3, GPMC_CONFIG3 + GPMC_CONFIG_CS0);
278 __raw_writel(M_NAND_GPMC_CONFIG4, GPMC_CONFIG4 + GPMC_CONFIG_CS0);
279 __raw_writel(M_NAND_GPMC_CONFIG5, GPMC_CONFIG5 + GPMC_CONFIG_CS0);
280 __raw_writel(M_NAND_GPMC_CONFIG6, GPMC_CONFIG6 + GPMC_CONFIG_CS0);
282 /* Enable the GPMC Mapping */
283 __raw_writel((((OMAP34XX_GPMC_CS0_SIZE & 0xF)<<8) |
284 ((NAND_BASE_ADR>>24) & 0x3F) |
285 (1<<6)), (GPMC_CONFIG7 + GPMC_CONFIG_CS0));
288 nand_readid(&mfr, &id);
291 if ((mfr == 0x20) && (id == 0xba))
294 /*********************************************************************
295 * config_3430sdram_ddr() - Init DDR on 3430SDP dev board.
296 *********************************************************************/
297 void config_3430sdram_ddr(void)
299 /* reset sdrc controller */
300 __raw_writel(SOFTRESET, SDRC_SYSCONFIG);
301 wait_on_value(BIT0, BIT0, SDRC_STATUS, 12000000);
302 __raw_writel(0, SDRC_SYSCONFIG);
304 /* setup sdrc to ball mux */
305 __raw_writel(SDP_SDRC_SHARING, SDRC_SHARING);
307 if (beagle_revision() == REVISION_XM) {
308 if (identify_xm_ddr() == MICRON_DDR) {
309 __raw_writel(0x2, SDRC_CS_CFG); /* 256MB/bank */
310 __raw_writel(SDP_SDRC_MDCFG_0_DDR_MICRON_XM, SDRC_MCFG_0);
311 __raw_writel(SDP_SDRC_MDCFG_0_DDR_MICRON_XM, SDRC_MCFG_1);
312 __raw_writel(MICRON_V_ACTIMA_200, SDRC_ACTIM_CTRLA_0);
313 __raw_writel(MICRON_V_ACTIMB_200, SDRC_ACTIM_CTRLB_0);
314 __raw_writel(MICRON_V_ACTIMA_200, SDRC_ACTIM_CTRLA_1);
315 __raw_writel(MICRON_V_ACTIMB_200, SDRC_ACTIM_CTRLB_1);
316 __raw_writel(SDP_3430_SDRC_RFR_CTRL_200MHz, SDRC_RFR_CTRL_0);
317 __raw_writel(SDP_3430_SDRC_RFR_CTRL_200MHz, SDRC_RFR_CTRL_1);
319 __raw_writel(0x4, SDRC_CS_CFG); /* 512MB/bank */
320 __raw_writel(SDP_SDRC_MDCFG_0_DDR_NUMONYX_XM, SDRC_MCFG_0);
321 __raw_writel(SDP_SDRC_MDCFG_0_DDR_NUMONYX_XM, SDRC_MCFG_1);
322 __raw_writel(NUMONYX_V_ACTIMA_165, SDRC_ACTIM_CTRLA_0);
323 __raw_writel(NUMONYX_V_ACTIMB_165, SDRC_ACTIM_CTRLB_0);
324 __raw_writel(NUMONYX_V_ACTIMA_165, SDRC_ACTIM_CTRLA_1);
325 __raw_writel(NUMONYX_V_ACTIMB_165, SDRC_ACTIM_CTRLB_1);
326 __raw_writel(SDP_3430_SDRC_RFR_CTRL_165MHz, SDRC_RFR_CTRL_0);
327 __raw_writel(SDP_3430_SDRC_RFR_CTRL_165MHz, SDRC_RFR_CTRL_1);
330 __raw_writel(0x1, SDRC_CS_CFG); /* 128MB/bank */
331 __raw_writel(SDP_SDRC_MDCFG_0_DDR, SDRC_MCFG_0);
332 __raw_writel(SDP_SDRC_MDCFG_0_DDR, SDRC_MCFG_1);
333 __raw_writel(MICRON_V_ACTIMA_165, SDRC_ACTIM_CTRLA_0);
334 __raw_writel(MICRON_V_ACTIMB_165, SDRC_ACTIM_CTRLB_0);
335 __raw_writel(MICRON_V_ACTIMA_165, SDRC_ACTIM_CTRLA_1);
336 __raw_writel(MICRON_V_ACTIMB_165, SDRC_ACTIM_CTRLB_1);
337 __raw_writel(SDP_3430_SDRC_RFR_CTRL_165MHz, SDRC_RFR_CTRL_0);
338 __raw_writel(SDP_3430_SDRC_RFR_CTRL_165MHz, SDRC_RFR_CTRL_1);
341 __raw_writel(SDP_SDRC_POWER_POP, SDRC_POWER);
343 /* init sequence for mDDR/mSDR using manual commands (DDR is different) */
344 __raw_writel(CMD_NOP, SDRC_MANUAL_0);
345 __raw_writel(CMD_NOP, SDRC_MANUAL_1);
349 __raw_writel(CMD_PRECHARGE, SDRC_MANUAL_0);
350 __raw_writel(CMD_PRECHARGE, SDRC_MANUAL_1);
352 __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0);
353 __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_1);
355 __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0);
356 __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_1);
359 __raw_writel(SDP_SDRC_MR_0_DDR, SDRC_MR_0);
360 __raw_writel(SDP_SDRC_MR_0_DDR, SDRC_MR_1);
363 __raw_writel(SDP_SDRC_DLLAB_CTRL, SDRC_DLLA_CTRL);
364 delay(0x2000); /* give time to lock */
367 #endif /* CFG_3430SDRAM_DDR */
369 /*************************************************************
370 * get_sys_clk_speed - determine reference oscillator speed
371 * based on known 32kHz clock and gptimer.
372 *************************************************************/
373 u32 get_osc_clk_speed(void)
375 u32 start, cstart, cend, cdiff, cdiv, val;
377 val = __raw_readl(PRM_CLKSRC_CTRL);
379 if (val & SYSCLKDIV_2)
385 val = __raw_readl(CM_CLKSEL_WKUP) | BIT0;
386 __raw_writel(val, CM_CLKSEL_WKUP); /* select sys_clk for GPT1 */
388 /* Enable I and F Clocks for GPT1 */
389 val = __raw_readl(CM_ICLKEN_WKUP) | BIT0 | BIT2;
390 __raw_writel(val, CM_ICLKEN_WKUP);
391 val = __raw_readl(CM_FCLKEN_WKUP) | BIT0;
392 __raw_writel(val, CM_FCLKEN_WKUP);
394 __raw_writel(0, OMAP34XX_GPT1 + TLDR); /* start counting at 0 */
395 __raw_writel(GPT_EN, OMAP34XX_GPT1 + TCLR); /* enable clock */
396 /* enable 32kHz source */
397 /* enabled out of reset */
398 /* determine sys_clk via gauging */
400 start = 20 + __raw_readl(S32K_CR); /* start time in 20 cycles */
401 while (__raw_readl(S32K_CR) < start) ; /* dead loop till start time */
402 cstart = __raw_readl(OMAP34XX_GPT1 + TCRR); /* get start sys_clk count */
403 while (__raw_readl(S32K_CR) < (start + 20)) ; /* wait for 40 cycles */
404 cend = __raw_readl(OMAP34XX_GPT1 + TCRR); /* get end sys_clk count */
405 cdiff = cend - cstart; /* get elapsed ticks */
408 /* based on number of ticks assign speed */
411 else if (cdiff > 15200)
413 else if (cdiff > 13000)
415 else if (cdiff > 9000)
417 else if (cdiff > 7600)
423 /******************************************************************************
424 * get_sys_clkin_sel() - returns the sys_clkin_sel field value based on
425 * -- input oscillator clock frequency.
427 *****************************************************************************/
428 void get_sys_clkin_sel(u32 osc_clk, u32 *sys_clkin_sel)
430 if (osc_clk == S38_4M)
432 else if (osc_clk == S26M)
434 else if (osc_clk == S19_2M)
436 else if (osc_clk == S13M)
438 else if (osc_clk == S12M)
442 /******************************************************************************
443 * prcm_init() - inits clocks for PRCM as defined in clocks.h
444 * -- called from SRAM, or Flash (using temp SRAM stack).
445 *****************************************************************************/
448 u32 osc_clk = 0, sys_clkin_sel;
449 dpll_param *dpll_param_p;
450 u32 clk_index, sil_index;
452 /* Gauge the input clock speed and find out the sys_clkin_sel
453 * value corresponding to the input clock.
455 osc_clk = get_osc_clk_speed();
456 get_sys_clkin_sel(osc_clk, &sys_clkin_sel);
458 sr32(PRM_CLKSEL, 0, 3, sys_clkin_sel); /* set input crystal speed */
460 /* If the input clock is greater than 19.2M always divide/2 */
461 if (sys_clkin_sel > 2) {
462 sr32(PRM_CLKSRC_CTRL, 6, 2, 2); /* input clock divider */
463 clk_index = sys_clkin_sel / 2;
465 sr32(PRM_CLKSRC_CTRL, 6, 2, 1); /* input clock divider */
466 clk_index = sys_clkin_sel;
469 sr32(PRM_CLKSRC_CTRL, 0, 2, 0);/* Bypass mode: T2 inputs a square clock */
471 /* The DPLL tables are defined according to sysclk value and
472 * silicon revision. The clk_index value will be used to get
473 * the values for that input sysclk from the DPLL param table
474 * and sil_index will get the values for that SysClk for the
475 * appropriate silicon rev.
477 sil_index = get_cpu_rev() - 1;
479 /* Unlock MPU DPLL (slows things down, and needed later) */
480 sr32(CM_CLKEN_PLL_MPU, 0, 3, PLL_LOW_POWER_BYPASS);
481 wait_on_value(BIT0, 0, CM_IDLEST_PLL_MPU, LDELAY);
483 /* Getting the base address of Core DPLL param table */
484 dpll_param_p = (dpll_param *) get_core_dpll_param();
485 /* Moving it to the right sysclk and ES rev base */
486 dpll_param_p = dpll_param_p + 3 * clk_index + sil_index;
488 /* sr32(CM_CLKSEL2_EMU) set override to work when asleep */
489 sr32(CM_CLKEN_PLL, 0, 3, PLL_FAST_RELOCK_BYPASS);
490 wait_on_value(BIT0, 0, CM_IDLEST_CKGEN, LDELAY);
492 /* For 3430 ES1.0 Errata 1.50, default value directly doesnt
493 work. write another value and then default value. */
494 sr32(CM_CLKSEL1_EMU, 16, 5, CORE_M3X2 + 1); /* m3x2 */
495 sr32(CM_CLKSEL1_EMU, 16, 5, CORE_M3X2); /* m3x2 */
496 sr32(CM_CLKSEL1_PLL, 27, 2, dpll_param_p->m2); /* Set M2 */
497 sr32(CM_CLKSEL1_PLL, 16, 11, dpll_param_p->m); /* Set M */
498 sr32(CM_CLKSEL1_PLL, 8, 7, dpll_param_p->n); /* Set N */
499 sr32(CM_CLKSEL1_PLL, 6, 1, 0); /* 96M Src */
500 sr32(CM_CLKSEL_CORE, 8, 4, CORE_SSI_DIV); /* ssi */
501 sr32(CM_CLKSEL_CORE, 4, 2, CORE_FUSB_DIV); /* fsusb */
502 sr32(CM_CLKSEL_CORE, 2, 2, CORE_L4_DIV); /* l4 */
503 sr32(CM_CLKSEL_CORE, 0, 2, CORE_L3_DIV); /* l3 */
504 sr32(CM_CLKSEL_GFX, 0, 3, GFX_DIV); /* gfx */
505 sr32(CM_CLKSEL_WKUP, 1, 2, WKUP_RSM); /* reset mgr */
506 sr32(CM_CLKEN_PLL, 4, 4, dpll_param_p->fsel); /* FREQSEL */
507 sr32(CM_CLKEN_PLL, 0, 3, PLL_LOCK); /* lock mode */
508 wait_on_value(BIT0, 1, CM_IDLEST_CKGEN, LDELAY);
510 /* Getting the base address to PER DPLL param table */
511 dpll_param_p = (dpll_param *) get_per_dpll_param();
512 /* Moving it to the right sysclk base */
513 dpll_param_p = dpll_param_p + clk_index;
515 sr32(CM_CLKEN_PLL, 16, 3, PLL_STOP);
516 wait_on_value(BIT1, 0, CM_IDLEST_CKGEN, LDELAY);
517 sr32(CM_CLKSEL1_EMU, 24, 5, PER_M6X2); /* set M6 */
518 sr32(CM_CLKSEL_CAM, 0, 5, PER_M5X2); /* set M5 */
519 sr32(CM_CLKSEL_DSS, 0, 5, PER_M4X2); /* set M4 */
520 sr32(CM_CLKSEL_DSS, 8, 5, PER_M3X2); /* set M3 */
522 if (beagle_revision() == REVISION_XM) {
523 sr32(CM_CLKSEL3_PLL, 0, 5, CORE_DPLL_PARAM_M2); /* set M2 */
524 sr32(CM_CLKSEL2_PLL, 8, 11, CORE_DPLL_PARAM_M); /* set m */
525 sr32(CM_CLKSEL2_PLL, 0, 7, CORE_DPLL_PARAM_N); /* set n */
527 sr32(CM_CLKSEL3_PLL, 0, 5, dpll_param_p->m2); /* set M2 */
528 sr32(CM_CLKSEL2_PLL, 8, 11, dpll_param_p->m); /* set m */
529 sr32(CM_CLKSEL2_PLL, 0, 7, dpll_param_p->n); /* set n */
532 sr32(CM_CLKEN_PLL, 20, 4, dpll_param_p->fsel); /* FREQSEL */
533 sr32(CM_CLKEN_PLL, 16, 3, PLL_LOCK); /* lock mode */
534 wait_on_value(BIT1, 2, CM_IDLEST_CKGEN, LDELAY);
536 /* Getting the base address to MPU DPLL param table */
537 dpll_param_p = (dpll_param *) get_mpu_dpll_param();
539 /* Moving it to the right sysclk and ES rev base */
540 dpll_param_p = dpll_param_p + 3 * clk_index + sil_index;
542 /* MPU DPLL (unlocked already) */
543 sr32(CM_CLKSEL2_PLL_MPU, 0, 5, dpll_param_p->m2); /* Set M2 */
544 sr32(CM_CLKSEL1_PLL_MPU, 8, 11, dpll_param_p->m); /* Set M */
545 sr32(CM_CLKSEL1_PLL_MPU, 0, 7, dpll_param_p->n); /* Set N */
546 sr32(CM_CLKEN_PLL_MPU, 4, 4, dpll_param_p->fsel); /* FREQSEL */
547 sr32(CM_CLKEN_PLL_MPU, 0, 3, PLL_LOCK); /* lock mode */
548 wait_on_value(BIT0, 1, CM_IDLEST_PLL_MPU, LDELAY);
550 /* Getting the base address to IVA DPLL param table */
551 dpll_param_p = (dpll_param *) get_iva_dpll_param();
552 /* Moving it to the right sysclk and ES rev base */
553 dpll_param_p = dpll_param_p + 3 * clk_index + sil_index;
554 /* IVA DPLL (set to 12*20=240MHz) */
555 sr32(CM_CLKEN_PLL_IVA2, 0, 3, PLL_STOP);
556 wait_on_value(BIT0, 0, CM_IDLEST_PLL_IVA2, LDELAY);
557 sr32(CM_CLKSEL2_PLL_IVA2, 0, 5, dpll_param_p->m2); /* set M2 */
558 sr32(CM_CLKSEL1_PLL_IVA2, 8, 11, dpll_param_p->m); /* set M */
559 sr32(CM_CLKSEL1_PLL_IVA2, 0, 7, dpll_param_p->n); /* set N */
560 sr32(CM_CLKEN_PLL_IVA2, 4, 4, dpll_param_p->fsel); /* FREQSEL */
561 sr32(CM_CLKEN_PLL_IVA2, 0, 3, PLL_LOCK); /* lock mode */
562 wait_on_value(BIT0, 1, CM_IDLEST_PLL_IVA2, LDELAY);
564 /* Set up GPTimers to sys_clk source only */
565 sr32(CM_CLKSEL_PER, 0, 8, 0xff);
566 sr32(CM_CLKSEL_WKUP, 0, 1, 1);
571 /*****************************************
572 * Routine: secure_unlock
573 * Description: Setup security registers for access
575 *****************************************/
576 void secure_unlock(void)
578 /* Permission values for registers -Full fledged permissions to all */
579 #define UNLOCK_1 0xFFFFFFFF
580 #define UNLOCK_2 0x00000000
581 #define UNLOCK_3 0x0000FFFF
582 /* Protection Module Register Target APE (PM_RT) */
583 __raw_writel(UNLOCK_1, RT_REQ_INFO_PERMISSION_1);
584 __raw_writel(UNLOCK_1, RT_READ_PERMISSION_0);
585 __raw_writel(UNLOCK_1, RT_WRITE_PERMISSION_0);
586 __raw_writel(UNLOCK_2, RT_ADDR_MATCH_1);
588 __raw_writel(UNLOCK_3, GPMC_REQ_INFO_PERMISSION_0);
589 __raw_writel(UNLOCK_3, GPMC_READ_PERMISSION_0);
590 __raw_writel(UNLOCK_3, GPMC_WRITE_PERMISSION_0);
592 __raw_writel(UNLOCK_3, OCM_REQ_INFO_PERMISSION_0);
593 __raw_writel(UNLOCK_3, OCM_READ_PERMISSION_0);
594 __raw_writel(UNLOCK_3, OCM_WRITE_PERMISSION_0);
595 __raw_writel(UNLOCK_2, OCM_ADDR_MATCH_2);
598 __raw_writel(UNLOCK_3, IVA2_REQ_INFO_PERMISSION_0);
599 __raw_writel(UNLOCK_3, IVA2_READ_PERMISSION_0);
600 __raw_writel(UNLOCK_3, IVA2_WRITE_PERMISSION_0);
602 __raw_writel(UNLOCK_1, SMS_RG_ATT0); /* SDRC region 0 public */
605 /**********************************************************
606 * Routine: try_unlock_sram()
607 * Description: If chip is GP type, unlock the SRAM for
609 ***********************************************************/
610 void try_unlock_memory(void)
614 /* if GP device unlock device SRAM for general use */
615 /* secure code breaks for Secure/Emulation device - HS/E/T */
616 mode = get_device_type();
617 if (mode == GP_DEVICE)
622 /**********************************************************
624 * Description: Does early system init of muxing and clocks.
625 * - Called at time when only stack is available.
626 **********************************************************/
631 #ifdef CONFIG_3430_AS_3410
632 /* setup the scalability control register for
633 * 3430 to work in 3410 mode
635 __raw_writel(0x5ABF, CONTROL_SCALABLE_OMAP_OCP);
642 config_3430sdram_ddr();
645 /*******************************************************
646 * Routine: misc_init_r
647 * Description: Init ethernet (done here so udelay works)
648 ********************************************************/
649 int misc_init_r(void)
653 rev = beagle_revision();
656 printf("Beagle Rev Ax/Bx\n");
659 printf("Beagle Rev C1/C2/C3\n");
662 printf("Beagle Rev C4\n");
665 printf("Beagle xM Rev A\n");
668 printf("Beagle unknown 0x%02x\n", rev);
674 /******************************************************
675 * Routine: wait_for_command_complete
676 * Description: Wait for posting to finish on watchdog
677 ******************************************************/
678 void wait_for_command_complete(unsigned int wd_base)
682 pending = __raw_readl(wd_base + WWPS);
686 /****************************************
687 * Routine: watchdog_init
688 * Description: Shut down watch dogs
689 *****************************************/
690 void watchdog_init(void)
692 /* There are 3 watch dogs WD1=Secure, WD2=MPU, WD3=IVA. WD1 is
693 * either taken care of by ROM (HS/EMU) or not accessible (GP).
694 * We need to take care of WD2-MPU or take a PRCM reset. WD3
695 * should not be running and does not generate a PRCM reset.
697 sr32(CM_FCLKEN_WKUP, 5, 1, 1);
698 sr32(CM_ICLKEN_WKUP, 5, 1, 1);
699 wait_on_value(BIT5, 0x20, CM_IDLEST_WKUP, 5); /* some issue here */
701 __raw_writel(WD_UNLOCK1, WD2_BASE + WSPR);
702 wait_for_command_complete(WD2_BASE);
703 __raw_writel(WD_UNLOCK2, WD2_BASE + WSPR);
706 /**********************************************
708 * Description: sets uboots idea of sdram size
709 **********************************************/
715 /*****************************************************************
716 * Routine: peripheral_enable
717 * Description: Enable the clks & power for perifs (GPT2, UART1,...)
718 ******************************************************************/
719 void per_clocks_enable(void)
721 /* Enable GP2 timer. */
722 sr32(CM_CLKSEL_PER, 0, 1, 0x1); /* GPT2 = sys clk */
723 sr32(CM_ICLKEN_PER, 3, 1, 0x1); /* ICKen GPT2 */
724 sr32(CM_FCLKEN_PER, 3, 1, 0x1); /* FCKen GPT2 */
728 sr32(CM_FCLKEN1_CORE, 13, 1, 0x1);
729 sr32(CM_ICLKEN1_CORE, 13, 1, 0x1);
732 sr32(CM_FCLKEN_PER, 11, 1, 0x1);
733 sr32(CM_ICLKEN_PER, 11, 1, 0x1);
737 #ifdef CONFIG_DRIVER_OMAP34XX_I2C
738 /* Turn on all 3 I2C clocks */
739 sr32(CM_FCLKEN1_CORE, 15, 3, 0x7);
740 sr32(CM_ICLKEN1_CORE, 15, 3, 0x7); /* I2C1,2,3 = on */
743 /* Enable the ICLK for 32K Sync Timer as its used in udelay */
744 sr32(CM_ICLKEN_WKUP, 2, 1, 0x1);
746 sr32(CM_FCLKEN_IVA2, 0, 32, FCK_IVA2_ON);
747 sr32(CM_FCLKEN1_CORE, 0, 32, FCK_CORE1_ON);
748 sr32(CM_ICLKEN1_CORE, 0, 32, ICK_CORE1_ON);
749 sr32(CM_ICLKEN2_CORE, 0, 32, ICK_CORE2_ON);
750 sr32(CM_FCLKEN_WKUP, 0, 32, FCK_WKUP_ON);
751 sr32(CM_ICLKEN_WKUP, 0, 32, ICK_WKUP_ON);
752 sr32(CM_FCLKEN_DSS, 0, 32, FCK_DSS_ON);
753 sr32(CM_ICLKEN_DSS, 0, 32, ICK_DSS_ON);
754 sr32(CM_FCLKEN_CAM, 0, 32, FCK_CAM_ON);
755 sr32(CM_ICLKEN_CAM, 0, 32, ICK_CAM_ON);
756 sr32(CM_FCLKEN_PER, 0, 32, FCK_PER_ON);
757 sr32(CM_ICLKEN_PER, 0, 32, ICK_PER_ON);
759 /* Enable GPIO 5 & GPIO 6 clocks */
760 sr32(CM_FCLKEN_PER, 17, 2, 0x3);
761 sr32(CM_ICLKEN_PER, 17, 2, 0x3);
766 /* Set MUX for UART, GPMC, SDRC, GPIO */
768 #define MUX_VAL(OFFSET,VALUE)\
769 __raw_writew((VALUE), OMAP34XX_CTRL_BASE + (OFFSET));
771 #define CP(x) (CONTROL_PADCONF_##x)
774 * IDIS - Input Disable
775 * PTD - Pull type Down
777 * DIS - Pull type selection is inactive
778 * EN - Pull type selection is active
780 * The commented string gives the final mux configuration for that pin
782 #define MUX_DEFAULT()\
783 MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) /*SDRC_D0*/\
784 MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) /*SDRC_D1*/\
785 MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) /*SDRC_D2*/\
786 MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) /*SDRC_D3*/\
787 MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) /*SDRC_D4*/\
788 MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) /*SDRC_D5*/\
789 MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) /*SDRC_D6*/\
790 MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) /*SDRC_D7*/\
791 MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) /*SDRC_D8*/\
792 MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) /*SDRC_D9*/\
793 MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) /*SDRC_D10*/\
794 MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) /*SDRC_D11*/\
795 MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) /*SDRC_D12*/\
796 MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) /*SDRC_D13*/\
797 MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) /*SDRC_D14*/\
798 MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) /*SDRC_D15*/\
799 MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) /*SDRC_D16*/\
800 MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) /*SDRC_D17*/\
801 MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) /*SDRC_D18*/\
802 MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) /*SDRC_D19*/\
803 MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) /*SDRC_D20*/\
804 MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) /*SDRC_D21*/\
805 MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) /*SDRC_D22*/\
806 MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) /*SDRC_D23*/\
807 MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) /*SDRC_D24*/\
808 MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) /*SDRC_D25*/\
809 MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) /*SDRC_D26*/\
810 MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) /*SDRC_D27*/\
811 MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) /*SDRC_D28*/\
812 MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) /*SDRC_D29*/\
813 MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) /*SDRC_D30*/\
814 MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) /*SDRC_D31*/\
815 MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) /*SDRC_CLK*/\
816 MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) /*SDRC_DQS0*/\
817 MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) /*SDRC_DQS1*/\
818 MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) /*SDRC_DQS2*/\
819 MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) /*SDRC_DQS3*/\
820 MUX_VAL(CP(GPMC_A1), (IDIS | PTD | DIS | M0)) /*GPMC_A1*/\
821 MUX_VAL(CP(GPMC_A2), (IDIS | PTD | DIS | M0)) /*GPMC_A2*/\
822 MUX_VAL(CP(GPMC_A3), (IDIS | PTD | DIS | M0)) /*GPMC_A3*/\
823 MUX_VAL(CP(GPMC_A4), (IDIS | PTD | DIS | M0)) /*GPMC_A4*/\
824 MUX_VAL(CP(GPMC_A5), (IDIS | PTD | DIS | M0)) /*GPMC_A5*/\
825 MUX_VAL(CP(GPMC_A6), (IDIS | PTD | DIS | M0)) /*GPMC_A6*/\
826 MUX_VAL(CP(GPMC_A7), (IDIS | PTD | DIS | M0)) /*GPMC_A7*/\
827 MUX_VAL(CP(GPMC_A8), (IDIS | PTD | DIS | M0)) /*GPMC_A8*/\
828 MUX_VAL(CP(GPMC_A9), (IDIS | PTD | DIS | M0)) /*GPMC_A9*/\
829 MUX_VAL(CP(GPMC_A10), (IDIS | PTD | DIS | M0)) /*GPMC_A10*/\
830 MUX_VAL(CP(GPMC_D0), (IEN | PTD | DIS | M0)) /*GPMC_D0*/\
831 MUX_VAL(CP(GPMC_D1), (IEN | PTD | DIS | M0)) /*GPMC_D1*/\
832 MUX_VAL(CP(GPMC_D2), (IEN | PTD | DIS | M0)) /*GPMC_D2*/\
833 MUX_VAL(CP(GPMC_D3), (IEN | PTD | DIS | M0)) /*GPMC_D3*/\
834 MUX_VAL(CP(GPMC_D4), (IEN | PTD | DIS | M0)) /*GPMC_D4*/\
835 MUX_VAL(CP(GPMC_D5), (IEN | PTD | DIS | M0)) /*GPMC_D5*/\
836 MUX_VAL(CP(GPMC_D6), (IEN | PTD | DIS | M0)) /*GPMC_D6*/\
837 MUX_VAL(CP(GPMC_D7), (IEN | PTD | DIS | M0)) /*GPMC_D7*/\
838 MUX_VAL(CP(GPMC_D8), (IEN | PTD | DIS | M0)) /*GPMC_D8*/\
839 MUX_VAL(CP(GPMC_D9), (IEN | PTD | DIS | M0)) /*GPMC_D9*/\
840 MUX_VAL(CP(GPMC_D10), (IEN | PTD | DIS | M0)) /*GPMC_D10*/\
841 MUX_VAL(CP(GPMC_D11), (IEN | PTD | DIS | M0)) /*GPMC_D11*/\
842 MUX_VAL(CP(GPMC_D12), (IEN | PTD | DIS | M0)) /*GPMC_D12*/\
843 MUX_VAL(CP(GPMC_D13), (IEN | PTD | DIS | M0)) /*GPMC_D13*/\
844 MUX_VAL(CP(GPMC_D14), (IEN | PTD | DIS | M0)) /*GPMC_D14*/\
845 MUX_VAL(CP(GPMC_D15), (IEN | PTD | DIS | M0)) /*GPMC_D15*/\
846 MUX_VAL(CP(GPMC_nCS0), (IDIS | PTU | EN | M0)) /*GPMC_nCS0*/\
847 MUX_VAL(CP(GPMC_nCS1), (IDIS | PTU | EN | M0)) /*GPMC_nCS1*/\
848 MUX_VAL(CP(GPMC_nCS2), (IDIS | PTU | EN | M0)) /*GPMC_nCS2*/\
849 MUX_VAL(CP(GPMC_nCS3), (IDIS | PTU | EN | M0)) /*GPMC_nCS3*/\
850 MUX_VAL(CP(GPMC_nCS4), (IDIS | PTU | EN | M0)) /*GPMC_nCS4*/\
851 MUX_VAL(CP(GPMC_nCS5), (IDIS | PTD | DIS | M0)) /*GPMC_nCS5*/\
852 MUX_VAL(CP(GPMC_nCS6), (IEN | PTD | DIS | M1)) /*GPMC_nCS6*/\
853 MUX_VAL(CP(GPMC_nCS7), (IEN | PTU | EN | M1)) /*GPMC_nCS7*/\
854 MUX_VAL(CP(GPMC_CLK), (IDIS | PTD | DIS | M0)) /*GPMC_CLK*/\
855 MUX_VAL(CP(GPMC_nADV_ALE), (IDIS | PTD | DIS | M0)) /*GPMC_nADV_ALE*/\
856 MUX_VAL(CP(GPMC_nOE), (IDIS | PTD | DIS | M0)) /*GPMC_nOE*/\
857 MUX_VAL(CP(GPMC_nWE), (IDIS | PTD | DIS | M0)) /*GPMC_nWE*/\
858 MUX_VAL(CP(GPMC_nBE0_CLE), (IDIS | PTD | DIS | M0)) /*GPMC_nBE0_CLE*/\
859 MUX_VAL(CP(GPMC_nBE1), (IEN | PTD | DIS | M0)) /*GPIO_61*/\
860 MUX_VAL(CP(GPMC_nWP), (IEN | PTD | DIS | M0)) /*GPMC_nWP*/\
861 MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) /*GPMC_WAIT0*/\
862 MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0)) /*GPMC_WAIT1*/\
863 MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M0)) /*GPIO_64*/\
864 MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M0)) /*GPIO_65*/\
865 MUX_VAL(CP(DSS_DATA18), (IEN | PTD | DIS | M4)) /*GPIO_88*/\
866 MUX_VAL(CP(DSS_DATA19), (IEN | PTD | DIS | M4)) /*GPIO_89*/\
867 MUX_VAL(CP(DSS_DATA20), (IEN | PTD | DIS | M4)) /*GPIO_90*/\
868 MUX_VAL(CP(DSS_DATA21), (IEN | PTD | DIS | M4)) /*GPIO_91*/\
869 MUX_VAL(CP(CAM_WEN), (IEN | PTD | DIS | M4)) /*GPIO_167*/\
870 MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0)) /*MMC1_CLK*/\
871 MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)) /*MMC1_CMD*/\
872 MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)) /*MMC1_DAT0*/\
873 MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)) /*MMC1_DAT1*/\
874 MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)) /*MMC1_DAT2*/\
875 MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)) /*MMC1_DAT3*/\
876 MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | EN | M0)) /*MMC1_DAT4*/\
877 MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M0)) /*MMC1_DAT5*/\
878 MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M0)) /*MMC1_DAT6*/\
879 MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M0)) /*MMC1_DAT7*/\
880 MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) /*UART1_TX*/\
881 MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M4)) /*GPIO_149*/\
882 MUX_VAL(CP(UART1_CTS), (IDIS | PTD | DIS | M4)) /*GPIO_150*/\
883 MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) /*UART1_RX*/\
884 MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTD | EN | M0)) /*UART3_CTS_RCTX */\
885 MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTD | DIS | M0)) /*UART3_RTS_SD */\
886 MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)) /*UART3_RX_IRRX*/\
887 MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) /*UART3_TX_IRTX*/\
888 MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) /*I2C1_SCL*/\
889 MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) /*I2C1_SDA*/\
890 MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0)) /*I2C2_SCL*/\
891 MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0)) /*I2C2_SDA*/\
892 MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)) /*I2C3_SCL*/\
893 MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)) /*I2C3_SDA*/\
894 MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) /*I2C4_SCL*/\
895 MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) /*I2C4_SDA*/\
896 MUX_VAL(CP(McSPI1_CLK), (IEN | PTU | EN | M4)) /*GPIO_171*/\
897 MUX_VAL(CP(McSPI1_SIMO), (IEN | PTU | EN | M4)) /*GPIO_172*/\
898 MUX_VAL(CP(McSPI1_SOMI), (IEN | PTU | EN | M4)) /*GPIO_173*/\
899 MUX_VAL(CP(McBSP1_DX), (IEN | PTD | DIS | M4)) /*GPIO_158*/\
900 MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) /*SYS_32K*/\
901 MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) /*GPIO_2 */\
902 MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) /*GPIO_3 */\
903 MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) /*GPIO_4 */\
904 MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)) /*GPIO_5 */\
905 MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) /*GPIO_6 */\
906 MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)) /*GPIO_7 */\
907 MUX_VAL(CP(SYS_BOOT6), (IEN | PTD | DIS | M4)) /*GPIO_8 */\
908 MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M4)) /*GPIO_186*/\
909 MUX_VAL(CP(JTAG_nTRST), (IEN | PTD | DIS | M0)) /*JTAG_nTRST*/\
910 MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)) /*JTAG_TCK*/\
911 MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)) /*JTAG_TMS*/\
912 MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)) /*JTAG_TDI*/\
913 MUX_VAL(CP(JTAG_EMU0), (IEN | PTD | DIS | M0)) /*JTAG_EMU0*/\
914 MUX_VAL(CP(JTAG_EMU1), (IEN | PTD | DIS | M0)) /*JTAG_EMU1*/\
915 MUX_VAL(CP(ETK_CLK), (IEN | PTD | DIS | M4)) /*GPIO_12*/\
916 MUX_VAL(CP(ETK_CTL), (IEN | PTD | DIS | M4)) /*GPIO_13*/\
917 MUX_VAL(CP(ETK_D0), (IEN | PTD | DIS | M4)) /*GPIO_14*/\
918 MUX_VAL(CP(ETK_D1), (IEN | PTD | DIS | M4)) /*GPIO_15*/\
919 MUX_VAL(CP(ETK_D2), (IEN | PTD | DIS | M4)) /*GPIO_16*/\
920 MUX_VAL(CP(ETK_D11), (IEN | PTD | DIS | M4)) /*GPIO_25*/\
921 MUX_VAL(CP(ETK_D12), (IEN | PTD | DIS | M4)) /*GPIO_26*/\
922 MUX_VAL(CP(ETK_D13), (IEN | PTD | DIS | M4)) /*GPIO_27*/\
923 MUX_VAL(CP(ETK_D14), (IEN | PTD | DIS | M4)) /*GPIO_28*/\
924 MUX_VAL(CP(ETK_D15), (IEN | PTD | DIS | M4)) /*GPIO_29 */\
925 MUX_VAL(CP(sdrc_cke0), (IDIS | PTU | EN | M0)) /*sdrc_cke0 */\
926 MUX_VAL(CP(sdrc_cke1), (IDIS | PTD | DIS | M7)) /*sdrc_cke1 not used*/
928 /**********************************************************
929 * Routine: set_muxconf_regs
930 * Description: Setting up the configuration Mux registers
931 * specific to the hardware. Many pins need
932 * to be moved from protect to primary mode.
933 *********************************************************/
934 void set_muxconf_regs(void)
939 /**********************************************************
940 * Routine: nand+_init
941 * Description: Set up nand for nand and jffs2 commands
942 *********************************************************/
946 /* global settings */
947 __raw_writel(0x10, GPMC_SYSCONFIG); /* smart idle */
948 __raw_writel(0x0, GPMC_IRQENABLE); /* isr's sources masked */
949 __raw_writel(0, GPMC_TIMEOUT_CONTROL);/* timeout disable */
951 /* Set the GPMC Vals, NAND is mapped at CS0, oneNAND at CS0.
952 * We configure only GPMC CS0 with required values. Configiring other devices
953 * at other CS is done in u-boot. So we don't have to bother doing it here.
955 __raw_writel(0 , GPMC_CONFIG7 + GPMC_CONFIG_CS0);
958 #ifdef CFG_NAND_K9F1G08R0A
959 if ((get_mem_type() == GPMC_NAND) || (get_mem_type() == MMC_NAND)) {
960 __raw_writel(M_NAND_GPMC_CONFIG1, GPMC_CONFIG1 + GPMC_CONFIG_CS0);
961 __raw_writel(M_NAND_GPMC_CONFIG2, GPMC_CONFIG2 + GPMC_CONFIG_CS0);
962 __raw_writel(M_NAND_GPMC_CONFIG3, GPMC_CONFIG3 + GPMC_CONFIG_CS0);
963 __raw_writel(M_NAND_GPMC_CONFIG4, GPMC_CONFIG4 + GPMC_CONFIG_CS0);
964 __raw_writel(M_NAND_GPMC_CONFIG5, GPMC_CONFIG5 + GPMC_CONFIG_CS0);
965 __raw_writel(M_NAND_GPMC_CONFIG6, GPMC_CONFIG6 + GPMC_CONFIG_CS0);
967 /* Enable the GPMC Mapping */
968 __raw_writel((((OMAP34XX_GPMC_CS0_SIZE & 0xF)<<8) |
969 ((NAND_BASE_ADR>>24) & 0x3F) |
970 (1<<6)), (GPMC_CONFIG7 + GPMC_CONFIG_CS0));
975 printf("Unsupported Chip!\n");
983 if ((get_mem_type() == GPMC_ONENAND) || (get_mem_type() == MMC_ONENAND)) {
984 __raw_writel(ONENAND_GPMC_CONFIG1, GPMC_CONFIG1 + GPMC_CONFIG_CS0);
985 __raw_writel(ONENAND_GPMC_CONFIG2, GPMC_CONFIG2 + GPMC_CONFIG_CS0);
986 __raw_writel(ONENAND_GPMC_CONFIG3, GPMC_CONFIG3 + GPMC_CONFIG_CS0);
987 __raw_writel(ONENAND_GPMC_CONFIG4, GPMC_CONFIG4 + GPMC_CONFIG_CS0);
988 __raw_writel(ONENAND_GPMC_CONFIG5, GPMC_CONFIG5 + GPMC_CONFIG_CS0);
989 __raw_writel(ONENAND_GPMC_CONFIG6, GPMC_CONFIG6 + GPMC_CONFIG_CS0);
991 /* Enable the GPMC Mapping */
992 __raw_writel((((OMAP34XX_GPMC_CS0_SIZE & 0xF)<<8) |
993 ((ONENAND_BASE>>24) & 0x3F) |
994 (1<<6)), (GPMC_CONFIG7 + GPMC_CONFIG_CS0));
997 if (onenand_chip()) {
999 printf("OneNAND Unsupported !\n");
1008 #define DEBUG_LED1 149 /* gpio */
1009 #define DEBUG_LED2 150 /* gpio */
1015 /* Alternately turn the LEDs on and off */
1016 p = (unsigned long *)OMAP34XX_GPIO5_BASE;
1018 /* turn LED1 on and LED2 off */
1019 *(unsigned long *)(p + 0x94) = 1 << (DEBUG_LED1 % 32);
1020 *(unsigned long *)(p + 0x90) = 1 << (DEBUG_LED2 % 32);
1022 /* delay for a while */
1025 /* turn LED1 off and LED2 on */
1026 *(unsigned long *)(p + 0x90) = 1 << (DEBUG_LED1 % 32);
1027 *(unsigned long *)(p + 0x94) = 1 << (DEBUG_LED2 % 32);
1029 /* delay for a while */
1034 /* optionally do something like blinking LED */
1035 void board_hang(void)
1041 /******************************************************************************
1042 * Dummy function to handle errors for EABI incompatibility
1043 *****************************************************************************/
1048 /******************************************************************************
1049 * Dummy function to handle errors for EABI incompatibility
1050 *****************************************************************************/