3 * Texas Instruments, <www.ti.com>
4 * Jian Zhang <jzhang@ti.com>
5 * Richard Woodruff <r-woodruff2@ti.com>
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
30 #include <asm/arch/cpu.h>
31 #include <asm/arch/bits.h>
32 #include <asm/arch/mux.h>
33 #include <asm/arch/gpio.h>
34 #include <asm/arch/sys_proto.h>
35 #include <asm/arch/sys_info.h>
36 #include <asm/arch/clocks.h>
37 #include <asm/arch/mem.h>
40 #define CORE_DPLL_PARAM_M2 0x09
41 #define CORE_DPLL_PARAM_M 0x360
42 #define CORE_DPLL_PARAM_N 0xC
44 /* BeagleBoard revisions */
45 #define REVISION_AXBX 0x7
46 #define REVISION_CX 0x6
47 #define REVISION_C4 0x5
48 #define REVISION_XM 0x0
50 /* Used to index into DPLL parameter tables */
58 typedef struct dpll_param dpll_param;
60 /* Following functions are exported from lowlevel_init.S */
61 extern dpll_param *get_mpu_dpll_param();
62 extern dpll_param *get_iva_dpll_param();
63 extern dpll_param *get_core_dpll_param();
64 extern dpll_param *get_per_dpll_param();
66 #define __raw_readl(a) (*(volatile unsigned int *)(a))
67 #define __raw_writel(v, a) (*(volatile unsigned int *)(a) = (v))
68 #define __raw_readw(a) (*(volatile unsigned short *)(a))
69 #define __raw_writew(v, a) (*(volatile unsigned short *)(a) = (v))
71 /*******************************************************
73 * Description: spinning delay to use before udelay works
74 ******************************************************/
75 static inline void delay(unsigned long loops)
77 __asm__ volatile ("1:\n" "subs %0, %1, #1\n"
78 "bne 1b":"=r" (loops):"0"(loops));
81 void udelay (unsigned long usecs) {
85 /*****************************************
87 * Description: Early hardware init.
88 *****************************************/
94 /*************************************************************
95 * Routine: get_mem_type(void) - returns the kind of memory connected
96 * to GPMC that we are trying to boot form. Uses SYS BOOT settings.
97 *************************************************************/
98 u32 get_mem_type(void)
101 if (beagle_revision() == REVISION_XM)
104 u32 mem_type = get_sysboot_value();
146 /******************************************
147 * cpu_is_3410(void) - returns true for 3410
148 ******************************************/
149 u32 cpu_is_3410(void)
152 if (get_cpu_rev() < CPU_3430_ES2) {
155 /* read scalability status and return 1 for 3410*/
156 status = __raw_readl(CONTROL_SCALABLE_OMAP_STATUS);
157 /* Check whether MPU frequency is set to 266 MHz which
158 * is nominal for 3410. If yes return true else false
160 if (((status >> 8) & 0x3) == 0x2)
167 /******************************************
169 * Description: Detect if we are running on a Beagle revision Ax/Bx,
170 * C1/2/3, C4 or D. This can be done by reading
171 * the level of GPIO173, GPIO172 and GPIO171. This should
173 * GPIO173, GPIO172, GPIO171: 1 1 1 => Ax/Bx
174 * GPIO173, GPIO172, GPIO171: 1 1 0 => C1/2/3
175 * GPIO173, GPIO172, GPIO171: 1 0 1 => C4
176 * GPIO173, GPIO172, GPIO171: 0 0 0 => XM
178 ******************************************/
179 int beagle_revision(void)
183 omap_request_gpio(171);
184 omap_request_gpio(172);
185 omap_request_gpio(173);
186 omap_set_gpio_direction(171, 1);
187 omap_set_gpio_direction(172, 1);
188 omap_set_gpio_direction(173, 1);
190 rev = omap_get_gpio_datain(173) << 2 |
191 omap_get_gpio_datain(172) << 1 |
192 omap_get_gpio_datain(171);
194 /* Default newer board revisions to XM */
212 #ifdef CFG_3430SDRAM_DDR
215 #define NUMONYX_MCP 1
217 int identify_xm_ddr()
221 __raw_writel(M_NAND_GPMC_CONFIG1, GPMC_CONFIG1 + GPMC_CONFIG_CS0);
222 __raw_writel(M_NAND_GPMC_CONFIG2, GPMC_CONFIG2 + GPMC_CONFIG_CS0);
223 __raw_writel(M_NAND_GPMC_CONFIG3, GPMC_CONFIG3 + GPMC_CONFIG_CS0);
224 __raw_writel(M_NAND_GPMC_CONFIG4, GPMC_CONFIG4 + GPMC_CONFIG_CS0);
225 __raw_writel(M_NAND_GPMC_CONFIG5, GPMC_CONFIG5 + GPMC_CONFIG_CS0);
226 __raw_writel(M_NAND_GPMC_CONFIG6, GPMC_CONFIG6 + GPMC_CONFIG_CS0);
228 /* Enable the GPMC Mapping */
229 __raw_writel((((OMAP34XX_GPMC_CS0_SIZE & 0xF)<<8) |
230 ((NAND_BASE_ADR>>24) & 0x3F) |
231 (1<<6)), (GPMC_CONFIG7 + GPMC_CONFIG_CS0));
234 nand_readid(&mfr, &id);
237 if ((mfr == 0x20) && (id == 0xba))
239 if ((mfr == 0x2c) && (id == 0xbc))
242 /*********************************************************************
243 * config_3430sdram_ddr() - Init DDR on 3430SDP dev board.
244 *********************************************************************/
245 void config_3430sdram_ddr(void)
247 /* reset sdrc controller */
248 __raw_writel(SOFTRESET, SDRC_SYSCONFIG);
249 wait_on_value(BIT0, BIT0, SDRC_STATUS, 12000000);
250 __raw_writel(0, SDRC_SYSCONFIG);
252 /* setup sdrc to ball mux */
253 __raw_writel(SDP_SDRC_SHARING, SDRC_SHARING);
255 switch(beagle_revision()) {
257 if (identify_xm_ddr() == NUMONYX_MCP) {
258 __raw_writel(0x4, SDRC_CS_CFG); /* 512MB/bank */
259 __raw_writel(SDP_SDRC_MDCFG_0_DDR_NUMONYX_XM, SDRC_MCFG_0);
260 __raw_writel(SDP_SDRC_MDCFG_0_DDR_NUMONYX_XM, SDRC_MCFG_1);
261 __raw_writel(NUMONYX_V_ACTIMA_165, SDRC_ACTIM_CTRLA_0);
262 __raw_writel(NUMONYX_V_ACTIMB_165, SDRC_ACTIM_CTRLB_0);
263 __raw_writel(NUMONYX_V_ACTIMA_165, SDRC_ACTIM_CTRLA_1);
264 __raw_writel(NUMONYX_V_ACTIMB_165, SDRC_ACTIM_CTRLB_1);
265 __raw_writel(SDP_3430_SDRC_RFR_CTRL_165MHz, SDRC_RFR_CTRL_0);
266 __raw_writel(SDP_3430_SDRC_RFR_CTRL_165MHz, SDRC_RFR_CTRL_1);
267 } else if (identify_xm_ddr() == MICRON_MCP) {
268 /* Beagleboard Rev C5 */
269 __raw_writel(0x2, SDRC_CS_CFG); /* 256MB/bank */
270 __raw_writel(SDP_SDRC_MDCFG_0_DDR_MICRON_XM, SDRC_MCFG_0);
271 __raw_writel(SDP_SDRC_MDCFG_0_DDR_MICRON_XM, SDRC_MCFG_1);
272 __raw_writel(MICRON_V_ACTIMA_200, SDRC_ACTIM_CTRLA_0);
273 __raw_writel(MICRON_V_ACTIMB_200, SDRC_ACTIM_CTRLB_0);
274 __raw_writel(MICRON_V_ACTIMA_200, SDRC_ACTIM_CTRLA_1);
275 __raw_writel(MICRON_V_ACTIMB_200, SDRC_ACTIM_CTRLB_1);
276 __raw_writel(SDP_3430_SDRC_RFR_CTRL_200MHz, SDRC_RFR_CTRL_0);
277 __raw_writel(SDP_3430_SDRC_RFR_CTRL_200MHz, SDRC_RFR_CTRL_1);
279 __raw_writel(0x1, SDRC_CS_CFG); /* 128MB/bank */
280 __raw_writel(SDP_SDRC_MDCFG_0_DDR, SDRC_MCFG_0);
281 __raw_writel(SDP_SDRC_MDCFG_0_DDR, SDRC_MCFG_1);
282 __raw_writel(MICRON_V_ACTIMA_165, SDRC_ACTIM_CTRLA_0);
283 __raw_writel(MICRON_V_ACTIMB_165, SDRC_ACTIM_CTRLB_0);
284 __raw_writel(MICRON_V_ACTIMA_165, SDRC_ACTIM_CTRLA_1);
285 __raw_writel(MICRON_V_ACTIMB_165, SDRC_ACTIM_CTRLB_1);
286 __raw_writel(SDP_3430_SDRC_RFR_CTRL_165MHz, SDRC_RFR_CTRL_0);
287 __raw_writel(SDP_3430_SDRC_RFR_CTRL_165MHz, SDRC_RFR_CTRL_1);
291 if (identify_xm_ddr() == MICRON_DDR) {
292 __raw_writel(0x2, SDRC_CS_CFG); /* 256MB/bank */
293 __raw_writel(SDP_SDRC_MDCFG_0_DDR_MICRON_XM, SDRC_MCFG_0);
294 __raw_writel(SDP_SDRC_MDCFG_0_DDR_MICRON_XM, SDRC_MCFG_1);
295 __raw_writel(MICRON_V_ACTIMA_200, SDRC_ACTIM_CTRLA_0);
296 __raw_writel(MICRON_V_ACTIMB_200, SDRC_ACTIM_CTRLB_0);
297 __raw_writel(MICRON_V_ACTIMA_200, SDRC_ACTIM_CTRLA_1);
298 __raw_writel(MICRON_V_ACTIMB_200, SDRC_ACTIM_CTRLB_1);
299 __raw_writel(SDP_3430_SDRC_RFR_CTRL_200MHz, SDRC_RFR_CTRL_0);
300 __raw_writel(SDP_3430_SDRC_RFR_CTRL_200MHz, SDRC_RFR_CTRL_1);
302 __raw_writel(0x4, SDRC_CS_CFG); /* 512MB/bank */
303 __raw_writel(SDP_SDRC_MDCFG_0_DDR_NUMONYX_XM, SDRC_MCFG_0);
304 __raw_writel(SDP_SDRC_MDCFG_0_DDR_NUMONYX_XM, SDRC_MCFG_1);
305 __raw_writel(NUMONYX_V_ACTIMA_165, SDRC_ACTIM_CTRLA_0);
306 __raw_writel(NUMONYX_V_ACTIMB_165, SDRC_ACTIM_CTRLB_0);
307 __raw_writel(NUMONYX_V_ACTIMA_165, SDRC_ACTIM_CTRLA_1);
308 __raw_writel(NUMONYX_V_ACTIMB_165, SDRC_ACTIM_CTRLB_1);
309 __raw_writel(SDP_3430_SDRC_RFR_CTRL_165MHz, SDRC_RFR_CTRL_0);
310 __raw_writel(SDP_3430_SDRC_RFR_CTRL_165MHz, SDRC_RFR_CTRL_1);
314 __raw_writel(0x1, SDRC_CS_CFG); /* 128MB/bank */
315 __raw_writel(SDP_SDRC_MDCFG_0_DDR, SDRC_MCFG_0);
316 __raw_writel(SDP_SDRC_MDCFG_0_DDR, SDRC_MCFG_1);
317 __raw_writel(MICRON_V_ACTIMA_165, SDRC_ACTIM_CTRLA_0);
318 __raw_writel(MICRON_V_ACTIMB_165, SDRC_ACTIM_CTRLB_0);
319 __raw_writel(MICRON_V_ACTIMA_165, SDRC_ACTIM_CTRLA_1);
320 __raw_writel(MICRON_V_ACTIMB_165, SDRC_ACTIM_CTRLB_1);
321 __raw_writel(SDP_3430_SDRC_RFR_CTRL_165MHz, SDRC_RFR_CTRL_0);
322 __raw_writel(SDP_3430_SDRC_RFR_CTRL_165MHz, SDRC_RFR_CTRL_1);
325 __raw_writel(SDP_SDRC_POWER_POP, SDRC_POWER);
327 /* init sequence for mDDR/mSDR using manual commands (DDR is different) */
328 __raw_writel(CMD_NOP, SDRC_MANUAL_0);
329 __raw_writel(CMD_NOP, SDRC_MANUAL_1);
333 __raw_writel(CMD_PRECHARGE, SDRC_MANUAL_0);
334 __raw_writel(CMD_PRECHARGE, SDRC_MANUAL_1);
336 __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0);
337 __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_1);
339 __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0);
340 __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_1);
343 __raw_writel(SDP_SDRC_MR_0_DDR, SDRC_MR_0);
344 __raw_writel(SDP_SDRC_MR_0_DDR, SDRC_MR_1);
347 __raw_writel(SDP_SDRC_DLLAB_CTRL, SDRC_DLLA_CTRL);
348 delay(0x2000); /* give time to lock */
351 #endif /* CFG_3430SDRAM_DDR */
353 /*************************************************************
354 * get_sys_clk_speed - determine reference oscillator speed
355 * based on known 32kHz clock and gptimer.
356 *************************************************************/
357 u32 get_osc_clk_speed(void)
359 u32 start, cstart, cend, cdiff, cdiv, val;
361 val = __raw_readl(PRM_CLKSRC_CTRL);
363 if (val & SYSCLKDIV_2)
369 val = __raw_readl(CM_CLKSEL_WKUP) | BIT0;
370 __raw_writel(val, CM_CLKSEL_WKUP); /* select sys_clk for GPT1 */
372 /* Enable I and F Clocks for GPT1 */
373 val = __raw_readl(CM_ICLKEN_WKUP) | BIT0 | BIT2;
374 __raw_writel(val, CM_ICLKEN_WKUP);
375 val = __raw_readl(CM_FCLKEN_WKUP) | BIT0;
376 __raw_writel(val, CM_FCLKEN_WKUP);
378 __raw_writel(0, OMAP34XX_GPT1 + TLDR); /* start counting at 0 */
379 __raw_writel(GPT_EN, OMAP34XX_GPT1 + TCLR); /* enable clock */
380 /* enable 32kHz source */
381 /* enabled out of reset */
382 /* determine sys_clk via gauging */
384 start = 20 + __raw_readl(S32K_CR); /* start time in 20 cycles */
385 while (__raw_readl(S32K_CR) < start) ; /* dead loop till start time */
386 cstart = __raw_readl(OMAP34XX_GPT1 + TCRR); /* get start sys_clk count */
387 while (__raw_readl(S32K_CR) < (start + 20)) ; /* wait for 40 cycles */
388 cend = __raw_readl(OMAP34XX_GPT1 + TCRR); /* get end sys_clk count */
389 cdiff = cend - cstart; /* get elapsed ticks */
392 /* based on number of ticks assign speed */
395 else if (cdiff > 15200)
397 else if (cdiff > 13000)
399 else if (cdiff > 9000)
401 else if (cdiff > 7600)
407 /******************************************************************************
408 * prcm_init() - inits clocks for PRCM as defined in clocks.h
409 * -- called from SRAM, or Flash (using temp SRAM stack).
410 *****************************************************************************/
413 u32 osc_clk = 0, sys_clkin_sel;
414 dpll_param *dpll_param_p;
415 u32 clk_index, sil_index;
417 /* Gauge the input clock speed and find out the sys_clkin_sel
418 * value corresponding to the input clock.
420 osc_clk = get_osc_clk_speed();
421 get_sys_clkin_sel(osc_clk, &sys_clkin_sel);
423 sr32(PRM_CLKSEL, 0, 3, sys_clkin_sel); /* set input crystal speed */
425 /* If the input clock is greater than 19.2M always divide/2 */
426 if (sys_clkin_sel > 2) {
427 sr32(PRM_CLKSRC_CTRL, 6, 2, 2); /* input clock divider */
428 clk_index = sys_clkin_sel / 2;
430 sr32(PRM_CLKSRC_CTRL, 6, 2, 1); /* input clock divider */
431 clk_index = sys_clkin_sel;
434 sr32(PRM_CLKSRC_CTRL, 0, 2, 0);/* Bypass mode: T2 inputs a square clock */
436 /* The DPLL tables are defined according to sysclk value and
437 * silicon revision. The clk_index value will be used to get
438 * the values for that input sysclk from the DPLL param table
439 * and sil_index will get the values for that SysClk for the
440 * appropriate silicon rev.
442 sil_index = get_cpu_rev() - 1;
444 /* Unlock MPU DPLL (slows things down, and needed later) */
445 sr32(CM_CLKEN_PLL_MPU, 0, 3, PLL_LOW_POWER_BYPASS);
446 wait_on_value(BIT0, 0, CM_IDLEST_PLL_MPU, LDELAY);
448 /* Getting the base address of Core DPLL param table */
449 dpll_param_p = (dpll_param *) get_core_dpll_param();
450 /* Moving it to the right sysclk and ES rev base */
451 dpll_param_p = dpll_param_p + 3 * clk_index + sil_index;
453 /* sr32(CM_CLKSEL2_EMU) set override to work when asleep */
454 sr32(CM_CLKEN_PLL, 0, 3, PLL_FAST_RELOCK_BYPASS);
455 wait_on_value(BIT0, 0, CM_IDLEST_CKGEN, LDELAY);
457 /* For 3430 ES1.0 Errata 1.50, default value directly doesnt
458 work. write another value and then default value. */
459 sr32(CM_CLKSEL1_EMU, 16, 5, CORE_M3X2 + 1); /* m3x2 */
460 sr32(CM_CLKSEL1_EMU, 16, 5, CORE_M3X2); /* m3x2 */
461 sr32(CM_CLKSEL1_PLL, 27, 2, dpll_param_p->m2); /* Set M2 */
462 sr32(CM_CLKSEL1_PLL, 16, 11, dpll_param_p->m); /* Set M */
463 sr32(CM_CLKSEL1_PLL, 8, 7, dpll_param_p->n); /* Set N */
464 sr32(CM_CLKSEL1_PLL, 6, 1, 0); /* 96M Src */
465 sr32(CM_CLKSEL_CORE, 8, 4, CORE_SSI_DIV); /* ssi */
466 sr32(CM_CLKSEL_CORE, 4, 2, CORE_FUSB_DIV); /* fsusb */
467 sr32(CM_CLKSEL_CORE, 2, 2, CORE_L4_DIV); /* l4 */
468 sr32(CM_CLKSEL_CORE, 0, 2, CORE_L3_DIV); /* l3 */
469 sr32(CM_CLKSEL_GFX, 0, 3, GFX_DIV); /* gfx */
470 sr32(CM_CLKSEL_WKUP, 1, 2, WKUP_RSM); /* reset mgr */
471 sr32(CM_CLKEN_PLL, 4, 4, dpll_param_p->fsel); /* FREQSEL */
472 sr32(CM_CLKEN_PLL, 0, 3, PLL_LOCK); /* lock mode */
473 wait_on_value(BIT0, 1, CM_IDLEST_CKGEN, LDELAY);
475 /* Getting the base address to PER DPLL param table */
476 dpll_param_p = (dpll_param *) get_per_dpll_param();
477 /* Moving it to the right sysclk base */
478 dpll_param_p = dpll_param_p + clk_index;
480 sr32(CM_CLKEN_PLL, 16, 3, PLL_STOP);
481 wait_on_value(BIT1, 0, CM_IDLEST_CKGEN, LDELAY);
482 sr32(CM_CLKSEL1_EMU, 24, 5, PER_M6X2); /* set M6 */
483 sr32(CM_CLKSEL_CAM, 0, 5, PER_M5X2); /* set M5 */
484 sr32(CM_CLKSEL_DSS, 0, 5, PER_M4X2); /* set M4 */
485 sr32(CM_CLKSEL_DSS, 8, 5, PER_M3X2); /* set M3 */
487 if (beagle_revision() == REVISION_XM) {
488 sr32(CM_CLKSEL3_PLL, 0, 5, CORE_DPLL_PARAM_M2); /* set M2 */
489 sr32(CM_CLKSEL2_PLL, 8, 11, CORE_DPLL_PARAM_M); /* set m */
490 sr32(CM_CLKSEL2_PLL, 0, 7, CORE_DPLL_PARAM_N); /* set n */
492 sr32(CM_CLKSEL3_PLL, 0, 5, dpll_param_p->m2); /* set M2 */
493 sr32(CM_CLKSEL2_PLL, 8, 11, dpll_param_p->m); /* set m */
494 sr32(CM_CLKSEL2_PLL, 0, 7, dpll_param_p->n); /* set n */
497 sr32(CM_CLKEN_PLL, 20, 4, dpll_param_p->fsel); /* FREQSEL */
498 sr32(CM_CLKEN_PLL, 16, 3, PLL_LOCK); /* lock mode */
499 wait_on_value(BIT1, 2, CM_IDLEST_CKGEN, LDELAY);
501 /* Getting the base address to MPU DPLL param table */
502 dpll_param_p = (dpll_param *) get_mpu_dpll_param();
504 /* Moving it to the right sysclk and ES rev base */
505 dpll_param_p = dpll_param_p + 3 * clk_index + sil_index;
507 /* MPU DPLL (unlocked already) */
508 sr32(CM_CLKSEL2_PLL_MPU, 0, 5, dpll_param_p->m2); /* Set M2 */
509 sr32(CM_CLKSEL1_PLL_MPU, 8, 11, dpll_param_p->m); /* Set M */
510 sr32(CM_CLKSEL1_PLL_MPU, 0, 7, dpll_param_p->n); /* Set N */
511 sr32(CM_CLKEN_PLL_MPU, 4, 4, dpll_param_p->fsel); /* FREQSEL */
512 sr32(CM_CLKEN_PLL_MPU, 0, 3, PLL_LOCK); /* lock mode */
513 wait_on_value(BIT0, 1, CM_IDLEST_PLL_MPU, LDELAY);
515 /* Getting the base address to IVA DPLL param table */
516 dpll_param_p = (dpll_param *) get_iva_dpll_param();
517 /* Moving it to the right sysclk and ES rev base */
518 dpll_param_p = dpll_param_p + 3 * clk_index + sil_index;
519 /* IVA DPLL (set to 12*20=240MHz) */
520 sr32(CM_CLKEN_PLL_IVA2, 0, 3, PLL_STOP);
521 wait_on_value(BIT0, 0, CM_IDLEST_PLL_IVA2, LDELAY);
522 sr32(CM_CLKSEL2_PLL_IVA2, 0, 5, dpll_param_p->m2); /* set M2 */
523 sr32(CM_CLKSEL1_PLL_IVA2, 8, 11, dpll_param_p->m); /* set M */
524 sr32(CM_CLKSEL1_PLL_IVA2, 0, 7, dpll_param_p->n); /* set N */
525 sr32(CM_CLKEN_PLL_IVA2, 4, 4, dpll_param_p->fsel); /* FREQSEL */
526 sr32(CM_CLKEN_PLL_IVA2, 0, 3, PLL_LOCK); /* lock mode */
527 wait_on_value(BIT0, 1, CM_IDLEST_PLL_IVA2, LDELAY);
529 /* Set up GPTimers to sys_clk source only */
530 sr32(CM_CLKSEL_PER, 0, 8, 0xff);
531 sr32(CM_CLKSEL_WKUP, 0, 1, 1);
536 /**********************************************************
538 * Description: Does early system init of muxing and clocks.
539 * - Called at time when only stack is available.
540 **********************************************************/
545 #ifdef CONFIG_3430_AS_3410
546 /* setup the scalability control register for
547 * 3430 to work in 3410 mode
549 __raw_writel(0x5ABF, CONTROL_SCALABLE_OMAP_OCP);
556 config_3430sdram_ddr();
559 /*******************************************************
560 * Routine: misc_init_r
561 * Description: Init ethernet (done here so udelay works)
562 ********************************************************/
563 int misc_init_r(void)
567 rev = beagle_revision();
570 printf("Beagle Rev Ax/Bx\n");
573 printf("Beagle Rev C1/C2/C3\n");
576 if (identify_xm_ddr() == NUMONYX_MCP)
577 printf("Beagle Rev C4 from Special Computing\n");
578 else if(identify_xm_ddr() == MICRON_MCP)
579 printf("Beagle Rev C5\n");
581 printf("Beagle Rev C4\n");
584 printf("Beagle xM\n");
587 printf("Beagle unknown 0x%02x\n", rev);
593 /******************************************************
594 * Routine: wait_for_command_complete
595 * Description: Wait for posting to finish on watchdog
596 ******************************************************/
597 void wait_for_command_complete(unsigned int wd_base)
601 pending = __raw_readl(wd_base + WWPS);
605 /****************************************
606 * Routine: watchdog_init
607 * Description: Shut down watch dogs
608 *****************************************/
609 void watchdog_init(void)
611 /* There are 3 watch dogs WD1=Secure, WD2=MPU, WD3=IVA. WD1 is
612 * either taken care of by ROM (HS/EMU) or not accessible (GP).
613 * We need to take care of WD2-MPU or take a PRCM reset. WD3
614 * should not be running and does not generate a PRCM reset.
616 sr32(CM_FCLKEN_WKUP, 5, 1, 1);
617 sr32(CM_ICLKEN_WKUP, 5, 1, 1);
618 wait_on_value(BIT5, 0x20, CM_IDLEST_WKUP, 5); /* some issue here */
620 __raw_writel(WD_UNLOCK1, WD2_BASE + WSPR);
621 wait_for_command_complete(WD2_BASE);
622 __raw_writel(WD_UNLOCK2, WD2_BASE + WSPR);
625 /**********************************************
627 * Description: sets uboots idea of sdram size
628 **********************************************/
634 /*****************************************************************
635 * Routine: peripheral_enable
636 * Description: Enable the clks & power for perifs (GPT2, UART1,...)
637 ******************************************************************/
638 void per_clocks_enable(void)
640 /* Enable GP2 timer. */
641 sr32(CM_CLKSEL_PER, 0, 1, 0x1); /* GPT2 = sys clk */
642 sr32(CM_ICLKEN_PER, 3, 1, 0x1); /* ICKen GPT2 */
643 sr32(CM_FCLKEN_PER, 3, 1, 0x1); /* FCKen GPT2 */
647 sr32(CM_FCLKEN1_CORE, 13, 1, 0x1);
648 sr32(CM_ICLKEN1_CORE, 13, 1, 0x1);
651 sr32(CM_FCLKEN_PER, 11, 1, 0x1);
652 sr32(CM_ICLKEN_PER, 11, 1, 0x1);
656 #ifdef CONFIG_DRIVER_OMAP34XX_I2C
657 /* Turn on all 3 I2C clocks */
658 sr32(CM_FCLKEN1_CORE, 15, 3, 0x7);
659 sr32(CM_ICLKEN1_CORE, 15, 3, 0x7); /* I2C1,2,3 = on */
662 /* Enable the ICLK for 32K Sync Timer as its used in udelay */
663 sr32(CM_ICLKEN_WKUP, 2, 1, 0x1);
665 sr32(CM_FCLKEN_IVA2, 0, 32, FCK_IVA2_ON);
666 sr32(CM_FCLKEN1_CORE, 0, 32, FCK_CORE1_ON);
667 sr32(CM_ICLKEN1_CORE, 0, 32, ICK_CORE1_ON);
668 sr32(CM_ICLKEN2_CORE, 0, 32, ICK_CORE2_ON);
669 sr32(CM_FCLKEN_WKUP, 0, 32, FCK_WKUP_ON);
670 sr32(CM_ICLKEN_WKUP, 0, 32, ICK_WKUP_ON);
671 sr32(CM_FCLKEN_DSS, 0, 32, FCK_DSS_ON);
672 sr32(CM_ICLKEN_DSS, 0, 32, ICK_DSS_ON);
673 sr32(CM_FCLKEN_CAM, 0, 32, FCK_CAM_ON);
674 sr32(CM_ICLKEN_CAM, 0, 32, ICK_CAM_ON);
675 sr32(CM_FCLKEN_PER, 0, 32, FCK_PER_ON);
676 sr32(CM_ICLKEN_PER, 0, 32, ICK_PER_ON);
678 /* Enable GPIO 5 & GPIO 6 clocks */
679 sr32(CM_FCLKEN_PER, 17, 2, 0x3);
680 sr32(CM_ICLKEN_PER, 17, 2, 0x3);
685 /* Set MUX for UART, GPMC, SDRC, GPIO */
687 #define MUX_VAL(OFFSET,VALUE)\
688 __raw_writew((VALUE), OMAP34XX_CTRL_BASE + (OFFSET));
690 #define CP(x) (CONTROL_PADCONF_##x)
693 * IDIS - Input Disable
694 * PTD - Pull type Down
696 * DIS - Pull type selection is inactive
697 * EN - Pull type selection is active
699 * The commented string gives the final mux configuration for that pin
701 #define MUX_DEFAULT()\
702 MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) /*SDRC_D0*/\
703 MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) /*SDRC_D1*/\
704 MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) /*SDRC_D2*/\
705 MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) /*SDRC_D3*/\
706 MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) /*SDRC_D4*/\
707 MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) /*SDRC_D5*/\
708 MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) /*SDRC_D6*/\
709 MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) /*SDRC_D7*/\
710 MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) /*SDRC_D8*/\
711 MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) /*SDRC_D9*/\
712 MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) /*SDRC_D10*/\
713 MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) /*SDRC_D11*/\
714 MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) /*SDRC_D12*/\
715 MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) /*SDRC_D13*/\
716 MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) /*SDRC_D14*/\
717 MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) /*SDRC_D15*/\
718 MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) /*SDRC_D16*/\
719 MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) /*SDRC_D17*/\
720 MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) /*SDRC_D18*/\
721 MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) /*SDRC_D19*/\
722 MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) /*SDRC_D20*/\
723 MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) /*SDRC_D21*/\
724 MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) /*SDRC_D22*/\
725 MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) /*SDRC_D23*/\
726 MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) /*SDRC_D24*/\
727 MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) /*SDRC_D25*/\
728 MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) /*SDRC_D26*/\
729 MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) /*SDRC_D27*/\
730 MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) /*SDRC_D28*/\
731 MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) /*SDRC_D29*/\
732 MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) /*SDRC_D30*/\
733 MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) /*SDRC_D31*/\
734 MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) /*SDRC_CLK*/\
735 MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) /*SDRC_DQS0*/\
736 MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) /*SDRC_DQS1*/\
737 MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) /*SDRC_DQS2*/\
738 MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) /*SDRC_DQS3*/\
739 MUX_VAL(CP(GPMC_A1), (IDIS | PTD | DIS | M0)) /*GPMC_A1*/\
740 MUX_VAL(CP(GPMC_A2), (IDIS | PTD | DIS | M0)) /*GPMC_A2*/\
741 MUX_VAL(CP(GPMC_A3), (IDIS | PTD | DIS | M0)) /*GPMC_A3*/\
742 MUX_VAL(CP(GPMC_A4), (IDIS | PTD | DIS | M0)) /*GPMC_A4*/\
743 MUX_VAL(CP(GPMC_A5), (IDIS | PTD | DIS | M0)) /*GPMC_A5*/\
744 MUX_VAL(CP(GPMC_A6), (IDIS | PTD | DIS | M0)) /*GPMC_A6*/\
745 MUX_VAL(CP(GPMC_A7), (IDIS | PTD | DIS | M0)) /*GPMC_A7*/\
746 MUX_VAL(CP(GPMC_A8), (IDIS | PTD | DIS | M0)) /*GPMC_A8*/\
747 MUX_VAL(CP(GPMC_A9), (IDIS | PTD | DIS | M0)) /*GPMC_A9*/\
748 MUX_VAL(CP(GPMC_A10), (IDIS | PTD | DIS | M0)) /*GPMC_A10*/\
749 MUX_VAL(CP(GPMC_D0), (IEN | PTD | DIS | M0)) /*GPMC_D0*/\
750 MUX_VAL(CP(GPMC_D1), (IEN | PTD | DIS | M0)) /*GPMC_D1*/\
751 MUX_VAL(CP(GPMC_D2), (IEN | PTD | DIS | M0)) /*GPMC_D2*/\
752 MUX_VAL(CP(GPMC_D3), (IEN | PTD | DIS | M0)) /*GPMC_D3*/\
753 MUX_VAL(CP(GPMC_D4), (IEN | PTD | DIS | M0)) /*GPMC_D4*/\
754 MUX_VAL(CP(GPMC_D5), (IEN | PTD | DIS | M0)) /*GPMC_D5*/\
755 MUX_VAL(CP(GPMC_D6), (IEN | PTD | DIS | M0)) /*GPMC_D6*/\
756 MUX_VAL(CP(GPMC_D7), (IEN | PTD | DIS | M0)) /*GPMC_D7*/\
757 MUX_VAL(CP(GPMC_D8), (IEN | PTD | DIS | M0)) /*GPMC_D8*/\
758 MUX_VAL(CP(GPMC_D9), (IEN | PTD | DIS | M0)) /*GPMC_D9*/\
759 MUX_VAL(CP(GPMC_D10), (IEN | PTD | DIS | M0)) /*GPMC_D10*/\
760 MUX_VAL(CP(GPMC_D11), (IEN | PTD | DIS | M0)) /*GPMC_D11*/\
761 MUX_VAL(CP(GPMC_D12), (IEN | PTD | DIS | M0)) /*GPMC_D12*/\
762 MUX_VAL(CP(GPMC_D13), (IEN | PTD | DIS | M0)) /*GPMC_D13*/\
763 MUX_VAL(CP(GPMC_D14), (IEN | PTD | DIS | M0)) /*GPMC_D14*/\
764 MUX_VAL(CP(GPMC_D15), (IEN | PTD | DIS | M0)) /*GPMC_D15*/\
765 MUX_VAL(CP(GPMC_nCS0), (IDIS | PTU | EN | M0)) /*GPMC_nCS0*/\
766 MUX_VAL(CP(GPMC_nCS1), (IDIS | PTU | EN | M0)) /*GPMC_nCS1*/\
767 MUX_VAL(CP(GPMC_nCS2), (IDIS | PTU | EN | M0)) /*GPMC_nCS2*/\
768 MUX_VAL(CP(GPMC_nCS3), (IDIS | PTU | EN | M0)) /*GPMC_nCS3*/\
769 MUX_VAL(CP(GPMC_nCS4), (IDIS | PTU | EN | M0)) /*GPMC_nCS4*/\
770 MUX_VAL(CP(GPMC_nCS5), (IDIS | PTD | DIS | M0)) /*GPMC_nCS5*/\
771 MUX_VAL(CP(GPMC_nCS6), (IEN | PTD | DIS | M1)) /*GPMC_nCS6*/\
772 MUX_VAL(CP(GPMC_nCS7), (IEN | PTU | EN | M1)) /*GPMC_nCS7*/\
773 MUX_VAL(CP(GPMC_CLK), (IDIS | PTD | DIS | M0)) /*GPMC_CLK*/\
774 MUX_VAL(CP(GPMC_nADV_ALE), (IDIS | PTD | DIS | M0)) /*GPMC_nADV_ALE*/\
775 MUX_VAL(CP(GPMC_nOE), (IDIS | PTD | DIS | M0)) /*GPMC_nOE*/\
776 MUX_VAL(CP(GPMC_nWE), (IDIS | PTD | DIS | M0)) /*GPMC_nWE*/\
777 MUX_VAL(CP(GPMC_nBE0_CLE), (IDIS | PTD | DIS | M0)) /*GPMC_nBE0_CLE*/\
778 MUX_VAL(CP(GPMC_nBE1), (IEN | PTD | DIS | M0)) /*GPIO_61*/\
779 MUX_VAL(CP(GPMC_nWP), (IEN | PTD | DIS | M0)) /*GPMC_nWP*/\
780 MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) /*GPMC_WAIT0*/\
781 MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0)) /*GPMC_WAIT1*/\
782 MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M0)) /*GPIO_64*/\
783 MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M0)) /*GPIO_65*/\
784 MUX_VAL(CP(DSS_DATA18), (IEN | PTD | DIS | M4)) /*GPIO_88*/\
785 MUX_VAL(CP(DSS_DATA19), (IEN | PTD | DIS | M4)) /*GPIO_89*/\
786 MUX_VAL(CP(DSS_DATA20), (IEN | PTD | DIS | M4)) /*GPIO_90*/\
787 MUX_VAL(CP(DSS_DATA21), (IEN | PTD | DIS | M4)) /*GPIO_91*/\
788 MUX_VAL(CP(CAM_WEN), (IEN | PTD | DIS | M4)) /*GPIO_167*/\
789 MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0)) /*MMC1_CLK*/\
790 MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)) /*MMC1_CMD*/\
791 MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)) /*MMC1_DAT0*/\
792 MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)) /*MMC1_DAT1*/\
793 MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)) /*MMC1_DAT2*/\
794 MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)) /*MMC1_DAT3*/\
795 MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | EN | M0)) /*MMC1_DAT4*/\
796 MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M0)) /*MMC1_DAT5*/\
797 MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M0)) /*MMC1_DAT6*/\
798 MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M0)) /*MMC1_DAT7*/\
799 MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) /*UART1_TX*/\
800 MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M4)) /*GPIO_149*/\
801 MUX_VAL(CP(UART1_CTS), (IDIS | PTD | DIS | M4)) /*GPIO_150*/\
802 MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) /*UART1_RX*/\
803 MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTD | EN | M0)) /*UART3_CTS_RCTX */\
804 MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTD | DIS | M0)) /*UART3_RTS_SD */\
805 MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)) /*UART3_RX_IRRX*/\
806 MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) /*UART3_TX_IRTX*/\
807 MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) /*I2C1_SCL*/\
808 MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) /*I2C1_SDA*/\
809 MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0)) /*I2C2_SCL*/\
810 MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0)) /*I2C2_SDA*/\
811 MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)) /*I2C3_SCL*/\
812 MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)) /*I2C3_SDA*/\
813 MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) /*I2C4_SCL*/\
814 MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) /*I2C4_SDA*/\
815 MUX_VAL(CP(McSPI1_CLK), (IEN | PTU | EN | M4)) /*GPIO_171*/\
816 MUX_VAL(CP(McSPI1_SIMO), (IEN | PTU | EN | M4)) /*GPIO_172*/\
817 MUX_VAL(CP(McSPI1_SOMI), (IEN | PTU | EN | M4)) /*GPIO_173*/\
818 MUX_VAL(CP(McBSP1_DX), (IEN | PTD | DIS | M4)) /*GPIO_158*/\
819 MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) /*SYS_32K*/\
820 MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) /*GPIO_2 */\
821 MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) /*GPIO_3 */\
822 MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) /*GPIO_4 */\
823 MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)) /*GPIO_5 */\
824 MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) /*GPIO_6 */\
825 MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)) /*GPIO_7 */\
826 MUX_VAL(CP(SYS_BOOT6), (IEN | PTD | DIS | M4)) /*GPIO_8 */\
827 MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M4)) /*GPIO_186*/\
828 MUX_VAL(CP(JTAG_nTRST), (IEN | PTD | DIS | M0)) /*JTAG_nTRST*/\
829 MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)) /*JTAG_TCK*/\
830 MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)) /*JTAG_TMS*/\
831 MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)) /*JTAG_TDI*/\
832 MUX_VAL(CP(JTAG_EMU0), (IEN | PTD | DIS | M0)) /*JTAG_EMU0*/\
833 MUX_VAL(CP(JTAG_EMU1), (IEN | PTD | DIS | M0)) /*JTAG_EMU1*/\
834 MUX_VAL(CP(ETK_CLK), (IEN | PTD | DIS | M4)) /*GPIO_12*/\
835 MUX_VAL(CP(ETK_CTL), (IEN | PTD | DIS | M4)) /*GPIO_13*/\
836 MUX_VAL(CP(ETK_D0), (IEN | PTD | DIS | M4)) /*GPIO_14*/\
837 MUX_VAL(CP(ETK_D1), (IEN | PTD | DIS | M4)) /*GPIO_15*/\
838 MUX_VAL(CP(ETK_D2), (IEN | PTD | DIS | M4)) /*GPIO_16*/\
839 MUX_VAL(CP(ETK_D11), (IEN | PTD | DIS | M4)) /*GPIO_25*/\
840 MUX_VAL(CP(ETK_D12), (IEN | PTD | DIS | M4)) /*GPIO_26*/\
841 MUX_VAL(CP(ETK_D13), (IEN | PTD | DIS | M4)) /*GPIO_27*/\
842 MUX_VAL(CP(ETK_D14), (IEN | PTD | DIS | M4)) /*GPIO_28*/\
843 MUX_VAL(CP(ETK_D15), (IEN | PTD | DIS | M4)) /*GPIO_29 */\
844 MUX_VAL(CP(sdrc_cke0), (IDIS | PTU | EN | M0)) /*sdrc_cke0 */\
845 MUX_VAL(CP(sdrc_cke1), (IDIS | PTD | DIS | M7)) /*sdrc_cke1 not used*/
847 /**********************************************************
848 * Routine: set_muxconf_regs
849 * Description: Setting up the configuration Mux registers
850 * specific to the hardware. Many pins need
851 * to be moved from protect to primary mode.
852 *********************************************************/
853 void set_muxconf_regs(void)
858 /**********************************************************
859 * Routine: nand+_init
860 * Description: Set up nand for nand and jffs2 commands
861 *********************************************************/
865 /* global settings */
866 __raw_writel(0x10, GPMC_SYSCONFIG); /* smart idle */
867 __raw_writel(0x0, GPMC_IRQENABLE); /* isr's sources masked */
868 __raw_writel(0, GPMC_TIMEOUT_CONTROL);/* timeout disable */
870 /* Set the GPMC Vals, NAND is mapped at CS0, oneNAND at CS0.
871 * We configure only GPMC CS0 with required values. Configiring other devices
872 * at other CS is done in u-boot. So we don't have to bother doing it here.
874 __raw_writel(0 , GPMC_CONFIG7 + GPMC_CONFIG_CS0);
877 #ifdef CFG_NAND_K9F1G08R0A
878 if ((get_mem_type() == GPMC_NAND) || (get_mem_type() == MMC_NAND)) {
879 __raw_writel(M_NAND_GPMC_CONFIG1, GPMC_CONFIG1 + GPMC_CONFIG_CS0);
880 __raw_writel(M_NAND_GPMC_CONFIG2, GPMC_CONFIG2 + GPMC_CONFIG_CS0);
881 __raw_writel(M_NAND_GPMC_CONFIG3, GPMC_CONFIG3 + GPMC_CONFIG_CS0);
882 __raw_writel(M_NAND_GPMC_CONFIG4, GPMC_CONFIG4 + GPMC_CONFIG_CS0);
883 __raw_writel(M_NAND_GPMC_CONFIG5, GPMC_CONFIG5 + GPMC_CONFIG_CS0);
884 __raw_writel(M_NAND_GPMC_CONFIG6, GPMC_CONFIG6 + GPMC_CONFIG_CS0);
886 /* Enable the GPMC Mapping */
887 __raw_writel((((OMAP34XX_GPMC_CS0_SIZE & 0xF)<<8) |
888 ((NAND_BASE_ADR>>24) & 0x3F) |
889 (1<<6)), (GPMC_CONFIG7 + GPMC_CONFIG_CS0));
894 printf("Unsupported Chip!\n");
902 if ((get_mem_type() == GPMC_ONENAND) || (get_mem_type() == MMC_ONENAND)) {
903 __raw_writel(ONENAND_GPMC_CONFIG1, GPMC_CONFIG1 + GPMC_CONFIG_CS0);
904 __raw_writel(ONENAND_GPMC_CONFIG2, GPMC_CONFIG2 + GPMC_CONFIG_CS0);
905 __raw_writel(ONENAND_GPMC_CONFIG3, GPMC_CONFIG3 + GPMC_CONFIG_CS0);
906 __raw_writel(ONENAND_GPMC_CONFIG4, GPMC_CONFIG4 + GPMC_CONFIG_CS0);
907 __raw_writel(ONENAND_GPMC_CONFIG5, GPMC_CONFIG5 + GPMC_CONFIG_CS0);
908 __raw_writel(ONENAND_GPMC_CONFIG6, GPMC_CONFIG6 + GPMC_CONFIG_CS0);
910 /* Enable the GPMC Mapping */
911 __raw_writel((((OMAP34XX_GPMC_CS0_SIZE & 0xF)<<8) |
912 ((ONENAND_BASE>>24) & 0x3F) |
913 (1<<6)), (GPMC_CONFIG7 + GPMC_CONFIG_CS0));
916 if (onenand_chip()) {
918 printf("OneNAND Unsupported !\n");
927 #define DEBUG_LED1 149 /* gpio */
928 #define DEBUG_LED2 150 /* gpio */
934 /* Alternately turn the LEDs on and off */
935 p = (unsigned long *)OMAP34XX_GPIO5_BASE;
937 /* turn LED1 on and LED2 off */
938 *(unsigned long *)(p + 0x94) = 1 << (DEBUG_LED1 % 32);
939 *(unsigned long *)(p + 0x90) = 1 << (DEBUG_LED2 % 32);
941 /* delay for a while */
944 /* turn LED1 off and LED2 on */
945 *(unsigned long *)(p + 0x90) = 1 << (DEBUG_LED1 % 32);
946 *(unsigned long *)(p + 0x94) = 1 << (DEBUG_LED2 % 32);
948 /* delay for a while */
953 /* optionally do something like blinking LED */
954 void board_hang(void)
960 /******************************************************************************
961 * Dummy function to handle errors for EABI incompatibility
962 *****************************************************************************/
967 /******************************************************************************
968 * Dummy function to handle errors for EABI incompatibility
969 *****************************************************************************/