2 * (C) Copyright 2006-2008
3 * Texas Instruments, <www.ti.com>
4 * Jian Zhang <jzhang@ti.com>
5 * Richard Woodruff <r-woodruff2@ti.com>
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <asm/arch/cpu.h>
27 #include <asm/arch/bits.h>
28 #include <asm/arch/mux.h>
29 #include <asm/arch/sys_proto.h>
30 #include <asm/arch/sys_info.h>
31 #include <asm/arch/clocks.h>
32 #include <asm/arch/mem.h>
34 /* Used to index into DPLL parameter tables */
42 typedef struct dpll_param dpll_param;
44 #define MAX_SIL_INDEX 3
46 /* Following functions are exported from lowlevel_init.S */
47 extern dpll_param * get_mpu_dpll_param(void);
48 extern dpll_param * get_iva_dpll_param(void);
49 extern dpll_param * get_core_dpll_param(void);
50 extern dpll_param * get_per_dpll_param(void);
52 #define __raw_readl(a) (*(volatile unsigned int *)(a))
53 #define __raw_writel(v,a) (*(volatile unsigned int *)(a) = (v))
54 #define __raw_readw(a) (*(volatile unsigned short *)(a))
55 #define __raw_writew(v,a) (*(volatile unsigned short *)(a) = (v))
57 /*******************************************************
59 * Description: spinning delay to use before udelay works
60 ******************************************************/
61 static inline void delay(unsigned long loops)
63 __asm__ volatile ("1:\n" "subs %0, %1, #1\n"
64 "bne 1b":"=r" (loops):"0"(loops));
67 /*****************************************
69 * Description: Early hardware init.
70 *****************************************/
76 /******************************************
77 * get_cpu_rev(void) - extract version info
78 ******************************************/
82 /* On ES1.0 the IDCODE register is not exposed on L4
83 * so using CPU ID to differentiate
84 * between ES2.0 and ES1.0.
86 __asm__ __volatile__("mrc p15, 0, %0, c0, c0, 0":"=r" (cpuid));
87 if((cpuid & 0xf) == 0x0)
94 /******************************************
95 * cpu_is_3410(void) - returns true for 3410
96 ******************************************/
100 if(get_cpu_rev() < CPU_3430_ES2) {
103 /* read scalability status and return 1 for 3410*/
104 status = __raw_readl(CONTROL_SCALABLE_OMAP_STATUS);
105 /* Check whether MPU frequency is set to 266 MHz which
106 * is nominal for 3410. If yes return true else false
108 if (((status >> 8) & 0x3) == 0x2)
115 /*****************************************************************
116 * sr32 - clear & set a value in a bit range for a 32 bit address
117 *****************************************************************/
118 void sr32(u32 addr, u32 start_bit, u32 num_bits, u32 value)
123 tmp = __raw_readl(addr) & ~(msk << start_bit);
124 tmp |= value << start_bit;
125 __raw_writel(tmp, addr);
128 /*********************************************************************
129 * wait_on_value() - common routine to allow waiting for changes in
131 *********************************************************************/
132 u32 wait_on_value(u32 read_bit_mask, u32 match_value, u32 read_addr, u32 bound)
137 val = __raw_readl(read_addr) & read_bit_mask;
138 if (val == match_value)
145 #ifdef CFG_3430SDRAM_DDR
146 /*********************************************************************
147 * config_3430sdram_ddr() - Init DDR on 3430SDP dev board.
148 *********************************************************************/
149 void config_3430sdram_ddr(void)
151 /* reset sdrc controller */
152 __raw_writel(SOFTRESET, SDRC_SYSCONFIG);
153 wait_on_value(BIT0, BIT0, SDRC_STATUS, 12000000);
154 __raw_writel(0, SDRC_SYSCONFIG);
156 /* setup sdrc to ball mux */
157 __raw_writel(SDP_SDRC_SHARING, SDRC_SHARING);
160 __raw_writel(SDP_SDRC_MDCFG_0_DDR, SDRC_MCFG_0);
163 __raw_writel(SDP_SDRC_ACTIM_CTRLA_0, SDRC_ACTIM_CTRLA_0);
164 __raw_writel(SDP_SDRC_ACTIM_CTRLB_0, SDRC_ACTIM_CTRLB_0);
165 __raw_writel(SDP_SDRC_RFR_CTRL, SDRC_RFR_CTRL);
167 /* init sequence for mDDR/mSDR using manual commands (DDR is different) */
168 __raw_writel(CMD_NOP, SDRC_MANUAL_0);
170 __raw_writel(CMD_PRECHARGE, SDRC_MANUAL_0);
171 __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0);
172 __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0);
175 __raw_writel(SDP_SDRC_MR_0_DDR, SDRC_MR_0);
178 __raw_writel(SDP_SDRC_DLLAB_CTRL, SDRC_DLLA_CTRL);
179 delay(0x2000); /* give time to lock */
182 #endif // CFG_3430SDRAM_DDR
184 /*************************************************************
185 * get_sys_clk_speed - determine reference oscillator speed
186 * based on known 32kHz clock and gptimer.
187 *************************************************************/
188 u32 get_osc_clk_speed(void)
190 u32 start, cstart, cend, cdiff, val;
192 val = __raw_readl(PRM_CLKSRC_CTRL);
193 /* If SYS_CLK is being divided by 2, remove for now */
194 val = (val & (~BIT7)) | BIT6;
195 __raw_writel(val, PRM_CLKSRC_CTRL);
198 val = __raw_readl(CM_CLKSEL_WKUP) | BIT0;
199 __raw_writel(val, CM_CLKSEL_WKUP); /* select sys_clk for GPT1 */
201 /* Enable I and F Clocks for GPT1 */
202 val = __raw_readl(CM_ICLKEN_WKUP) | BIT0 | BIT2;
203 __raw_writel(val, CM_ICLKEN_WKUP);
204 val = __raw_readl(CM_FCLKEN_WKUP) | BIT0;
205 __raw_writel(val, CM_FCLKEN_WKUP);
207 __raw_writel(0, OMAP34XX_GPT1 + TLDR); /* start counting at 0 */
208 __raw_writel(GPT_EN, OMAP34XX_GPT1 + TCLR); /* enable clock */
209 /* enable 32kHz source *//* enabled out of reset */
210 /* determine sys_clk via gauging */
212 start = 20 + __raw_readl(S32K_CR); /* start time in 20 cycles */
213 while (__raw_readl(S32K_CR) < start); /* dead loop till start time */
214 cstart = __raw_readl(OMAP34XX_GPT1 + TCRR); /* get start sys_clk count */
215 while (__raw_readl(S32K_CR) < (start + 20)); /* wait for 40 cycles */
216 cend = __raw_readl(OMAP34XX_GPT1 + TCRR); /* get end sys_clk count */
217 cdiff = cend - cstart; /* get elapsed ticks */
219 /* based on number of ticks assign speed */
222 else if (cdiff > 15200)
224 else if (cdiff > 13000)
226 else if (cdiff > 9000)
228 else if (cdiff > 7600)
234 /******************************************************************************
235 * get_sys_clkin_sel() - returns the sys_clkin_sel field value based on
236 * -- input oscillator clock frequency.
238 *****************************************************************************/
239 void get_sys_clkin_sel(u32 osc_clk, u32 *sys_clkin_sel)
241 if(osc_clk == S38_4M)
243 else if(osc_clk == S26M)
245 else if(osc_clk == S19_2M)
247 else if(osc_clk == S13M)
249 else if(osc_clk == S12M)
253 /******************************************************************************
254 * prcm_init() - inits clocks for PRCM as defined in clocks.h
255 * -- called from SRAM, or Flash (using temp SRAM stack).
256 *****************************************************************************/
259 u32 osc_clk=0, sys_clkin_sel;
260 dpll_param *dpll_param_p;
261 u32 clk_index, sil_index;
263 /* Gauge the input clock speed and find out the sys_clkin_sel
264 * value corresponding to the input clock.
266 osc_clk = get_osc_clk_speed();
267 get_sys_clkin_sel(osc_clk, &sys_clkin_sel);
269 sr32(PRM_CLKSEL, 0, 3, sys_clkin_sel); /* set input crystal speed */
271 /* If the input clock is greater than 19.2M always divide/2 */
272 if(sys_clkin_sel > 2) {
273 sr32(PRM_CLKSRC_CTRL, 6, 2, 2);/* input clock divider */
274 clk_index = sys_clkin_sel/2;
276 sr32(PRM_CLKSRC_CTRL, 6, 2, 1);/* input clock divider */
277 clk_index = sys_clkin_sel;
280 sr32(PRM_CLKSRC_CTRL, 0, 2, 0);/* Bypass mode: T2 inputs a square clock */
282 /* The DPLL tables are defined according to sysclk value and
283 * silicon revision. The clk_index value will be used to get
284 * the values for that input sysclk from the DPLL param table
285 * and sil_index will get the values for that SysClk for the
286 * appropriate silicon rev.
291 if(get_cpu_rev() == CPU_3430_ES1)
293 else if(get_cpu_rev() == CPU_3430_ES2)
297 /* Unlock MPU DPLL (slows things down, and needed later) */
298 sr32(CM_CLKEN_PLL_MPU, 0, 3, PLL_LOW_POWER_BYPASS);
299 wait_on_value(BIT0, 0, CM_IDLEST_PLL_MPU, LDELAY);
301 /* Getting the base address of Core DPLL param table*/
302 dpll_param_p = (dpll_param *)get_core_dpll_param();
303 /* Moving it to the right sysclk and ES rev base */
304 dpll_param_p = dpll_param_p + MAX_SIL_INDEX*clk_index + sil_index;
306 /* sr32(CM_CLKSEL2_EMU) set override to work when asleep */
307 sr32(CM_CLKEN_PLL, 0, 3, PLL_FAST_RELOCK_BYPASS);
308 wait_on_value(BIT0, 0, CM_IDLEST_CKGEN, LDELAY);
309 /* For 3430 ES1.0 Errata 1.50, default value directly doesnt
310 work. write another value and then default value. */
311 sr32(CM_CLKSEL1_EMU, 16, 5, CORE_M3X2 + 1); /* m3x2 */
312 sr32(CM_CLKSEL1_EMU, 16, 5, CORE_M3X2); /* m3x2 */
313 sr32(CM_CLKSEL1_PLL, 27, 2, dpll_param_p->m2); /* Set M2 */
314 sr32(CM_CLKSEL1_PLL, 16, 11, dpll_param_p->m); /* Set M */
315 sr32(CM_CLKSEL1_PLL, 8, 7, dpll_param_p->n); /* Set N */
316 sr32(CM_CLKSEL1_PLL, 6, 1, 0); /* 96M Src */
317 sr32(CM_CLKSEL_CORE, 8, 4, CORE_SSI_DIV); /* ssi */
318 sr32(CM_CLKSEL_CORE, 4, 2, CORE_FUSB_DIV); /* fsusb ES1 only */
319 sr32(CM_CLKSEL_CORE, 2, 2, CORE_L4_DIV); /* l4 */
320 sr32(CM_CLKSEL_CORE, 0, 2, CORE_L3_DIV); /* l3 */
321 sr32(CM_CLKSEL_GFX, 0, 3, GFX_DIV); /* gfx */
322 sr32(CM_CLKSEL_WKUP, 1, 2, WKUP_RSM); /* reset mgr */
323 sr32(CM_CLKEN_PLL, 4, 4, dpll_param_p->fsel); /* FREQSEL */
324 sr32(CM_CLKEN_PLL, 0, 3, PLL_LOCK); /* lock mode */
325 wait_on_value(BIT0, 1, CM_IDLEST_CKGEN, LDELAY);
327 /* Getting the base address to PER DPLL param table*/
328 dpll_param_p = (dpll_param *)get_per_dpll_param();
329 /* Moving it to the right sysclk base */
330 dpll_param_p = dpll_param_p + clk_index;
332 sr32(CM_CLKEN_PLL, 16, 3, PLL_STOP);
333 wait_on_value(BIT1, 0, CM_IDLEST_CKGEN, LDELAY);
334 sr32(CM_CLKSEL1_EMU, 24, 5, PER_M6X2); /* set M6 */
335 sr32(CM_CLKSEL_CAM, 0, 5, PER_M5X2); /* set M5 */
336 sr32(CM_CLKSEL_DSS, 0, 5, PER_M4X2); /* set M4 */
337 sr32(CM_CLKSEL_DSS, 8, 5, PER_M3X2); /* set M3 */
338 sr32(CM_CLKSEL3_PLL, 0, 5, dpll_param_p->m2); /* set M2 */
339 sr32(CM_CLKSEL2_PLL, 8, 11, dpll_param_p->m); /* set m */
340 sr32(CM_CLKSEL2_PLL, 0, 7, dpll_param_p->n); /* set n */
341 sr32(CM_CLKEN_PLL, 20, 4, dpll_param_p->fsel);/* FREQSEL */
342 sr32(CM_CLKEN_PLL, 16, 3, PLL_LOCK); /* lock mode */
343 wait_on_value(BIT1, 2, CM_IDLEST_CKGEN, LDELAY);
345 /* Getting the base address to MPU DPLL param table*/
346 dpll_param_p = (dpll_param *)get_mpu_dpll_param();
347 /* Moving it to the right sysclk and ES rev base */
348 dpll_param_p = dpll_param_p + MAX_SIL_INDEX*clk_index + sil_index;
349 /* MPU DPLL (unlocked already) */
350 sr32(CM_CLKSEL2_PLL_MPU, 0, 5, dpll_param_p->m2); /* Set M2 */
351 sr32(CM_CLKSEL1_PLL_MPU, 8, 11, dpll_param_p->m); /* Set M */
352 sr32(CM_CLKSEL1_PLL_MPU, 0, 7, dpll_param_p->n); /* Set N */
353 sr32(CM_CLKEN_PLL_MPU, 4, 4, dpll_param_p->fsel); /* FREQSEL */
354 sr32(CM_CLKEN_PLL_MPU, 0, 3, PLL_LOCK); /* lock mode */
355 wait_on_value(BIT0, 1, CM_IDLEST_PLL_MPU, LDELAY);
357 /* Getting the base address to IVA DPLL param table*/
358 dpll_param_p = (dpll_param *)get_iva_dpll_param();
359 /* Moving it to the right sysclk and ES rev base */
360 dpll_param_p = dpll_param_p + MAX_SIL_INDEX*clk_index + sil_index;
361 /* IVA DPLL (set to 12*20=240MHz) */
362 sr32(CM_CLKEN_PLL_IVA2, 0, 3, PLL_STOP);
363 wait_on_value(BIT0, 0, CM_IDLEST_PLL_IVA2, LDELAY);
364 sr32(CM_CLKSEL2_PLL_IVA2, 0, 5, dpll_param_p->m2); /* set M2 */
365 sr32(CM_CLKSEL1_PLL_IVA2, 8, 11, dpll_param_p->m); /* set M */
366 sr32(CM_CLKSEL1_PLL_IVA2, 0, 7, dpll_param_p->n); /* set N */
367 sr32(CM_CLKEN_PLL_IVA2, 4, 4, dpll_param_p->fsel); /* FREQSEL */
368 sr32(CM_CLKEN_PLL_IVA2, 0, 3, PLL_LOCK); /* lock mode */
369 wait_on_value(BIT0, 1, CM_IDLEST_PLL_IVA2, LDELAY);
371 /* Set up GPTimers to sys_clk source only */
372 sr32(CM_CLKSEL_PER, 0, 8, 0xff);
373 sr32(CM_CLKSEL_WKUP, 0, 1, 1);
378 /*****************************************
379 * Routine: secure_unlock
380 * Description: Setup security registers for access
382 *****************************************/
383 void secure_unlock(void)
385 /* Permission values for registers -Full fledged permissions to all */
386 #define UNLOCK_1 0xFFFFFFFF
387 #define UNLOCK_2 0x00000000
388 #define UNLOCK_3 0x0000FFFF
389 /* Protection Module Register Target APE (PM_RT)*/
390 __raw_writel(UNLOCK_1, RT_REQ_INFO_PERMISSION_1);
391 __raw_writel(UNLOCK_1, RT_READ_PERMISSION_0);
392 __raw_writel(UNLOCK_1, RT_WRITE_PERMISSION_0);
393 __raw_writel(UNLOCK_2, RT_ADDR_MATCH_1);
395 __raw_writel(UNLOCK_3, GPMC_REQ_INFO_PERMISSION_0);
396 __raw_writel(UNLOCK_3, GPMC_READ_PERMISSION_0);
397 __raw_writel(UNLOCK_3, GPMC_WRITE_PERMISSION_0);
399 __raw_writel(UNLOCK_3, OCM_REQ_INFO_PERMISSION_0);
400 __raw_writel(UNLOCK_3, OCM_READ_PERMISSION_0);
401 __raw_writel(UNLOCK_3, OCM_WRITE_PERMISSION_0);
402 __raw_writel(UNLOCK_2, OCM_ADDR_MATCH_2);
405 __raw_writel(UNLOCK_3, IVA2_REQ_INFO_PERMISSION_0);
406 __raw_writel(UNLOCK_3, IVA2_READ_PERMISSION_0);
407 __raw_writel(UNLOCK_3, IVA2_WRITE_PERMISSION_0);
409 __raw_writel(UNLOCK_1, SMS_RG_ATT0); /* SDRC region 0 public */
412 /**********************************************************
413 * Routine: try_unlock_sram()
414 * Description: If chip is GP type, unlock the SRAM for
416 ***********************************************************/
417 void try_unlock_memory(void)
421 /* if GP device unlock device SRAM for general use */
422 /* secure code breaks for Secure/Emulation device - HS/E/T*/
423 mode = get_device_type();
424 if (mode == GP_DEVICE) {
430 /**********************************************************
432 * Description: Does early system init of muxing and clocks.
433 * - Called at time when only stack is available.
434 **********************************************************/
439 #ifdef CONFIG_3430_AS_3410
440 /* setup the scalability control register for
441 * 3430 to work in 3410 mode
443 __raw_writel(0x5ABF,CONTROL_SCALABLE_OMAP_OCP);
450 config_3430sdram_ddr();
453 /*******************************************************
454 * Routine: misc_init_r
455 * Description: Init ethernet (done here so udelay works)
456 ********************************************************/
457 int misc_init_r (void)
462 /******************************************************
463 * Routine: wait_for_command_complete
464 * Description: Wait for posting to finish on watchdog
465 ******************************************************/
466 void wait_for_command_complete(unsigned int wd_base)
470 pending = __raw_readl(wd_base + WWPS);
474 /****************************************
475 * Routine: watchdog_init
476 * Description: Shut down watch dogs
477 *****************************************/
478 void watchdog_init(void)
480 /* There are 3 watch dogs WD1=Secure, WD2=MPU, WD3=IVA. WD1 is
481 * either taken care of by ROM (HS/EMU) or not accessible (GP).
482 * We need to take care of WD2-MPU or take a PRCM reset. WD3
483 * should not be running and does not generate a PRCM reset.
485 sr32(CM_FCLKEN_WKUP, 5, 1, 1);
486 sr32(CM_ICLKEN_WKUP, 5, 1, 1);
487 wait_on_value(BIT5, 0x20, CM_IDLEST_WKUP, 5); /* some issue here */
489 __raw_writel(WD_UNLOCK1, WD2_BASE + WSPR);
490 wait_for_command_complete(WD2_BASE);
491 __raw_writel(WD_UNLOCK2, WD2_BASE + WSPR);
494 /**********************************************
496 * Description: sets uboots idea of sdram size
497 **********************************************/
503 /*****************************************************************
504 * Routine: peripheral_enable
505 * Description: Enable the clks & power for perifs (GPT2, UART1,...)
506 ******************************************************************/
507 void per_clocks_enable(void)
509 /* Enable GP2 timer. */
510 sr32(CM_CLKSEL_PER, 0, 1, 0x1); /* GPT2 = sys clk */
511 sr32(CM_ICLKEN_PER, 3, 1, 0x1); /* ICKen GPT2 */
512 sr32(CM_FCLKEN_PER, 3, 1, 0x1); /* FCKen GPT2 */
515 ////#ifdef CONFIG_SERIAL3
516 sr32(CM_FCLKEN_PER, 11, 1, 0x1);
517 sr32(CM_ICLKEN_PER, 11, 1, 0x1);
519 /* Enable UART1 clocks */
520 sr32(CM_FCLKEN1_CORE, 13, 1, 0x1);
521 sr32(CM_ICLKEN1_CORE, 13, 1, 0x1);
527 /* Set MUX for UART, GPMC, SDRC, GPIO */
529 #define MUX_VAL(OFFSET,VALUE)\
530 __raw_writew((VALUE), OMAP34XX_CTRL_BASE + (OFFSET));
532 #define CP(x) (CONTROL_PADCONF_##x)
535 * IDIS - Input Disable
536 * PTD - Pull type Down
538 * DIS - Pull type selection is inactive
539 * EN - Pull type selection is active
541 * The commented string gives the final mux configuration for that pin
543 #define MUX_DEFAULT()\
545 MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) /*SDRC_D0*/\
546 MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) /*SDRC_D1*/\
547 MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) /*SDRC_D2*/\
548 MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) /*SDRC_D3*/\
549 MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) /*SDRC_D4*/\
550 MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) /*SDRC_D5*/\
551 MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) /*SDRC_D6*/\
552 MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) /*SDRC_D7*/\
553 MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) /*SDRC_D8*/\
554 MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) /*SDRC_D9*/\
555 MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) /*SDRC_D10*/\
556 MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) /*SDRC_D11*/\
557 MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) /*SDRC_D12*/\
558 MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) /*SDRC_D13*/\
559 MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) /*SDRC_D14*/\
560 MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) /*SDRC_D15*/\
561 MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) /*SDRC_D16*/\
562 MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) /*SDRC_D17*/\
563 MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) /*SDRC_D18*/\
564 MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) /*SDRC_D19*/\
565 MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) /*SDRC_D20*/\
566 MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) /*SDRC_D21*/\
567 MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) /*SDRC_D22*/\
568 MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) /*SDRC_D23*/\
569 MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) /*SDRC_D24*/\
570 MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) /*SDRC_D25*/\
571 MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) /*SDRC_D26*/\
572 MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) /*SDRC_D27*/\
573 MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) /*SDRC_D28*/\
574 MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) /*SDRC_D29*/\
575 MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) /*SDRC_D30*/\
576 MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) /*SDRC_D31*/\
577 MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) /*SDRC_CLK*/\
578 MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) /*SDRC_DQS0*/\
579 MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) /*SDRC_DQS1*/\
580 MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) /*SDRC_DQS2*/\
581 MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) /*SDRC_DQS3*/\
583 MUX_VAL(CP(GPMC_A1), (IDIS | PTD | DIS | M0)) /*GPMC_A1*/\
584 MUX_VAL(CP(GPMC_A2), (IDIS | PTD | DIS | M0)) /*GPMC_A2*/\
585 MUX_VAL(CP(GPMC_A3), (IDIS | PTD | DIS | M0)) /*GPMC_A3*/\
586 MUX_VAL(CP(GPMC_A4), (IDIS | PTD | DIS | M0)) /*GPMC_A4*/\
587 MUX_VAL(CP(GPMC_A5), (IDIS | PTD | DIS | M0)) /*GPMC_A5*/\
588 MUX_VAL(CP(GPMC_A6), (IDIS | PTD | DIS | M0)) /*GPMC_A6*/\
589 MUX_VAL(CP(GPMC_A7), (IDIS | PTD | DIS | M0)) /*GPMC_A7*/\
590 MUX_VAL(CP(GPMC_A8), (IDIS | PTD | DIS | M0)) /*GPMC_A8*/\
591 MUX_VAL(CP(GPMC_A9), (IDIS | PTD | DIS | M0)) /*GPMC_A9*/\
592 MUX_VAL(CP(GPMC_A10), (IDIS | PTD | DIS | M0)) /*GPMC_A10*/\
593 MUX_VAL(CP(GPMC_D0), (IEN | PTD | DIS | M0)) /*GPMC_D0*/\
594 MUX_VAL(CP(GPMC_D1), (IEN | PTD | DIS | M0)) /*GPMC_D1*/\
595 MUX_VAL(CP(GPMC_D2), (IEN | PTD | DIS | M0)) /*GPMC_D2*/\
596 MUX_VAL(CP(GPMC_D3), (IEN | PTD | DIS | M0)) /*GPMC_D3*/\
597 MUX_VAL(CP(GPMC_D4), (IEN | PTD | DIS | M0)) /*GPMC_D4*/\
598 MUX_VAL(CP(GPMC_D5), (IEN | PTD | DIS | M0)) /*GPMC_D5*/\
599 MUX_VAL(CP(GPMC_D6), (IEN | PTD | DIS | M0)) /*GPMC_D6*/\
600 MUX_VAL(CP(GPMC_D7), (IEN | PTD | DIS | M0)) /*GPMC_D7*/\
601 MUX_VAL(CP(GPMC_D8), (IEN | PTD | DIS | M0)) /*GPMC_D8*/\
602 MUX_VAL(CP(GPMC_D9), (IEN | PTD | DIS | M0)) /*GPMC_D9*/\
603 MUX_VAL(CP(GPMC_D10), (IEN | PTD | DIS | M0)) /*GPMC_D10*/\
604 MUX_VAL(CP(GPMC_D11), (IEN | PTD | DIS | M0)) /*GPMC_D11*/\
605 MUX_VAL(CP(GPMC_D12), (IEN | PTD | DIS | M0)) /*GPMC_D12*/\
606 MUX_VAL(CP(GPMC_D13), (IEN | PTD | DIS | M0)) /*GPMC_D13*/\
607 MUX_VAL(CP(GPMC_D14), (IEN | PTD | DIS | M0)) /*GPMC_D14*/\
608 MUX_VAL(CP(GPMC_D15), (IEN | PTD | DIS | M0)) /*GPMC_D15*/\
609 MUX_VAL(CP(GPMC_nCS0), (IDIS | PTU | EN | M0)) /*GPMC_nCS0*/\
610 MUX_VAL(CP(GPMC_nCS1), (IDIS | PTU | EN | M0)) /*GPMC_nCS1*/\
611 MUX_VAL(CP(GPMC_nCS2), (IDIS | PTU | EN | M0)) /*GPMC_nCS2*/\
612 MUX_VAL(CP(GPMC_nCS3), (IDIS | PTU | EN | M0)) /*GPMC_nCS3*/\
613 MUX_VAL(CP(GPMC_nCS4), (IDIS | PTU | EN | M0)) /*GPMC_nCS4 lab*/\
614 MUX_VAL(CP(GPMC_nCS5), (IDIS | PTD | DIS | M0)) /*GPMC_nCS5 lab*/\
615 MUX_VAL(CP(GPMC_nCS6), (IEN | PTD | DIS | M1)) /*sys_ndmareq1 lab*/\
616 MUX_VAL(CP(GPMC_nCS7), (IEN | PTU | EN | M1)) /*GPMC_IO_DIR lab*/\
617 MUX_VAL(CP(GPMC_CLK), (IDIS | PTD | DIS | M0)) /*GPMC_CLK*/\
618 MUX_VAL(CP(GPMC_nADV_ALE), (IDIS | PTD | DIS | M0)) /*GPMC_nADV_ALE*/\
619 MUX_VAL(CP(GPMC_nOE), (IDIS | PTD | DIS | M0)) /*GPMC_nOE*/\
620 MUX_VAL(CP(GPMC_nWE), (IDIS | PTD | DIS | M0)) /*GPMC_nWE*/\
621 MUX_VAL(CP(GPMC_nBE0_CLE), (IDIS | PTD | DIS | M0)) /*GPMC_nBE0_CLE*/\
622 MUX_VAL(CP(GPMC_nBE1), (IEN | PTD | DIS | M0)) /*GPMC_nBE1 lab*/\
623 MUX_VAL(CP(GPMC_nWP), (IEN | PTD | DIS | M0)) /*GPMC_nWP*/\
624 MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) /*GPMC_WAIT0*/\
625 MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0)) /*GPMC_WAIT1*/\
626 MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M0)) /*gpmc_nWait lab*/\
627 MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M0)) /*gpmc_nWait lab*/\
628 MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0)) /*DSS_DATA18*/\
629 MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0)) /*DSS_DATA19*/\
630 MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0)) /*DSS_DATA20*/\
631 MUX_VAL(CP(CAM_XCLKB), (IDIS | PTD | DIS | M0)) /*CAM_XCLKB*/\
632 MUX_VAL(CP(CAM_WEN), (IEN | PTD | DIS | M4)) /*GPIO_167*/\
633 MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) /*UART1_TX*/\
634 MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M0)) /*UART1_RTS*/\
635 MUX_VAL(CP(UART1_CTS), (IEN | PTU | DIS | M0)) /*UART1_CTS*/\
636 MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) /*UART1_RX*/\
637 MUX_VAL(CP(McBSP1_DX), (IEN | PTD | DIS | M4)) /*GPIO_158*/\
638 MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) /*SYS_32K*/\
639 MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) /*GPIO_2 */\
640 MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) /*GPIO_3 */\
641 MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) /*GPIO_4 */\
642 MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)) /*GPIO_5 */\
643 MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) /*GPIO_6 */\
644 MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)) /*GPIO_7 */\
645 MUX_VAL(CP(SYS_BOOT6), (IEN | PTD | DIS | M4)) /*GPIO_8 */\
646 MUX_VAL(CP(SYS_CLKOUT1), (IDIS | PTD | DIS | M0)) /*sys_clkout2 lab*/\
647 MUX_VAL(CP(SYS_CLKOUT2), (IDIS | PTD | DIS | M0)) /*sys_clkout2 lab*/\
648 MUX_VAL(CP(JTAG_nTRST), (IEN | PTD | DIS | M0)) /*JTAG_nTRST*/\
649 MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)) /*JTAG_TCK*/\
650 MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)) /*JTAG_TMS*/\
651 MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)) /*JTAG_TDI*/\
652 MUX_VAL(CP(JTAG_EMU0), (IEN | PTD | DIS | M0)) /*JTAG_EMU0*/\
653 MUX_VAL(CP(JTAG_EMU1), (IEN | PTD | DIS | M0)) /*JTAG_EMU1*/\
654 MUX_VAL(CP(ETK_CLK), (IEN | PTD | DIS | M4)) /*GPIO_12*/\
655 MUX_VAL(CP(ETK_CTL), (IEN | PTD | DIS | M4)) /*GPIO_13*/\
656 MUX_VAL(CP(ETK_D0 ), (IEN | PTD | DIS | M4)) /*GPIO_14*/\
657 MUX_VAL(CP(ETK_D1 ), (IEN | PTD | DIS | M4)) /*GPIO_15*/\
658 MUX_VAL(CP(ETK_D2 ), (IEN | PTD | DIS | M4)) /*GPIO_16*/\
659 MUX_VAL(CP(ETK_D10), (IEN | PTD | DIS | M4)) /*GPIO_24*/\
660 MUX_VAL(CP(ETK_D11), (IEN | PTD | DIS | M4)) /*GPIO_25*/\
661 MUX_VAL(CP(ETK_D12), (IEN | PTD | DIS | M4)) /*GPIO_26*/\
662 MUX_VAL(CP(ETK_D13), (IEN | PTD | DIS | M4)) /*GPIO_27*/\
663 MUX_VAL(CP(ETK_D14), (IEN | PTD | DIS | M4)) /*GPIO_28*/\
664 MUX_VAL(CP(ETK_D15), (IEN | PTD | DIS | M4)) /*GPIO_29*/\
665 MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTD | EN | M0)) /*UART3_CTS_RCTX */\
666 MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTD | DIS | M0)) /*UART3_RTS_SD */\
667 MUX_VAL(CP(UART3_RX_IRRX ), (IEN | PTD | DIS | M0)) /*UART3_RX_IRRX*/\
668 MUX_VAL(CP(UART3_TX_IRTX ), (IDIS | PTD | DIS | M0)) /*UART3_TX_IRTX*/\
669 MUX_VAL(CP(sdrc_cke0), (IDIS | PTU | EN | M0)) /*sdrc_cke0 */\
670 MUX_VAL(CP(sdrc_cke1), (IDIS | PTD | DIS | M7)) /*sdrc_cke1 not used*/
671 /**********************************************************
672 * Routine: set_muxconf_regs
673 * Description: Setting up the configuration Mux registers
674 * specific to the hardware. Many pins need
675 * to be moved from protect to primary mode.
676 *********************************************************/
677 void set_muxconf_regs(void)
682 /**********************************************************
683 * Routine: nand+_init
684 * Description: Set up nand for nand and jffs2 commands
685 *********************************************************/
688 /* global settings */
689 __raw_writel(0x10, GPMC_SYSCONFIG); /* smart idle */
690 __raw_writel(0x0, GPMC_IRQENABLE); /* isr's sources masked */
691 __raw_writel(0, GPMC_TIMEOUT_CONTROL);/* timeout disable */
693 __raw_writel(0x001, GPMC_CONFIG); /* set nWP, disable limited addr */
696 /* setup CS0 for Micron NAND, leave other CS's to u-boot */
697 __raw_writel(0 , GPMC_CONFIG7 + GPMC_CONFIG_CS0);
701 __raw_writel( M_NAND_GPMC_CONFIG1, GPMC_CONFIG1 + GPMC_CONFIG_CS0);
702 __raw_writel( M_NAND_GPMC_CONFIG2, GPMC_CONFIG2 + GPMC_CONFIG_CS0);
703 __raw_writel( M_NAND_GPMC_CONFIG3, GPMC_CONFIG3 + GPMC_CONFIG_CS0);
704 __raw_writel( M_NAND_GPMC_CONFIG4, GPMC_CONFIG4 + GPMC_CONFIG_CS0);
705 __raw_writel( M_NAND_GPMC_CONFIG5, GPMC_CONFIG5 + GPMC_CONFIG_CS0);
706 __raw_writel( M_NAND_GPMC_CONFIG6, GPMC_CONFIG6 + GPMC_CONFIG_CS0);
708 #else /* CFG_ONENAND */
709 __raw_writel( ONENAND_GPMC_CONFIG1, GPMC_CONFIG1 + GPMC_CONFIG_CS0);
710 __raw_writel( ONENAND_GPMC_CONFIG2, GPMC_CONFIG2 + GPMC_CONFIG_CS0);
711 __raw_writel( ONENAND_GPMC_CONFIG3, GPMC_CONFIG3 + GPMC_CONFIG_CS0);
712 __raw_writel( ONENAND_GPMC_CONFIG4, GPMC_CONFIG4 + GPMC_CONFIG_CS0);
713 __raw_writel( ONENAND_GPMC_CONFIG5, GPMC_CONFIG5 + GPMC_CONFIG_CS0);
714 __raw_writel( ONENAND_GPMC_CONFIG6, GPMC_CONFIG6 + GPMC_CONFIG_CS0);
717 /* Enable the GPMC Mapping */
718 __raw_writel(( ((OMAP34XX_GPMC_CS0_SIZE & 0xF)<<8) |
719 ((OMAP34XX_GPMC_CS0_MAP>>24) & 0x3F) |
720 (1<<6) ), (GPMC_CONFIG7 + GPMC_CONFIG_CS0));
726 printf("Unsupported Chip!\n");
733 printf("OneNAND Unsupported !\n");
741 /* optionally do something like blinking LED */
742 void board_hang (void)