3 * ISEE 2007 SL <www.iseebcn.com>
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 #include <asm/arch/cpu.h>
29 #include <asm/arch/bits.h>
30 #include <asm/arch/mux.h>
31 #include <asm/arch/sys_proto.h>
32 #include <asm/arch/sys_info.h>
33 #include <asm/arch/clocks.h>
34 #include <asm/arch/mem.h>
35 #include <asm/arch/gpio.h>
38 #define CORE_DPLL_PARAM_M2 0x09
39 #define CORE_DPLL_PARAM_M 0x360
40 #define CORE_DPLL_PARAM_N 0xC
42 /* Used to index into DPLL parameter tables */
50 typedef struct dpll_param dpll_param;
52 /* Following functions are exported from lowlevel_init.S */
53 extern dpll_param *get_mpu_dpll_param(void);
54 extern dpll_param *get_iva_dpll_param(void);
55 extern dpll_param *get_core_dpll_param(void);
56 extern dpll_param *get_per_dpll_param(void);
58 #define __raw_readl(a) (*(volatile unsigned int *)(a))
59 #define __raw_writel(v, a) (*(volatile unsigned int *)(a) = (v))
60 #define __raw_readw(a) (*(volatile unsigned short *)(a))
61 #define __raw_writew(v, a) (*(volatile unsigned short *)(a) = (v))
63 /*******************************************************
65 * Description: spinning delay to use before udelay works
66 ******************************************************/
67 static inline void delay(unsigned long loops)
69 __asm__ volatile ("1:\n" "subs %0, %1, #1\n"
70 "bne 1b":"=r" (loops):"0"(loops));
73 void udelay (unsigned long usecs) {
77 /*************************************************************
78 * Routine: get_mem_type(void) - returns the kind of memory connected
79 * to GPMC that we are trying to boot form. Uses SYS BOOT settings.
80 *************************************************************/
81 u32 get_mem_type(void)
86 /*************************************************************
87 * get_sys_clk_speed - determine reference oscillator speed
88 * based on known 32kHz clock and gptimer.
89 *************************************************************/
90 u32 get_osc_clk_speed(void)
92 u32 start, cstart, cend, cdiff, val;
94 val = __raw_readl(PRM_CLKSRC_CTRL);
95 /* If SYS_CLK is being divided by 2, remove for now */
96 val = (val & (~BIT7)) | BIT6;
97 __raw_writel(val, PRM_CLKSRC_CTRL);
100 val = __raw_readl(CM_CLKSEL_WKUP) | BIT0;
101 __raw_writel(val, CM_CLKSEL_WKUP); /* select sys_clk for GPT1 */
103 /* Enable I and F Clocks for GPT1 */
104 val = __raw_readl(CM_ICLKEN_WKUP) | BIT0 | BIT2;
105 __raw_writel(val, CM_ICLKEN_WKUP);
106 val = __raw_readl(CM_FCLKEN_WKUP) | BIT0;
107 __raw_writel(val, CM_FCLKEN_WKUP);
109 __raw_writel(0, OMAP34XX_GPT1 + TLDR); /* start counting at 0 */
110 __raw_writel(GPT_EN, OMAP34XX_GPT1 + TCLR); /* enable clock */
111 /* enable 32kHz source */
112 /* enabled out of reset */
113 /* determine sys_clk via gauging */
115 start = 20 + __raw_readl(S32K_CR); /* start time in 20 cycles */
116 while (__raw_readl(S32K_CR) < start) ; /* dead loop till start time */
117 cstart = __raw_readl(OMAP34XX_GPT1 + TCRR); /* get start sys_clk count */
118 while (__raw_readl(S32K_CR) < (start + 20)) ; /* wait for 40 cycles */
119 cend = __raw_readl(OMAP34XX_GPT1 + TCRR); /* get end sys_clk count */
120 cdiff = cend - cstart; /* get elapsed ticks */
122 /* based on number of ticks assign speed */
125 else if (cdiff > 15200)
127 else if (cdiff > 13000)
129 else if (cdiff > 9000)
131 else if (cdiff > 7600)
137 /******************************************************************************
138 * prcm_init() - inits clocks for PRCM as defined in clocks.h
139 * -- called from SRAM, or Flash (using temp SRAM stack).
140 *****************************************************************************/
143 u32 osc_clk = 0, sys_clkin_sel;
144 dpll_param *dpll_param_p;
145 u32 clk_index, sil_index;
147 /* Gauge the input clock speed and find out the sys_clkin_sel
148 * value corresponding to the input clock.
150 osc_clk = get_osc_clk_speed();
151 get_sys_clkin_sel(osc_clk, &sys_clkin_sel);
153 sr32(PRM_CLKSEL, 0, 3, sys_clkin_sel); /* set input crystal speed */
155 /* If the input clock is greater than 19.2M always divide/2 */
156 if (sys_clkin_sel > 2) {
157 sr32(PRM_CLKSRC_CTRL, 6, 2, 2); /* input clock divider */
158 clk_index = sys_clkin_sel / 2;
160 sr32(PRM_CLKSRC_CTRL, 6, 2, 1); /* input clock divider */
161 clk_index = sys_clkin_sel;
164 sr32(PRM_CLKSRC_CTRL, 0, 2, 0);/* Bypass mode: T2 inputs a square clock */
166 /* The DPLL tables are defined according to sysclk value and
167 * silicon revision. The clk_index value will be used to get
168 * the values for that input sysclk from the DPLL param table
169 * and sil_index will get the values for that SysClk for the
170 * appropriate silicon rev.
172 sil_index = get_cpu_rev() - 1;
174 /* Unlock MPU DPLL (slows things down, and needed later) */
175 sr32(CM_CLKEN_PLL_MPU, 0, 3, PLL_LOW_POWER_BYPASS);
176 wait_on_value(BIT0, 0, CM_IDLEST_PLL_MPU, LDELAY);
178 /* Getting the base address of Core DPLL param table */
179 dpll_param_p = (dpll_param *) get_core_dpll_param();
180 /* Moving it to the right sysclk and ES rev base */
181 dpll_param_p = dpll_param_p + 3 * clk_index + sil_index;
183 /* sr32(CM_CLKSEL2_EMU) set override to work when asleep */
184 sr32(CM_CLKEN_PLL, 0, 3, PLL_FAST_RELOCK_BYPASS);
185 wait_on_value(BIT0, 0, CM_IDLEST_CKGEN, LDELAY);
187 /* For 3430 ES1.0 Errata 1.50, default value directly doesnt
188 work. write another value and then default value. */
189 sr32(CM_CLKSEL1_EMU, 16, 5, CORE_M3X2 + 1); /* m3x2 */
190 sr32(CM_CLKSEL1_EMU, 16, 5, CORE_M3X2); /* m3x2 */
191 sr32(CM_CLKSEL1_PLL, 27, 2, dpll_param_p->m2); /* Set M2 */
192 sr32(CM_CLKSEL1_PLL, 16, 11, dpll_param_p->m); /* Set M */
193 sr32(CM_CLKSEL1_PLL, 8, 7, dpll_param_p->n); /* Set N */
194 sr32(CM_CLKSEL1_PLL, 6, 1, 0); /* 96M Src */
195 sr32(CM_CLKSEL_CORE, 8, 4, CORE_SSI_DIV); /* ssi */
196 sr32(CM_CLKSEL_CORE, 4, 2, CORE_FUSB_DIV); /* fsusb */
197 sr32(CM_CLKSEL_CORE, 2, 2, CORE_L4_DIV); /* l4 */
198 sr32(CM_CLKSEL_CORE, 0, 2, CORE_L3_DIV); /* l3 */
199 sr32(CM_CLKSEL_GFX, 0, 3, GFX_DIV); /* gfx */
200 sr32(CM_CLKSEL_WKUP, 1, 2, WKUP_RSM); /* reset mgr */
201 sr32(CM_CLKEN_PLL, 4, 4, dpll_param_p->fsel); /* FREQSEL */
202 sr32(CM_CLKEN_PLL, 0, 3, PLL_LOCK); /* lock mode */
203 wait_on_value(BIT0, 1, CM_IDLEST_CKGEN, LDELAY);
205 /* Getting the base address to PER DPLL param table */
206 dpll_param_p = (dpll_param *) get_per_dpll_param();
207 /* Moving it to the right sysclk base */
208 dpll_param_p = dpll_param_p + clk_index;
210 sr32(CM_CLKEN_PLL, 16, 3, PLL_STOP);
211 wait_on_value(BIT1, 0, CM_IDLEST_CKGEN, LDELAY);
212 sr32(CM_CLKSEL1_EMU, 24, 5, PER_M6X2); /* set M6 */
213 sr32(CM_CLKSEL_CAM, 0, 5, PER_M5X2); /* set M5 */
214 sr32(CM_CLKSEL_DSS, 0, 5, PER_M4X2); /* set M4 */
215 sr32(CM_CLKSEL_DSS, 8, 5, PER_M3X2); /* set M3 */
217 if (get_cpu_family() == CPU_OMAP36XX) {
218 sr32(CM_CLKSEL3_PLL, 0, 5, CORE_DPLL_PARAM_M2); /* set M2 */
219 sr32(CM_CLKSEL2_PLL, 8, 11, CORE_DPLL_PARAM_M); /* set m */
220 sr32(CM_CLKSEL2_PLL, 0, 7, CORE_DPLL_PARAM_N); /* set n */
222 sr32(CM_CLKSEL3_PLL, 0, 5, dpll_param_p->m2); /* set M2 */
223 sr32(CM_CLKSEL2_PLL, 8, 11, dpll_param_p->m); /* set m */
224 sr32(CM_CLKSEL2_PLL, 0, 7, dpll_param_p->n); /* set n */
227 sr32(CM_CLKEN_PLL, 20, 4, dpll_param_p->fsel); /* FREQSEL */
228 sr32(CM_CLKEN_PLL, 16, 3, PLL_LOCK); /* lock mode */
229 wait_on_value(BIT1, 2, CM_IDLEST_CKGEN, LDELAY);
231 /* Getting the base address to MPU DPLL param table */
232 dpll_param_p = (dpll_param *) get_mpu_dpll_param();
234 /* Moving it to the right sysclk and ES rev base */
235 dpll_param_p = dpll_param_p + 3 * clk_index + sil_index;
237 /* MPU DPLL (unlocked already) */
238 sr32(CM_CLKSEL2_PLL_MPU, 0, 5, dpll_param_p->m2); /* Set M2 */
239 sr32(CM_CLKSEL1_PLL_MPU, 8, 11, dpll_param_p->m); /* Set M */
240 sr32(CM_CLKSEL1_PLL_MPU, 0, 7, dpll_param_p->n); /* Set N */
241 sr32(CM_CLKEN_PLL_MPU, 4, 4, dpll_param_p->fsel); /* FREQSEL */
242 sr32(CM_CLKEN_PLL_MPU, 0, 3, PLL_LOCK); /* lock mode */
243 wait_on_value(BIT0, 1, CM_IDLEST_PLL_MPU, LDELAY);
245 /* Getting the base address to IVA DPLL param table */
246 dpll_param_p = (dpll_param *) get_iva_dpll_param();
247 /* Moving it to the right sysclk and ES rev base */
248 dpll_param_p = dpll_param_p + 3 * clk_index + sil_index;
249 /* IVA DPLL (set to 12*20=240MHz) */
250 sr32(CM_CLKEN_PLL_IVA2, 0, 3, PLL_STOP);
251 wait_on_value(BIT0, 0, CM_IDLEST_PLL_IVA2, LDELAY);
252 sr32(CM_CLKSEL2_PLL_IVA2, 0, 5, dpll_param_p->m2); /* set M2 */
253 sr32(CM_CLKSEL1_PLL_IVA2, 8, 11, dpll_param_p->m); /* set M */
254 sr32(CM_CLKSEL1_PLL_IVA2, 0, 7, dpll_param_p->n); /* set N */
255 sr32(CM_CLKEN_PLL_IVA2, 4, 4, dpll_param_p->fsel); /* FREQSEL */
256 sr32(CM_CLKEN_PLL_IVA2, 0, 3, PLL_LOCK); /* lock mode */
257 wait_on_value(BIT0, 1, CM_IDLEST_PLL_IVA2, LDELAY);
259 /* Set up GPTimers to sys_clk source only */
260 sr32(CM_CLKSEL_PER, 0, 8, 0xff);
261 sr32(CM_CLKSEL_WKUP, 0, 1, 1);
266 /*****************************************
267 * Routine: secure_unlock
268 * Description: Setup security registers for access
270 *****************************************/
271 void secure_unlock(void)
273 /* Permission values for registers -Full fledged permissions to all */
274 #define UNLOCK_1 0xFFFFFFFF
275 #define UNLOCK_2 0x00000000
276 #define UNLOCK_3 0x0000FFFF
277 /* Protection Module Register Target APE (PM_RT) */
278 __raw_writel(UNLOCK_1, RT_REQ_INFO_PERMISSION_1);
279 __raw_writel(UNLOCK_1, RT_READ_PERMISSION_0);
280 __raw_writel(UNLOCK_1, RT_WRITE_PERMISSION_0);
281 __raw_writel(UNLOCK_2, RT_ADDR_MATCH_1);
283 __raw_writel(UNLOCK_3, GPMC_REQ_INFO_PERMISSION_0);
284 __raw_writel(UNLOCK_3, GPMC_READ_PERMISSION_0);
285 __raw_writel(UNLOCK_3, GPMC_WRITE_PERMISSION_0);
287 __raw_writel(UNLOCK_3, OCM_REQ_INFO_PERMISSION_0);
288 __raw_writel(UNLOCK_3, OCM_READ_PERMISSION_0);
289 __raw_writel(UNLOCK_3, OCM_WRITE_PERMISSION_0);
290 __raw_writel(UNLOCK_2, OCM_ADDR_MATCH_2);
293 __raw_writel(UNLOCK_3, IVA2_REQ_INFO_PERMISSION_0);
294 __raw_writel(UNLOCK_3, IVA2_READ_PERMISSION_0);
295 __raw_writel(UNLOCK_3, IVA2_WRITE_PERMISSION_0);
297 __raw_writel(UNLOCK_1, SMS_RG_ATT0); /* SDRC region 0 public */
300 /**********************************************************
301 * Routine: try_unlock_sram()
302 * Description: If chip is GP type, unlock the SRAM for
304 ***********************************************************/
305 void try_unlock_memory(void)
309 /* if GP device unlock device SRAM for general use */
310 /* secure code breaks for Secure/Emulation device - HS/E/T */
311 mode = get_device_type();
312 if (mode == GP_DEVICE)
317 /*********************************************************************
318 * config_sdram_m65kx002am() - 2 dice of 2Gb, DDR x32 I/O, 4KB page
319 *********************************************************************/
320 void config_sdram_m65kx002am(void)
322 /* M65KX002AM - 2 dice of 2Gb */
323 /* reset sdrc controller */
324 __raw_writel(SOFTRESET, SDRC_SYSCONFIG);
325 wait_on_value(BIT0, BIT0, SDRC_STATUS, 12000000);
326 __raw_writel(0, SDRC_SYSCONFIG);
328 /* setup sdrc to ball mux */
329 __raw_writel(SDP_SDRC_SHARING, SDRC_SHARING);
330 __raw_writel(0x2, SDRC_CS_CFG); /* 256 MB/bank */
332 /* CS0 SDRC Mode Register */
333 __raw_writel(MK65KX002AM_SDRC_MCDCFG, SDRC_MCFG_0);
335 /* CS1 SDRC Mode Register */
336 __raw_writel(MK65KX002AM_SDRC_MCDCFG, SDRC_MCFG_1);
339 __raw_writel(NUMONYX_SDRC_ACTIM_CTRLA_0, SDRC_ACTIM_CTRLA_0);
340 __raw_writel(NUMONYX_SDRC_ACTIM_CTRLB_0, SDRC_ACTIM_CTRLB_0);
341 __raw_writel(NUMONYX_SDRC_ACTIM_CTRLA_0, SDRC_ACTIM_CTRLA_1);
342 __raw_writel(NUMONYX_SDRC_ACTIM_CTRLB_0, SDRC_ACTIM_CTRLB_1);
344 __raw_writel(SDP_SDRC_RFR_CTRL, SDRC_RFR_CTRL_0);
345 __raw_writel(SDP_SDRC_RFR_CTRL, SDRC_RFR_CTRL_1);
347 __raw_writel(SDP_SDRC_POWER_POP, SDRC_POWER);
349 /* init sequence for mDDR/mSDR using manual commands (DDR is different) */
350 __raw_writel(CMD_NOP, SDRC_MANUAL_0);
351 __raw_writel(CMD_NOP, SDRC_MANUAL_1);
355 __raw_writel(CMD_PRECHARGE, SDRC_MANUAL_0);
356 __raw_writel(CMD_PRECHARGE, SDRC_MANUAL_1);
358 __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0);
359 __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_1);
361 __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0);
362 __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_1);
365 __raw_writel(SDP_SDRC_MR_0_DDR, SDRC_MR_0);
366 __raw_writel(SDP_SDRC_MR_0_DDR, SDRC_MR_1);
369 __raw_writel(SDP_SDRC_DLLAB_CTRL, SDRC_DLLA_CTRL);
370 delay(0x2000); /* give time to lock */
373 /*********************************************************************
374 * config_onenand_nand0xgr4wxa() - 4-Gbit DDP or 2-Gbit OneNAND Flash
375 *********************************************************************/
376 void config_onenand_nand0xgr4wxa(void)
378 /* global settings */
379 __raw_writel(0x10, GPMC_SYSCONFIG); /* smart idle */
380 __raw_writel(0x0, GPMC_IRQENABLE); /* isr's sources masked */
381 __raw_writel(0, GPMC_TIMEOUT_CONTROL);/* timeout disable */
383 /* Set the GPMC Vals, NAND is mapped at CS0, oneNAND at CS0.
384 * We configure only GPMC CS0 with required values. Configuring other devices
385 * at other CS is done in u-boot. So we don't have to bother doing it here.
387 __raw_writel(0 , GPMC_CONFIG7 + GPMC_CONFIG_CS0);
390 __raw_writel(ONENAND_GPMC_CONFIG1, GPMC_CONFIG1 + GPMC_CONFIG_CS0);
391 __raw_writel(ONENAND_GPMC_CONFIG2, GPMC_CONFIG2 + GPMC_CONFIG_CS0);
392 __raw_writel(ONENAND_GPMC_CONFIG3, GPMC_CONFIG3 + GPMC_CONFIG_CS0);
393 __raw_writel(ONENAND_GPMC_CONFIG4, GPMC_CONFIG4 + GPMC_CONFIG_CS0);
394 __raw_writel(ONENAND_GPMC_CONFIG5, GPMC_CONFIG5 + GPMC_CONFIG_CS0);
395 __raw_writel(ONENAND_GPMC_CONFIG6, GPMC_CONFIG6 + GPMC_CONFIG_CS0);
397 /* Enable the GPMC Mapping */
398 __raw_writel((((OMAP34XX_GPMC_CS0_SIZE & 0xF)<<8) |
399 ((ONENAND_BASE>>24) & 0x3F) |
400 (1<<6)), (GPMC_CONFIG7 + GPMC_CONFIG_CS0));
404 /**********************************************************
406 * Description: Does early system init of muxing and clocks.
407 * - Called at time when only stack is available.
408 **********************************************************/
418 config_sdram_m65kx002am();
421 /*****************************************
422 * Routine: board_init
423 * Description: Early hardware init.
424 *****************************************/
430 /*******************************************************
431 * Routine: misc_init_r
432 * Description: Init ethernet (done here so udelay works)
433 ********************************************************/
434 int misc_init_r(void)
436 omap_request_gpio(27);
437 omap_set_gpio_direction(27, 0);
438 omap_set_gpio_dataout(27, 1);
443 /******************************************************
444 * Routine: wait_for_command_complete
445 * Description: Wait for posting to finish on watchdog
446 ******************************************************/
447 void wait_for_command_complete(unsigned int wd_base)
451 pending = __raw_readl(wd_base + WWPS);
455 /****************************************
456 * Routine: watchdog_init
457 * Description: Shut down watch dogs
458 *****************************************/
459 void watchdog_init(void)
461 /* There are 3 watch dogs WD1=Secure, WD2=MPU, WD3=IVA. WD1 is
462 * either taken care of by ROM (HS/EMU) or not accessible (GP).
463 * We need to take care of WD2-MPU or take a PRCM reset. WD3
464 * should not be running and does not generate a PRCM reset.
466 sr32(CM_FCLKEN_WKUP, 5, 1, 1);
467 sr32(CM_ICLKEN_WKUP, 5, 1, 1);
468 wait_on_value(BIT5, 0x20, CM_IDLEST_WKUP, 5); /* some issue here */
470 #ifdef CONFIG_WATCHDOG
471 /* Enable WD2 watchdog */
472 __raw_writel(WD_UNLOCK3, WD2_BASE + WSPR);
473 wait_for_command_complete(WD2_BASE);
474 __raw_writel(WD_UNLOCK4, WD2_BASE + WSPR);
476 /* Disable WD2 watchdog */
477 __raw_writel(WD_UNLOCK1, WD2_BASE + WSPR);
478 wait_for_command_complete(WD2_BASE);
479 __raw_writel(WD_UNLOCK2, WD2_BASE + WSPR);
483 /**********************************************
485 * Description: sets uboots idea of sdram size
486 **********************************************/
492 /*****************************************************************
493 * Routine: peripheral_enable
494 * Description: Enable the clks & power for perifs (GPT2, UART1,...)
495 ******************************************************************/
496 void per_clocks_enable(void)
498 /* Enable GP2 timer. */
499 sr32(CM_CLKSEL_PER, 0, 1, 0x1); /* GPT2 = sys clk */
500 sr32(CM_ICLKEN_PER, 3, 1, 0x1); /* ICKen GPT2 */
501 sr32(CM_FCLKEN_PER, 3, 1, 0x1); /* FCKen GPT2 */
505 sr32(CM_FCLKEN1_CORE, 13, 1, 0x1);
506 sr32(CM_ICLKEN1_CORE, 13, 1, 0x1);
509 sr32(CM_FCLKEN_PER, 11, 1, 0x1);
510 sr32(CM_ICLKEN_PER, 11, 1, 0x1);
514 #ifdef CONFIG_DRIVER_OMAP34XX_I2C
515 /* Turn on all 3 I2C clocks */
516 sr32(CM_FCLKEN1_CORE, 15, 3, 0x7);
517 sr32(CM_ICLKEN1_CORE, 15, 3, 0x7); /* I2C1,2,3 = on */
520 /* Enable the ICLK for 32K Sync Timer as its used in udelay */
521 sr32(CM_ICLKEN_WKUP, 2, 1, 0x1);
523 sr32(CM_FCLKEN_IVA2, 0, 32, FCK_IVA2_ON);
524 sr32(CM_FCLKEN1_CORE, 0, 32, FCK_CORE1_ON);
525 sr32(CM_ICLKEN1_CORE, 0, 32, ICK_CORE1_ON);
526 sr32(CM_ICLKEN2_CORE, 0, 32, ICK_CORE2_ON);
527 sr32(CM_FCLKEN_WKUP, 0, 32, FCK_WKUP_ON);
528 sr32(CM_ICLKEN_WKUP, 0, 32, ICK_WKUP_ON);
529 sr32(CM_FCLKEN_DSS, 0, 32, FCK_DSS_ON);
530 sr32(CM_ICLKEN_DSS, 0, 32, ICK_DSS_ON);
531 sr32(CM_FCLKEN_CAM, 0, 32, FCK_CAM_ON);
532 sr32(CM_ICLKEN_CAM, 0, 32, ICK_CAM_ON);
533 sr32(CM_FCLKEN_PER, 0, 32, FCK_PER_ON);
534 sr32(CM_ICLKEN_PER, 0, 32, ICK_PER_ON);
539 /* Set MUX for UART, GPMC, SDRC, GPIO */
541 #define MUX_VAL(OFFSET,VALUE)\
542 __raw_writew((VALUE), OMAP34XX_CTRL_BASE + (OFFSET));
544 #define CP(x) (CONTROL_PADCONF_##x)
547 * IDIS - Input Disable
548 * PTD - Pull type Down
550 * DIS - Pull type selection is inactive
551 * EN - Pull type selection is active
553 * The commented string gives the final mux configuration for that pin
555 #define MUX_DEFAULT()\
556 MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) /*SDRC_D0*/\
557 MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) /*SDRC_D1*/\
558 MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) /*SDRC_D2*/\
559 MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) /*SDRC_D3*/\
560 MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) /*SDRC_D4*/\
561 MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) /*SDRC_D5*/\
562 MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) /*SDRC_D6*/\
563 MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) /*SDRC_D7*/\
564 MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) /*SDRC_D8*/\
565 MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) /*SDRC_D9*/\
566 MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) /*SDRC_D10*/\
567 MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) /*SDRC_D11*/\
568 MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) /*SDRC_D12*/\
569 MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) /*SDRC_D13*/\
570 MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) /*SDRC_D14*/\
571 MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) /*SDRC_D15*/\
572 MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) /*SDRC_D16*/\
573 MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) /*SDRC_D17*/\
574 MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) /*SDRC_D18*/\
575 MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) /*SDRC_D19*/\
576 MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) /*SDRC_D20*/\
577 MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) /*SDRC_D21*/\
578 MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) /*SDRC_D22*/\
579 MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) /*SDRC_D23*/\
580 MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) /*SDRC_D24*/\
581 MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) /*SDRC_D25*/\
582 MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) /*SDRC_D26*/\
583 MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) /*SDRC_D27*/\
584 MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) /*SDRC_D28*/\
585 MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) /*SDRC_D29*/\
586 MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) /*SDRC_D30*/\
587 MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) /*SDRC_D31*/\
588 MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) /*SDRC_CLK*/\
589 MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) /*SDRC_DQS0*/\
590 MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) /*SDRC_DQS1*/\
591 MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) /*SDRC_DQS2*/\
592 MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) /*SDRC_DQS3*/\
593 MUX_VAL(CP(GPMC_A1), (IDIS | PTD | DIS | M0)) /*GPMC_A1*/\
594 MUX_VAL(CP(GPMC_A2), (IDIS | PTD | DIS | M0)) /*GPMC_A2*/\
595 MUX_VAL(CP(GPMC_A3), (IDIS | PTD | DIS | M0)) /*GPMC_A3*/\
596 MUX_VAL(CP(GPMC_A4), (IDIS | PTD | DIS | M0)) /*GPMC_A4*/\
597 MUX_VAL(CP(GPMC_A5), (IDIS | PTD | DIS | M0)) /*GPMC_A5*/\
598 MUX_VAL(CP(GPMC_A6), (IDIS | PTD | DIS | M0)) /*GPMC_A6*/\
599 MUX_VAL(CP(GPMC_A7), (IDIS | PTD | DIS | M0)) /*GPMC_A7*/\
600 MUX_VAL(CP(GPMC_A8), (IDIS | PTD | DIS | M0)) /*GPMC_A8*/\
601 MUX_VAL(CP(GPMC_A9), (IDIS | PTD | DIS | M0)) /*GPMC_A9*/\
602 MUX_VAL(CP(GPMC_A10), (IDIS | PTD | DIS | M0)) /*GPMC_A10*/\
603 MUX_VAL(CP(GPMC_D0), (IEN | PTD | DIS | M0)) /*GPMC_D0*/\
604 MUX_VAL(CP(GPMC_D1), (IEN | PTD | DIS | M0)) /*GPMC_D1*/\
605 MUX_VAL(CP(GPMC_D2), (IEN | PTD | DIS | M0)) /*GPMC_D2*/\
606 MUX_VAL(CP(GPMC_D3), (IEN | PTD | DIS | M0)) /*GPMC_D3*/\
607 MUX_VAL(CP(GPMC_D4), (IEN | PTD | DIS | M0)) /*GPMC_D4*/\
608 MUX_VAL(CP(GPMC_D5), (IEN | PTD | DIS | M0)) /*GPMC_D5*/\
609 MUX_VAL(CP(GPMC_D6), (IEN | PTD | DIS | M0)) /*GPMC_D6*/\
610 MUX_VAL(CP(GPMC_D7), (IEN | PTD | DIS | M0)) /*GPMC_D7*/\
611 MUX_VAL(CP(GPMC_D8), (IEN | PTD | DIS | M0)) /*GPMC_D8*/\
612 MUX_VAL(CP(GPMC_D9), (IEN | PTD | DIS | M0)) /*GPMC_D9*/\
613 MUX_VAL(CP(GPMC_D10), (IEN | PTD | DIS | M0)) /*GPMC_D10*/\
614 MUX_VAL(CP(GPMC_D11), (IEN | PTD | DIS | M0)) /*GPMC_D11*/\
615 MUX_VAL(CP(GPMC_D12), (IEN | PTD | DIS | M0)) /*GPMC_D12*/\
616 MUX_VAL(CP(GPMC_D13), (IEN | PTD | DIS | M0)) /*GPMC_D13*/\
617 MUX_VAL(CP(GPMC_D14), (IEN | PTD | DIS | M0)) /*GPMC_D14*/\
618 MUX_VAL(CP(GPMC_D15), (IEN | PTD | DIS | M0)) /*GPMC_D15*/\
619 MUX_VAL(CP(GPMC_nCS0), (IDIS | PTU | EN | M0)) /*GPMC_nCS0*/\
620 MUX_VAL(CP(GPMC_nCS1), (IDIS | PTU | EN | M0)) /*GPMC_nCS1*/\
621 MUX_VAL(CP(GPMC_nCS2), (IDIS | PTU | EN | M0)) /*GPMC_nCS2*/\
622 MUX_VAL(CP(GPMC_nCS3), (IDIS | PTU | EN | M0)) /*GPMC_nCS3*/\
623 MUX_VAL(CP(GPMC_nCS4), (IDIS | PTU | EN | M0)) /*GPMC_nCS4*/\
624 MUX_VAL(CP(GPMC_nCS5), (IDIS | PTU | EN | M0)) /*GPMC_nCS5*/\
625 MUX_VAL(CP(GPMC_nCS6), (IDIS | PTU | EN | M0)) /*GPMC_nCS6*/\
626 MUX_VAL(CP(GPMC_nCS7), (IDIS | PTU | EN | M0)) /*GPMC_nCS7*/\
627 MUX_VAL(CP(GPMC_CLK), (IDIS | PTD | DIS | M0)) /*GPMC_CLK*/\
628 MUX_VAL(CP(GPMC_nADV_ALE), (IDIS | PTD | DIS | M0)) /*GPMC_nADV_ALE*/\
629 MUX_VAL(CP(GPMC_nOE), (IDIS | PTD | DIS | M0)) /*GPMC_nOE*/\
630 MUX_VAL(CP(GPMC_nWE), (IDIS | PTD | DIS | M0)) /*GPMC_nWE*/\
631 MUX_VAL(CP(GPMC_nBE0_CLE), (IDIS | PTD | DIS | M0)) /*GPMC_nBE0_CLE*/\
632 MUX_VAL(CP(GPMC_nBE1), (IEN | PTD | DIS | M0)) /*GPIO_61*/\
633 MUX_VAL(CP(GPMC_nWP), (IEN | PTD | DIS | M0)) /*GPMC_nWP*/\
634 MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) /*GPMC_WAIT0*/\
635 MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0)) /*GPMC_WAIT1*/\
636 MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M4)) /*GPIO_64*/\
637 MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M4)) /*GPIO_65*/\
638 MUX_VAL(CP(DSS_DATA18), (IEN | PTD | DIS | M4)) /*GPIO_88*/\
639 MUX_VAL(CP(DSS_DATA19), (IEN | PTD | DIS | M4)) /*GPIO_89*/\
640 MUX_VAL(CP(DSS_DATA20), (IEN | PTD | DIS | M4)) /*GPIO_90*/\
641 MUX_VAL(CP(DSS_DATA21), (IEN | PTD | DIS | M4)) /*GPIO_91*/\
642 MUX_VAL(CP(CAM_WEN), (IEN | PTD | DIS | M4)) /*GPIO_167*/\
643 MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0)) /*MMC1_CLK*/\
644 MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)) /*MMC1_CMD*/\
645 MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)) /*MMC1_DAT0*/\
646 MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)) /*MMC1_DAT1*/\
647 MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)) /*MMC1_DAT2*/\
648 MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)) /*MMC1_DAT3*/\
649 MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | EN | M0)) /*MMC1_DAT4*/\
650 MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M0)) /*MMC1_DAT5*/\
651 MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M0)) /*MMC1_DAT6*/\
652 MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M0)) /*MMC1_DAT7*/\
653 MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) /*UART1_TX*/\
654 MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M0)) /*UART1_RTS*/\
655 MUX_VAL(CP(UART1_CTS), (IEN | PTU | DIS | M0)) /*UART1_CTS*/\
656 MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) /*UART1_RX*/\
657 MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTD | EN | M0)) /*UART3_CTS_RCTX */\
658 MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTD | DIS | M0)) /*UART3_RTS_SD */\
659 MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)) /*UART3_RX_IRRX*/\
660 MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) /*UART3_TX_IRTX*/\
661 MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) /*I2C1_SCL*/\
662 MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) /*I2C1_SDA*/\
663 MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0)) /*I2C2_SCL*/\
664 MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0)) /*I2C2_SDA*/\
665 MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)) /*I2C3_SCL*/\
666 MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)) /*I2C3_SDA*/\
667 MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) /*I2C4_SCL*/\
668 MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) /*I2C4_SDA*/\
669 MUX_VAL(CP(McBSP1_DX), (IEN | PTD | DIS | M4)) /*GPIO_158*/\
670 MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) /*SYS_32K*/\
671 MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) /*GPIO_2 */\
672 MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) /*GPIO_3 */\
673 MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) /*GPIO_4 */\
674 MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)) /*GPIO_5 */\
675 MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) /*GPIO_6 */\
676 MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)) /*GPIO_7 */\
677 MUX_VAL(CP(SYS_BOOT6), (IEN | PTD | DIS | M4)) /*GPIO_8 */\
678 MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M4)) /*GPIO_186*/\
679 MUX_VAL(CP(JTAG_nTRST), (IEN | PTD | DIS | M0)) /*JTAG_nTRST*/\
680 MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)) /*JTAG_TCK*/\
681 MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)) /*JTAG_TMS*/\
682 MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)) /*JTAG_TDI*/\
683 MUX_VAL(CP(JTAG_EMU0), (IEN | PTD | DIS | M0)) /*JTAG_EMU0*/\
684 MUX_VAL(CP(JTAG_EMU1), (IEN | PTD | DIS | M0)) /*JTAG_EMU1*/\
685 MUX_VAL(CP(ETK_CLK), (IEN | PTD | DIS | M4)) /*GPIO_12*/\
686 MUX_VAL(CP(ETK_CTL), (IEN | PTD | DIS | M4)) /*GPIO_13*/\
687 MUX_VAL(CP(ETK_D0), (IEN | PTD | DIS | M4)) /*GPIO_14*/\
688 MUX_VAL(CP(ETK_D1), (IEN | PTD | DIS | M4)) /*GPIO_15*/\
689 MUX_VAL(CP(ETK_D2), (IEN | PTD | DIS | M4)) /*GPIO_16*/\
690 MUX_VAL(CP(ETK_D11), (IEN | PTD | DIS | M4)) /*GPIO_25*/\
691 MUX_VAL(CP(ETK_D12), (IDIS | PTD | DIS | M4)) /*GPIO_26*/\
692 MUX_VAL(CP(ETK_D13), (IDIS | PTD | DIS | M4)) /*GPIO_27*/\
693 MUX_VAL(CP(ETK_D14), (IEN | PTD | DIS | M4)) /*GPIO_28*/\
694 MUX_VAL(CP(ETK_D15), (IEN | PTD | DIS | M4)) /*GPIO_29 */\
695 MUX_VAL(CP(sdrc_cke0), (IDIS | PTU | EN | M0)) /*sdrc_cke0 */\
696 MUX_VAL(CP(sdrc_cke1), (IDIS | PTD | DIS | M7)) /*sdrc_cke1 not used*/
698 /**********************************************************
699 * Routine: set_muxconf_regs
700 * Description: Setting up the configuration Mux registers
701 * specific to the hardware. Many pins need
702 * to be moved from protect to primary mode.
703 *********************************************************/
704 void set_muxconf_regs(void)
709 /**********************************************************
711 * Description: Set up flash, NAND and OneNAND
712 *********************************************************/
716 config_onenand_nand0xgr4wxa();
717 if (onenand_chip()) {
719 printf("OneNAND Unsupported !\n");
728 /* optionally do something */
729 void board_hang(void)
733 /******************************************************************************
734 * Dummy function to handle errors for EABI incompatibility
735 *****************************************************************************/