board/gateworks/gw_ventana/gw_ventana.c

   1 /*
   2  * Copyright (C) 2013 Gateworks Corporation
   3  *
   4  * Author: Tim Harvey <tharvey@gateworks.com>
   5  *
   6  * SPDX-License-Identifier: GPL-2.0+
   7  */
   8
   9 #include <common.h>
  10 #include <asm/io.h>
  11 #include <asm/arch/clock.h>
  12 #include <asm/arch/imx-regs.h>
  13 #include <asm/arch/iomux.h>
  14 #include <asm/arch/mx6-pins.h>
  15 #include <asm/arch/mxc_hdmi.h>
  16 #include <asm/arch/crm_regs.h>
  17 #include <asm/arch/sys_proto.h>
  18 #include <asm/gpio.h>
  19 #include <asm/imx-common/iomux-v3.h>
  20 #include <asm/imx-common/mxc_i2c.h>
  21 #include <asm/imx-common/boot_mode.h>
  22 #include <asm/imx-common/sata.h>
  23 #include <asm/imx-common/spi.h>
  24 #include <asm/imx-common/video.h>
  25 #include <jffs2/load_kernel.h>
  26 #include <hwconfig.h>
  27 #include <i2c.h>
  28 #include <linux/ctype.h>
  29 #include <fdt_support.h>
  30 #include <fsl_esdhc.h>
  31 #include <miiphy.h>
  32 #include <mmc.h>
  33 #include <mtd_node.h>
  34 #include <netdev.h>
  35 #include <pci.h>
  36 #include <power/pmic.h>
  37 #include <power/ltc3676_pmic.h>
  38 #include <power/pfuze100_pmic.h>
  39 #include <fdt_support.h>
  40 #include <jffs2/load_kernel.h>
  41 #include <spi_flash.h>
  42
  43 #include "gsc.h"
  44 #include "ventana_eeprom.h"
  45
  46 DECLARE_GLOBAL_DATA_PTR;
  47
  48 /* GPIO's common to all baseboards */
  49 #define GP_PHY_RST      IMX_GPIO_NR(1, 30)
  50 #define GP_USB_OTG_PWR  IMX_GPIO_NR(3, 22)
  51 #define GP_SD3_CD       IMX_GPIO_NR(7, 0)
  52 #define GP_RS232_EN     IMX_GPIO_NR(2, 11)
  53 #define GP_MSATA_SEL    IMX_GPIO_NR(2, 8)
  54
  55 #define UART_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |             \
  56         PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
  57         PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  58
  59 #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |             \
  60         PAD_CTL_PUS_47K_UP  | PAD_CTL_SPEED_LOW |               \
  61         PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  62
  63 #define ENET_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |             \
  64         PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED   |             \
  65         PAD_CTL_DSE_40ohm   | PAD_CTL_HYS)
  66
  67 #define SPI_PAD_CTRL (PAD_CTL_HYS |                             \
  68         PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED |             \
  69         PAD_CTL_DSE_40ohm     | PAD_CTL_SRE_FAST)
  70
  71 #define DIO_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |              \
  72         PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
  73         PAD_CTL_DSE_34ohm | PAD_CTL_HYS | PAD_CTL_SRE_FAST)
  74
  75 #define I2C_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                    \
  76         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |   \
  77         PAD_CTL_ODE | PAD_CTL_SRE_FAST)
  78
  79 #define IRQ_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |              \
  80         PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
  81         PAD_CTL_DSE_34ohm | PAD_CTL_HYS | PAD_CTL_SRE_FAST)
  82
  83 #define DIO_PAD_CFG   (MUX_PAD_CTRL(DIO_PAD_CTRL) | MUX_MODE_SION)
  84
  85
  86 /*
  87  * EEPROM board info struct populated by read_eeprom so that we only have to
  88  * read it once.
  89  */
  90 struct ventana_board_info ventana_info;
  91
  92 static int board_type;
  93
  94 /* UART1: Function varies per baseboard */
  95 static iomux_v3_cfg_t const uart1_pads[] = {
  96         IOMUX_PADS(PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
  97         IOMUX_PADS(PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
  98 };
  99
 100 /* UART2: Serial Console */
 101 static iomux_v3_cfg_t const uart2_pads[] = {
 102         IOMUX_PADS(PAD_SD4_DAT7__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
 103         IOMUX_PADS(PAD_SD4_DAT4__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
 104 };
 105
 106 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
 107
 108 /* I2C1: GSC */
 109 static struct i2c_pads_info mx6q_i2c_pad_info0 = {
 110         .scl = {
 111                 .i2c_mode = MX6Q_PAD_EIM_D21__I2C1_SCL | PC,
 112                 .gpio_mode = MX6Q_PAD_EIM_D21__GPIO3_IO21 | PC,
 113                 .gp = IMX_GPIO_NR(3, 21)
 114         },
 115         .sda = {
 116                 .i2c_mode = MX6Q_PAD_EIM_D28__I2C1_SDA | PC,
 117                 .gpio_mode = MX6Q_PAD_EIM_D28__GPIO3_IO28 | PC,
 118                 .gp = IMX_GPIO_NR(3, 28)
 119         }
 120 };
 121 static struct i2c_pads_info mx6dl_i2c_pad_info0 = {
 122         .scl = {
 123                 .i2c_mode = MX6DL_PAD_EIM_D21__I2C1_SCL | PC,
 124                 .gpio_mode = MX6DL_PAD_EIM_D21__GPIO3_IO21 | PC,
 125                 .gp = IMX_GPIO_NR(3, 21)
 126         },
 127         .sda = {
 128                 .i2c_mode = MX6DL_PAD_EIM_D28__I2C1_SDA | PC,
 129                 .gpio_mode = MX6DL_PAD_EIM_D28__GPIO3_IO28 | PC,
 130                 .gp = IMX_GPIO_NR(3, 28)
 131         }
 132 };
 133
 134 /* I2C2: PMIC/PCIe Switch/PCIe Clock/Mezz */
 135 static struct i2c_pads_info mx6q_i2c_pad_info1 = {
 136         .scl = {
 137                 .i2c_mode = MX6Q_PAD_KEY_COL3__I2C2_SCL | PC,
 138                 .gpio_mode = MX6Q_PAD_KEY_COL3__GPIO4_IO12 | PC,
 139                 .gp = IMX_GPIO_NR(4, 12)
 140         },
 141         .sda = {
 142                 .i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA | PC,
 143                 .gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO4_IO13 | PC,
 144                 .gp = IMX_GPIO_NR(4, 13)
 145         }
 146 };
 147 static struct i2c_pads_info mx6dl_i2c_pad_info1 = {
 148         .scl = {
 149                 .i2c_mode = MX6DL_PAD_KEY_COL3__I2C2_SCL | PC,
 150                 .gpio_mode = MX6DL_PAD_KEY_COL3__GPIO4_IO12 | PC,
 151                 .gp = IMX_GPIO_NR(4, 12)
 152         },
 153         .sda = {
 154                 .i2c_mode = MX6DL_PAD_KEY_ROW3__I2C2_SDA | PC,
 155                 .gpio_mode = MX6DL_PAD_KEY_ROW3__GPIO4_IO13 | PC,
 156                 .gp = IMX_GPIO_NR(4, 13)
 157         }
 158 };
 159
 160 /* I2C3: Misc/Expansion */
 161 static struct i2c_pads_info mx6q_i2c_pad_info2 = {
 162         .scl = {
 163                 .i2c_mode = MX6Q_PAD_GPIO_3__I2C3_SCL | PC,
 164                 .gpio_mode = MX6Q_PAD_GPIO_3__GPIO1_IO03 | PC,
 165                 .gp = IMX_GPIO_NR(1, 3)
 166         },
 167         .sda = {
 168                 .i2c_mode = MX6Q_PAD_GPIO_6__I2C3_SDA | PC,
 169                 .gpio_mode = MX6Q_PAD_GPIO_6__GPIO1_IO06 | PC,
 170                 .gp = IMX_GPIO_NR(1, 6)
 171         }
 172 };
 173 static struct i2c_pads_info mx6dl_i2c_pad_info2 = {
 174         .scl = {
 175                 .i2c_mode = MX6DL_PAD_GPIO_3__I2C3_SCL | PC,
 176                 .gpio_mode = MX6DL_PAD_GPIO_3__GPIO1_IO03 | PC,
 177                 .gp = IMX_GPIO_NR(1, 3)
 178         },
 179         .sda = {
 180                 .i2c_mode = MX6DL_PAD_GPIO_6__I2C3_SDA | PC,
 181                 .gpio_mode = MX6DL_PAD_GPIO_6__GPIO1_IO06 | PC,
 182                 .gp = IMX_GPIO_NR(1, 6)
 183         }
 184 };
 185
 186 /* MMC */
 187 static iomux_v3_cfg_t const usdhc3_pads[] = {
 188         IOMUX_PADS(PAD_SD3_CLK__SD3_CLK    | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 189         IOMUX_PADS(PAD_SD3_CMD__SD3_CMD    | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 190         IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 191         IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 192         IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 193         IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 194         /* CD */
 195         IOMUX_PADS(PAD_SD3_DAT5__GPIO7_IO00  | MUX_PAD_CTRL(IRQ_PAD_CTRL)),
 196 };
 197
 198 /* ENET */
 199 static iomux_v3_cfg_t const enet_pads[] = {
 200         IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 201         IOMUX_PADS(PAD_ENET_MDC__ENET_MDC    | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 202         IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 203         IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 204         IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 205         IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 206         IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 207         IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL |
 208                    MUX_PAD_CTRL(ENET_PAD_CTRL)),
 209         IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK |
 210                    MUX_PAD_CTRL(ENET_PAD_CTRL)),
 211         IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 212         IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 213         IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 214         IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 215         IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 216         IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL |
 217                    MUX_PAD_CTRL(ENET_PAD_CTRL)),
 218         /* PHY nRST */
 219         IOMUX_PADS(PAD_ENET_TXD0__GPIO1_IO30 | DIO_PAD_CFG),
 220 };
 221
 222 /* NAND */
 223 static iomux_v3_cfg_t const nfc_pads[] = {
 224         IOMUX_PADS(PAD_NANDF_CLE__NAND_CLE     | MUX_PAD_CTRL(NO_PAD_CTRL)),
 225         IOMUX_PADS(PAD_NANDF_ALE__NAND_ALE     | MUX_PAD_CTRL(NO_PAD_CTRL)),
 226         IOMUX_PADS(PAD_NANDF_WP_B__NAND_WP_B   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 227         IOMUX_PADS(PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
 228         IOMUX_PADS(PAD_NANDF_CS0__NAND_CE0_B   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 229         IOMUX_PADS(PAD_SD4_CMD__NAND_RE_B      | MUX_PAD_CTRL(NO_PAD_CTRL)),
 230         IOMUX_PADS(PAD_SD4_CLK__NAND_WE_B      | MUX_PAD_CTRL(NO_PAD_CTRL)),
 231         IOMUX_PADS(PAD_NANDF_D0__NAND_DATA00   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 232         IOMUX_PADS(PAD_NANDF_D1__NAND_DATA01   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 233         IOMUX_PADS(PAD_NANDF_D2__NAND_DATA02   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 234         IOMUX_PADS(PAD_NANDF_D3__NAND_DATA03   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 235         IOMUX_PADS(PAD_NANDF_D4__NAND_DATA04   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 236         IOMUX_PADS(PAD_NANDF_D5__NAND_DATA05   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 237         IOMUX_PADS(PAD_NANDF_D6__NAND_DATA06   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 238         IOMUX_PADS(PAD_NANDF_D7__NAND_DATA07   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 239 };
 240
 241 #ifdef CONFIG_CMD_NAND
 242 static void setup_gpmi_nand(void)
 243 {
 244         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 245
 246         /* config gpmi nand iomux */
 247         SETUP_IOMUX_PADS(nfc_pads);
 248
 249         /* config gpmi and bch clock to 100 MHz */
 250         clrsetbits_le32(&mxc_ccm->cs2cdr,
 251                         MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
 252                         MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
 253                         MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
 254                         MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
 255                         MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
 256                         MXC_CCM_CS2CDR_ENFC_CLK_SEL(3));
 257
 258         /* enable gpmi and bch clock gating */
 259         setbits_le32(&mxc_ccm->CCGR4,
 260                      MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
 261                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
 262                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
 263                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
 264                      MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET);
 265
 266         /* enable apbh clock gating */
 267         setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
 268 }
 269 #endif
 270
 271 static void setup_iomux_enet(int gpio)
 272 {
 273         SETUP_IOMUX_PADS(enet_pads);
 274
 275         /* toggle PHY_RST# */
 276         gpio_request(gpio, "phy_rst#");
 277         gpio_direction_output(gpio, 0);
 278         mdelay(2);
 279         gpio_set_value(gpio, 1);
 280 }
 281
 282 static void setup_iomux_uart(void)
 283 {
 284         SETUP_IOMUX_PADS(uart1_pads);
 285         SETUP_IOMUX_PADS(uart2_pads);
 286 }
 287
 288 #ifdef CONFIG_USB_EHCI_MX6
 289 static iomux_v3_cfg_t const usb_pads[] = {
 290         IOMUX_PADS(PAD_GPIO_1__USB_OTG_ID   | DIO_PAD_CFG),
 291         IOMUX_PADS(PAD_KEY_COL4__USB_OTG_OC | DIO_PAD_CFG),
 292         /* OTG PWR */
 293         IOMUX_PADS(PAD_EIM_D22__GPIO3_IO22  | DIO_PAD_CFG),
 294 };
 295
 296 int board_ehci_hcd_init(int port)
 297 {
 298         struct ventana_board_info *info = &ventana_info;
 299         int gpio;
 300
 301         SETUP_IOMUX_PADS(usb_pads);
 302
 303         /* Reset USB HUB (present on GW54xx/GW53xx) */
 304         switch (info->model[3]) {
 305         case '3': /* GW53xx */
 306         case '5': /* GW552x */
 307                 SETUP_IOMUX_PAD(PAD_GPIO_9__GPIO1_IO09 | DIO_PAD_CFG);
 308                 gpio = (IMX_GPIO_NR(1, 9));
 309                 break;
 310         case '4': /* GW54xx */
 311                 SETUP_IOMUX_PAD(PAD_SD1_DAT0__GPIO1_IO16 | DIO_PAD_CFG);
 312                 gpio = (IMX_GPIO_NR(1, 16));
 313                 break;
 314         default:
 315                 return 0;
 316         }
 317
 318         /* request and toggle hub rst */
 319         gpio_request(gpio, "usb_hub_rst#");
 320         gpio_direction_output(gpio, 0);
 321         mdelay(2);
 322         gpio_set_value(gpio, 1);
 323
 324         return 0;
 325 }
 326
 327 int board_ehci_power(int port, int on)
 328 {
 329         if (port)
 330                 return 0;
 331         gpio_request(GP_USB_OTG_PWR, "usb_otg_pwr");
 332         gpio_set_value(GP_USB_OTG_PWR, on);
 333         return 0;
 334 }
 335 #endif /* CONFIG_USB_EHCI_MX6 */
 336
 337 #ifdef CONFIG_FSL_ESDHC
 338 static struct fsl_esdhc_cfg usdhc_cfg = { USDHC3_BASE_ADDR };
 339
 340 int board_mmc_getcd(struct mmc *mmc)
 341 {
 342         /* Card Detect */
 343         gpio_request(GP_SD3_CD, "sd_cd");
 344         gpio_direction_input(GP_SD3_CD);
 345         return !gpio_get_value(GP_SD3_CD);
 346 }
 347
 348 int board_mmc_init(bd_t *bis)
 349 {
 350         /* Only one USDHC controller on Ventana */
 351         SETUP_IOMUX_PADS(usdhc3_pads);
 352         usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
 353         usdhc_cfg.max_bus_width = 4;
 354
 355         return fsl_esdhc_initialize(bis, &usdhc_cfg);
 356 }
 357 #endif /* CONFIG_FSL_ESDHC */
 358
 359 #ifdef CONFIG_MXC_SPI
 360 iomux_v3_cfg_t const ecspi1_pads[] = {
 361         /* SS1 */
 362         IOMUX_PADS(PAD_EIM_D19__GPIO3_IO19  | MUX_PAD_CTRL(SPI_PAD_CTRL)),
 363         IOMUX_PADS(PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL)),
 364         IOMUX_PADS(PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL)),
 365         IOMUX_PADS(PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL)),
 366 };
 367
 368 int board_spi_cs_gpio(unsigned bus, unsigned cs)
 369 {
 370         return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(3, 19)) : -1;
 371 }
 372
 373 static void setup_spi(void)
 374 {
 375         gpio_request(IMX_GPIO_NR(3, 19), "spi_cs");
 376         gpio_direction_output(IMX_GPIO_NR(3, 19), 1);
 377         SETUP_IOMUX_PADS(ecspi1_pads);
 378 }
 379 #endif
 380
 381 /* configure eth0 PHY board-specific LED behavior */
 382 int board_phy_config(struct phy_device *phydev)
 383 {
 384         unsigned short val;
 385
 386         /* Marvel 88E1510 */
 387         if (phydev->phy_id == 0x1410dd1) {
 388                 /*
 389                  * Page 3, Register 16: LED[2:0] Function Control Register
 390                  * LED[0] (SPD:Amber) R16_3.3:0 to 0111: on-GbE link
 391                  * LED[1] (LNK:Green) R16_3.7:4 to 0001: on-link, blink-activity
 392                  */
 393                 phy_write(phydev, MDIO_DEVAD_NONE, 22, 3);
 394                 val = phy_read(phydev, MDIO_DEVAD_NONE, 16);
 395                 val &= 0xff00;
 396                 val |= 0x0017;
 397                 phy_write(phydev, MDIO_DEVAD_NONE, 16, val);
 398                 phy_write(phydev, MDIO_DEVAD_NONE, 22, 0);
 399         }
 400
 401         if (phydev->drv->config)
 402                 phydev->drv->config(phydev);
 403
 404         return 0;
 405 }
 406
 407 int board_eth_init(bd_t *bis)
 408 {
 409 #ifdef CONFIG_FEC_MXC
 410         if (board_type != GW551x && board_type != GW552x) {
 411                 setup_iomux_enet(GP_PHY_RST);
 412                 cpu_eth_init(bis);
 413         }
 414 #endif
 415
 416 #ifdef CONFIG_E1000
 417         e1000_initialize(bis);
 418 #endif
 419
 420 #ifdef CONFIG_CI_UDC
 421         /* For otg ethernet*/
 422         usb_eth_initialize(bis);
 423 #endif
 424
 425         /* default to the first detected enet dev */
 426         if (!getenv("ethprime")) {
 427                 struct eth_device *dev = eth_get_dev_by_index(0);
 428                 if (dev) {
 429                         setenv("ethprime", dev->name);
 430                         printf("set ethprime to %s\n", getenv("ethprime"));
 431                 }
 432         }
 433
 434         return 0;
 435 }
 436
 437 #if defined(CONFIG_VIDEO_IPUV3)
 438
 439 static void enable_hdmi(struct display_info_t const *dev)
 440 {
 441         imx_enable_hdmi_phy();
 442 }
 443
 444 static int detect_i2c(struct display_info_t const *dev)
 445 {
 446         return i2c_set_bus_num(dev->bus) == 0 &&
 447                 i2c_probe(dev->addr) == 0;
 448 }
 449
 450 static void enable_lvds(struct display_info_t const *dev)
 451 {
 452         struct iomuxc *iomux = (struct iomuxc *)
 453                                 IOMUXC_BASE_ADDR;
 454
 455         /* set CH0 data width to 24bit (IOMUXC_GPR2:5 0=18bit, 1=24bit) */
 456         u32 reg = readl(&iomux->gpr[2]);
 457         reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT;
 458         writel(reg, &iomux->gpr[2]);
 459
 460         /* Enable Backlight */
 461         gpio_request(IMX_GPIO_NR(1, 18), "bklt_en");
 462         SETUP_IOMUX_PAD(PAD_SD1_CMD__GPIO1_IO18 | DIO_PAD_CFG);
 463         gpio_direction_output(IMX_GPIO_NR(1, 18), 1);
 464 }
 465
 466 struct display_info_t const displays[] = {{
 467         /* HDMI Output */
 468         .bus    = -1,
 469         .addr   = 0,
 470         .pixfmt = IPU_PIX_FMT_RGB24,
 471         .detect = detect_hdmi,
 472         .enable = enable_hdmi,
 473         .mode   = {
 474                 .name           = "HDMI",
 475                 .refresh        = 60,
 476                 .xres           = 1024,
 477                 .yres           = 768,
 478                 .pixclock       = 15385,
 479                 .left_margin    = 220,
 480                 .right_margin   = 40,
 481                 .upper_margin   = 21,
 482                 .lower_margin   = 7,
 483                 .hsync_len      = 60,
 484                 .vsync_len      = 10,
 485                 .sync           = FB_SYNC_EXT,
 486                 .vmode          = FB_VMODE_NONINTERLACED
 487 } }, {
 488         /* Freescale MXC-LVDS1: HannStar HSD100PXN1-A00 w/ egalx_ts cont */
 489         .bus    = 2,
 490         .addr   = 0x4,
 491         .pixfmt = IPU_PIX_FMT_LVDS666,
 492         .detect = detect_i2c,
 493         .enable = enable_lvds,
 494         .mode   = {
 495                 .name           = "Hannstar-XGA",
 496                 .refresh        = 60,
 497                 .xres           = 1024,
 498                 .yres           = 768,
 499                 .pixclock       = 15385,
 500                 .left_margin    = 220,
 501                 .right_margin   = 40,
 502                 .upper_margin   = 21,
 503                 .lower_margin   = 7,
 504                 .hsync_len      = 60,
 505                 .vsync_len      = 10,
 506                 .sync           = FB_SYNC_EXT,
 507                 .vmode          = FB_VMODE_NONINTERLACED
 508 } }, {
 509         /* DLC700JMG-T-4 */
 510         .bus    = 0,
 511         .addr   = 0,
 512         .detect = NULL,
 513         .enable = enable_lvds,
 514         .pixfmt = IPU_PIX_FMT_LVDS666,
 515         .mode   = {
 516                 .name           = "DLC700JMGT4",
 517                 .refresh        = 60,
 518                 .xres           = 1024,         /* 1024x600active pixels */
 519                 .yres           = 600,
 520                 .pixclock       = 15385,        /* 64MHz */
 521                 .left_margin    = 220,
 522                 .right_margin   = 40,
 523                 .upper_margin   = 21,
 524                 .lower_margin   = 7,
 525                 .hsync_len      = 60,
 526                 .vsync_len      = 10,
 527                 .sync           = FB_SYNC_EXT,
 528                 .vmode          = FB_VMODE_NONINTERLACED
 529 } }, {
 530         /* DLC800FIG-T-3 */
 531         .bus    = 0,
 532         .addr   = 0,
 533         .detect = NULL,
 534         .enable = enable_lvds,
 535         .pixfmt = IPU_PIX_FMT_LVDS666,
 536         .mode   = {
 537                 .name           = "DLC800FIGT3",
 538                 .refresh        = 60,
 539                 .xres           = 1024,         /* 1024x768 active pixels */
 540                 .yres           = 768,
 541                 .pixclock       = 15385,        /* 64MHz */
 542                 .left_margin    = 220,
 543                 .right_margin   = 40,
 544                 .upper_margin   = 21,
 545                 .lower_margin   = 7,
 546                 .hsync_len      = 60,
 547                 .vsync_len      = 10,
 548                 .sync           = FB_SYNC_EXT,
 549                 .vmode          = FB_VMODE_NONINTERLACED
 550 } } };
 551 size_t display_count = ARRAY_SIZE(displays);
 552
 553 static void setup_display(void)
 554 {
 555         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 556         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 557         int reg;
 558
 559         enable_ipu_clock();
 560         imx_setup_hdmi();
 561         /* Turn on LDB0,IPU,IPU DI0 clocks */
 562         reg = __raw_readl(&mxc_ccm->CCGR3);
 563         reg |= MXC_CCM_CCGR3_LDB_DI0_MASK;
 564         writel(reg, &mxc_ccm->CCGR3);
 565
 566         /* set LDB0, LDB1 clk select to 011/011 */
 567         reg = readl(&mxc_ccm->cs2cdr);
 568         reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
 569                  |MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
 570         reg |= (3<<MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
 571               |(3<<MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
 572         writel(reg, &mxc_ccm->cs2cdr);
 573
 574         reg = readl(&mxc_ccm->cscmr2);
 575         reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
 576         writel(reg, &mxc_ccm->cscmr2);
 577
 578         reg = readl(&mxc_ccm->chsccdr);
 579         reg |= (CHSCCDR_CLK_SEL_LDB_DI0
 580                 <<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
 581         writel(reg, &mxc_ccm->chsccdr);
 582
 583         reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
 584              |IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
 585              |IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
 586              |IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
 587              |IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
 588              |IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
 589              |IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
 590              |IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
 591              |IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
 592         writel(reg, &iomux->gpr[2]);
 593
 594         reg = readl(&iomux->gpr[3]);
 595         reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK)
 596             | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
 597                <<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
 598         writel(reg, &iomux->gpr[3]);
 599
 600         /* Backlight CABEN on LVDS connector */
 601         gpio_request(IMX_GPIO_NR(1, 10), "bklt_gpio");
 602         SETUP_IOMUX_PAD(PAD_SD2_CLK__GPIO1_IO10 | DIO_PAD_CFG);
 603         gpio_direction_output(IMX_GPIO_NR(1, 10), 0);
 604 }
 605 #endif /* CONFIG_VIDEO_IPUV3 */
 606
 607 /*
 608  * Baseboard specific GPIO
 609  */
 610
 611 /* common to add baseboards */
 612 static iomux_v3_cfg_t const gw_gpio_pads[] = {
 613         /* MSATA_EN */
 614         IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08 | DIO_PAD_CFG),
 615         /* RS232_EN# */
 616         IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | DIO_PAD_CFG),
 617 };
 618
 619 /* prototype */
 620 static iomux_v3_cfg_t const gwproto_gpio_pads[] = {
 621         /* PANLEDG# */
 622         IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG),
 623         /* PANLEDR# */
 624         IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG),
 625         /* LOCLED# */
 626         IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG),
 627         /* RS485_EN */
 628         IOMUX_PADS(PAD_SD3_DAT4__GPIO7_IO01 | DIO_PAD_CFG),
 629         /* IOEXP_PWREN# */
 630         IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG),
 631         /* IOEXP_IRQ# */
 632         IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)),
 633         /* VID_EN */
 634         IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | DIO_PAD_CFG),
 635         /* DIOI2C_DIS# */
 636         IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | DIO_PAD_CFG),
 637         /* PCICK_SSON */
 638         IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20 | DIO_PAD_CFG),
 639         /* PCI_RST# */
 640         IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG),
 641 };
 642
 643 static iomux_v3_cfg_t const gw51xx_gpio_pads[] = {
 644         /* PANLEDG# */
 645         IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG),
 646         /* PANLEDR# */
 647         IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG),
 648         /* IOEXP_PWREN# */
 649         IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG),
 650         /* IOEXP_IRQ# */
 651         IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)),
 652
 653         /* GPS_SHDN */
 654         IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | DIO_PAD_CFG),
 655         /* VID_PWR */
 656         IOMUX_PADS(PAD_CSI0_DATA_EN__GPIO5_IO20 | DIO_PAD_CFG),
 657         /* PCI_RST# */
 658         IOMUX_PADS(PAD_GPIO_0__GPIO1_IO00 | DIO_PAD_CFG),
 659         /* PCIESKT_WDIS# */
 660         IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG),
 661 };
 662
 663 static iomux_v3_cfg_t const gw52xx_gpio_pads[] = {
 664         /* PANLEDG# */
 665         IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG),
 666         /* PANLEDR# */
 667         IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG),
 668         /* IOEXP_PWREN# */
 669         IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG),
 670         /* IOEXP_IRQ# */
 671         IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)),
 672
 673         /* MX6_LOCLED# */
 674         IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG),
 675         /* GPS_SHDN */
 676         IOMUX_PADS(PAD_ENET_RXD0__GPIO1_IO27 | DIO_PAD_CFG),
 677         /* USBOTG_SEL */
 678         IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | DIO_PAD_CFG),
 679         /* VID_PWR */
 680         IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | DIO_PAD_CFG),
 681         /* PCI_RST# */
 682         IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG),
 683         /* PCI_RST# (GW522x) */
 684         IOMUX_PADS(PAD_EIM_D23__GPIO3_IO23 | DIO_PAD_CFG),
 685         /* PCIESKT_WDIS# */
 686         IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG),
 687 };
 688
 689 static iomux_v3_cfg_t const gw53xx_gpio_pads[] = {
 690         /* PANLEDG# */
 691         IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG),
 692         /* PANLEDR# */
 693         IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG),
 694         /* MX6_LOCLED# */
 695         IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG),
 696         /* IOEXP_PWREN# */
 697         IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG),
 698         /* IOEXP_IRQ# */
 699         IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)),
 700         /* DIOI2C_DIS# */
 701         IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | DIO_PAD_CFG),
 702         /* GPS_SHDN */
 703         IOMUX_PADS(PAD_ENET_RXD0__GPIO1_IO27 | DIO_PAD_CFG),
 704         /* VID_EN */
 705         IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | DIO_PAD_CFG),
 706         /* PCI_RST# */
 707         IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG),
 708         /* PCIESKT_WDIS# */
 709         IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG),
 710 };
 711
 712 static iomux_v3_cfg_t const gw54xx_gpio_pads[] = {
 713         /* PANLEDG# */
 714         IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG),
 715         /* PANLEDR# */
 716         IOMUX_PADS(PAD_KEY_COL2__GPIO4_IO10 | DIO_PAD_CFG),
 717         /* MX6_LOCLED# */
 718         IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG),
 719         /* MIPI_DIO */
 720         IOMUX_PADS(PAD_SD1_DAT3__GPIO1_IO21 | DIO_PAD_CFG),
 721         /* RS485_EN */
 722         IOMUX_PADS(PAD_EIM_D24__GPIO3_IO24 | DIO_PAD_CFG),
 723         /* IOEXP_PWREN# */
 724         IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG),
 725         /* IOEXP_IRQ# */
 726         IOMUX_PADS(PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(IRQ_PAD_CTRL)),
 727         /* DIOI2C_DIS# */
 728         IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | DIO_PAD_CFG),
 729         /* PCI_RST# */
 730         IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG),
 731         /* VID_EN */
 732         IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | DIO_PAD_CFG),
 733         /* PCIESKT_WDIS# */
 734         IOMUX_PADS(PAD_DISP0_DAT23__GPIO5_IO17 | DIO_PAD_CFG),
 735 };
 736
 737 static iomux_v3_cfg_t const gw551x_gpio_pads[] = {
 738         /* PANLED# */
 739         IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG),
 740         /* PCI_RST# */
 741         IOMUX_PADS(PAD_GPIO_0__GPIO1_IO00 | DIO_PAD_CFG),
 742         /* PCIESKT_WDIS# */
 743         IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG),
 744 };
 745
 746 static iomux_v3_cfg_t const gw552x_gpio_pads[] = {
 747         /* PANLEDG# */
 748         IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG),
 749         /* PANLEDR# */
 750         IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG),
 751         /* MX6_LOCLED# */
 752         IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG),
 753         /* PCI_RST# */
 754         IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG),
 755         /* MX6_DIO[4:9] */
 756         IOMUX_PADS(PAD_CSI0_PIXCLK__GPIO5_IO18 | DIO_PAD_CFG),
 757         IOMUX_PADS(PAD_CSI0_DATA_EN__GPIO5_IO20 | DIO_PAD_CFG),
 758         IOMUX_PADS(PAD_CSI0_VSYNC__GPIO5_IO21 | DIO_PAD_CFG),
 759         IOMUX_PADS(PAD_CSI0_DAT4__GPIO5_IO22 | DIO_PAD_CFG),
 760         IOMUX_PADS(PAD_CSI0_DAT5__GPIO5_IO23 | DIO_PAD_CFG),
 761         IOMUX_PADS(PAD_CSI0_DAT7__GPIO5_IO25 | DIO_PAD_CFG),
 762         /* PCIEGBE1_OFF# */
 763         IOMUX_PADS(PAD_GPIO_1__GPIO1_IO01 | DIO_PAD_CFG),
 764         /* PCIEGBE2_OFF# */
 765         IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | DIO_PAD_CFG),
 766         /* PCIESKT_WDIS# */
 767         IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG),
 768 };
 769
 770 /*
 771  * each baseboard has 4 user configurable Digital IO lines which can
 772  * be pinmuxed as a GPIO or in some cases a PWM
 773  */
 774 struct dio_cfg {
 775         iomux_v3_cfg_t gpio_padmux[2];
 776         unsigned gpio_param;
 777         iomux_v3_cfg_t pwm_padmux[2];
 778         unsigned pwm_param;
 779 };
 780
 781 struct ventana {
 782         /* pinmux */
 783         iomux_v3_cfg_t const *gpio_pads;
 784         int num_pads;
 785         /* DIO pinmux/val */
 786         struct dio_cfg dio_cfg[4];
 787         int num_gpios;
 788         /* various gpios (0 if non-existent) */
 789         int leds[3];
 790         int pcie_rst;
 791         int mezz_pwren;
 792         int mezz_irq;
 793         int rs485en;
 794         int gps_shdn;
 795         int vidin_en;
 796         int dioi2c_en;
 797         int pcie_sson;
 798         int usb_sel;
 799         int wdis;
 800 };
 801
 802 static struct ventana gpio_cfg[] = {
 803         /* GW5400proto */
 804         {
 805                 .gpio_pads = gw54xx_gpio_pads,
 806                 .num_pads = ARRAY_SIZE(gw54xx_gpio_pads)/2,
 807                 .dio_cfg = {
 808                         {
 809                                 { IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09) },
 810                                 IMX_GPIO_NR(1, 9),
 811                                 { IOMUX_PADS(PAD_GPIO_9__PWM1_OUT) },
 812                                 1
 813                         },
 814                         {
 815                                 { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
 816                                 IMX_GPIO_NR(1, 19),
 817                                 { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
 818                                 2
 819                         },
 820                         {
 821                                 { IOMUX_PADS(PAD_SD4_DAT1__GPIO2_IO09) },
 822                                 IMX_GPIO_NR(2, 9),
 823                                 { IOMUX_PADS(PAD_SD4_DAT1__PWM3_OUT) },
 824                                 3
 825                         },
 826                         {
 827                                 { IOMUX_PADS(PAD_SD4_DAT2__GPIO2_IO10) },
 828                                 IMX_GPIO_NR(2, 10),
 829                                 { IOMUX_PADS(PAD_SD4_DAT2__PWM4_OUT) },
 830                                 4
 831                         },
 832                 },
 833                 .num_gpios = 4,
 834                 .leds = {
 835                         IMX_GPIO_NR(4, 6),
 836                         IMX_GPIO_NR(4, 10),
 837                         IMX_GPIO_NR(4, 15),
 838                 },
 839                 .pcie_rst = IMX_GPIO_NR(1, 29),
 840                 .mezz_pwren = IMX_GPIO_NR(4, 7),
 841                 .mezz_irq = IMX_GPIO_NR(4, 9),
 842                 .rs485en = IMX_GPIO_NR(3, 24),
 843                 .dioi2c_en = IMX_GPIO_NR(4,  5),
 844                 .pcie_sson = IMX_GPIO_NR(1, 20),
 845         },
 846
 847         /* GW51xx */
 848         {
 849                 .gpio_pads = gw51xx_gpio_pads,
 850                 .num_pads = ARRAY_SIZE(gw51xx_gpio_pads)/2,
 851                 .dio_cfg = {
 852                         {
 853                                 { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) },
 854                                 IMX_GPIO_NR(1, 16),
 855                                 { 0, 0 },
 856                                 0
 857                         },
 858                         {
 859                                 { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
 860                                 IMX_GPIO_NR(1, 19),
 861                                 { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
 862                                 2
 863                         },
 864                         {
 865                                 { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) },
 866                                 IMX_GPIO_NR(1, 17),
 867                                 { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) },
 868                                 3
 869                         },
 870                         {
 871                                 { IOMUX_PADS(PAD_SD1_CMD__GPIO1_IO18) },
 872                                 IMX_GPIO_NR(1, 18),
 873                                 { IOMUX_PADS(PAD_SD1_CMD__PWM4_OUT) },
 874                                 4
 875                         },
 876                 },
 877                 .num_gpios = 4,
 878                 .leds = {
 879                         IMX_GPIO_NR(4, 6),
 880                         IMX_GPIO_NR(4, 10),
 881                 },
 882                 .pcie_rst = IMX_GPIO_NR(1, 0),
 883                 .mezz_pwren = IMX_GPIO_NR(2, 19),
 884                 .mezz_irq = IMX_GPIO_NR(2, 18),
 885                 .gps_shdn = IMX_GPIO_NR(1, 2),
 886                 .vidin_en = IMX_GPIO_NR(5, 20),
 887                 .wdis = IMX_GPIO_NR(7, 12),
 888         },
 889
 890         /* GW52xx */
 891         {
 892                 .gpio_pads = gw52xx_gpio_pads,
 893                 .num_pads = ARRAY_SIZE(gw52xx_gpio_pads)/2,
 894                 .dio_cfg = {
 895                         {
 896                                 { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) },
 897                                 IMX_GPIO_NR(1, 16),
 898                                 { 0, 0 },
 899                                 0
 900                         },
 901                         {
 902                                 { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
 903                                 IMX_GPIO_NR(1, 19),
 904                                 { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
 905                                 2
 906                         },
 907                         {
 908                                 { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) },
 909                                 IMX_GPIO_NR(1, 17),
 910                                 { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) },
 911                                 3
 912                         },
 913                         {
 914                                 { IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20) },
 915                                 IMX_GPIO_NR(1, 20),
 916                                 { 0, 0 },
 917                                 0
 918                         },
 919                 },
 920                 .num_gpios = 4,
 921                 .leds = {
 922                         IMX_GPIO_NR(4, 6),
 923                         IMX_GPIO_NR(4, 7),
 924                         IMX_GPIO_NR(4, 15),
 925                 },
 926                 .pcie_rst = IMX_GPIO_NR(1, 29),
 927                 .mezz_pwren = IMX_GPIO_NR(2, 19),
 928                 .mezz_irq = IMX_GPIO_NR(2, 18),
 929                 .gps_shdn = IMX_GPIO_NR(1, 27),
 930                 .vidin_en = IMX_GPIO_NR(3, 31),
 931                 .usb_sel = IMX_GPIO_NR(1, 2),
 932                 .wdis = IMX_GPIO_NR(7, 12),
 933         },
 934
 935         /* GW53xx */
 936         {
 937                 .gpio_pads = gw53xx_gpio_pads,
 938                 .num_pads = ARRAY_SIZE(gw53xx_gpio_pads)/2,
 939                 .dio_cfg = {
 940                         {
 941                                 { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) },
 942                                 IMX_GPIO_NR(1, 16),
 943                                 { 0, 0 },
 944                                 0
 945                         },
 946                         {
 947                                 { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
 948                                 IMX_GPIO_NR(1, 19),
 949                                 { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
 950                                 2
 951                         },
 952                         {
 953                                 { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) },
 954                                 IMX_GPIO_NR(1, 17),
 955                                 { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) },
 956                                 3
 957                         },
 958                         {
 959                                 {IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20) },
 960                                 IMX_GPIO_NR(1, 20),
 961                                 { 0, 0 },
 962                                 0
 963                         },
 964                 },
 965                 .num_gpios = 4,
 966                 .leds = {
 967                         IMX_GPIO_NR(4, 6),
 968                         IMX_GPIO_NR(4, 7),
 969                         IMX_GPIO_NR(4, 15),
 970                 },
 971                 .pcie_rst = IMX_GPIO_NR(1, 29),
 972                 .mezz_pwren = IMX_GPIO_NR(2, 19),
 973                 .mezz_irq = IMX_GPIO_NR(2, 18),
 974                 .gps_shdn = IMX_GPIO_NR(1, 27),
 975                 .vidin_en = IMX_GPIO_NR(3, 31),
 976                 .wdis = IMX_GPIO_NR(7, 12),
 977         },
 978
 979         /* GW54xx */
 980         {
 981                 .gpio_pads = gw54xx_gpio_pads,
 982                 .num_pads = ARRAY_SIZE(gw54xx_gpio_pads)/2,
 983                 .dio_cfg = {
 984                         {
 985                                 { IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09) },
 986                                 IMX_GPIO_NR(1, 9),
 987                                 { IOMUX_PADS(PAD_GPIO_9__PWM1_OUT) },
 988                                 1
 989                         },
 990                         {
 991                                 { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
 992                                 IMX_GPIO_NR(1, 19),
 993                                 { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
 994                                 2
 995                         },
 996                         {
 997                                 { IOMUX_PADS(PAD_SD4_DAT1__GPIO2_IO09) },
 998                                 IMX_GPIO_NR(2, 9),
 999                                 { IOMUX_PADS(PAD_SD4_DAT1__PWM3_OUT) },
1000                                 3
1001                         },
1002                         {
1003                                 { IOMUX_PADS(PAD_SD4_DAT2__GPIO2_IO10) },
1004                                 IMX_GPIO_NR(2, 10),
1005                                 { IOMUX_PADS(PAD_SD4_DAT2__PWM4_OUT) },
1006                                 4
1007                         },
1008                 },
1009                 .num_gpios = 4,
1010                 .leds = {
1011                         IMX_GPIO_NR(4, 6),
1012                         IMX_GPIO_NR(4, 7),
1013                         IMX_GPIO_NR(4, 15),
1014                 },
1015                 .pcie_rst = IMX_GPIO_NR(1, 29),
1016                 .mezz_pwren = IMX_GPIO_NR(2, 19),
1017                 .mezz_irq = IMX_GPIO_NR(2, 18),
1018                 .rs485en = IMX_GPIO_NR(7, 1),
1019                 .vidin_en = IMX_GPIO_NR(3, 31),
1020                 .dioi2c_en = IMX_GPIO_NR(4,  5),
1021                 .pcie_sson = IMX_GPIO_NR(1, 20),
1022                 .wdis = IMX_GPIO_NR(5, 17),
1023         },
1024
1025         /* GW551x */
1026         {
1027                 .gpio_pads = gw551x_gpio_pads,
1028                 .num_pads = ARRAY_SIZE(gw551x_gpio_pads)/2,
1029                 .dio_cfg = {
1030                         {
1031                                 { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) },
1032                                 IMX_GPIO_NR(1, 16),
1033                                 { 0, 0 },
1034                                 0
1035                         },
1036                         {
1037                                 { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
1038                                 IMX_GPIO_NR(1, 19),
1039                                 { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
1040                                 2
1041                         },
1042                         {
1043                                 { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) },
1044                                 IMX_GPIO_NR(1, 17),
1045                                 { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) },
1046                                 3
1047                         },
1048                         {
1049                                 { IOMUX_PADS(PAD_SD1_CMD__GPIO1_IO18) },
1050                                 IMX_GPIO_NR(1, 18),
1051                                 { IOMUX_PADS(PAD_SD1_CMD__PWM4_OUT) },
1052                                 4
1053                         },
1054                 },
1055                 .num_gpios = 2,
1056                 .leds = {
1057                         IMX_GPIO_NR(4, 7),
1058                 },
1059                 .pcie_rst = IMX_GPIO_NR(1, 0),
1060                 .wdis = IMX_GPIO_NR(7, 12),
1061         },
1062
1063         /* GW552x */
1064         {
1065                 .gpio_pads = gw552x_gpio_pads,
1066                 .num_pads = ARRAY_SIZE(gw552x_gpio_pads)/2,
1067                 .dio_cfg = {
1068                         {
1069                                 { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
1070                                 IMX_GPIO_NR(1, 19),
1071                                 { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
1072                                 2
1073                         },
1074                         {
1075                                 { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) },
1076                                 IMX_GPIO_NR(1, 17),
1077                                 { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) },
1078                                 3
1079                         },
1080                 },
1081                 .num_gpios = 4,
1082                 .leds = {
1083                         IMX_GPIO_NR(4, 6),
1084                         IMX_GPIO_NR(4, 7),
1085                         IMX_GPIO_NR(4, 15),
1086                 },
1087                 .pcie_rst = IMX_GPIO_NR(1, 29),
1088                 .wdis = IMX_GPIO_NR(7, 12),
1089         },
1090 };
1091
1092 /* setup board specific PMIC */
1093 int power_init_board(void)
1094 {
1095         struct pmic *p;
1096         u32 reg;
1097
1098         /* configure PFUZE100 PMIC */
1099         if (board_type == GW54xx || board_type == GW54proto) {
1100                 power_pfuze100_init(CONFIG_I2C_PMIC);
1101                 p = pmic_get("PFUZE100");
1102                 if (p && !pmic_probe(p)) {
1103                         pmic_reg_read(p, PFUZE100_DEVICEID, &reg);
1104                         printf("PMIC:  PFUZE100 ID=0x%02x\n", reg);
1105
1106                         /* Set VGEN1 to 1.5V and enable */
1107                         pmic_reg_read(p, PFUZE100_VGEN1VOL, &reg);
1108                         reg &= ~(LDO_VOL_MASK);
1109                         reg |= (LDOA_1_50V | LDO_EN);
1110                         pmic_reg_write(p, PFUZE100_VGEN1VOL, reg);
1111
1112                         /* Set SWBST to 5.0V and enable */
1113                         pmic_reg_read(p, PFUZE100_SWBSTCON1, &reg);
1114                         reg &= ~(SWBST_MODE_MASK | SWBST_VOL_MASK);
1115                         reg |= (SWBST_5_00V | SWBST_MODE_AUTO);
1116                         pmic_reg_write(p, PFUZE100_SWBSTCON1, reg);
1117                 }
1118         }
1119
1120         /* configure LTC3676 PMIC */
1121         else {
1122                 power_ltc3676_init(CONFIG_I2C_PMIC);
1123                 p = pmic_get("LTC3676_PMIC");
1124                 if (p && !pmic_probe(p)) {
1125                         puts("PMIC:  LTC3676\n");
1126                         /*
1127                          * set board-specific scalar for max CPU frequency
1128                          * per CPU based on the LDO enabled Operating Ranges
1129                          * defined in the respective IMX6DQ and IMX6SDL
1130                          * datasheets. The voltage resulting from the R1/R2
1131                          * feedback inputs on Ventana is 1308mV. Note that this
1132                          * is a bit shy of the Vmin of 1350mV in the datasheet
1133                          * for LDO enabled mode but is as high as we can go.
1134                          *
1135                          * We will rely on an OS kernel driver to properly
1136                          * regulate these per CPU operating point and use LDO
1137                          * bypass mode when using the higher frequency
1138                          * operating points to compensate as LDO bypass mode
1139                          * allows the rails be 125mV lower.
1140                          */
1141                         /* mask PGOOD during SW1 transition */
1142                         pmic_reg_write(p, LTC3676_DVB1B,
1143                                        0x1f | LTC3676_PGOOD_MASK);
1144                         /* set SW1 (VDD_SOC) */
1145                         pmic_reg_write(p, LTC3676_DVB1A, 0x1f);
1146
1147                         /* mask PGOOD during SW3 transition */
1148                         pmic_reg_write(p, LTC3676_DVB3B,
1149                                        0x1f | LTC3676_PGOOD_MASK);
1150                         /* set SW3 (VDD_ARM) */
1151                         pmic_reg_write(p, LTC3676_DVB3A, 0x1f);
1152                 }
1153         }
1154
1155         return 0;
1156 }
1157
1158 /* setup GPIO pinmux and default configuration per baseboard */
1159 static void setup_board_gpio(int board)
1160 {
1161         struct ventana_board_info *info = &ventana_info;
1162         const char *s;
1163         char arg[10];
1164         size_t len;
1165         int i;
1166         int quiet = simple_strtol(getenv("quiet"), NULL, 10);
1167
1168         if (board >= GW_UNKNOWN)
1169                 return;
1170
1171         /* RS232_EN# */
1172         gpio_request(GP_RS232_EN, "rs232_en");
1173         gpio_direction_output(GP_RS232_EN, (hwconfig("rs232")) ? 0 : 1);
1174
1175         /* MSATA Enable */
1176         gpio_request(GP_MSATA_SEL, "msata_en");
1177         if (is_cpu_type(MXC_CPU_MX6Q) &&
1178             test_bit(EECONFIG_SATA, info->config)) {
1179                 gpio_direction_output(GP_MSATA_SEL,
1180                                       (hwconfig("msata")) ?  1 : 0);
1181         } else {
1182                 gpio_direction_output(GP_MSATA_SEL, 0);
1183         }
1184
1185 #if !defined(CONFIG_CMD_PCI)
1186         /* GW522x Uses GPIO3_IO23 for PCIE_RST# */
1187         if (board_type == GW52xx && info->model[4] == '2')
1188                 gpio_cfg[board].pcie_rst = IMX_GPIO_NR(3, 23);
1189
1190         /* assert PCI_RST# (released by OS when clock is valid) */
1191         gpio_request(gpio_cfg[board].pcie_rst, "pci_rst#");
1192         gpio_direction_output(gpio_cfg[board].pcie_rst, 0);
1193 #endif
1194
1195         /* turn off (active-high) user LED's */
1196         for (i = 0; i < ARRAY_SIZE(gpio_cfg[board].leds); i++) {
1197                 if (gpio_cfg[board].leds[i]) {
1198                         gpio_requestf(gpio_cfg[board].leds[i], "led_user%d", i);
1199                         gpio_direction_output(gpio_cfg[board].leds[i], 1);
1200                 }
1201         }
1202
1203         /* Expansion Mezzanine IO */
1204         if (gpio_cfg[board].mezz_pwren) {
1205                 gpio_request(gpio_cfg[board].mezz_pwren, "mezz_pwr");
1206                 gpio_direction_output(gpio_cfg[board].mezz_pwren, 0);
1207         }
1208         if (gpio_cfg[board].mezz_irq) {
1209                 gpio_request(gpio_cfg[board].mezz_irq, "mezz_irq#");
1210                 gpio_direction_input(gpio_cfg[board].mezz_irq);
1211         }
1212
1213         /* RS485 Transmit Enable */
1214         if (gpio_cfg[board].rs485en) {
1215                 gpio_request(gpio_cfg[board].rs485en, "rs485_en");
1216                 gpio_direction_output(gpio_cfg[board].rs485en, 0);
1217         }
1218
1219         /* GPS_SHDN */
1220         if (gpio_cfg[board].gps_shdn) {
1221                 gpio_request(gpio_cfg[board].gps_shdn, "gps_shdn");
1222                 gpio_direction_output(gpio_cfg[board].gps_shdn, 1);
1223         }
1224
1225         /* Analog video codec power enable */
1226         if (gpio_cfg[board].vidin_en) {
1227                 gpio_request(gpio_cfg[board].vidin_en, "anavidin_en");
1228                 gpio_direction_output(gpio_cfg[board].vidin_en, 1);
1229         }
1230
1231         /* DIOI2C_DIS# */
1232         if (gpio_cfg[board].dioi2c_en) {
1233                 gpio_request(gpio_cfg[board].dioi2c_en, "dioi2c_dis#");
1234                 gpio_direction_output(gpio_cfg[board].dioi2c_en, 0);
1235         }
1236
1237         /* PCICK_SSON: disable spread-spectrum clock */
1238         if (gpio_cfg[board].pcie_sson) {
1239                 gpio_request(gpio_cfg[board].pcie_sson, "pci_sson");
1240                 gpio_direction_output(gpio_cfg[board].pcie_sson, 0);
1241         }
1242
1243         /* USBOTG Select (PCISKT or FrontPanel) */
1244         if (gpio_cfg[board].usb_sel) {
1245                 gpio_request(gpio_cfg[board].usb_sel, "usb_pcisel");
1246                 gpio_direction_output(gpio_cfg[board].usb_sel,
1247                                       (hwconfig("usb_pcisel")) ? 1 : 0);
1248         }
1249
1250
1251         /* PCISKT_WDIS# (Wireless disable GPIO to miniPCIe sockets) */
1252         if (gpio_cfg[board].wdis) {
1253                 gpio_request(gpio_cfg[board].wdis, "wlan_dis");
1254                 gpio_direction_output(gpio_cfg[board].wdis, 1);
1255         }
1256
1257         /*
1258          * Configure DIO pinmux/padctl registers
1259          * see IMX6DQRM/IMX6SDLRM IOMUXC_SW_PAD_CTL_PAD_* register definitions
1260          */
1261         for (i = 0; i < 4; i++) {
1262                 struct dio_cfg *cfg = &gpio_cfg[board].dio_cfg[i];
1263                 iomux_v3_cfg_t ctrl = DIO_PAD_CFG;
1264                 unsigned cputype = is_cpu_type(MXC_CPU_MX6Q) ? 0 : 1;
1265
1266                 if (!cfg->gpio_padmux[0] && !cfg->gpio_padmux[1])
1267                         continue;
1268                 sprintf(arg, "dio%d", i);
1269                 if (!hwconfig(arg))
1270                         continue;
1271                 s = hwconfig_subarg(arg, "padctrl", &len);
1272                 if (s) {
1273                         ctrl = MUX_PAD_CTRL(simple_strtoul(s, NULL, 16)
1274                                             & 0x1ffff) | MUX_MODE_SION;
1275                 }
1276                 if (hwconfig_subarg_cmp(arg, "mode", "gpio")) {
1277                         if (!quiet) {
1278                                 printf("DIO%d:  GPIO%d_IO%02d (gpio-%d)\n", i,
1279                                        (cfg->gpio_param/32)+1,
1280                                        cfg->gpio_param%32,
1281                                        cfg->gpio_param);
1282                         }
1283                         imx_iomux_v3_setup_pad(cfg->gpio_padmux[cputype] |
1284                                                ctrl);
1285                         gpio_requestf(cfg->gpio_param, "dio%d", i);
1286                         gpio_direction_input(cfg->gpio_param);
1287                 } else if (hwconfig_subarg_cmp("dio2", "mode", "pwm") &&
1288                            cfg->pwm_padmux) {
1289                         if (!quiet)
1290                                 printf("DIO%d:  pwm%d\n", i, cfg->pwm_param);
1291                         imx_iomux_v3_setup_pad(cfg->pwm_padmux[cputype] |
1292                                                MUX_PAD_CTRL(ctrl));
1293                 }
1294         }
1295
1296         if (!quiet) {
1297                 if (is_cpu_type(MXC_CPU_MX6Q) &&
1298                     (test_bit(EECONFIG_SATA, info->config))) {
1299                         printf("MSATA: %s\n", (hwconfig("msata") ?
1300                                "enabled" : "disabled"));
1301                 }
1302                 printf("RS232: %s\n", (hwconfig("rs232")) ?
1303                        "enabled" : "disabled");
1304         }
1305 }
1306
1307 #if defined(CONFIG_CMD_PCI)
1308 int imx6_pcie_toggle_reset(void)
1309 {
1310         if (board_type < GW_UNKNOWN) {
1311                 uint pin = gpio_cfg[board_type].pcie_rst;
1312                 gpio_request(pin, "pci_rst#");
1313                 gpio_direction_output(pin, 0);
1314                 mdelay(50);
1315                 gpio_direction_output(pin, 1);
1316         }
1317         return 0;
1318 }
1319
1320 /*
1321  * Most Ventana boards have a PLX PEX860x PCIe switch onboard and use its
1322  * GPIO's as PERST# signals for its downstream ports - configure the GPIO's
1323  * properly and assert reset for 100ms.
1324  */
1325 void board_pci_fixup_dev(struct pci_controller *hose, pci_dev_t dev,
1326                          unsigned short vendor, unsigned short device,
1327                          unsigned short class)
1328 {
1329         u32 dw;
1330
1331         debug("%s: %02d:%02d.%02d: %04x:%04x\n", __func__,
1332               PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev), vendor, device);
1333         if (vendor == PCI_VENDOR_ID_PLX &&
1334             (device & 0xfff0) == 0x8600 &&
1335             PCI_DEV(dev) == 0 && PCI_FUNC(dev) == 0) {
1336                 debug("configuring PLX 860X downstream PERST#\n");
1337                 pci_hose_read_config_dword(hose, dev, 0x62c, &dw);
1338                 dw |= 0xaaa8; /* GPIO1-7 outputs */
1339                 pci_hose_write_config_dword(hose, dev, 0x62c, dw);
1340
1341                 pci_hose_read_config_dword(hose, dev, 0x644, &dw);
1342                 dw |= 0xfe;   /* GPIO1-7 output high */
1343                 pci_hose_write_config_dword(hose, dev, 0x644, dw);
1344
1345                 mdelay(100);
1346         }
1347 }
1348 #endif /* CONFIG_CMD_PCI */
1349
1350 #ifdef CONFIG_SERIAL_TAG
1351 /*
1352  * called when setting up ATAGS before booting kernel
1353  * populate serialnum from the following (in order of priority):
1354  *   serial# env var
1355  *   eeprom
1356  */
1357 void get_board_serial(struct tag_serialnr *serialnr)
1358 {
1359         char *serial = getenv("serial#");
1360
1361         if (serial) {
1362                 serialnr->high = 0;
1363                 serialnr->low = simple_strtoul(serial, NULL, 10);
1364         } else if (ventana_info.model[0]) {
1365                 serialnr->high = 0;
1366                 serialnr->low = ventana_info.serial;
1367         } else {
1368                 serialnr->high = 0;
1369                 serialnr->low = 0;
1370         }
1371 }
1372 #endif
1373
1374 /*
1375  * Board Support
1376  */
1377
1378 /* called from SPL board_init_f() */
1379 int board_early_init_f(void)
1380 {
1381         setup_iomux_uart();
1382
1383         gpio_direction_output(GP_USB_OTG_PWR, 0); /* OTG power off */
1384
1385 #if defined(CONFIG_VIDEO_IPUV3)
1386         setup_display();
1387 #endif
1388         return 0;
1389 }
1390
1391 int dram_init(void)
1392 {
1393         gd->ram_size = imx_ddr_size();
1394         return 0;
1395 }
1396
1397 int board_init(void)
1398 {
1399         struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
1400
1401         clrsetbits_le32(&iomuxc_regs->gpr[1],
1402                         IOMUXC_GPR1_OTG_ID_MASK,
1403                         IOMUXC_GPR1_OTG_ID_GPIO1);
1404
1405         /* address of linux boot parameters */
1406         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
1407
1408 #ifdef CONFIG_CMD_NAND
1409         setup_gpmi_nand();
1410 #endif
1411 #ifdef CONFIG_MXC_SPI
1412         setup_spi();
1413 #endif
1414         if (is_cpu_type(MXC_CPU_MX6Q)) {
1415                 setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info0);
1416                 setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info1);
1417                 setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info2);
1418         } else {
1419                 setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info0);
1420                 setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info1);
1421                 setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info2);
1422         }
1423
1424 #ifdef CONFIG_CMD_SATA
1425         setup_sata();
1426 #endif
1427         /* read Gateworks EEPROM into global struct (used later) */
1428         board_type = read_eeprom(CONFIG_I2C_GSC, &ventana_info);
1429
1430         /* board-specifc GPIO iomux */
1431         SETUP_IOMUX_PADS(gw_gpio_pads);
1432         if (board_type < GW_UNKNOWN) {
1433                 iomux_v3_cfg_t const *p = gpio_cfg[board_type].gpio_pads;
1434                 int count = gpio_cfg[board_type].num_pads;
1435
1436                 imx_iomux_v3_setup_multiple_pads(p, count);
1437         }
1438
1439         return 0;
1440 }
1441
1442 #if defined(CONFIG_DISPLAY_BOARDINFO_LATE)
1443 /*
1444  * called during late init (after relocation and after board_init())
1445  * by virtue of CONFIG_DISPLAY_BOARDINFO_LATE as we needed i2c initialized and
1446  * EEPROM read.
1447  */
1448 int checkboard(void)
1449 {
1450         struct ventana_board_info *info = &ventana_info;
1451         unsigned char buf[4];
1452         const char *p;
1453         int quiet; /* Quiet or minimal output mode */
1454
1455         quiet = 0;
1456         p = getenv("quiet");
1457         if (p)
1458                 quiet = simple_strtol(p, NULL, 10);
1459         else
1460                 setenv("quiet", "0");
1461
1462         puts("\nGateworks Corporation Copyright 2014\n");
1463         if (info->model[0]) {
1464                 printf("Model: %s\n", info->model);
1465                 printf("MFGDate: %02x-%02x-%02x%02x\n",
1466                        info->mfgdate[0], info->mfgdate[1],
1467                        info->mfgdate[2], info->mfgdate[3]);
1468                 printf("Serial:%d\n", info->serial);
1469         } else {
1470                 puts("Invalid EEPROM - board will not function fully\n");
1471         }
1472         if (quiet)
1473                 return 0;
1474
1475         /* Display GSC firmware revision/CRC/status */
1476         gsc_info(0);
1477
1478         /* Display RTC */
1479         if (!gsc_i2c_read(GSC_RTC_ADDR, 0x00, 1, buf, 4)) {
1480                 printf("RTC:   %d\n",
1481                        buf[0] | buf[1]<<8 | buf[2]<<16 | buf[3]<<24);
1482         }
1483
1484         return 0;
1485 }
1486 #endif
1487
1488 #ifdef CONFIG_CMD_BMODE
1489 /*
1490  * BOOT_CFG1, BOOT_CFG2, BOOT_CFG3, BOOT_CFG4
1491  * see Table 8-11 and Table 5-9
1492  *  BOOT_CFG1[7] = 1 (boot from NAND)
1493  *  BOOT_CFG1[5] = 0 - raw NAND
1494  *  BOOT_CFG1[4] = 0 - default pad settings
1495  *  BOOT_CFG1[3:2] = 00 - devices = 1
1496  *  BOOT_CFG1[1:0] = 00 - Row Address Cycles = 3
1497  *  BOOT_CFG2[4:3] = 00 - Boot Search Count = 2
1498  *  BOOT_CFG2[2:1] = 01 - Pages In Block = 64
1499  *  BOOT_CFG2[0] = 0 - Reset time 12ms
1500  */
1501 static const struct boot_mode board_boot_modes[] = {
1502         /* NAND: 64pages per block, 3 row addr cycles, 2 copies of FCB/DBBT */
1503         { "nand", MAKE_CFGVAL(0x80, 0x02, 0x00, 0x00) },
1504         { NULL, 0 },
1505 };
1506 #endif
1507
1508 /* late init */
1509 int misc_init_r(void)
1510 {
1511         struct ventana_board_info *info = &ventana_info;
1512         unsigned char reg;
1513
1514         /* set env vars based on EEPROM data */
1515         if (ventana_info.model[0]) {
1516                 char str[16], fdt[36];
1517                 char *p;
1518                 const char *cputype = "";
1519                 int i;
1520
1521                 /*
1522                  * FDT name will be prefixed with CPU type.  Three versions
1523                  * will be created each increasingly generic and bootloader
1524                  * env scripts will try loading each from most specific to
1525                  * least.
1526                  */
1527                 if (is_cpu_type(MXC_CPU_MX6Q) ||
1528                     is_cpu_type(MXC_CPU_MX6D))
1529                         cputype = "imx6q";
1530                 else if (is_cpu_type(MXC_CPU_MX6DL) ||
1531                          is_cpu_type(MXC_CPU_MX6SOLO))
1532                         cputype = "imx6dl";
1533                 setenv("soctype", cputype);
1534                 if (8 << (ventana_info.nand_flash_size-1) >= 2048)
1535                         setenv("flash_layout", "large");
1536                 else
1537                         setenv("flash_layout", "normal");
1538                 memset(str, 0, sizeof(str));
1539                 for (i = 0; i < (sizeof(str)-1) && info->model[i]; i++)
1540                         str[i] = tolower(info->model[i]);
1541                 if (!getenv("model"))
1542                         setenv("model", str);
1543                 if (!getenv("fdt_file")) {
1544                         sprintf(fdt, "%s-%s.dtb", cputype, str);
1545                         setenv("fdt_file", fdt);
1546                 }
1547                 p = strchr(str, '-');
1548                 if (p) {
1549                         *p++ = 0;
1550
1551                         setenv("model_base", str);
1552                         if (!getenv("fdt_file1")) {
1553                                 sprintf(fdt, "%s-%s.dtb", cputype, str);
1554                                 setenv("fdt_file1", fdt);
1555                         }
1556                         if (board_type != GW551x && board_type != GW552x)
1557                                 str[4] = 'x';
1558                         str[5] = 'x';
1559                         str[6] = 0;
1560                         if (!getenv("fdt_file2")) {
1561                                 sprintf(fdt, "%s-%s.dtb", cputype, str);
1562                                 setenv("fdt_file2", fdt);
1563                         }
1564                 }
1565
1566                 /* initialize env from EEPROM */
1567                 if (test_bit(EECONFIG_ETH0, info->config) &&
1568                     !getenv("ethaddr")) {
1569                         eth_setenv_enetaddr("ethaddr", info->mac0);
1570                 }
1571                 if (test_bit(EECONFIG_ETH1, info->config) &&
1572                     !getenv("eth1addr")) {
1573                         eth_setenv_enetaddr("eth1addr", info->mac1);
1574                 }
1575
1576                 /* board serial-number */
1577                 sprintf(str, "%6d", info->serial);
1578                 setenv("serial#", str);
1579
1580                 /* memory MB */
1581                 sprintf(str, "%d", (int) (gd->ram_size >> 20));
1582                 setenv("mem_mb", str);
1583         }
1584
1585
1586         /* setup baseboard specific GPIO pinmux and config */
1587         setup_board_gpio(board_type);
1588
1589 #ifdef CONFIG_CMD_BMODE
1590         add_board_boot_modes(board_boot_modes);
1591 #endif
1592
1593         /*
1594          *  The Gateworks System Controller implements a boot
1595          *  watchdog (always enabled) as a workaround for IMX6 boot related
1596          *  errata such as:
1597          *    ERR005768 - no fix scheduled
1598          *    ERR006282 - fixed in silicon r1.2
1599          *    ERR007117 - fixed in silicon r1.3
1600          *    ERR007220 - fixed in silicon r1.3
1601          *    ERR007926 - no fix scheduled
1602          *  see http://cache.freescale.com/files/32bit/doc/errata/IMX6DQCE.pdf
1603          *
1604          * Disable the boot watchdog and display/clear the timeout flag if set
1605          */
1606         i2c_set_bus_num(CONFIG_I2C_GSC);
1607         if (!gsc_i2c_read(GSC_SC_ADDR, GSC_SC_CTRL1, 1, &reg, 1)) {
1608                 reg |= (1 << GSC_SC_CTRL1_WDDIS);
1609                 if (gsc_i2c_write(GSC_SC_ADDR, GSC_SC_CTRL1, 1, &reg, 1))
1610                         puts("Error: could not disable GSC Watchdog\n");
1611         } else {
1612                 puts("Error: could not disable GSC Watchdog\n");
1613         }
1614
1615         return 0;
1616 }
1617
1618 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
1619
1620 static int ft_sethdmiinfmt(void *blob, char *mode)
1621 {
1622         int off;
1623
1624         if (!mode)
1625                 return -EINVAL;
1626
1627         off = fdt_node_offset_by_compatible(blob, -1, "nxp,tda1997x");
1628         if (off < 0)
1629                 return off;
1630
1631         if (0 == strcasecmp(mode, "yuv422bt656")) {
1632                 u8 cfg[] = { 0x00, 0x00, 0x00, 0x82, 0x81, 0x00,
1633                              0x00, 0x00, 0x00 };
1634                 mode = "422_ccir";
1635                 fdt_setprop(blob, off, "vidout_fmt", mode, strlen(mode) + 1);
1636                 fdt_setprop_u32(blob, off, "vidout_trc", 1);
1637                 fdt_setprop_u32(blob, off, "vidout_blc", 1);
1638                 fdt_setprop(blob, off, "vidout_portcfg", cfg, sizeof(cfg));
1639                 printf("   set HDMI input mode to %s\n", mode);
1640         } else if (0 == strcasecmp(mode, "yuv422smp")) {
1641                 u8 cfg[] = { 0x00, 0x00, 0x00, 0x88, 0x87, 0x00,
1642                              0x82, 0x81, 0x00 };
1643                 mode = "422_smp";
1644                 fdt_setprop(blob, off, "vidout_fmt", mode, strlen(mode) + 1);
1645                 fdt_setprop_u32(blob, off, "vidout_trc", 0);
1646                 fdt_setprop_u32(blob, off, "vidout_blc", 0);
1647                 fdt_setprop(blob, off, "vidout_portcfg", cfg, sizeof(cfg));
1648                 printf("   set HDMI input mode to %s\n", mode);
1649         } else {
1650                 return -EINVAL;
1651         }
1652
1653         return 0;
1654 }
1655
1656 /*
1657  * called prior to booting kernel or by 'fdt boardsetup' command
1658  *
1659  * unless 'fdt_noauto' env var is set we will update the following in the DTB:
1660  *  - mtd partitions based on mtdparts/mtdids env
1661  *  - system-serial (board serial num from EEPROM)
1662  *  - board (full model from EEPROM)
1663  *  - peripherals removed from DTB if not loaded on board (per EEPROM config)
1664  */
1665 int ft_board_setup(void *blob, bd_t *bd)
1666 {
1667         struct ventana_board_info *info = &ventana_info;
1668         struct ventana_eeprom_config *cfg;
1669         struct node_info nodes[] = {
1670                 { "sst,w25q256",          MTD_DEV_TYPE_NOR, },  /* SPI flash */
1671                 { "fsl,imx6q-gpmi-nand",  MTD_DEV_TYPE_NAND, }, /* NAND flash */
1672         };
1673         const char *model = getenv("model");
1674         const char *display = getenv("display");
1675         int i;
1676         char rev = 0;
1677
1678         /* determine board revision */
1679         for (i = sizeof(ventana_info.model) - 1; i > 0; i--) {
1680                 if (ventana_info.model[i] >= 'A') {
1681                         rev = ventana_info.model[i];
1682                         break;
1683                 }
1684         }
1685
1686         if (getenv("fdt_noauto")) {
1687                 puts("   Skiping ft_board_setup (fdt_noauto defined)\n");
1688                 return 0;
1689         }
1690
1691         /* Update partition nodes using info from mtdparts env var */
1692         puts("   Updating MTD partitions...\n");
1693         fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
1694
1695         /* Update display timings from display env var */
1696         if (display) {
1697                 if (fdt_fixup_display(blob, fdt_get_alias(blob, "lvds0"),
1698                                       display) >= 0)
1699                         printf("   Set display timings for %s...\n", display);
1700         }
1701
1702         if (!model) {
1703                 puts("invalid board info: Leaving FDT fully enabled\n");
1704                 return 0;
1705         }
1706         printf("   Adjusting FDT per EEPROM for %s...\n", model);
1707
1708         /* board serial number */
1709         fdt_setprop(blob, 0, "system-serial", getenv("serial#"),
1710                     strlen(getenv("serial#")) + 1);
1711
1712         /* board (model contains model from device-tree) */
1713         fdt_setprop(blob, 0, "board", info->model,
1714                     strlen((const char *)info->model) + 1);
1715
1716         /* set desired digital video capture format */
1717         ft_sethdmiinfmt(blob, getenv("hdmiinfmt"));
1718
1719         /*
1720          * disable serial2 node for GW54xx for compatibility with older
1721          * 3.10.x kernel that improperly had this node enabled in the DT
1722          */
1723         if (board_type == GW54xx) {
1724                 i = fdt_path_offset(blob,
1725                                     "/soc/aips-bus@02100000/serial@021ec000");
1726                 if (i)
1727                         fdt_del_node(blob, i);
1728         }
1729
1730         /*
1731          * disable wdog1/wdog2 nodes for GW51xx below revC to work around
1732          * errata causing wdog timer to be unreliable.
1733          */
1734         if (board_type == GW51xx && rev >= 'A' && rev < 'C') {
1735                 i = fdt_path_offset(blob,
1736                                     "/soc/aips-bus@02000000/wdog@020bc000");
1737                 if (i)
1738                         fdt_status_disabled(blob, i);
1739         }
1740
1741         /* GW522x Uses GPIO3_IO23 instead of GPIO1_IO29 */
1742         else if (board_type == GW52xx && info->model[4] == '2') {
1743                 u32 handle = 0;
1744                 u32 *range = NULL;
1745
1746                 i = fdt_node_offset_by_compatible(blob, -1, "fsl,imx6q-pcie");
1747                 if (i)
1748                         range = (u32 *)fdt_getprop(blob, i, "reset-gpio",
1749                                                    NULL);
1750
1751                 if (range) {
1752                         i = fdt_path_offset(blob,
1753                                             "/soc/aips-bus@02000000/gpio@020a4000");
1754                         if (i)
1755                                 handle = fdt_get_phandle(blob, i);
1756                         if (handle) {
1757                                 range[0] = cpu_to_fdt32(handle);
1758                                 range[1] = cpu_to_fdt32(23);
1759                         }
1760                 }
1761         }
1762
1763         /*
1764          * isolate CSI0_DATA_EN for GW551x below revB to work around
1765          * errata causing non functional digital video in (it is not hooked up)
1766          */
1767         else if (board_type == GW551x && rev == 'A') {
1768                 u32 *range = NULL;
1769                 int len;
1770                 const u32 *handle = NULL;
1771
1772                 i = fdt_node_offset_by_compatible(blob, -1,
1773                                                   "fsl,imx-tda1997x-video");
1774                 if (i)
1775                         handle = fdt_getprop(blob, i, "pinctrl-0", NULL);
1776                 if (handle)
1777                         i = fdt_node_offset_by_phandle(blob,
1778                                                        fdt32_to_cpu(*handle));
1779                 if (i)
1780                         range = (u32 *)fdt_getprop(blob, i, "fsl,pins", &len);
1781                 if (range) {
1782                         len /= sizeof(u32);
1783                         for (i = 0; i < len; i += 6) {
1784                                 u32 mux_reg = fdt32_to_cpu(range[i+0]);
1785                                 u32 conf_reg = fdt32_to_cpu(range[i+1]);
1786                                 /* mux PAD_CSI0_DATA_EN to GPIO */
1787                                 if (is_cpu_type(MXC_CPU_MX6Q) &&
1788                                     mux_reg == 0x260 && conf_reg == 0x630)
1789                                         range[i+3] = cpu_to_fdt32(0x5);
1790                                 else if (!is_cpu_type(MXC_CPU_MX6Q) &&
1791                                     mux_reg == 0x08c && conf_reg == 0x3a0)
1792                                         range[i+3] = cpu_to_fdt32(0x5);
1793                         }
1794                         fdt_setprop_inplace(blob, i, "fsl,pins", range, len);
1795                 }
1796
1797                 /* set BT656 video format */
1798                 ft_sethdmiinfmt(blob, "yuv422bt656");
1799         }
1800
1801         /*
1802          * Peripheral Config:
1803          *  remove nodes by alias path if EEPROM config tells us the
1804          *  peripheral is not loaded on the board.
1805          */
1806         if (getenv("fdt_noconfig")) {
1807                 puts("   Skiping periperhal config (fdt_noconfig defined)\n");
1808                 return 0;
1809         }
1810         cfg = econfig;
1811         while (cfg->name) {
1812                 if (!test_bit(cfg->bit, info->config)) {
1813                         fdt_del_node_and_alias(blob, cfg->dtalias ?
1814                                                cfg->dtalias : cfg->name);
1815                 }
1816                 cfg++;
1817         }
1818
1819         return 0;
1820 }
1821 #endif /* defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) */
1822