board/gateworks/gw_ventana/gw_ventana.c

   1 /*
   2  * Copyright (C) 2013 Gateworks Corporation
   3  *
   4  * Author: Tim Harvey <tharvey@gateworks.com>
   5  *
   6  * SPDX-License-Identifier: GPL-2.0+
   7  */
   8
   9 #include <common.h>
  10 #include <asm/arch/clock.h>
  11 #include <asm/arch/crm_regs.h>
  12 #include <asm/arch/iomux.h>
  13 #include <asm/arch/mx6-pins.h>
  14 #include <asm/arch/mxc_hdmi.h>
  15 #include <asm/arch/sys_proto.h>
  16 #include <asm/gpio.h>
  17 #include <asm/imx-common/boot_mode.h>
  18 #include <asm/imx-common/sata.h>
  19 #include <asm/imx-common/spi.h>
  20 #include <asm/imx-common/video.h>
  21 #include <asm/io.h>
  22 #include <dm.h>
  23 #include <dm/platform_data/serial_mxc.h>
  24 #include <hwconfig.h>
  25 #include <i2c.h>
  26 #include <fdt_support.h>
  27 #include <fsl_esdhc.h>
  28 #include <jffs2/load_kernel.h>
  29 #include <linux/ctype.h>
  30 #include <miiphy.h>
  31 #include <mtd_node.h>
  32 #include <netdev.h>
  33 #include <pci.h>
  34 #include <power/pmic.h>
  35 #include <power/ltc3676_pmic.h>
  36 #include <power/pfuze100_pmic.h>
  37 #include <fdt_support.h>
  38 #include <jffs2/load_kernel.h>
  39 #include <spi_flash.h>
  40
  41 #include "gsc.h"
  42 #include "common.h"
  43
  44 DECLARE_GLOBAL_DATA_PTR;
  45
  46
  47 /*
  48  * EEPROM board info struct populated by read_eeprom so that we only have to
  49  * read it once.
  50  */
  51 struct ventana_board_info ventana_info;
  52
  53 static int board_type;
  54
  55 /* ENET */
  56 static iomux_v3_cfg_t const enet_pads[] = {
  57         IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  58         IOMUX_PADS(PAD_ENET_MDC__ENET_MDC    | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  59         IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  60         IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  61         IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  62         IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  63         IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  64         IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL |
  65                    MUX_PAD_CTRL(ENET_PAD_CTRL)),
  66         IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK |
  67                    MUX_PAD_CTRL(ENET_PAD_CTRL)),
  68         IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  69         IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  70         IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  71         IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  72         IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  73         IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL |
  74                    MUX_PAD_CTRL(ENET_PAD_CTRL)),
  75         /* PHY nRST */
  76         IOMUX_PADS(PAD_ENET_TXD0__GPIO1_IO30 | DIO_PAD_CFG),
  77 };
  78
  79 /* NAND */
  80 static iomux_v3_cfg_t const nfc_pads[] = {
  81         IOMUX_PADS(PAD_NANDF_CLE__NAND_CLE     | MUX_PAD_CTRL(NO_PAD_CTRL)),
  82         IOMUX_PADS(PAD_NANDF_ALE__NAND_ALE     | MUX_PAD_CTRL(NO_PAD_CTRL)),
  83         IOMUX_PADS(PAD_NANDF_WP_B__NAND_WP_B   | MUX_PAD_CTRL(NO_PAD_CTRL)),
  84         IOMUX_PADS(PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
  85         IOMUX_PADS(PAD_NANDF_CS0__NAND_CE0_B   | MUX_PAD_CTRL(NO_PAD_CTRL)),
  86         IOMUX_PADS(PAD_SD4_CMD__NAND_RE_B      | MUX_PAD_CTRL(NO_PAD_CTRL)),
  87         IOMUX_PADS(PAD_SD4_CLK__NAND_WE_B      | MUX_PAD_CTRL(NO_PAD_CTRL)),
  88         IOMUX_PADS(PAD_NANDF_D0__NAND_DATA00   | MUX_PAD_CTRL(NO_PAD_CTRL)),
  89         IOMUX_PADS(PAD_NANDF_D1__NAND_DATA01   | MUX_PAD_CTRL(NO_PAD_CTRL)),
  90         IOMUX_PADS(PAD_NANDF_D2__NAND_DATA02   | MUX_PAD_CTRL(NO_PAD_CTRL)),
  91         IOMUX_PADS(PAD_NANDF_D3__NAND_DATA03   | MUX_PAD_CTRL(NO_PAD_CTRL)),
  92         IOMUX_PADS(PAD_NANDF_D4__NAND_DATA04   | MUX_PAD_CTRL(NO_PAD_CTRL)),
  93         IOMUX_PADS(PAD_NANDF_D5__NAND_DATA05   | MUX_PAD_CTRL(NO_PAD_CTRL)),
  94         IOMUX_PADS(PAD_NANDF_D6__NAND_DATA06   | MUX_PAD_CTRL(NO_PAD_CTRL)),
  95         IOMUX_PADS(PAD_NANDF_D7__NAND_DATA07   | MUX_PAD_CTRL(NO_PAD_CTRL)),
  96 };
  97
  98 #ifdef CONFIG_CMD_NAND
  99 static void setup_gpmi_nand(void)
 100 {
 101         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 102
 103         /* config gpmi nand iomux */
 104         SETUP_IOMUX_PADS(nfc_pads);
 105
 106         /* config gpmi and bch clock to 100 MHz */
 107         clrsetbits_le32(&mxc_ccm->cs2cdr,
 108                         MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
 109                         MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
 110                         MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
 111                         MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
 112                         MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
 113                         MXC_CCM_CS2CDR_ENFC_CLK_SEL(3));
 114
 115         /* enable gpmi and bch clock gating */
 116         setbits_le32(&mxc_ccm->CCGR4,
 117                      MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
 118                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
 119                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
 120                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
 121                      MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET);
 122
 123         /* enable apbh clock gating */
 124         setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
 125 }
 126 #endif
 127
 128 static void setup_iomux_enet(int gpio)
 129 {
 130         SETUP_IOMUX_PADS(enet_pads);
 131
 132         /* toggle PHY_RST# */
 133         gpio_request(gpio, "phy_rst#");
 134         gpio_direction_output(gpio, 0);
 135         mdelay(2);
 136         gpio_set_value(gpio, 1);
 137 }
 138
 139 #ifdef CONFIG_USB_EHCI_MX6
 140 static iomux_v3_cfg_t const usb_pads[] = {
 141         IOMUX_PADS(PAD_GPIO_1__USB_OTG_ID   | DIO_PAD_CFG),
 142         IOMUX_PADS(PAD_KEY_COL4__USB_OTG_OC | DIO_PAD_CFG),
 143         /* OTG PWR */
 144         IOMUX_PADS(PAD_EIM_D22__GPIO3_IO22  | DIO_PAD_CFG),
 145 };
 146
 147 int board_ehci_hcd_init(int port)
 148 {
 149         int gpio;
 150
 151         SETUP_IOMUX_PADS(usb_pads);
 152
 153         /* Reset USB HUB */
 154         switch (board_type) {
 155         case GW53xx:
 156         case GW552x:
 157                 gpio = (IMX_GPIO_NR(1, 9));
 158                 break;
 159         case GW54proto:
 160         case GW54xx:
 161                 gpio = (IMX_GPIO_NR(1, 16));
 162                 break;
 163         default:
 164                 return 0;
 165         }
 166
 167         /* request and toggle hub rst */
 168         gpio_request(gpio, "usb_hub_rst#");
 169         gpio_direction_output(gpio, 0);
 170         mdelay(2);
 171         gpio_set_value(gpio, 1);
 172
 173         return 0;
 174 }
 175
 176 int board_ehci_power(int port, int on)
 177 {
 178         if (port)
 179                 return 0;
 180         gpio_set_value(GP_USB_OTG_PWR, on);
 181         return 0;
 182 }
 183 #endif /* CONFIG_USB_EHCI_MX6 */
 184
 185 #ifdef CONFIG_MXC_SPI
 186 iomux_v3_cfg_t const ecspi1_pads[] = {
 187         /* SS1 */
 188         IOMUX_PADS(PAD_EIM_D19__GPIO3_IO19  | MUX_PAD_CTRL(SPI_PAD_CTRL)),
 189         IOMUX_PADS(PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL)),
 190         IOMUX_PADS(PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL)),
 191         IOMUX_PADS(PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL)),
 192 };
 193
 194 int board_spi_cs_gpio(unsigned bus, unsigned cs)
 195 {
 196         return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(3, 19)) : -1;
 197 }
 198
 199 static void setup_spi(void)
 200 {
 201         gpio_request(IMX_GPIO_NR(3, 19), "spi_cs");
 202         gpio_direction_output(IMX_GPIO_NR(3, 19), 1);
 203         SETUP_IOMUX_PADS(ecspi1_pads);
 204 }
 205 #endif
 206
 207 /* configure eth0 PHY board-specific LED behavior */
 208 int board_phy_config(struct phy_device *phydev)
 209 {
 210         unsigned short val;
 211
 212         /* Marvel 88E1510 */
 213         if (phydev->phy_id == 0x1410dd1) {
 214                 /*
 215                  * Page 3, Register 16: LED[2:0] Function Control Register
 216                  * LED[0] (SPD:Amber) R16_3.3:0 to 0111: on-GbE link
 217                  * LED[1] (LNK:Green) R16_3.7:4 to 0001: on-link, blink-activity
 218                  */
 219                 phy_write(phydev, MDIO_DEVAD_NONE, 22, 3);
 220                 val = phy_read(phydev, MDIO_DEVAD_NONE, 16);
 221                 val &= 0xff00;
 222                 val |= 0x0017;
 223                 phy_write(phydev, MDIO_DEVAD_NONE, 16, val);
 224                 phy_write(phydev, MDIO_DEVAD_NONE, 22, 0);
 225         }
 226
 227         if (phydev->drv->config)
 228                 phydev->drv->config(phydev);
 229
 230         return 0;
 231 }
 232
 233 int board_eth_init(bd_t *bis)
 234 {
 235 #ifdef CONFIG_FEC_MXC
 236         struct ventana_board_info *info = &ventana_info;
 237
 238         if (test_bit(EECONFIG_ETH0, info->config)) {
 239                 setup_iomux_enet(GP_PHY_RST);
 240                 cpu_eth_init(bis);
 241         }
 242 #endif
 243
 244 #ifdef CONFIG_E1000
 245         e1000_initialize(bis);
 246 #endif
 247
 248 #ifdef CONFIG_CI_UDC
 249         /* For otg ethernet*/
 250         usb_eth_initialize(bis);
 251 #endif
 252
 253         /* default to the first detected enet dev */
 254         if (!getenv("ethprime")) {
 255                 struct eth_device *dev = eth_get_dev_by_index(0);
 256                 if (dev) {
 257                         setenv("ethprime", dev->name);
 258                         printf("set ethprime to %s\n", getenv("ethprime"));
 259                 }
 260         }
 261
 262         return 0;
 263 }
 264
 265 #if defined(CONFIG_VIDEO_IPUV3)
 266
 267 static void enable_hdmi(struct display_info_t const *dev)
 268 {
 269         imx_enable_hdmi_phy();
 270 }
 271
 272 static int detect_i2c(struct display_info_t const *dev)
 273 {
 274         return i2c_set_bus_num(dev->bus) == 0 &&
 275                 i2c_probe(dev->addr) == 0;
 276 }
 277
 278 static void enable_lvds(struct display_info_t const *dev)
 279 {
 280         struct iomuxc *iomux = (struct iomuxc *)
 281                                 IOMUXC_BASE_ADDR;
 282
 283         /* set CH0 data width to 24bit (IOMUXC_GPR2:5 0=18bit, 1=24bit) */
 284         u32 reg = readl(&iomux->gpr[2]);
 285         reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT;
 286         writel(reg, &iomux->gpr[2]);
 287
 288         /* Enable Backlight */
 289         gpio_request(IMX_GPIO_NR(1, 10), "bklt_gpio");
 290         gpio_direction_output(IMX_GPIO_NR(1, 10), 0);
 291         gpio_request(IMX_GPIO_NR(1, 18), "bklt_en");
 292         SETUP_IOMUX_PAD(PAD_SD1_CMD__GPIO1_IO18 | DIO_PAD_CFG);
 293         gpio_direction_output(IMX_GPIO_NR(1, 18), 1);
 294 }
 295
 296 struct display_info_t const displays[] = {{
 297         /* HDMI Output */
 298         .bus    = -1,
 299         .addr   = 0,
 300         .pixfmt = IPU_PIX_FMT_RGB24,
 301         .detect = detect_hdmi,
 302         .enable = enable_hdmi,
 303         .mode   = {
 304                 .name           = "HDMI",
 305                 .refresh        = 60,
 306                 .xres           = 1024,
 307                 .yres           = 768,
 308                 .pixclock       = 15385,
 309                 .left_margin    = 220,
 310                 .right_margin   = 40,
 311                 .upper_margin   = 21,
 312                 .lower_margin   = 7,
 313                 .hsync_len      = 60,
 314                 .vsync_len      = 10,
 315                 .sync           = FB_SYNC_EXT,
 316                 .vmode          = FB_VMODE_NONINTERLACED
 317 } }, {
 318         /* Freescale MXC-LVDS1: HannStar HSD100PXN1-A00 w/ egalx_ts cont */
 319         .bus    = 2,
 320         .addr   = 0x4,
 321         .pixfmt = IPU_PIX_FMT_LVDS666,
 322         .detect = detect_i2c,
 323         .enable = enable_lvds,
 324         .mode   = {
 325                 .name           = "Hannstar-XGA",
 326                 .refresh        = 60,
 327                 .xres           = 1024,
 328                 .yres           = 768,
 329                 .pixclock       = 15385,
 330                 .left_margin    = 220,
 331                 .right_margin   = 40,
 332                 .upper_margin   = 21,
 333                 .lower_margin   = 7,
 334                 .hsync_len      = 60,
 335                 .vsync_len      = 10,
 336                 .sync           = FB_SYNC_EXT,
 337                 .vmode          = FB_VMODE_NONINTERLACED
 338 } }, {
 339         /* DLC700JMG-T-4 */
 340         .bus    = 0,
 341         .addr   = 0,
 342         .detect = NULL,
 343         .enable = enable_lvds,
 344         .pixfmt = IPU_PIX_FMT_LVDS666,
 345         .mode   = {
 346                 .name           = "DLC700JMGT4",
 347                 .refresh        = 60,
 348                 .xres           = 1024,         /* 1024x600active pixels */
 349                 .yres           = 600,
 350                 .pixclock       = 15385,        /* 64MHz */
 351                 .left_margin    = 220,
 352                 .right_margin   = 40,
 353                 .upper_margin   = 21,
 354                 .lower_margin   = 7,
 355                 .hsync_len      = 60,
 356                 .vsync_len      = 10,
 357                 .sync           = FB_SYNC_EXT,
 358                 .vmode          = FB_VMODE_NONINTERLACED
 359 } }, {
 360         /* DLC800FIG-T-3 */
 361         .bus    = 0,
 362         .addr   = 0,
 363         .detect = NULL,
 364         .enable = enable_lvds,
 365         .pixfmt = IPU_PIX_FMT_LVDS666,
 366         .mode   = {
 367                 .name           = "DLC800FIGT3",
 368                 .refresh        = 60,
 369                 .xres           = 1024,         /* 1024x768 active pixels */
 370                 .yres           = 768,
 371                 .pixclock       = 15385,        /* 64MHz */
 372                 .left_margin    = 220,
 373                 .right_margin   = 40,
 374                 .upper_margin   = 21,
 375                 .lower_margin   = 7,
 376                 .hsync_len      = 60,
 377                 .vsync_len      = 10,
 378                 .sync           = FB_SYNC_EXT,
 379                 .vmode          = FB_VMODE_NONINTERLACED
 380 } } };
 381 size_t display_count = ARRAY_SIZE(displays);
 382
 383 static void setup_display(void)
 384 {
 385         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 386         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 387         int reg;
 388
 389         enable_ipu_clock();
 390         imx_setup_hdmi();
 391         /* Turn on LDB0,IPU,IPU DI0 clocks */
 392         reg = __raw_readl(&mxc_ccm->CCGR3);
 393         reg |= MXC_CCM_CCGR3_LDB_DI0_MASK;
 394         writel(reg, &mxc_ccm->CCGR3);
 395
 396         /* set LDB0, LDB1 clk select to 011/011 */
 397         reg = readl(&mxc_ccm->cs2cdr);
 398         reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
 399                  |MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
 400         reg |= (3<<MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
 401               |(3<<MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
 402         writel(reg, &mxc_ccm->cs2cdr);
 403
 404         reg = readl(&mxc_ccm->cscmr2);
 405         reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
 406         writel(reg, &mxc_ccm->cscmr2);
 407
 408         reg = readl(&mxc_ccm->chsccdr);
 409         reg |= (CHSCCDR_CLK_SEL_LDB_DI0
 410                 <<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
 411         writel(reg, &mxc_ccm->chsccdr);
 412
 413         reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
 414              |IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
 415              |IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
 416              |IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
 417              |IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
 418              |IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
 419              |IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
 420              |IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
 421              |IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
 422         writel(reg, &iomux->gpr[2]);
 423
 424         reg = readl(&iomux->gpr[3]);
 425         reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK)
 426             | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
 427                <<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
 428         writel(reg, &iomux->gpr[3]);
 429
 430         /* LVDS Backlight GPIO on LVDS connector - output low */
 431         SETUP_IOMUX_PAD(PAD_SD2_CLK__GPIO1_IO10 | DIO_PAD_CFG);
 432         gpio_direction_output(IMX_GPIO_NR(1, 10), 0);
 433 }
 434 #endif /* CONFIG_VIDEO_IPUV3 */
 435
 436 /* setup board specific PMIC */
 437 int power_init_board(void)
 438 {
 439         setup_pmic();
 440         return 0;
 441 }
 442
 443 #if defined(CONFIG_CMD_PCI)
 444 int imx6_pcie_toggle_reset(void)
 445 {
 446         if (board_type < GW_UNKNOWN) {
 447                 uint pin = gpio_cfg[board_type].pcie_rst;
 448                 gpio_request(pin, "pci_rst#");
 449                 gpio_direction_output(pin, 0);
 450                 mdelay(50);
 451                 gpio_direction_output(pin, 1);
 452         }
 453         return 0;
 454 }
 455
 456 /*
 457  * Most Ventana boards have a PLX PEX860x PCIe switch onboard and use its
 458  * GPIO's as PERST# signals for its downstream ports - configure the GPIO's
 459  * properly and assert reset for 100ms.
 460  */
 461 #define MAX_PCI_DEVS    32
 462 struct pci_dev {
 463         pci_dev_t devfn;
 464         unsigned short vendor;
 465         unsigned short device;
 466         unsigned short class;
 467         unsigned short busno; /* subbordinate busno */
 468         struct pci_dev *ppar;
 469 };
 470 struct pci_dev pci_devs[MAX_PCI_DEVS];
 471 int pci_devno;
 472 int pci_bridgeno;
 473
 474 void board_pci_fixup_dev(struct pci_controller *hose, pci_dev_t dev,
 475                          unsigned short vendor, unsigned short device,
 476                          unsigned short class)
 477 {
 478         int i;
 479         u32 dw;
 480         struct pci_dev *pdev = &pci_devs[pci_devno++];
 481
 482         debug("%s: %02d:%02d.%02d: %04x:%04x\n", __func__,
 483               PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev), vendor, device);
 484
 485         /* store array of devs for later use in device-tree fixup */
 486         pdev->devfn = dev;
 487         pdev->vendor = vendor;
 488         pdev->device = device;
 489         pdev->class = class;
 490         pdev->ppar = NULL;
 491         if (class == PCI_CLASS_BRIDGE_PCI)
 492                 pdev->busno = ++pci_bridgeno;
 493         else
 494                 pdev->busno = 0;
 495
 496         /* fixup RC - it should be 00:00.0 not 00:01.0 */
 497         if (PCI_BUS(dev) == 0)
 498                 pdev->devfn = 0;
 499
 500         /* find dev's parent */
 501         for (i = 0; i < pci_devno; i++) {
 502                 if (pci_devs[i].busno == PCI_BUS(pdev->devfn)) {
 503                         pdev->ppar = &pci_devs[i];
 504                         break;
 505                 }
 506         }
 507
 508         /* assert downstream PERST# */
 509         if (vendor == PCI_VENDOR_ID_PLX &&
 510             (device & 0xfff0) == 0x8600 &&
 511             PCI_DEV(dev) == 0 && PCI_FUNC(dev) == 0) {
 512                 debug("configuring PLX 860X downstream PERST#\n");
 513                 pci_hose_read_config_dword(hose, dev, 0x62c, &dw);
 514                 dw |= 0xaaa8; /* GPIO1-7 outputs */
 515                 pci_hose_write_config_dword(hose, dev, 0x62c, dw);
 516
 517                 pci_hose_read_config_dword(hose, dev, 0x644, &dw);
 518                 dw |= 0xfe;   /* GPIO1-7 output high */
 519                 pci_hose_write_config_dword(hose, dev, 0x644, dw);
 520
 521                 mdelay(100);
 522         }
 523 }
 524 #endif /* CONFIG_CMD_PCI */
 525
 526 #ifdef CONFIG_SERIAL_TAG
 527 /*
 528  * called when setting up ATAGS before booting kernel
 529  * populate serialnum from the following (in order of priority):
 530  *   serial# env var
 531  *   eeprom
 532  */
 533 void get_board_serial(struct tag_serialnr *serialnr)
 534 {
 535         char *serial = getenv("serial#");
 536
 537         if (serial) {
 538                 serialnr->high = 0;
 539                 serialnr->low = simple_strtoul(serial, NULL, 10);
 540         } else if (ventana_info.model[0]) {
 541                 serialnr->high = 0;
 542                 serialnr->low = ventana_info.serial;
 543         } else {
 544                 serialnr->high = 0;
 545                 serialnr->low = 0;
 546         }
 547 }
 548 #endif
 549
 550 /*
 551  * Board Support
 552  */
 553
 554 int board_early_init_f(void)
 555 {
 556         setup_iomux_uart();
 557
 558 #if defined(CONFIG_VIDEO_IPUV3)
 559         setup_display();
 560 #endif
 561         return 0;
 562 }
 563
 564 int dram_init(void)
 565 {
 566         gd->ram_size = imx_ddr_size();
 567         return 0;
 568 }
 569
 570 int board_init(void)
 571 {
 572         struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
 573
 574         clrsetbits_le32(&iomuxc_regs->gpr[1],
 575                         IOMUXC_GPR1_OTG_ID_MASK,
 576                         IOMUXC_GPR1_OTG_ID_GPIO1);
 577
 578         /* address of linux boot parameters */
 579         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 580
 581 #ifdef CONFIG_CMD_NAND
 582         setup_gpmi_nand();
 583 #endif
 584 #ifdef CONFIG_MXC_SPI
 585         setup_spi();
 586 #endif
 587         setup_ventana_i2c();
 588
 589 #ifdef CONFIG_CMD_SATA
 590         setup_sata();
 591 #endif
 592         /* read Gateworks EEPROM into global struct (used later) */
 593         board_type = read_eeprom(CONFIG_I2C_GSC, &ventana_info);
 594
 595         setup_iomux_gpio(board_type, &ventana_info);
 596
 597         return 0;
 598 }
 599
 600 #if defined(CONFIG_DISPLAY_BOARDINFO_LATE)
 601 /*
 602  * called during late init (after relocation and after board_init())
 603  * by virtue of CONFIG_DISPLAY_BOARDINFO_LATE as we needed i2c initialized and
 604  * EEPROM read.
 605  */
 606 int checkboard(void)
 607 {
 608         struct ventana_board_info *info = &ventana_info;
 609         unsigned char buf[4];
 610         const char *p;
 611         int quiet; /* Quiet or minimal output mode */
 612
 613         quiet = 0;
 614         p = getenv("quiet");
 615         if (p)
 616                 quiet = simple_strtol(p, NULL, 10);
 617         else
 618                 setenv("quiet", "0");
 619
 620         puts("\nGateworks Corporation Copyright 2014\n");
 621         if (info->model[0]) {
 622                 printf("Model: %s\n", info->model);
 623                 printf("MFGDate: %02x-%02x-%02x%02x\n",
 624                        info->mfgdate[0], info->mfgdate[1],
 625                        info->mfgdate[2], info->mfgdate[3]);
 626                 printf("Serial:%d\n", info->serial);
 627         } else {
 628                 puts("Invalid EEPROM - board will not function fully\n");
 629         }
 630         if (quiet)
 631                 return 0;
 632
 633         /* Display GSC firmware revision/CRC/status */
 634         gsc_info(0);
 635
 636         /* Display RTC */
 637         if (!gsc_i2c_read(GSC_RTC_ADDR, 0x00, 1, buf, 4)) {
 638                 printf("RTC:   %d\n",
 639                        buf[0] | buf[1]<<8 | buf[2]<<16 | buf[3]<<24);
 640         }
 641
 642         return 0;
 643 }
 644 #endif
 645
 646 #ifdef CONFIG_CMD_BMODE
 647 /*
 648  * BOOT_CFG1, BOOT_CFG2, BOOT_CFG3, BOOT_CFG4
 649  * see Table 8-11 and Table 5-9
 650  *  BOOT_CFG1[7] = 1 (boot from NAND)
 651  *  BOOT_CFG1[5] = 0 - raw NAND
 652  *  BOOT_CFG1[4] = 0 - default pad settings
 653  *  BOOT_CFG1[3:2] = 00 - devices = 1
 654  *  BOOT_CFG1[1:0] = 00 - Row Address Cycles = 3
 655  *  BOOT_CFG2[4:3] = 00 - Boot Search Count = 2
 656  *  BOOT_CFG2[2:1] = 01 - Pages In Block = 64
 657  *  BOOT_CFG2[0] = 0 - Reset time 12ms
 658  */
 659 static const struct boot_mode board_boot_modes[] = {
 660         /* NAND: 64pages per block, 3 row addr cycles, 2 copies of FCB/DBBT */
 661         { "nand", MAKE_CFGVAL(0x80, 0x02, 0x00, 0x00) },
 662         { NULL, 0 },
 663 };
 664 #endif
 665
 666 /* late init */
 667 int misc_init_r(void)
 668 {
 669         struct ventana_board_info *info = &ventana_info;
 670         char buf[256];
 671         int i;
 672
 673         /* set env vars based on EEPROM data */
 674         if (ventana_info.model[0]) {
 675                 char str[16], fdt[36];
 676                 char *p;
 677                 const char *cputype = "";
 678
 679                 /*
 680                  * FDT name will be prefixed with CPU type.  Three versions
 681                  * will be created each increasingly generic and bootloader
 682                  * env scripts will try loading each from most specific to
 683                  * least.
 684                  */
 685                 if (is_cpu_type(MXC_CPU_MX6Q) ||
 686                     is_cpu_type(MXC_CPU_MX6D))
 687                         cputype = "imx6q";
 688                 else if (is_cpu_type(MXC_CPU_MX6DL) ||
 689                          is_cpu_type(MXC_CPU_MX6SOLO))
 690                         cputype = "imx6dl";
 691                 setenv("soctype", cputype);
 692                 if (8 << (ventana_info.nand_flash_size-1) >= 2048)
 693                         setenv("flash_layout", "large");
 694                 else
 695                         setenv("flash_layout", "normal");
 696                 memset(str, 0, sizeof(str));
 697                 for (i = 0; i < (sizeof(str)-1) && info->model[i]; i++)
 698                         str[i] = tolower(info->model[i]);
 699                 setenv("model", str);
 700                 if (!getenv("fdt_file")) {
 701                         sprintf(fdt, "%s-%s.dtb", cputype, str);
 702                         setenv("fdt_file", fdt);
 703                 }
 704                 p = strchr(str, '-');
 705                 if (p) {
 706                         *p++ = 0;
 707
 708                         setenv("model_base", str);
 709                         sprintf(fdt, "%s-%s.dtb", cputype, str);
 710                         setenv("fdt_file1", fdt);
 711                         if (board_type != GW551x &&
 712                             board_type != GW552x &&
 713                             board_type != GW553x)
 714                                 str[4] = 'x';
 715                         str[5] = 'x';
 716                         str[6] = 0;
 717                         sprintf(fdt, "%s-%s.dtb", cputype, str);
 718                         setenv("fdt_file2", fdt);
 719                 }
 720
 721                 /* initialize env from EEPROM */
 722                 if (test_bit(EECONFIG_ETH0, info->config) &&
 723                     !getenv("ethaddr")) {
 724                         eth_setenv_enetaddr("ethaddr", info->mac0);
 725                 }
 726                 if (test_bit(EECONFIG_ETH1, info->config) &&
 727                     !getenv("eth1addr")) {
 728                         eth_setenv_enetaddr("eth1addr", info->mac1);
 729                 }
 730
 731                 /* board serial-number */
 732                 sprintf(str, "%6d", info->serial);
 733                 setenv("serial#", str);
 734
 735                 /* memory MB */
 736                 sprintf(str, "%d", (int) (gd->ram_size >> 20));
 737                 setenv("mem_mb", str);
 738         }
 739
 740         /* Set a non-initialized hwconfig based on board configuration */
 741         if (!strcmp(getenv("hwconfig"), "_UNKNOWN_")) {
 742                 buf[0] = 0;
 743                 if (gpio_cfg[board_type].rs232_en)
 744                         strcat(buf, "rs232;");
 745                 for (i = 0; i < gpio_cfg[board_type].dio_num; i++) {
 746                         char buf1[32];
 747                         sprintf(buf1, "dio%d:mode=gpio;", i);
 748                         if (strlen(buf) + strlen(buf1) < sizeof(buf))
 749                                 strcat(buf, buf1);
 750                 }
 751                 setenv("hwconfig", buf);
 752         }
 753
 754         /* setup baseboard specific GPIO based on board and env */
 755         setup_board_gpio(board_type, info);
 756
 757 #ifdef CONFIG_CMD_BMODE
 758         add_board_boot_modes(board_boot_modes);
 759 #endif
 760
 761         /* disable boot watchdog */
 762         gsc_boot_wd_disable();
 763
 764         return 0;
 765 }
 766
 767 #ifdef CONFIG_OF_BOARD_SETUP
 768
 769 static int ft_sethdmiinfmt(void *blob, char *mode)
 770 {
 771         int off;
 772
 773         if (!mode)
 774                 return -EINVAL;
 775
 776         off = fdt_node_offset_by_compatible(blob, -1, "nxp,tda1997x");
 777         if (off < 0)
 778                 return off;
 779
 780         if (0 == strcasecmp(mode, "yuv422bt656")) {
 781                 u8 cfg[] = { 0x00, 0x00, 0x00, 0x82, 0x81, 0x00,
 782                              0x00, 0x00, 0x00 };
 783                 mode = "422_ccir";
 784                 fdt_setprop(blob, off, "vidout_fmt", mode, strlen(mode) + 1);
 785                 fdt_setprop_u32(blob, off, "vidout_trc", 1);
 786                 fdt_setprop_u32(blob, off, "vidout_blc", 1);
 787                 fdt_setprop(blob, off, "vidout_portcfg", cfg, sizeof(cfg));
 788                 printf("   set HDMI input mode to %s\n", mode);
 789         } else if (0 == strcasecmp(mode, "yuv422smp")) {
 790                 u8 cfg[] = { 0x00, 0x00, 0x00, 0x88, 0x87, 0x00,
 791                              0x82, 0x81, 0x00 };
 792                 mode = "422_smp";
 793                 fdt_setprop(blob, off, "vidout_fmt", mode, strlen(mode) + 1);
 794                 fdt_setprop_u32(blob, off, "vidout_trc", 0);
 795                 fdt_setprop_u32(blob, off, "vidout_blc", 0);
 796                 fdt_setprop(blob, off, "vidout_portcfg", cfg, sizeof(cfg));
 797                 printf("   set HDMI input mode to %s\n", mode);
 798         } else {
 799                 return -EINVAL;
 800         }
 801
 802         return 0;
 803 }
 804
 805 /* enable a property of a node if the node is found */
 806 static inline void ft_enable_path(void *blob, const char *path)
 807 {
 808         int i = fdt_path_offset(blob, path);
 809         if (i >= 0) {
 810                 debug("enabling %s\n", path);
 811                 fdt_status_okay(blob, i);
 812         }
 813 }
 814
 815 /* remove a property of a node if the node is found */
 816 static inline void ft_delprop_path(void *blob, const char *path,
 817                                    const char *name)
 818 {
 819         int i = fdt_path_offset(blob, path);
 820         if (i) {
 821                 debug("removing %s/%s\n", path, name);
 822                 fdt_delprop(blob, i, name);
 823         }
 824 }
 825
 826 #if defined(CONFIG_CMD_PCI)
 827 #define PCI_ID(x) ( \
 828         (PCI_BUS(x->devfn)<<16)| \
 829         (PCI_DEV(x->devfn)<<11)| \
 830         (PCI_FUNC(x->devfn)<<8) \
 831         )
 832 #define PCIE_PATH       "/soc/pcie@0x01000000"
 833 int fdt_add_pci_node(void *blob, int par, struct pci_dev *dev)
 834 {
 835         uint32_t reg[5];
 836         char node[32];
 837         int np;
 838
 839         sprintf(node, "pcie@%d,%d,%d", PCI_BUS(dev->devfn),
 840                 PCI_DEV(dev->devfn), PCI_FUNC(dev->devfn));
 841
 842         np = fdt_subnode_offset(blob, par, node);
 843         if (np >= 0)
 844                 return np;
 845         np = fdt_add_subnode(blob, par, node);
 846         if (np < 0) {
 847                 printf("   %s failed: no space\n", __func__);
 848                 return np;
 849         }
 850
 851         memset(reg, 0, sizeof(reg));
 852         reg[0] = cpu_to_fdt32(PCI_ID(dev));
 853         fdt_setprop(blob, np, "reg", reg, sizeof(reg));
 854
 855         return np;
 856 }
 857
 858 /* build a path of nested PCI devs for all bridges passed through */
 859 int fdt_add_pci_path(void *blob, struct pci_dev *dev)
 860 {
 861         struct pci_dev *bridges[MAX_PCI_DEVS];
 862         int k, np;
 863
 864         /* build list of parents */
 865         np = fdt_path_offset(blob, PCIE_PATH);
 866         if (np < 0)
 867                 return np;
 868
 869         k = 0;
 870         while (dev) {
 871                 bridges[k++] = dev;
 872                 dev = dev->ppar;
 873         };
 874
 875         /* now add them the to DT in reverse order */
 876         while (k--) {
 877                 np = fdt_add_pci_node(blob, np, bridges[k]);
 878                 if (np < 0)
 879                         break;
 880         }
 881
 882         return np;
 883 }
 884
 885 /*
 886  * The GW16082 has a hardware errata errata such that it's
 887  * INTA/B/C/D are mis-mapped to its four slots (slot12-15). Because
 888  * of this normal PCI interrupt swizzling will not work so we will
 889  * provide an irq-map via device-tree.
 890  */
 891 int fdt_fixup_gw16082(void *blob, int np, struct pci_dev *dev)
 892 {
 893         int len;
 894         int host;
 895         uint32_t imap_new[8*4*4];
 896         const uint32_t *imap;
 897         uint32_t irq[4];
 898         uint32_t reg[4];
 899         int i;
 900
 901         /* build irq-map based on host controllers map */
 902         host = fdt_path_offset(blob, PCIE_PATH);
 903         if (host < 0) {
 904                 printf("   %s failed: missing host\n", __func__);
 905                 return host;
 906         }
 907
 908         /* use interrupt data from root complex's node */
 909         imap = fdt_getprop(blob, host, "interrupt-map", &len);
 910         if (!imap || len != 128) {
 911                 printf("   %s failed: invalid interrupt-map\n",
 912                        __func__);
 913                 return -FDT_ERR_NOTFOUND;
 914         }
 915
 916         /* obtain irq's of host controller in pin order */
 917         for (i = 0; i < 4; i++)
 918                 irq[(fdt32_to_cpu(imap[(i*8)+3])-1)%4] = imap[(i*8)+6];
 919
 920         /*
 921          * determine number of swizzles necessary:
 922          *   For each bridge we pass through we need to swizzle
 923          *   the number of the slot we are on.
 924          */
 925         struct pci_dev *d;
 926         int b;
 927         b = 0;
 928         d = dev->ppar;
 929         while(d && d->ppar) {
 930                 b += PCI_DEV(d->devfn);
 931                 d = d->ppar;
 932         }
 933
 934         /* create new irq mappings for slots12-15
 935          * <skt> <idsel> <slot> <skt-inta> <skt-intb>
 936          * J3    AD28    12     INTD      INTA
 937          * J4    AD29    13     INTC      INTD
 938          * J5    AD30    14     INTB      INTC
 939          * J2    AD31    15     INTA      INTB
 940          */
 941         for (i = 0; i < 4; i++) {
 942                 /* addr matches bus:dev:func */
 943                 u32 addr = dev->busno << 16 | (12+i) << 11;
 944
 945                 /* default cells from root complex */
 946                 memcpy(&imap_new[i*32], imap, 128);
 947                 /* first cell is PCI device address (BDF) */
 948                 imap_new[(i*32)+(0*8)+0] = cpu_to_fdt32(addr);
 949                 imap_new[(i*32)+(1*8)+0] = cpu_to_fdt32(addr);
 950                 imap_new[(i*32)+(2*8)+0] = cpu_to_fdt32(addr);
 951                 imap_new[(i*32)+(3*8)+0] = cpu_to_fdt32(addr);
 952                 /* third cell is pin */
 953                 imap_new[(i*32)+(0*8)+3] = cpu_to_fdt32(1);
 954                 imap_new[(i*32)+(1*8)+3] = cpu_to_fdt32(2);
 955                 imap_new[(i*32)+(2*8)+3] = cpu_to_fdt32(3);
 956                 imap_new[(i*32)+(3*8)+3] = cpu_to_fdt32(4);
 957                 /* sixth cell is relative interrupt */
 958                 imap_new[(i*32)+(0*8)+6] = irq[(15-(12+i)+b+0)%4];
 959                 imap_new[(i*32)+(1*8)+6] = irq[(15-(12+i)+b+1)%4];
 960                 imap_new[(i*32)+(2*8)+6] = irq[(15-(12+i)+b+2)%4];
 961                 imap_new[(i*32)+(3*8)+6] = irq[(15-(12+i)+b+3)%4];
 962         }
 963         fdt_setprop(blob, np, "interrupt-map", imap_new,
 964                     sizeof(imap_new));
 965         reg[0] = cpu_to_fdt32(0xfff00);
 966         reg[1] = 0;
 967         reg[2] = 0;
 968         reg[3] = cpu_to_fdt32(0x7);
 969         fdt_setprop(blob, np, "interrupt-map-mask", reg, sizeof(reg));
 970         fdt_setprop_cell(blob, np, "#interrupt-cells", 1);
 971         fdt_setprop_string(blob, np, "device_type", "pci");
 972         fdt_setprop_cell(blob, np, "#address-cells", 3);
 973         fdt_setprop_cell(blob, np, "#size-cells", 2);
 974         printf("   Added custom interrupt-map for GW16082\n");
 975
 976         return 0;
 977 }
 978
 979 /* The sky2 GigE MAC obtains it's MAC addr from device-tree by default */
 980 int fdt_fixup_sky2(void *blob, int np, struct pci_dev *dev)
 981 {
 982         char *tmp, *end;
 983         char mac[16];
 984         unsigned char mac_addr[6];
 985         int j;
 986
 987         sprintf(mac, "eth1addr");
 988         tmp = getenv(mac);
 989         if (tmp) {
 990                 for (j = 0; j < 6; j++) {
 991                         mac_addr[j] = tmp ?
 992                                       simple_strtoul(tmp, &end,16) : 0;
 993                         if (tmp)
 994                                 tmp = (*end) ? end+1 : end;
 995                 }
 996                 fdt_setprop(blob, np, "local-mac-address", mac_addr,
 997                             sizeof(mac_addr));
 998                 printf("   Added mac addr for eth1\n");
 999                 return 0;
1000         }
1001
1002         return -1;
1003 }
1004
1005 /*
1006  * PCI DT nodes must be nested therefore if we need to apply a DT fixup
1007  * we will walk the PCI bus and add bridge nodes up to the device receiving
1008  * the fixup.
1009  */
1010 void ft_board_pci_fixup(void *blob, bd_t *bd)
1011 {
1012         int i, np;
1013         struct pci_dev *dev;
1014
1015         for (i = 0; i < pci_devno; i++) {
1016                 dev = &pci_devs[i];
1017
1018                 /*
1019                  * The GW16082 consists of a TI XIO2001 PCIe-to-PCI bridge and
1020                  * an EEPROM at i2c1-0x50.
1021                  */
1022                 if ((dev->vendor == PCI_VENDOR_ID_TI) &&
1023                     (dev->device == 0x8240) &&
1024                     (i2c_set_bus_num(1) == 0) &&
1025                     (i2c_probe(0x50) == 0))
1026                 {
1027                         np = fdt_add_pci_path(blob, dev);
1028                         if (np > 0)
1029                                 fdt_fixup_gw16082(blob, np, dev);
1030                 }
1031
1032                 /* ethernet1 mac address */
1033                 else if ((dev->vendor == PCI_VENDOR_ID_MARVELL) &&
1034                          (dev->device == 0x4380))
1035                 {
1036                         np = fdt_add_pci_path(blob, dev);
1037                         if (np > 0)
1038                                 fdt_fixup_sky2(blob, np, dev);
1039                 }
1040         }
1041 }
1042 #endif /* if defined(CONFIG_CMD_PCI) */
1043
1044 /*
1045  * called prior to booting kernel or by 'fdt boardsetup' command
1046  *
1047  * unless 'fdt_noauto' env var is set we will update the following in the DTB:
1048  *  - mtd partitions based on mtdparts/mtdids env
1049  *  - system-serial (board serial num from EEPROM)
1050  *  - board (full model from EEPROM)
1051  *  - peripherals removed from DTB if not loaded on board (per EEPROM config)
1052  */
1053 #define UART1_PATH      "/soc/aips-bus@02100000/serial@021ec000"
1054 #define WDOG1_PATH      "/soc/aips-bus@02000000/wdog@020bc000"
1055 #define WDOG2_PATH      "/soc/aips-bus@02000000/wdog@020c0000"
1056 #define GPIO3_PATH      "/soc/aips-bus@02000000/gpio@020a4000"
1057 int ft_board_setup(void *blob, bd_t *bd)
1058 {
1059         struct ventana_board_info *info = &ventana_info;
1060         struct ventana_eeprom_config *cfg;
1061         struct node_info nodes[] = {
1062                 { "sst,w25q256",          MTD_DEV_TYPE_NOR, },  /* SPI flash */
1063                 { "fsl,imx6q-gpmi-nand",  MTD_DEV_TYPE_NAND, }, /* NAND flash */
1064         };
1065         const char *model = getenv("model");
1066         const char *display = getenv("display");
1067         int i;
1068         char rev = 0;
1069
1070         /* determine board revision */
1071         for (i = sizeof(ventana_info.model) - 1; i > 0; i--) {
1072                 if (ventana_info.model[i] >= 'A') {
1073                         rev = ventana_info.model[i];
1074                         break;
1075                 }
1076         }
1077
1078         if (getenv("fdt_noauto")) {
1079                 puts("   Skiping ft_board_setup (fdt_noauto defined)\n");
1080                 return 0;
1081         }
1082
1083         if (test_bit(EECONFIG_NAND, info->config)) {
1084                 /* Update partition nodes using info from mtdparts env var */
1085                 puts("   Updating MTD partitions...\n");
1086                 fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
1087         }
1088
1089         /* Update display timings from display env var */
1090         if (display) {
1091                 if (fdt_fixup_display(blob, fdt_get_alias(blob, "lvds0"),
1092                                       display) >= 0)
1093                         printf("   Set display timings for %s...\n", display);
1094         }
1095
1096         printf("   Adjusting FDT per EEPROM for %s...\n", model);
1097
1098         /* board serial number */
1099         fdt_setprop(blob, 0, "system-serial", getenv("serial#"),
1100                     strlen(getenv("serial#")) + 1);
1101
1102         /* board (model contains model from device-tree) */
1103         fdt_setprop(blob, 0, "board", info->model,
1104                     strlen((const char *)info->model) + 1);
1105
1106         /* set desired digital video capture format */
1107         ft_sethdmiinfmt(blob, getenv("hdmiinfmt"));
1108
1109         /*
1110          * Board model specific fixups
1111          */
1112         switch (board_type) {
1113         case GW51xx:
1114                 /*
1115                  * disable wdog node for GW51xx-A/B to work around
1116                  * errata causing wdog timer to be unreliable.
1117                  */
1118                 if (rev >= 'A' && rev < 'C') {
1119                         i = fdt_path_offset(blob, WDOG1_PATH);
1120                         if (i)
1121                                 fdt_status_disabled(blob, i);
1122                 }
1123
1124                 /* GW51xx-E adds WDOG1_B external reset */
1125                 if (rev < 'E')
1126                         ft_delprop_path(blob, WDOG1_PATH,
1127                                         "fsl,ext-reset-output");
1128                 break;
1129
1130         case GW52xx:
1131                 /* GW522x Uses GPIO3_IO23 instead of GPIO1_IO29 */
1132                 if (info->model[4] == '2') {
1133                         u32 handle = 0;
1134                         u32 *range = NULL;
1135
1136                         i = fdt_node_offset_by_compatible(blob, -1,
1137                                                           "fsl,imx6q-pcie");
1138                         if (i)
1139                                 range = (u32 *)fdt_getprop(blob, i,
1140                                                            "reset-gpio", NULL);
1141
1142                         if (range) {
1143                                 i = fdt_path_offset(blob, GPIO3_PATH);
1144                                 if (i)
1145                                         handle = fdt_get_phandle(blob, i);
1146                                 if (handle) {
1147                                         range[0] = cpu_to_fdt32(handle);
1148                                         range[1] = cpu_to_fdt32(23);
1149                                 }
1150                         }
1151
1152                         /* these have broken usd_vsel */
1153                         if (strstr((const char *)info->model, "SP318-B") ||
1154                             strstr((const char *)info->model, "SP331-B"))
1155                                 gpio_cfg[board_type].usd_vsel = 0;
1156
1157                         /* GW520x-E adds WDOG1_B external reset */
1158                         if (info->model[4] == '0' && rev < 'E')
1159                                 ft_delprop_path(blob, WDOG1_PATH,
1160                                                 "fsl,ext-reset-output");
1161
1162                         /* GW522x-B adds WDOG1_B external reset */
1163                         if (info->model[4] == '2' && rev < 'B')
1164                                 ft_delprop_path(blob, WDOG1_PATH,
1165                                                 "fsl,ext-reset-output");
1166                 }
1167                 break;
1168
1169         case GW53xx:
1170                 /* GW53xx-E adds WDOG1_B external reset */
1171                 if (rev < 'E')
1172                         ft_delprop_path(blob, WDOG1_PATH,
1173                                         "fsl,ext-reset-output");
1174                 break;
1175
1176         case GW54xx:
1177                 /*
1178                  * disable serial2 node for GW54xx for compatibility with older
1179                  * 3.10.x kernel that improperly had this node enabled in the DT
1180                  */
1181                 i = fdt_path_offset(blob, UART1_PATH);
1182                 if (i)
1183                         fdt_del_node(blob, i);
1184
1185                 /* GW54xx-E adds WDOG2_B external reset */
1186                 if (rev < 'E')
1187                         ft_delprop_path(blob, WDOG2_PATH,
1188                                         "fsl,ext-reset-output");
1189                 break;
1190
1191         case GW551x:
1192                 /*
1193                  * isolate CSI0_DATA_EN for GW551x-A to work around errata
1194                  * causing non functional digital video in (it is not hooked up)
1195                  */
1196                 if (rev == 'A') {
1197                         u32 *range = NULL;
1198                         int len;
1199                         const u32 *handle = NULL;
1200
1201                         i = fdt_node_offset_by_compatible(blob, -1,
1202                                                 "fsl,imx-tda1997x-video");
1203                         if (i)
1204                                 handle = fdt_getprop(blob, i, "pinctrl-0",
1205                                                      NULL);
1206                         if (handle)
1207                                 i = fdt_node_offset_by_phandle(blob,
1208                                                         fdt32_to_cpu(*handle));
1209                         if (i)
1210                                 range = (u32 *)fdt_getprop(blob, i, "fsl,pins",
1211                                                            &len);
1212                         if (range) {
1213                                 len /= sizeof(u32);
1214                                 for (i = 0; i < len; i += 6) {
1215                                         u32 mux_reg = fdt32_to_cpu(range[i+0]);
1216                                         u32 conf_reg = fdt32_to_cpu(range[i+1]);
1217                                         /* mux PAD_CSI0_DATA_EN to GPIO */
1218                                         if (is_cpu_type(MXC_CPU_MX6Q) &&
1219                                             mux_reg == 0x260 &&
1220                                             conf_reg == 0x630)
1221                                                 range[i+3] = cpu_to_fdt32(0x5);
1222                                         else if (!is_cpu_type(MXC_CPU_MX6Q) &&
1223                                                  mux_reg == 0x08c &&
1224                                                  conf_reg == 0x3a0)
1225                                                 range[i+3] = cpu_to_fdt32(0x5);
1226                                 }
1227                                 fdt_setprop_inplace(blob, i, "fsl,pins", range,
1228                                                     len);
1229                         }
1230
1231                         /* set BT656 video format */
1232                         ft_sethdmiinfmt(blob, "yuv422bt656");
1233                 }
1234
1235                 /* GW551x-C adds WDOG1_B external reset */
1236                 if (rev < 'C')
1237                         ft_delprop_path(blob, WDOG1_PATH,
1238                                         "fsl,ext-reset-output");
1239                 break;
1240         }
1241
1242         /* Configure DIO */
1243         for (i = 0; i < gpio_cfg[board_type].dio_num; i++) {
1244                 struct dio_cfg *cfg = &gpio_cfg[board_type].dio_cfg[i];
1245                 char arg[10];
1246
1247                 sprintf(arg, "dio%d", i);
1248                 if (!hwconfig(arg))
1249                         continue;
1250                 if (hwconfig_subarg_cmp(arg, "mode", "pwm") && cfg->pwm_param)
1251                 {
1252                         char path[48];
1253                         sprintf(path, "/soc/aips-bus@02000000/pwm@%08x",
1254                                 0x02080000 + (0x4000 * (cfg->pwm_param - 1)));
1255                         printf("   Enabling pwm%d for DIO%d\n",
1256                                cfg->pwm_param, i);
1257                         ft_enable_path(blob, path);
1258                 }
1259         }
1260
1261         /* remove no-1-8-v if UHS-I support is present */
1262         if (gpio_cfg[board_type].usd_vsel) {
1263                 debug("Enabling UHS-I support\n");
1264                 ft_delprop_path(blob, "/soc/aips-bus@02100000/usdhc@02198000",
1265                                 "no-1-8-v");
1266         }
1267
1268 #if defined(CONFIG_CMD_PCI)
1269         if (!getenv("nopcifixup"))
1270                 ft_board_pci_fixup(blob, bd);
1271 #endif
1272
1273         /*
1274          * Peripheral Config:
1275          *  remove nodes by alias path if EEPROM config tells us the
1276          *  peripheral is not loaded on the board.
1277          */
1278         if (getenv("fdt_noconfig")) {
1279                 puts("   Skiping periperhal config (fdt_noconfig defined)\n");
1280                 return 0;
1281         }
1282         cfg = econfig;
1283         while (cfg->name) {
1284                 if (!test_bit(cfg->bit, info->config)) {
1285                         fdt_del_node_and_alias(blob, cfg->dtalias ?
1286                                                cfg->dtalias : cfg->name);
1287                 }
1288                 cfg++;
1289         }
1290
1291         return 0;
1292 }
1293 #endif /* CONFIG_OF_BOARD_SETUP */
1294
1295 static struct mxc_serial_platdata ventana_mxc_serial_plat = {
1296         .reg = (struct mxc_uart *)UART2_BASE,
1297 };
1298
1299 U_BOOT_DEVICE(ventana_serial) = {
1300         .name   = "serial_mxc",
1301         .platdata = &ventana_mxc_serial_plat,
1302 };