board/gateworks/gw_ventana/gw_ventana.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2013 Gateworks Corporation
   4  *
   5  * Author: Tim Harvey <tharvey@gateworks.com>
   6  */
   7
   8 #include <common.h>
   9 #include <asm/arch/clock.h>
  10 #include <asm/arch/crm_regs.h>
  11 #include <asm/arch/iomux.h>
  12 #include <asm/arch/mx6-pins.h>
  13 #include <asm/arch/mxc_hdmi.h>
  14 #include <asm/arch/sys_proto.h>
  15 #include <asm/gpio.h>
  16 #include <asm/mach-imx/boot_mode.h>
  17 #include <asm/mach-imx/sata.h>
  18 #include <asm/mach-imx/spi.h>
  19 #include <asm/mach-imx/video.h>
  20 #include <asm/io.h>
  21 #include <asm/setup.h>
  22 #include <dm.h>
  23 #include <dm/platform_data/serial_mxc.h>
  24 #include <environment.h>
  25 #include <hwconfig.h>
  26 #include <i2c.h>
  27 #include <fdt_support.h>
  28 #include <fsl_esdhc.h>
  29 #include <jffs2/load_kernel.h>
  30 #include <linux/ctype.h>
  31 #include <miiphy.h>
  32 #include <mtd_node.h>
  33 #include <netdev.h>
  34 #include <pci.h>
  35 #include <power/pmic.h>
  36 #include <power/ltc3676_pmic.h>
  37 #include <power/pfuze100_pmic.h>
  38 #include <fdt_support.h>
  39 #include <jffs2/load_kernel.h>
  40 #include <spi_flash.h>
  41
  42 #include "gsc.h"
  43 #include "common.h"
  44
  45 DECLARE_GLOBAL_DATA_PTR;
  46
  47
  48 /*
  49  * EEPROM board info struct populated by read_eeprom so that we only have to
  50  * read it once.
  51  */
  52 struct ventana_board_info ventana_info;
  53
  54 static int board_type;
  55
  56 /* ENET */
  57 static iomux_v3_cfg_t const enet_pads[] = {
  58         IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  59         IOMUX_PADS(PAD_ENET_MDC__ENET_MDC    | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  60         IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  61         IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  62         IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  63         IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  64         IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  65         IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL |
  66                    MUX_PAD_CTRL(ENET_PAD_CTRL)),
  67         IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK |
  68                    MUX_PAD_CTRL(ENET_PAD_CTRL)),
  69         IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  70         IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  71         IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  72         IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  73         IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  74         IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL |
  75                    MUX_PAD_CTRL(ENET_PAD_CTRL)),
  76         /* PHY nRST */
  77         IOMUX_PADS(PAD_ENET_TXD0__GPIO1_IO30 | DIO_PAD_CFG),
  78 };
  79
  80 #ifdef CONFIG_CMD_NAND
  81 static iomux_v3_cfg_t const nfc_pads[] = {
  82         IOMUX_PADS(PAD_NANDF_CLE__NAND_CLE     | MUX_PAD_CTRL(NO_PAD_CTRL)),
  83         IOMUX_PADS(PAD_NANDF_ALE__NAND_ALE     | MUX_PAD_CTRL(NO_PAD_CTRL)),
  84         IOMUX_PADS(PAD_NANDF_WP_B__NAND_WP_B   | MUX_PAD_CTRL(NO_PAD_CTRL)),
  85         IOMUX_PADS(PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
  86         IOMUX_PADS(PAD_NANDF_CS0__NAND_CE0_B   | MUX_PAD_CTRL(NO_PAD_CTRL)),
  87         IOMUX_PADS(PAD_SD4_CMD__NAND_RE_B      | MUX_PAD_CTRL(NO_PAD_CTRL)),
  88         IOMUX_PADS(PAD_SD4_CLK__NAND_WE_B      | MUX_PAD_CTRL(NO_PAD_CTRL)),
  89         IOMUX_PADS(PAD_NANDF_D0__NAND_DATA00   | MUX_PAD_CTRL(NO_PAD_CTRL)),
  90         IOMUX_PADS(PAD_NANDF_D1__NAND_DATA01   | MUX_PAD_CTRL(NO_PAD_CTRL)),
  91         IOMUX_PADS(PAD_NANDF_D2__NAND_DATA02   | MUX_PAD_CTRL(NO_PAD_CTRL)),
  92         IOMUX_PADS(PAD_NANDF_D3__NAND_DATA03   | MUX_PAD_CTRL(NO_PAD_CTRL)),
  93         IOMUX_PADS(PAD_NANDF_D4__NAND_DATA04   | MUX_PAD_CTRL(NO_PAD_CTRL)),
  94         IOMUX_PADS(PAD_NANDF_D5__NAND_DATA05   | MUX_PAD_CTRL(NO_PAD_CTRL)),
  95         IOMUX_PADS(PAD_NANDF_D6__NAND_DATA06   | MUX_PAD_CTRL(NO_PAD_CTRL)),
  96         IOMUX_PADS(PAD_NANDF_D7__NAND_DATA07   | MUX_PAD_CTRL(NO_PAD_CTRL)),
  97 };
  98
  99 static void setup_gpmi_nand(void)
 100 {
 101         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 102
 103         /* config gpmi nand iomux */
 104         SETUP_IOMUX_PADS(nfc_pads);
 105
 106         /* config gpmi and bch clock to 100 MHz */
 107         clrsetbits_le32(&mxc_ccm->cs2cdr,
 108                         MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
 109                         MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
 110                         MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
 111                         MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
 112                         MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
 113                         MXC_CCM_CS2CDR_ENFC_CLK_SEL(3));
 114
 115         /* enable gpmi and bch clock gating */
 116         setbits_le32(&mxc_ccm->CCGR4,
 117                      MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
 118                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
 119                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
 120                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
 121                      MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET);
 122
 123         /* enable apbh clock gating */
 124         setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
 125 }
 126 #endif
 127
 128 static void setup_iomux_enet(int gpio)
 129 {
 130         SETUP_IOMUX_PADS(enet_pads);
 131
 132         /* toggle PHY_RST# */
 133         gpio_request(gpio, "phy_rst#");
 134         gpio_direction_output(gpio, 0);
 135         mdelay(10);
 136         gpio_set_value(gpio, 1);
 137         mdelay(100);
 138 }
 139
 140 #ifdef CONFIG_USB_EHCI_MX6
 141 static iomux_v3_cfg_t const usb_pads[] = {
 142         IOMUX_PADS(PAD_GPIO_1__USB_OTG_ID   | DIO_PAD_CFG),
 143         IOMUX_PADS(PAD_KEY_COL4__USB_OTG_OC | DIO_PAD_CFG),
 144         /* OTG PWR */
 145         IOMUX_PADS(PAD_EIM_D22__GPIO3_IO22  | DIO_PAD_CFG),
 146 };
 147
 148 int board_ehci_hcd_init(int port)
 149 {
 150         int gpio;
 151
 152         SETUP_IOMUX_PADS(usb_pads);
 153
 154         /* Reset USB HUB */
 155         switch (board_type) {
 156         case GW53xx:
 157         case GW552x:
 158                 gpio = (IMX_GPIO_NR(1, 9));
 159                 break;
 160         case GW54proto:
 161         case GW54xx:
 162                 gpio = (IMX_GPIO_NR(1, 16));
 163                 break;
 164         default:
 165                 return 0;
 166         }
 167
 168         /* request and toggle hub rst */
 169         gpio_request(gpio, "usb_hub_rst#");
 170         gpio_direction_output(gpio, 0);
 171         mdelay(2);
 172         gpio_set_value(gpio, 1);
 173
 174         return 0;
 175 }
 176
 177 int board_ehci_power(int port, int on)
 178 {
 179         /* enable OTG VBUS */
 180         if (!port && board_type < GW_UNKNOWN) {
 181                 if (gpio_cfg[board_type].otgpwr_en)
 182                         gpio_set_value(gpio_cfg[board_type].otgpwr_en, on);
 183         }
 184         return 0;
 185 }
 186 #endif /* CONFIG_USB_EHCI_MX6 */
 187
 188 #ifdef CONFIG_MXC_SPI
 189 iomux_v3_cfg_t const ecspi1_pads[] = {
 190         /* SS1 */
 191         IOMUX_PADS(PAD_EIM_D19__GPIO3_IO19  | MUX_PAD_CTRL(SPI_PAD_CTRL)),
 192         IOMUX_PADS(PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL)),
 193         IOMUX_PADS(PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL)),
 194         IOMUX_PADS(PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL)),
 195 };
 196
 197 int board_spi_cs_gpio(unsigned bus, unsigned cs)
 198 {
 199         return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(3, 19)) : -1;
 200 }
 201
 202 static void setup_spi(void)
 203 {
 204         gpio_request(IMX_GPIO_NR(3, 19), "spi_cs");
 205         gpio_direction_output(IMX_GPIO_NR(3, 19), 1);
 206         SETUP_IOMUX_PADS(ecspi1_pads);
 207 }
 208 #endif
 209
 210 /* configure eth0 PHY board-specific LED behavior */
 211 int board_phy_config(struct phy_device *phydev)
 212 {
 213         unsigned short val;
 214
 215         /* Marvel 88E1510 */
 216         if (phydev->phy_id == 0x1410dd1) {
 217                 /*
 218                  * Page 3, Register 16: LED[2:0] Function Control Register
 219                  * LED[0] (SPD:Amber) R16_3.3:0 to 0111: on-GbE link
 220                  * LED[1] (LNK:Green) R16_3.7:4 to 0001: on-link, blink-activity
 221                  */
 222                 phy_write(phydev, MDIO_DEVAD_NONE, 22, 3);
 223                 val = phy_read(phydev, MDIO_DEVAD_NONE, 16);
 224                 val &= 0xff00;
 225                 val |= 0x0017;
 226                 phy_write(phydev, MDIO_DEVAD_NONE, 16, val);
 227                 phy_write(phydev, MDIO_DEVAD_NONE, 22, 0);
 228         }
 229
 230         /* TI DP83867 */
 231         else if (phydev->phy_id == 0x2000a231) {
 232                 /* configure register 0x170 for ref CLKOUT */
 233                 phy_write(phydev, MDIO_DEVAD_NONE, 13, 0x001f);
 234                 phy_write(phydev, MDIO_DEVAD_NONE, 14, 0x0170);
 235                 phy_write(phydev, MDIO_DEVAD_NONE, 13, 0x401f);
 236                 val = phy_read(phydev, MDIO_DEVAD_NONE, 14);
 237                 val &= ~0x1f00;
 238                 val |= 0x0b00; /* chD tx clock*/
 239                 phy_write(phydev, MDIO_DEVAD_NONE, 14, val);
 240         }
 241
 242         if (phydev->drv->config)
 243                 phydev->drv->config(phydev);
 244
 245         return 0;
 246 }
 247
 248 #ifdef CONFIG_MV88E61XX_SWITCH
 249 int mv88e61xx_hw_reset(struct phy_device *phydev)
 250 {
 251         struct mii_dev *bus = phydev->bus;
 252
 253         /* GPIO[0] output, CLK125 */
 254         debug("enabling RGMII_REFCLK\n");
 255         bus->write(bus, 0x1c /*MV_GLOBAL2*/, 0,
 256                    0x1a /*MV_SCRATCH_MISC*/,
 257                    (1 << 15) | (0x62 /*MV_GPIO_DIR*/ << 8) | 0xfe);
 258         bus->write(bus, 0x1c /*MV_GLOBAL2*/, 0,
 259                    0x1a /*MV_SCRATCH_MISC*/,
 260                    (1 << 15) | (0x68 /*MV_GPIO01_CNTL*/ << 8) | 7);
 261
 262         /* RGMII delay - Physical Control register bit[15:14] */
 263         debug("setting port%d RGMII rx/tx delay\n", CONFIG_MV88E61XX_CPU_PORT);
 264         /* forced 1000mbps full-duplex link */
 265         bus->write(bus, 0x10 + CONFIG_MV88E61XX_CPU_PORT, 0, 1, 0xc0fe);
 266         phydev->autoneg = AUTONEG_DISABLE;
 267         phydev->speed = SPEED_1000;
 268         phydev->duplex = DUPLEX_FULL;
 269
 270         /* LED configuration: 7:4-green (8=Activity)  3:0 amber (8=Link) */
 271         bus->write(bus, 0x10, 0, 0x16, 0x8088);
 272         bus->write(bus, 0x11, 0, 0x16, 0x8088);
 273         bus->write(bus, 0x12, 0, 0x16, 0x8088);
 274         bus->write(bus, 0x13, 0, 0x16, 0x8088);
 275
 276         return 0;
 277 }
 278 #endif // CONFIG_MV88E61XX_SWITCH
 279
 280 int board_eth_init(bd_t *bis)
 281 {
 282 #ifdef CONFIG_FEC_MXC
 283         struct ventana_board_info *info = &ventana_info;
 284
 285         if (test_bit(EECONFIG_ETH0, info->config)) {
 286                 setup_iomux_enet(GP_PHY_RST);
 287                 cpu_eth_init(bis);
 288         }
 289 #endif
 290
 291 #ifdef CONFIG_E1000
 292         e1000_initialize(bis);
 293 #endif
 294
 295 #ifdef CONFIG_CI_UDC
 296         /* For otg ethernet*/
 297         usb_eth_initialize(bis);
 298 #endif
 299
 300         /* default to the first detected enet dev */
 301         if (!env_get("ethprime")) {
 302                 struct eth_device *dev = eth_get_dev_by_index(0);
 303                 if (dev) {
 304                         env_set("ethprime", dev->name);
 305                         printf("set ethprime to %s\n", env_get("ethprime"));
 306                 }
 307         }
 308
 309         return 0;
 310 }
 311
 312 #if defined(CONFIG_VIDEO_IPUV3)
 313
 314 static void enable_hdmi(struct display_info_t const *dev)
 315 {
 316         imx_enable_hdmi_phy();
 317 }
 318
 319 static int detect_i2c(struct display_info_t const *dev)
 320 {
 321         return i2c_set_bus_num(dev->bus) == 0 &&
 322                 i2c_probe(dev->addr) == 0;
 323 }
 324
 325 static void enable_lvds(struct display_info_t const *dev)
 326 {
 327         struct iomuxc *iomux = (struct iomuxc *)
 328                                 IOMUXC_BASE_ADDR;
 329
 330         /* set CH0 data width to 24bit (IOMUXC_GPR2:5 0=18bit, 1=24bit) */
 331         u32 reg = readl(&iomux->gpr[2]);
 332         reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT;
 333         writel(reg, &iomux->gpr[2]);
 334
 335         /* Enable Backlight */
 336         gpio_request(IMX_GPIO_NR(1, 10), "bklt_gpio");
 337         gpio_direction_output(IMX_GPIO_NR(1, 10), 0);
 338         gpio_request(IMX_GPIO_NR(1, 18), "bklt_en");
 339         SETUP_IOMUX_PAD(PAD_SD1_CMD__GPIO1_IO18 | DIO_PAD_CFG);
 340         gpio_direction_output(IMX_GPIO_NR(1, 18), 1);
 341 }
 342
 343 struct display_info_t const displays[] = {{
 344         /* HDMI Output */
 345         .bus    = -1,
 346         .addr   = 0,
 347         .pixfmt = IPU_PIX_FMT_RGB24,
 348         .detect = detect_hdmi,
 349         .enable = enable_hdmi,
 350         .mode   = {
 351                 .name           = "HDMI",
 352                 .refresh        = 60,
 353                 .xres           = 1024,
 354                 .yres           = 768,
 355                 .pixclock       = 15385,
 356                 .left_margin    = 220,
 357                 .right_margin   = 40,
 358                 .upper_margin   = 21,
 359                 .lower_margin   = 7,
 360                 .hsync_len      = 60,
 361                 .vsync_len      = 10,
 362                 .sync           = FB_SYNC_EXT,
 363                 .vmode          = FB_VMODE_NONINTERLACED
 364 } }, {
 365         /* Freescale MXC-LVDS1: HannStar HSD100PXN1-A00 w/ egalx_ts cont */
 366         .bus    = 2,
 367         .addr   = 0x4,
 368         .pixfmt = IPU_PIX_FMT_LVDS666,
 369         .detect = detect_i2c,
 370         .enable = enable_lvds,
 371         .mode   = {
 372                 .name           = "Hannstar-XGA",
 373                 .refresh        = 60,
 374                 .xres           = 1024,
 375                 .yres           = 768,
 376                 .pixclock       = 15385,
 377                 .left_margin    = 220,
 378                 .right_margin   = 40,
 379                 .upper_margin   = 21,
 380                 .lower_margin   = 7,
 381                 .hsync_len      = 60,
 382                 .vsync_len      = 10,
 383                 .sync           = FB_SYNC_EXT,
 384                 .vmode          = FB_VMODE_NONINTERLACED
 385 } }, {
 386         /* DLC700JMG-T-4 */
 387         .bus    = 0,
 388         .addr   = 0,
 389         .detect = NULL,
 390         .enable = enable_lvds,
 391         .pixfmt = IPU_PIX_FMT_LVDS666,
 392         .mode   = {
 393                 .name           = "DLC700JMGT4",
 394                 .refresh        = 60,
 395                 .xres           = 1024,         /* 1024x600active pixels */
 396                 .yres           = 600,
 397                 .pixclock       = 15385,        /* 64MHz */
 398                 .left_margin    = 220,
 399                 .right_margin   = 40,
 400                 .upper_margin   = 21,
 401                 .lower_margin   = 7,
 402                 .hsync_len      = 60,
 403                 .vsync_len      = 10,
 404                 .sync           = FB_SYNC_EXT,
 405                 .vmode          = FB_VMODE_NONINTERLACED
 406 } }, {
 407         /* DLC800FIG-T-3 */
 408         .bus    = 0,
 409         .addr   = 0,
 410         .detect = NULL,
 411         .enable = enable_lvds,
 412         .pixfmt = IPU_PIX_FMT_LVDS666,
 413         .mode   = {
 414                 .name           = "DLC800FIGT3",
 415                 .refresh        = 60,
 416                 .xres           = 1024,         /* 1024x768 active pixels */
 417                 .yres           = 768,
 418                 .pixclock       = 15385,        /* 64MHz */
 419                 .left_margin    = 220,
 420                 .right_margin   = 40,
 421                 .upper_margin   = 21,
 422                 .lower_margin   = 7,
 423                 .hsync_len      = 60,
 424                 .vsync_len      = 10,
 425                 .sync           = FB_SYNC_EXT,
 426                 .vmode          = FB_VMODE_NONINTERLACED
 427 } } };
 428 size_t display_count = ARRAY_SIZE(displays);
 429
 430 static void setup_display(void)
 431 {
 432         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 433         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 434         int reg;
 435
 436         enable_ipu_clock();
 437         imx_setup_hdmi();
 438         /* Turn on LDB0,IPU,IPU DI0 clocks */
 439         reg = __raw_readl(&mxc_ccm->CCGR3);
 440         reg |= MXC_CCM_CCGR3_LDB_DI0_MASK;
 441         writel(reg, &mxc_ccm->CCGR3);
 442
 443         /* set LDB0, LDB1 clk select to 011/011 */
 444         reg = readl(&mxc_ccm->cs2cdr);
 445         reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
 446                  |MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
 447         reg |= (3<<MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
 448               |(3<<MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
 449         writel(reg, &mxc_ccm->cs2cdr);
 450
 451         reg = readl(&mxc_ccm->cscmr2);
 452         reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
 453         writel(reg, &mxc_ccm->cscmr2);
 454
 455         reg = readl(&mxc_ccm->chsccdr);
 456         reg |= (CHSCCDR_CLK_SEL_LDB_DI0
 457                 <<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
 458         writel(reg, &mxc_ccm->chsccdr);
 459
 460         reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
 461              |IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
 462              |IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
 463              |IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
 464              |IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
 465              |IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
 466              |IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
 467              |IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
 468              |IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
 469         writel(reg, &iomux->gpr[2]);
 470
 471         reg = readl(&iomux->gpr[3]);
 472         reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK)
 473             | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
 474                <<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
 475         writel(reg, &iomux->gpr[3]);
 476
 477         /* LVDS Backlight GPIO on LVDS connector - output low */
 478         SETUP_IOMUX_PAD(PAD_SD2_CLK__GPIO1_IO10 | DIO_PAD_CFG);
 479         gpio_direction_output(IMX_GPIO_NR(1, 10), 0);
 480 }
 481 #endif /* CONFIG_VIDEO_IPUV3 */
 482
 483 /* setup board specific PMIC */
 484 int power_init_board(void)
 485 {
 486         setup_pmic();
 487         return 0;
 488 }
 489
 490 #if defined(CONFIG_CMD_PCI)
 491 int imx6_pcie_toggle_reset(void)
 492 {
 493         if (board_type < GW_UNKNOWN) {
 494                 uint pin = gpio_cfg[board_type].pcie_rst;
 495                 gpio_request(pin, "pci_rst#");
 496                 gpio_direction_output(pin, 0);
 497                 mdelay(50);
 498                 gpio_direction_output(pin, 1);
 499         }
 500         return 0;
 501 }
 502
 503 /*
 504  * Most Ventana boards have a PLX PEX860x PCIe switch onboard and use its
 505  * GPIO's as PERST# signals for its downstream ports - configure the GPIO's
 506  * properly and assert reset for 100ms.
 507  */
 508 #define MAX_PCI_DEVS    32
 509 struct pci_dev {
 510         pci_dev_t devfn;
 511         unsigned short vendor;
 512         unsigned short device;
 513         unsigned short class;
 514         unsigned short busno; /* subbordinate busno */
 515         struct pci_dev *ppar;
 516 };
 517 struct pci_dev pci_devs[MAX_PCI_DEVS];
 518 int pci_devno;
 519 int pci_bridgeno;
 520
 521 void board_pci_fixup_dev(struct pci_controller *hose, pci_dev_t dev,
 522                          unsigned short vendor, unsigned short device,
 523                          unsigned short class)
 524 {
 525         int i;
 526         u32 dw;
 527         struct pci_dev *pdev = &pci_devs[pci_devno++];
 528
 529         debug("%s: %02d:%02d.%02d: %04x:%04x\n", __func__,
 530               PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev), vendor, device);
 531
 532         /* store array of devs for later use in device-tree fixup */
 533         pdev->devfn = dev;
 534         pdev->vendor = vendor;
 535         pdev->device = device;
 536         pdev->class = class;
 537         pdev->ppar = NULL;
 538         if (class == PCI_CLASS_BRIDGE_PCI)
 539                 pdev->busno = ++pci_bridgeno;
 540         else
 541                 pdev->busno = 0;
 542
 543         /* fixup RC - it should be 00:00.0 not 00:01.0 */
 544         if (PCI_BUS(dev) == 0)
 545                 pdev->devfn = 0;
 546
 547         /* find dev's parent */
 548         for (i = 0; i < pci_devno; i++) {
 549                 if (pci_devs[i].busno == PCI_BUS(pdev->devfn)) {
 550                         pdev->ppar = &pci_devs[i];
 551                         break;
 552                 }
 553         }
 554
 555         /* assert downstream PERST# */
 556         if (vendor == PCI_VENDOR_ID_PLX &&
 557             (device & 0xfff0) == 0x8600 &&
 558             PCI_DEV(dev) == 0 && PCI_FUNC(dev) == 0) {
 559                 debug("configuring PLX 860X downstream PERST#\n");
 560                 pci_hose_read_config_dword(hose, dev, 0x62c, &dw);
 561                 dw |= 0xaaa8; /* GPIO1-7 outputs */
 562                 pci_hose_write_config_dword(hose, dev, 0x62c, dw);
 563
 564                 pci_hose_read_config_dword(hose, dev, 0x644, &dw);
 565                 dw |= 0xfe;   /* GPIO1-7 output high */
 566                 pci_hose_write_config_dword(hose, dev, 0x644, dw);
 567
 568                 mdelay(100);
 569         }
 570 }
 571 #endif /* CONFIG_CMD_PCI */
 572
 573 #ifdef CONFIG_SERIAL_TAG
 574 /*
 575  * called when setting up ATAGS before booting kernel
 576  * populate serialnum from the following (in order of priority):
 577  *   serial# env var
 578  *   eeprom
 579  */
 580 void get_board_serial(struct tag_serialnr *serialnr)
 581 {
 582         char *serial = env_get("serial#");
 583
 584         if (serial) {
 585                 serialnr->high = 0;
 586                 serialnr->low = simple_strtoul(serial, NULL, 10);
 587         } else if (ventana_info.model[0]) {
 588                 serialnr->high = 0;
 589                 serialnr->low = ventana_info.serial;
 590         } else {
 591                 serialnr->high = 0;
 592                 serialnr->low = 0;
 593         }
 594 }
 595 #endif
 596
 597 /*
 598  * Board Support
 599  */
 600
 601 int board_early_init_f(void)
 602 {
 603         setup_iomux_uart();
 604
 605 #if defined(CONFIG_VIDEO_IPUV3)
 606         setup_display();
 607 #endif
 608         return 0;
 609 }
 610
 611 int dram_init(void)
 612 {
 613         gd->ram_size = imx_ddr_size();
 614         return 0;
 615 }
 616
 617 int board_init(void)
 618 {
 619         struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
 620
 621         clrsetbits_le32(&iomuxc_regs->gpr[1],
 622                         IOMUXC_GPR1_OTG_ID_MASK,
 623                         IOMUXC_GPR1_OTG_ID_GPIO1);
 624
 625         /* address of linux boot parameters */
 626         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 627
 628 #ifdef CONFIG_CMD_NAND
 629         setup_gpmi_nand();
 630 #endif
 631 #ifdef CONFIG_MXC_SPI
 632         setup_spi();
 633 #endif
 634         setup_ventana_i2c(0);
 635         setup_ventana_i2c(1);
 636         setup_ventana_i2c(2);
 637
 638 #ifdef CONFIG_SATA
 639         setup_sata();
 640 #endif
 641         /* read Gateworks EEPROM into global struct (used later) */
 642         board_type = read_eeprom(CONFIG_I2C_GSC, &ventana_info);
 643
 644         setup_iomux_gpio(board_type, &ventana_info);
 645
 646         return 0;
 647 }
 648
 649 #if defined(CONFIG_DISPLAY_BOARDINFO_LATE)
 650 /*
 651  * called during late init (after relocation and after board_init())
 652  * by virtue of CONFIG_DISPLAY_BOARDINFO_LATE as we needed i2c initialized and
 653  * EEPROM read.
 654  */
 655 int checkboard(void)
 656 {
 657         struct ventana_board_info *info = &ventana_info;
 658         unsigned char buf[4];
 659         const char *p;
 660         int quiet; /* Quiet or minimal output mode */
 661
 662         quiet = 0;
 663         p = env_get("quiet");
 664         if (p)
 665                 quiet = simple_strtol(p, NULL, 10);
 666         else
 667                 env_set("quiet", "0");
 668
 669         puts("\nGateworks Corporation Copyright 2014\n");
 670         if (info->model[0]) {
 671                 printf("Model: %s\n", info->model);
 672                 printf("MFGDate: %02x-%02x-%02x%02x\n",
 673                        info->mfgdate[0], info->mfgdate[1],
 674                        info->mfgdate[2], info->mfgdate[3]);
 675                 printf("Serial:%d\n", info->serial);
 676         } else {
 677                 puts("Invalid EEPROM - board will not function fully\n");
 678         }
 679         if (quiet)
 680                 return 0;
 681
 682         /* Display GSC firmware revision/CRC/status */
 683         gsc_info(0);
 684
 685         /* Display RTC */
 686         if (!gsc_i2c_read(GSC_RTC_ADDR, 0x00, 1, buf, 4)) {
 687                 printf("RTC:   %d\n",
 688                        buf[0] | buf[1]<<8 | buf[2]<<16 | buf[3]<<24);
 689         }
 690
 691         return 0;
 692 }
 693 #endif
 694
 695 #ifdef CONFIG_CMD_BMODE
 696 /*
 697  * BOOT_CFG1, BOOT_CFG2, BOOT_CFG3, BOOT_CFG4
 698  * see Table 8-11 and Table 5-9
 699  *  BOOT_CFG1[7] = 1 (boot from NAND)
 700  *  BOOT_CFG1[5] = 0 - raw NAND
 701  *  BOOT_CFG1[4] = 0 - default pad settings
 702  *  BOOT_CFG1[3:2] = 00 - devices = 1
 703  *  BOOT_CFG1[1:0] = 00 - Row Address Cycles = 3
 704  *  BOOT_CFG2[4:3] = 00 - Boot Search Count = 2
 705  *  BOOT_CFG2[2:1] = 01 - Pages In Block = 64
 706  *  BOOT_CFG2[0] = 0 - Reset time 12ms
 707  */
 708 static const struct boot_mode board_boot_modes[] = {
 709         /* NAND: 64pages per block, 3 row addr cycles, 2 copies of FCB/DBBT */
 710         { "nand", MAKE_CFGVAL(0x80, 0x02, 0x00, 0x00) },
 711         { "emmc2", MAKE_CFGVAL(0x60, 0x48, 0x00, 0x00) }, /* GW5600 */
 712         { "emmc3", MAKE_CFGVAL(0x60, 0x50, 0x00, 0x00) }, /* GW5903/GW5904 */
 713         { NULL, 0 },
 714 };
 715 #endif
 716
 717 /* late init */
 718 int misc_init_r(void)
 719 {
 720         struct ventana_board_info *info = &ventana_info;
 721         char buf[256];
 722         int i;
 723
 724         /* set env vars based on EEPROM data */
 725         if (ventana_info.model[0]) {
 726                 char str[16], fdt[36];
 727                 char *p;
 728                 const char *cputype = "";
 729
 730                 /*
 731                  * FDT name will be prefixed with CPU type.  Three versions
 732                  * will be created each increasingly generic and bootloader
 733                  * env scripts will try loading each from most specific to
 734                  * least.
 735                  */
 736                 if (is_cpu_type(MXC_CPU_MX6Q) ||
 737                     is_cpu_type(MXC_CPU_MX6D))
 738                         cputype = "imx6q";
 739                 else if (is_cpu_type(MXC_CPU_MX6DL) ||
 740                          is_cpu_type(MXC_CPU_MX6SOLO))
 741                         cputype = "imx6dl";
 742                 env_set("soctype", cputype);
 743                 if (8 << (ventana_info.nand_flash_size-1) >= 2048)
 744                         env_set("flash_layout", "large");
 745                 else
 746                         env_set("flash_layout", "normal");
 747                 memset(str, 0, sizeof(str));
 748                 for (i = 0; i < (sizeof(str)-1) && info->model[i]; i++)
 749                         str[i] = tolower(info->model[i]);
 750                 env_set("model", str);
 751                 if (!env_get("fdt_file")) {
 752                         sprintf(fdt, "%s-%s.dtb", cputype, str);
 753                         env_set("fdt_file", fdt);
 754                 }
 755                 p = strchr(str, '-');
 756                 if (p) {
 757                         *p++ = 0;
 758
 759                         env_set("model_base", str);
 760                         sprintf(fdt, "%s-%s.dtb", cputype, str);
 761                         env_set("fdt_file1", fdt);
 762                         if (board_type != GW551x &&
 763                             board_type != GW552x &&
 764                             board_type != GW553x &&
 765                             board_type != GW560x)
 766                                 str[4] = 'x';
 767                         str[5] = 'x';
 768                         str[6] = 0;
 769                         sprintf(fdt, "%s-%s.dtb", cputype, str);
 770                         env_set("fdt_file2", fdt);
 771                 }
 772
 773                 /* initialize env from EEPROM */
 774                 if (test_bit(EECONFIG_ETH0, info->config) &&
 775                     !env_get("ethaddr")) {
 776                         eth_env_set_enetaddr("ethaddr", info->mac0);
 777                 }
 778                 if (test_bit(EECONFIG_ETH1, info->config) &&
 779                     !env_get("eth1addr")) {
 780                         eth_env_set_enetaddr("eth1addr", info->mac1);
 781                 }
 782
 783                 /* board serial-number */
 784                 sprintf(str, "%6d", info->serial);
 785                 env_set("serial#", str);
 786
 787                 /* memory MB */
 788                 sprintf(str, "%d", (int) (gd->ram_size >> 20));
 789                 env_set("mem_mb", str);
 790         }
 791
 792         /* Set a non-initialized hwconfig based on board configuration */
 793         if (!strcmp(env_get("hwconfig"), "_UNKNOWN_")) {
 794                 buf[0] = 0;
 795                 if (gpio_cfg[board_type].rs232_en)
 796                         strcat(buf, "rs232;");
 797                 for (i = 0; i < gpio_cfg[board_type].dio_num; i++) {
 798                         char buf1[32];
 799                         sprintf(buf1, "dio%d:mode=gpio;", i);
 800                         if (strlen(buf) + strlen(buf1) < sizeof(buf))
 801                                 strcat(buf, buf1);
 802                 }
 803                 env_set("hwconfig", buf);
 804         }
 805
 806         /* setup baseboard specific GPIO based on board and env */
 807         setup_board_gpio(board_type, info);
 808
 809 #ifdef CONFIG_CMD_BMODE
 810         add_board_boot_modes(board_boot_modes);
 811 #endif
 812
 813         /* disable boot watchdog */
 814         gsc_boot_wd_disable();
 815
 816         return 0;
 817 }
 818
 819 #ifdef CONFIG_OF_BOARD_SETUP
 820
 821 static int ft_sethdmiinfmt(void *blob, char *mode)
 822 {
 823         int off;
 824
 825         if (!mode)
 826                 return -EINVAL;
 827
 828         off = fdt_node_offset_by_compatible(blob, -1, "nxp,tda1997x");
 829         if (off < 0)
 830                 return off;
 831
 832         if (0 == strcasecmp(mode, "yuv422bt656")) {
 833                 u8 cfg[] = { 0x00, 0x00, 0x00, 0x82, 0x81, 0x00,
 834                              0x00, 0x00, 0x00 };
 835                 mode = "422_ccir";
 836                 fdt_setprop(blob, off, "vidout_fmt", mode, strlen(mode) + 1);
 837                 fdt_setprop_u32(blob, off, "vidout_trc", 1);
 838                 fdt_setprop_u32(blob, off, "vidout_blc", 1);
 839                 fdt_setprop(blob, off, "vidout_portcfg", cfg, sizeof(cfg));
 840                 printf("   set HDMI input mode to %s\n", mode);
 841         } else if (0 == strcasecmp(mode, "yuv422smp")) {
 842                 u8 cfg[] = { 0x00, 0x00, 0x00, 0x88, 0x87, 0x00,
 843                              0x82, 0x81, 0x00 };
 844                 mode = "422_smp";
 845                 fdt_setprop(blob, off, "vidout_fmt", mode, strlen(mode) + 1);
 846                 fdt_setprop_u32(blob, off, "vidout_trc", 0);
 847                 fdt_setprop_u32(blob, off, "vidout_blc", 0);
 848                 fdt_setprop(blob, off, "vidout_portcfg", cfg, sizeof(cfg));
 849                 printf("   set HDMI input mode to %s\n", mode);
 850         } else {
 851                 return -EINVAL;
 852         }
 853
 854         return 0;
 855 }
 856
 857 /* enable a property of a node if the node is found */
 858 static inline void ft_enable_path(void *blob, const char *path)
 859 {
 860         int i = fdt_path_offset(blob, path);
 861         if (i >= 0) {
 862                 debug("enabling %s\n", path);
 863                 fdt_status_okay(blob, i);
 864         }
 865 }
 866
 867 /* remove a property of a node if the node is found */
 868 static inline void ft_delprop_path(void *blob, const char *path,
 869                                    const char *name)
 870 {
 871         int i = fdt_path_offset(blob, path);
 872         if (i) {
 873                 debug("removing %s/%s\n", path, name);
 874                 fdt_delprop(blob, i, name);
 875         }
 876 }
 877
 878 #if defined(CONFIG_CMD_PCI)
 879 #define PCI_ID(x) ( \
 880         (PCI_BUS(x->devfn)<<16)| \
 881         (PCI_DEV(x->devfn)<<11)| \
 882         (PCI_FUNC(x->devfn)<<8) \
 883         )
 884 #define PCIE_PATH       "/soc/pcie@0x01000000"
 885 int fdt_add_pci_node(void *blob, int par, struct pci_dev *dev)
 886 {
 887         uint32_t reg[5];
 888         char node[32];
 889         int np;
 890
 891         sprintf(node, "pcie@%d,%d,%d", PCI_BUS(dev->devfn),
 892                 PCI_DEV(dev->devfn), PCI_FUNC(dev->devfn));
 893
 894         np = fdt_subnode_offset(blob, par, node);
 895         if (np >= 0)
 896                 return np;
 897         np = fdt_add_subnode(blob, par, node);
 898         if (np < 0) {
 899                 printf("   %s failed: no space\n", __func__);
 900                 return np;
 901         }
 902
 903         memset(reg, 0, sizeof(reg));
 904         reg[0] = cpu_to_fdt32(PCI_ID(dev));
 905         fdt_setprop(blob, np, "reg", reg, sizeof(reg));
 906
 907         return np;
 908 }
 909
 910 /* build a path of nested PCI devs for all bridges passed through */
 911 int fdt_add_pci_path(void *blob, struct pci_dev *dev)
 912 {
 913         struct pci_dev *bridges[MAX_PCI_DEVS];
 914         int k, np;
 915
 916         /* build list of parents */
 917         np = fdt_path_offset(blob, PCIE_PATH);
 918         if (np < 0)
 919                 return np;
 920
 921         k = 0;
 922         while (dev) {
 923                 bridges[k++] = dev;
 924                 dev = dev->ppar;
 925         };
 926
 927         /* now add them the to DT in reverse order */
 928         while (k--) {
 929                 np = fdt_add_pci_node(blob, np, bridges[k]);
 930                 if (np < 0)
 931                         break;
 932         }
 933
 934         return np;
 935 }
 936
 937 /*
 938  * The GW16082 has a hardware errata errata such that it's
 939  * INTA/B/C/D are mis-mapped to its four slots (slot12-15). Because
 940  * of this normal PCI interrupt swizzling will not work so we will
 941  * provide an irq-map via device-tree.
 942  */
 943 int fdt_fixup_gw16082(void *blob, int np, struct pci_dev *dev)
 944 {
 945         int len;
 946         int host;
 947         uint32_t imap_new[8*4*4];
 948         const uint32_t *imap;
 949         uint32_t irq[4];
 950         uint32_t reg[4];
 951         int i;
 952
 953         /* build irq-map based on host controllers map */
 954         host = fdt_path_offset(blob, PCIE_PATH);
 955         if (host < 0) {
 956                 printf("   %s failed: missing host\n", __func__);
 957                 return host;
 958         }
 959
 960         /* use interrupt data from root complex's node */
 961         imap = fdt_getprop(blob, host, "interrupt-map", &len);
 962         if (!imap || len != 128) {
 963                 printf("   %s failed: invalid interrupt-map\n",
 964                        __func__);
 965                 return -FDT_ERR_NOTFOUND;
 966         }
 967
 968         /* obtain irq's of host controller in pin order */
 969         for (i = 0; i < 4; i++)
 970                 irq[(fdt32_to_cpu(imap[(i*8)+3])-1)%4] = imap[(i*8)+6];
 971
 972         /*
 973          * determine number of swizzles necessary:
 974          *   For each bridge we pass through we need to swizzle
 975          *   the number of the slot we are on.
 976          */
 977         struct pci_dev *d;
 978         int b;
 979         b = 0;
 980         d = dev->ppar;
 981         while(d && d->ppar) {
 982                 b += PCI_DEV(d->devfn);
 983                 d = d->ppar;
 984         }
 985
 986         /* create new irq mappings for slots12-15
 987          * <skt> <idsel> <slot> <skt-inta> <skt-intb>
 988          * J3    AD28    12     INTD      INTA
 989          * J4    AD29    13     INTC      INTD
 990          * J5    AD30    14     INTB      INTC
 991          * J2    AD31    15     INTA      INTB
 992          */
 993         for (i = 0; i < 4; i++) {
 994                 /* addr matches bus:dev:func */
 995                 u32 addr = dev->busno << 16 | (12+i) << 11;
 996
 997                 /* default cells from root complex */
 998                 memcpy(&imap_new[i*32], imap, 128);
 999                 /* first cell is PCI device address (BDF) */
1000                 imap_new[(i*32)+(0*8)+0] = cpu_to_fdt32(addr);
1001                 imap_new[(i*32)+(1*8)+0] = cpu_to_fdt32(addr);
1002                 imap_new[(i*32)+(2*8)+0] = cpu_to_fdt32(addr);
1003                 imap_new[(i*32)+(3*8)+0] = cpu_to_fdt32(addr);
1004                 /* third cell is pin */
1005                 imap_new[(i*32)+(0*8)+3] = cpu_to_fdt32(1);
1006                 imap_new[(i*32)+(1*8)+3] = cpu_to_fdt32(2);
1007                 imap_new[(i*32)+(2*8)+3] = cpu_to_fdt32(3);
1008                 imap_new[(i*32)+(3*8)+3] = cpu_to_fdt32(4);
1009                 /* sixth cell is relative interrupt */
1010                 imap_new[(i*32)+(0*8)+6] = irq[(15-(12+i)+b+0)%4];
1011                 imap_new[(i*32)+(1*8)+6] = irq[(15-(12+i)+b+1)%4];
1012                 imap_new[(i*32)+(2*8)+6] = irq[(15-(12+i)+b+2)%4];
1013                 imap_new[(i*32)+(3*8)+6] = irq[(15-(12+i)+b+3)%4];
1014         }
1015         fdt_setprop(blob, np, "interrupt-map", imap_new,
1016                     sizeof(imap_new));
1017         reg[0] = cpu_to_fdt32(0xfff00);
1018         reg[1] = 0;
1019         reg[2] = 0;
1020         reg[3] = cpu_to_fdt32(0x7);
1021         fdt_setprop(blob, np, "interrupt-map-mask", reg, sizeof(reg));
1022         fdt_setprop_cell(blob, np, "#interrupt-cells", 1);
1023         fdt_setprop_string(blob, np, "device_type", "pci");
1024         fdt_setprop_cell(blob, np, "#address-cells", 3);
1025         fdt_setprop_cell(blob, np, "#size-cells", 2);
1026         printf("   Added custom interrupt-map for GW16082\n");
1027
1028         return 0;
1029 }
1030
1031 /* The sky2 GigE MAC obtains it's MAC addr from device-tree by default */
1032 int fdt_fixup_sky2(void *blob, int np, struct pci_dev *dev)
1033 {
1034         char *tmp, *end;
1035         char mac[16];
1036         unsigned char mac_addr[6];
1037         int j;
1038
1039         sprintf(mac, "eth1addr");
1040         tmp = env_get(mac);
1041         if (tmp) {
1042                 for (j = 0; j < 6; j++) {
1043                         mac_addr[j] = tmp ?
1044                                       simple_strtoul(tmp, &end,16) : 0;
1045                         if (tmp)
1046                                 tmp = (*end) ? end+1 : end;
1047                 }
1048                 fdt_setprop(blob, np, "local-mac-address", mac_addr,
1049                             sizeof(mac_addr));
1050                 printf("   Added mac addr for eth1\n");
1051                 return 0;
1052         }
1053
1054         return -1;
1055 }
1056
1057 /*
1058  * PCI DT nodes must be nested therefore if we need to apply a DT fixup
1059  * we will walk the PCI bus and add bridge nodes up to the device receiving
1060  * the fixup.
1061  */
1062 void ft_board_pci_fixup(void *blob, bd_t *bd)
1063 {
1064         int i, np;
1065         struct pci_dev *dev;
1066
1067         for (i = 0; i < pci_devno; i++) {
1068                 dev = &pci_devs[i];
1069
1070                 /*
1071                  * The GW16082 consists of a TI XIO2001 PCIe-to-PCI bridge and
1072                  * an EEPROM at i2c1-0x50.
1073                  */
1074                 if ((dev->vendor == PCI_VENDOR_ID_TI) &&
1075                     (dev->device == 0x8240) &&
1076                     (i2c_set_bus_num(1) == 0) &&
1077                     (i2c_probe(0x50) == 0))
1078                 {
1079                         np = fdt_add_pci_path(blob, dev);
1080                         if (np > 0)
1081                                 fdt_fixup_gw16082(blob, np, dev);
1082                 }
1083
1084                 /* ethernet1 mac address */
1085                 else if ((dev->vendor == PCI_VENDOR_ID_MARVELL) &&
1086                          (dev->device == 0x4380))
1087                 {
1088                         np = fdt_add_pci_path(blob, dev);
1089                         if (np > 0)
1090                                 fdt_fixup_sky2(blob, np, dev);
1091                 }
1092         }
1093 }
1094 #endif /* if defined(CONFIG_CMD_PCI) */
1095
1096 void ft_board_wdog_fixup(void *blob, const char *path)
1097 {
1098         ft_delprop_path(blob, path, "ext-reset-output");
1099         ft_delprop_path(blob, path, "fsl,ext-reset-output");
1100 }
1101
1102 /*
1103  * called prior to booting kernel or by 'fdt boardsetup' command
1104  *
1105  * unless 'fdt_noauto' env var is set we will update the following in the DTB:
1106  *  - mtd partitions based on mtdparts/mtdids env
1107  *  - system-serial (board serial num from EEPROM)
1108  *  - board (full model from EEPROM)
1109  *  - peripherals removed from DTB if not loaded on board (per EEPROM config)
1110  */
1111 #define UART1_PATH      "/soc/aips-bus@02100000/serial@021ec000"
1112 #define WDOG1_PATH      "/soc/aips-bus@02000000/wdog@020bc000"
1113 #define WDOG2_PATH      "/soc/aips-bus@02000000/wdog@020c0000"
1114 #define GPIO3_PATH      "/soc/aips-bus@02000000/gpio@020a4000"
1115 int ft_board_setup(void *blob, bd_t *bd)
1116 {
1117         struct ventana_board_info *info = &ventana_info;
1118         struct ventana_eeprom_config *cfg;
1119         static const struct node_info nodes[] = {
1120                 { "sst,w25q256",          MTD_DEV_TYPE_NOR, },  /* SPI flash */
1121                 { "fsl,imx6q-gpmi-nand",  MTD_DEV_TYPE_NAND, }, /* NAND flash */
1122         };
1123         const char *model = env_get("model");
1124         const char *display = env_get("display");
1125         int i;
1126         char rev = 0;
1127
1128         /* determine board revision */
1129         for (i = sizeof(ventana_info.model) - 1; i > 0; i--) {
1130                 if (ventana_info.model[i] >= 'A') {
1131                         rev = ventana_info.model[i];
1132                         break;
1133                 }
1134         }
1135
1136         if (env_get("fdt_noauto")) {
1137                 puts("   Skiping ft_board_setup (fdt_noauto defined)\n");
1138                 return 0;
1139         }
1140
1141         if (test_bit(EECONFIG_NAND, info->config)) {
1142                 /* Update partition nodes using info from mtdparts env var */
1143                 puts("   Updating MTD partitions...\n");
1144                 fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
1145         }
1146
1147         /* Update display timings from display env var */
1148         if (display) {
1149                 if (fdt_fixup_display(blob, fdt_get_alias(blob, "lvds0"),
1150                                       display) >= 0)
1151                         printf("   Set display timings for %s...\n", display);
1152         }
1153
1154         printf("   Adjusting FDT per EEPROM for %s...\n", model);
1155
1156         /* board serial number */
1157         fdt_setprop(blob, 0, "system-serial", env_get("serial#"),
1158                     strlen(env_get("serial#")) + 1);
1159
1160         /* board (model contains model from device-tree) */
1161         fdt_setprop(blob, 0, "board", info->model,
1162                     strlen((const char *)info->model) + 1);
1163
1164         /* set desired digital video capture format */
1165         ft_sethdmiinfmt(blob, env_get("hdmiinfmt"));
1166
1167         /*
1168          * Board model specific fixups
1169          */
1170         switch (board_type) {
1171         case GW51xx:
1172                 /*
1173                  * disable wdog node for GW51xx-A/B to work around
1174                  * errata causing wdog timer to be unreliable.
1175                  */
1176                 if (rev >= 'A' && rev < 'C') {
1177                         i = fdt_path_offset(blob, WDOG1_PATH);
1178                         if (i)
1179                                 fdt_status_disabled(blob, i);
1180                 }
1181
1182                 /* GW51xx-E adds WDOG1_B external reset */
1183                 if (rev < 'E')
1184                         ft_board_wdog_fixup(blob, WDOG1_PATH);
1185                 break;
1186
1187         case GW52xx:
1188                 /* GW522x Uses GPIO3_IO23 instead of GPIO1_IO29 */
1189                 if (info->model[4] == '2') {
1190                         u32 handle = 0;
1191                         u32 *range = NULL;
1192
1193                         i = fdt_node_offset_by_compatible(blob, -1,
1194                                                           "fsl,imx6q-pcie");
1195                         if (i)
1196                                 range = (u32 *)fdt_getprop(blob, i,
1197                                                            "reset-gpio", NULL);
1198
1199                         if (range) {
1200                                 i = fdt_path_offset(blob, GPIO3_PATH);
1201                                 if (i)
1202                                         handle = fdt_get_phandle(blob, i);
1203                                 if (handle) {
1204                                         range[0] = cpu_to_fdt32(handle);
1205                                         range[1] = cpu_to_fdt32(23);
1206                                 }
1207                         }
1208
1209                         /* these have broken usd_vsel */
1210                         if (strstr((const char *)info->model, "SP318-B") ||
1211                             strstr((const char *)info->model, "SP331-B"))
1212                                 gpio_cfg[board_type].usd_vsel = 0;
1213
1214                         /* GW522x-B adds WDOG1_B external reset */
1215                         ft_board_wdog_fixup(blob, WDOG1_PATH);
1216                 }
1217
1218                 /* GW520x-E adds WDOG1_B external reset */
1219                 else if (info->model[4] == '0' && rev < 'E')
1220                         ft_board_wdog_fixup(blob, WDOG1_PATH);
1221                 break;
1222
1223         case GW53xx:
1224                 /* GW53xx-E adds WDOG1_B external reset */
1225                 if (rev < 'E')
1226                         ft_board_wdog_fixup(blob, WDOG1_PATH);
1227                 break;
1228
1229         case GW54xx:
1230                 /*
1231                  * disable serial2 node for GW54xx for compatibility with older
1232                  * 3.10.x kernel that improperly had this node enabled in the DT
1233                  */
1234                 i = fdt_path_offset(blob, UART1_PATH);
1235                 if (i)
1236                         fdt_del_node(blob, i);
1237
1238                 /* GW54xx-E adds WDOG2_B external reset */
1239                 if (rev < 'E')
1240                         ft_board_wdog_fixup(blob, WDOG2_PATH);
1241                 break;
1242
1243         case GW551x:
1244                 /*
1245                  * isolate CSI0_DATA_EN for GW551x-A to work around errata
1246                  * causing non functional digital video in (it is not hooked up)
1247                  */
1248                 if (rev == 'A') {
1249                         u32 *range = NULL;
1250                         int len;
1251                         const u32 *handle = NULL;
1252
1253                         i = fdt_node_offset_by_compatible(blob, -1,
1254                                                 "fsl,imx-tda1997x-video");
1255                         if (i)
1256                                 handle = fdt_getprop(blob, i, "pinctrl-0",
1257                                                      NULL);
1258                         if (handle)
1259                                 i = fdt_node_offset_by_phandle(blob,
1260                                                         fdt32_to_cpu(*handle));
1261                         if (i)
1262                                 range = (u32 *)fdt_getprop(blob, i, "fsl,pins",
1263                                                            &len);
1264                         if (range) {
1265                                 len /= sizeof(u32);
1266                                 for (i = 0; i < len; i += 6) {
1267                                         u32 mux_reg = fdt32_to_cpu(range[i+0]);
1268                                         u32 conf_reg = fdt32_to_cpu(range[i+1]);
1269                                         /* mux PAD_CSI0_DATA_EN to GPIO */
1270                                         if (is_cpu_type(MXC_CPU_MX6Q) &&
1271                                             mux_reg == 0x260 &&
1272                                             conf_reg == 0x630)
1273                                                 range[i+3] = cpu_to_fdt32(0x5);
1274                                         else if (!is_cpu_type(MXC_CPU_MX6Q) &&
1275                                                  mux_reg == 0x08c &&
1276                                                  conf_reg == 0x3a0)
1277                                                 range[i+3] = cpu_to_fdt32(0x5);
1278                                 }
1279                                 fdt_setprop_inplace(blob, i, "fsl,pins", range,
1280                                                     len);
1281                         }
1282
1283                         /* set BT656 video format */
1284                         ft_sethdmiinfmt(blob, "yuv422bt656");
1285                 }
1286
1287                 /* GW551x-C adds WDOG1_B external reset */
1288                 if (rev < 'C')
1289                         ft_board_wdog_fixup(blob, WDOG1_PATH);
1290                 break;
1291         }
1292
1293         /* Configure DIO */
1294         for (i = 0; i < gpio_cfg[board_type].dio_num; i++) {
1295                 struct dio_cfg *cfg = &gpio_cfg[board_type].dio_cfg[i];
1296                 char arg[10];
1297
1298                 sprintf(arg, "dio%d", i);
1299                 if (!hwconfig(arg))
1300                         continue;
1301                 if (hwconfig_subarg_cmp(arg, "mode", "pwm") && cfg->pwm_param)
1302                 {
1303                         char path[48];
1304                         sprintf(path, "/soc/aips-bus@02000000/pwm@%08x",
1305                                 0x02080000 + (0x4000 * (cfg->pwm_param - 1)));
1306                         printf("   Enabling pwm%d for DIO%d\n",
1307                                cfg->pwm_param, i);
1308                         ft_enable_path(blob, path);
1309                 }
1310         }
1311
1312         /* remove no-1-8-v if UHS-I support is present */
1313         if (gpio_cfg[board_type].usd_vsel) {
1314                 debug("Enabling UHS-I support\n");
1315                 ft_delprop_path(blob, "/soc/aips-bus@02100000/usdhc@02198000",
1316                                 "no-1-8-v");
1317         }
1318
1319 #if defined(CONFIG_CMD_PCI)
1320         if (!env_get("nopcifixup"))
1321                 ft_board_pci_fixup(blob, bd);
1322 #endif
1323
1324         /*
1325          * Peripheral Config:
1326          *  remove nodes by alias path if EEPROM config tells us the
1327          *  peripheral is not loaded on the board.
1328          */
1329         if (env_get("fdt_noconfig")) {
1330                 puts("   Skiping periperhal config (fdt_noconfig defined)\n");
1331                 return 0;
1332         }
1333         cfg = econfig;
1334         while (cfg->name) {
1335                 if (!test_bit(cfg->bit, info->config)) {
1336                         fdt_del_node_and_alias(blob, cfg->dtalias ?
1337                                                cfg->dtalias : cfg->name);
1338                 }
1339                 cfg++;
1340         }
1341
1342         return 0;
1343 }
1344 #endif /* CONFIG_OF_BOARD_SETUP */
1345
1346 static struct mxc_serial_platdata ventana_mxc_serial_plat = {
1347         .reg = (struct mxc_uart *)UART2_BASE,
1348 };
1349
1350 U_BOOT_DEVICE(ventana_serial) = {
1351         .name   = "serial_mxc",
1352         .platdata = &ventana_mxc_serial_plat,
1353 };