board/data_modul/imx8mp_edm_sbc/spl.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2022 Marek Vasut <marex@denx.de>
   4  */
   5
   6 #include <hang.h>
   7 #include <image.h>
   8 #include <init.h>
   9 #include <spl.h>
  10
  11 #include <asm-generic/gpio.h>
  12 #include <asm/arch/clock.h>
  13 #include <asm/arch/ddr.h>
  14 #include <asm/arch/imx8mp_pins.h>
  15 #include <asm/arch/sys_proto.h>
  16 #include <asm/io.h>
  17 #include <asm/mach-imx/boot_mode.h>
  18
  19 #include <dm/uclass.h>
  20 #include <dm/device.h>
  21 #include <dm/uclass-internal.h>
  22 #include <dm/device-internal.h>
  23
  24 #include <power/pmic.h>
  25 #include <power/pca9450.h>
  26
  27 #include "lpddr4_timing.h"
  28
  29 #include "../common/common.h"
  30
  31 DECLARE_GLOBAL_DATA_PTR;
  32
  33 int data_modul_imx_edm_sbc_board_power_init(void)
  34 {
  35         struct udevice *dev;
  36         int ret;
  37
  38         ret = pmic_get("pmic@25", &dev);
  39         if (ret == -ENODEV) {
  40                 puts("Failed to get PMIC\n");
  41                 return 0;
  42         }
  43         if (ret != 0)
  44                 return ret;
  45
  46         /* BUCKxOUT_DVS0/1 control BUCK123 output. */
  47         pmic_reg_write(dev, PCA9450_BUCK123_DVS, 0x29);
  48
  49         /* Increase VDD_SOC to typical value 0.95V before first DRAM access. */
  50         if (IS_ENABLED(CONFIG_IMX8M_VDD_SOC_850MV))
  51                 /* Set DVS0 to 0.85V for special case. */
  52                 pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x14);
  53         else
  54                 pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x1c);
  55
  56         /* Set DVS1 to 0.85v for suspend. */
  57         pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0x14);
  58
  59         /*
  60          * Enable DVS control through PMIC_STBY_REQ and
  61          * set B1_ENMODE=1 (ON by PMIC_ON_REQ=H).
  62          */
  63         pmic_reg_write(dev, PCA9450_BUCK1CTRL, 0x59);
  64
  65         /* Kernel uses OD/OD frequency for SoC. */
  66
  67         /* To avoid timing risk from SoC to ARM, increase VDD_ARM to OD voltage 0.95V */
  68         pmic_reg_write(dev, PCA9450_BUCK2OUT_DVS0, 0x1c);
  69
  70         /* DRAM Vdd1 always FPWM */
  71         pmic_reg_write(dev, PCA9450_BUCK5CTRL, 0x0d);
  72         /* DRAM Vdd2/Vddq always FPWM */
  73         pmic_reg_write(dev, PCA9450_BUCK6CTRL, 0x0d);
  74
  75         /* Set LDO4 and CONFIG2 to enable the I2C level translator. */
  76         pmic_reg_write(dev, PCA9450_LDO4CTRL, 0x59);
  77         pmic_reg_write(dev, PCA9450_CONFIG2, 0x1);
  78
  79         return 0;
  80 }
  81
  82 void spl_board_init(void)
  83 {
  84         /*
  85          * Set GIC clock to 500 MHz for OD VDD_SOC. Kernel driver does not
  86          * allow to change it. Should set the clock after PMIC setting done.
  87          * Default is 400 MHz (system_pll1_800m with div = 2) set by ROM for
  88          * ND VDD_SOC.
  89          */
  90         clock_enable(CCGR_GIC, 0);
  91         clock_set_target_val(GIC_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(5));
  92         clock_enable(CCGR_GIC, 1);
  93 }
  94
  95 int spl_board_boot_device(enum boot_device boot_dev_spl)
  96 {
  97         if (boot_dev_spl == SPI_NOR_BOOT)       /* SPI NOR */
  98                 return BOOT_DEVICE_SPI;
  99
 100         if (boot_dev_spl == MMC3_BOOT)          /* eMMC */
 101                 return BOOT_DEVICE_MMC2;
 102
 103         return BOOT_DEVICE_MMC1;                /* SD */
 104 }
 105
 106 void board_boot_order(u32 *spl_boot_list)
 107 {
 108         int boot_device = spl_boot_device();
 109
 110         spl_boot_list[0] = boot_device;         /* 1:SD 2:eMMC 8:SPI NOR */
 111
 112         if (boot_device == BOOT_DEVICE_SPI) {           /* SPI, eMMC, SD */
 113                 spl_boot_list[1] = BOOT_DEVICE_MMC2;    /* eMMC */
 114                 spl_boot_list[2] = BOOT_DEVICE_MMC1;    /* SD */
 115         } else if (boot_device == BOOT_DEVICE_MMC1) {   /* SD, eMMC, SPI */
 116                 spl_boot_list[1] = BOOT_DEVICE_MMC2;    /* eMMC */
 117                 spl_boot_list[2] = BOOT_DEVICE_SPI;     /* SPI */
 118         } else {                                        /* eMMC, SPI, SD */
 119                 spl_boot_list[1] = BOOT_DEVICE_SPI;     /* SPI */
 120                 spl_boot_list[2] = BOOT_DEVICE_MMC1;    /* SD */
 121         }
 122
 123         spl_boot_list[3] = BOOT_DEVICE_UART;    /* YModem */
 124         spl_boot_list[4] = BOOT_DEVICE_NONE;
 125 }
 126
 127 unsigned long board_spl_mmc_get_uboot_raw_sector(struct mmc *mmc, unsigned long sect)
 128 {
 129         const u32 boot_dev = spl_boot_device();
 130         int part;
 131
 132         if (boot_dev == BOOT_DEVICE_MMC2) {     /* eMMC */
 133                 part = spl_mmc_emmc_boot_partition(mmc);
 134                 if (part == 1 || part == 2)     /* eMMC BOOT1/BOOT2 HW partitions */
 135                         return sect - 0x40;
 136         }
 137
 138         return sect;
 139 }
 140
 141 static struct dram_timing_info *dram_timing_info[8] = {
 142         &dmo_imx8mp_sbc_dram_timing_32_32,      /* 32 Gbit x32 */
 143         NULL,                                   /* 32 Gbit x16 */
 144         NULL,                                   /* 16 Gbit x32 */
 145         NULL,                                   /* 16 Gbit x16 */
 146         NULL,                                   /* 8 Gbit x32 */
 147         NULL,                                   /* 8 Gbit x16 */
 148         NULL,                                   /* INVALID */
 149         NULL,                                   /* INVALID */
 150 };
 151
 152 void board_init_f(ulong dummy)
 153 {
 154         dmo_board_init_f(MX8MP_PAD_GPIO1_IO02__WDOG1_WDOG_B, dram_timing_info);
 155 }